MB89123_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12509-6E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89120/120A Series

MB89121/P131/123A/P133A/125A/P135A/

MB89PV130A

■ DESCRIPTION

The MB89120 series is a line of single-chip microcontrollers containing a compact instruction set and a great

variety of peripheral functions such as a timer, serial interface, and external interrupt. The MB89120A series is

an extended variant of the MB89120, with a remote control transmission function and wake-up interrupt channels.

■ FEATURES

• F²MC-8L family CPU core

• Low-voltage operation

• Low current consumption (allowing for dual clock)

• Minimum execution time : 0.95 µs at 4.2 MHz

• 21-bit timebase counter

• I/O ports : Max. 36 ports

• External interrupts : 3 channels

• External interrupts (wake-up function) : 8 channels (only in the MB89120A series)

• 8-bit serial I/O : 1 channel

• 8-/16-bit timer/counter : 1 channel

• Built-in remote-control transmitting frequency generator (only in the MB89120A series)

• Low-power consumption modes (stop mode, sleep mode, watch mode)

• Package : QFP-48

• CMOS technology

■ PACKAGE

48-pin plastic QFP

(FPT-48P-M13)

MB89120/120A Series

■ PRODUCT LINEUP

Part number

MB89121

MB89123A

MB89125A

MB89P133A

MB89P131

Item

Mass-produced products

(Mask ROM products)

Classification

One-time products

8 K × 8 bits

4 K × 8 bits

(InternalPROMto (Internal PROM

be programmed tobeprogrammed

4 K × 8 bits

8 K × 8 bits

16 K × 8 bits

ROM size

(internal mask (internal mask (internal mask

with a general-

ROM)

purpose EPROM purpose EPROM

programmer)

RAM size

128 × 8 bits

256 × 8 bits

128 × 8 bits

The number of instructions

Instruction bit length

: 136

: 8 bits

Instruction length

Data bit length

: 1 to 3 bytes

: 1, 8, 16 bits

CPU functions

Minimum execution time

Minimum interrupt processing time

: 0.95 µs at 4.2 MHz

: 8.57 µs at 4.2 MHz

Output ports (N-ch open-drain)

Output ports (CMOS)

I/O ports (CMOS)

Total

: 4 (All also serves as peripherals.)

: 8

: 24 (8 ports also serve as peripherals.)

: 36

Ports

Timer/counter

Serial I/O

8-bit timer/counter × 2 channels or 16-bit event counter × 1 channel

8 bits

LSB/MSB first selectable

3 Independent channels (edge selection, interrupt vector, source flag)

Rising edge/falling edge/both edges selectable

External interrupt 1

Also for wake-up from stop/sleep mode (edge detection is also permitted in stop mode)

External interrupt 2

(wake-up function)

8 channels (only for level detection)

Remote control

transmitting frequen-

cy generator

1 channel

(pulse width and frequency selectable

by program)

Standby mode

Process

Sleep mode, stop mode, watch mode

CMOS

2.2 V to 4.0 V (with the dual clock option)

2.7 V to 6.0 V

Operating voltage*

EPROM for use

2.2 V to 6.0 V (with the single clock option)

* : Varies with conditions such as operating frequencies. (See “■ ELECTRICAL CHARACTERISTICS”.)

(Continued)

2

MB89120/120A Series

(Continued)

Part number

MB89P135A

MB89PV130A

Item

Classification

One-time PROM products

Piggyback/evaluation product

16 K × 8 bits

(internal PROM, to be programmed with

general-purpose EPROM programmer)

32 K × 8 bits

(external ROM)

ROM size

RAM size

512 × 8 bits

1 K × 8 bits

The number of instructions

Instruction bit length

: 136

: 8 bits

Instruction length

Data bit length

Minimum execution time

Minimum interrupt processing time

: 1 to 3 bytes

: 1, 8, 16 bits

: 0.95 µs/4.2 MHz

: 8.57 µs/4.2 MHz

CPU functions

Output ports (N-ch open-drain ports)

Output ports (CMOS)

I/O ports (CMOS)

: 4 (All also serve as peripherals.)

: 8

: 24 (8 ports also serve as peripherals.)

: 36

Ports

Total

Timer/counter

Serial I/O

8-bit timer/counter × 2 channels or 16-bit event counter × 1 channel

8 bits

LSB/MSB first selectable

3 independent channels (edge selection, interrupt vector, source flag)

Rising/falling/both edges selectable

Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop

mode.)

External interrupt 1

External interrupt 2

(wake-up function)

8 channels (only for level detection)

Remote control

transmitting fre-

quency generator

1 channel (Pulse width and cycle selectable by program)

Standby mode

Process

Sleep mode, stop mode, and clock mode

CMOS

Operating voltage

EPROM for use

2.7 V to 6.0 V

MBM27C256A-20TVM

3

MB89120/120A Series

■ PACKAGE AND CORRESPONDING PRODUCTS

Package

FPT-48P-M13

MQP-48C-P01

MB89121

MB89123A

MB89125A

MB89P133A

MB89P131

×

Package

FPT-48P-M13

MQP-48C-P01

MB89P135A

MB89PV130A

×

: Available,

: Not available

Note : Package details of OTPROM products and piggyback/evaluation products are common to those of MB89130/

130A series. Refer to the MB89130/130A series data sheet for details.

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the one-time ROM product, verify its difference from the product that will actually be

used. Take particular care on the following points :

• The number of register banks available is different between the MB89121 and the MB89123A/125A/P135A/

PV130A.

• The stack area, etc., is set at the upper limit of the RAM.

2. Current Consumption

• When operated at low speed, a product with an OTPROM (EPROM) will consume more current than a product

with a mask ROM. However, the same is current consumption in the sleep/stop mode is the same. (For more

information, see “■ ELECTRICAL CHARACTERISTICS”.)

• In the case of the MB89PV130A, added is the current consumed by the EPROM which is connected to the

top socket.

3. Mask Options

Functions that can be selected as options and how to designate these options vary with product.

Before using options, check “■ MASK OPTIONS”.

Take particular care on the following point :

• Pull-up resistor can’t be set for P40 to P43 on the MB89P135A.

• Options are fixed on the MB89PV130A.

4

MB89120/120A Series

■ PIN ASSIGNMENT

(TOP VIEW)

AVCC

RST

MOD0

MOD1

X0

X1

VCC

X0A

X1A

P27

1

2

3

4

5

6

7

8

36

35

34

33

32

31

30

29

28

27

26

25

P36/INT2

P37/BZ/(RCO)

P00/(INT20)

P01/(INT21)

P02/(INT22)

P03/(INT23)

P04/(INT24)

P05/(INT25)

P06/(INT26)

P07/(INT27)

P10

9

10

11

12

P26

P25

P11

-

(FPT 48P M13)

Note : Parenthesized function is available only for the MB89120A series.

5

MB89120/120A Series

■ PIN DESCRIPTION

Pin no.

Pin name

X0

Circuit type

Function

5

6

8

9

3

4

A

Main clock crystal oscillator pins (max. 4.2 MHz)

X1

X0A

B

C

Subclock crystal oscillator pins (for 32.768 kHz)

X1A

MOD0

MOD1

Operation mode select pins

Connect these pins directly to V^SS.

Reset I/O pin

This port is of N-ch open-drain output type with pull-up re-

sistor and a hysteresis input type. The internal circuit is ini-

tialized by the input of “L”. “L” is output from this pin by an

internal reset source as optional setting.

2

RST

D

I

General-purpose I/O ports

On the MB89120A series, these pins also serve as exter-

nal interrupt input.

P07/ (INT27) to

P00/ (INT20)

27 to 34

External interrupt input is hysteresis input.

18, 20 to 26

10 to 17

P17 to P10

P27 to P20

E

General-purpose I/O ports

G

General-purpose output-only ports

General-purpose I/O port

42

41

40

P30/SCK

P31/SO

P32/SI

F

Also serves as clock I/O for the 8-bit serial I/O interface.

This port is of hysteresis input type.

General-purpose I/O port

Also serves as a serial I/O data output. This port is of hys-

teresis input type.

General-purpose I/O port

Also serves as a serial I/O data input. This port is of hys-

teresis input type.

General-purpose I/O port

Also serves as the external clock input for the 8-bit timer/

counter. This port is of hysteresis input type.

System clock output is optional.

39

38

P33/EC/SCO

P34/TO/INT0

F

General-purpose I/O port

Also serves as the overflow output and external

interrupt input for the 8-bit timer/counter. This port is of

hysteresis input type.

F

General-purpose I/O ports

Also serve as an external interrupt input. These ports are

of hysteresis input type.

36,

37

P36/INT2,

P35/INT1

General-purpose I/O port

Also serves as a buzzer output. This port is of

hysteresis input type. On the MB89120A series, the pin

also serves as a remote control output.

35

P37/BZ/ (RCO)

(Continued)

6

MB89120/120A Series

(Continued)

Pin no.

Pin name

P43 to P40

V^CC

Circuit type

Function

45 to 48

H

N-ch open-drain output ports

7

—

Power supply pin

19

VSS

Power supply (GND) pin

Use this pin at the same voltage as VCC.

1

AV^CC

AVR

AV^SS

—

44

43

Reference voltage input pin

Power supply (GND) pin

Use this pin at the same voltage as VSS.

7

MB89120/120A Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Crystal and ceramic oscillation type (main clock)

• Cricuit for the MB89P133A/P131/P135A/PV130A

• External clock input select versions of MB89121/

123A/125A

X1

X0

At an oscillation feedback resistor of approximately

1 MΩ / 5 V

Standby control signal

A

• Crystal and ceramic oscillation type (main clock)

• Crystal or ceramic oscillator select versions of

MB89121/123A/125A

At an oscillation feedback resistor of approximately

1 MΩ / 5 V

X1

X0

Standby control signal

• Crystal and ceramic oscillation type (sub clock)

Circuit for the MB89121/123A/125A

At an oscillation feedback resistor of approximately

4.5 MΩ / 5 V

X1A

X0A

Standby control signal

B

• Crystal and ceramic oscillation type (sub clock)

Circuit for the MB89P131/P133A/P135A/PV130A

At an oscillation feedback resistor of approximately

4.5 MΩ / 5 V

X1A

X0A

Standby control signal

C

D

• Output pull-up resistor (P-ch) of approximately

50 kΩ / 5 V

• Hysteresis input

R

P-ch

N-ch

(Continued)

8

MB89120/120A Series

(Continued)

Type

Circuit

Remarks

• CMOS output

R

• CMOS input

• Pull-up resistor optional

P-ch

E

N-ch

• CMOS output

R

• Hysteresis input

• Pull-up resistor optional

P-ch

F

N-ch

• CMOS output

P-ch

G

H

N-ch

P-ch

• N-ch open-drain output

• Pull-up resistor optional

R

P-ch

N-ch

• CMOS output

R

• CMOS input

P-ch

• The interrupt input is a hysteresis input (available

only on the MB89120A series) .

• Pull-up resistor optional

P-ch

N-ch

I

Interrupt input

Only for the MB89120A series

9

MB89120/120A Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- and high- voltage pins, or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in “■ ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly, and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prevent the analog power supply (AV^CCand AVR) and analog input from exceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull-down

resistor.

3. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

4. Power Supply Voltage Fluctuations

Although operation is assured within the rated range of VCC power supply voltage, a rapid fluctuation of the

voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC

is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctu-

ations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz)

and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when

power is switched.

5. Precautions when Using an External Clock

When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and

release from stop mode.

6. Turning on the supply voltage (only for the MB89P135A)

When the power supply is turned on if MB89P135A is used, power on sharply up to 2.0 V within 13 clock cycles

after starting of oscillation.

Further, various option may be set, if power supply up to keep this condition.

10

MB89120/120A Series

■ PROGRAMMING TO THE EPROM ON THE MB89P131

The MB89P131 is a one-time PROM version of the MB89121.

1. Features

• 4-Kbyte PROM on chip

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in EPROM mode is diagrammed below :

Address

0000H

Single chip

EPROM mode

(Corresponding addresses in the EPROM programmer)

I/O

Not available

RAM

0000H

Not available

7000H

F000H

PROM

4 KB

EPROM

32 KB

FFFFH

7FFFH

3. Programming to the EPROM

In EPROM mode the MB89P131 functions equivalent to the MBM27C256A. This allows the EPROM to be

programmed with a general-purpose EPROM programmer by using the dedicated socket adapter. Note, how-

ever, that the electronic signature mode cannot be used.

• Programming procedure

(1) Set the EPROM programmer to MBM27C256A.

(2) Load program data into the EPROM programmer at 7000^Hto 7FFFH (note that addresses F000H to

FFFFH while operating as a single chip correspond to 7000H to 7FFFH in EPROM mode) .

(3) Program with the EPROM programmer.

11

MB89120/120A Series

■ PROGRAMMING TO THE EPROM ON THE MB89P133A

The MB89P133A is a one-time PROM version of the MP89123A.

1. Features

• 8-Kbyte PROM on chip

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in EPROM mode is diagrammed below :

Address

0000H

Single chip

EPROM mode

(Corresponding addresses in the EPROM programmer)

I/O

RAM

0000H

Not available

E000H

FFFFH

6000H

PROM

8 KB

EPROM

32 KB

7FFFH

3. Programming to the EPROM

In EPROM mode the MB89P133A functions equivalent to the MBM27C256A, This allows the EPROM to be

programmed with a general-purpose EPROM programmer by using the dedicated socket adapter. Note, how-

ever, that the MB89P133A cannot use the electronic signature mode.

• Programming procedure

(1) Set the EPROM programmer to MBM27C256A.

(2) Load program data into the EPROM programmer at 6000H to 7FFFH (note that addresses E000H to

FFFFH while operating as a single chip correspond to 6000H to 7FFFH in EPROM mode) .

(3) Program with the EPROM programmer.

12

MB89120/120A Series

■ PROGRAMMING TO THE EPROM ON THE MB89P135A

The MB89P135A is an OTPROM version of the MB89123A/125A.

1. Features

• 16-Kbyte PROM on chip

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in EPROM mode is diagrammed below.

Address

0000H

Single chip

I/O

EPROM mode

(Corresponding addresses on the EPROM programmer)

0080H

0280H

RAM

Not available

8000H

0000H

Vacancy

(Read value FFH)

BFF0H

BFF6H

3FF0H

Option area

3FF6H

Not available

Vacancy

(Read value FFH)

C000H

4000H

PROM

16 KB

EPROM

16 KB

7FFFH

FFFFH

3. Programming to the EPROM

In EPROM mode, the MB89P135A functions equivalent to the MBM27C256A. This allows the PROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter.

• Programming procedure

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to

FFFFH while operating as a single chip correspond to 4000H to 7FFFH in EPROM mode) .

(3) Load option data into the EPROM programmer at 3FF0H to 3FF6H.

(4) Program with the EPROM programmer.

13

MB89120/120A Series

4. Setting OTPROM Options (MB89P135A Only)

The programming procedure is the same as that for the PROM. Options can be set by programming values at

the addresses shown on the memory map. The relationship between bits and options is shown on the following

bit map :

• OTPROM option bit map

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Clock mode

Oscillation

Vacancy Vacancy Vacancy selection

Reset pin

output

Power-on

reset

stabilization time

3FF0^HReadable Readable Readable 1 : Single

00 : 2²/FCH 10 : 2¹⁶/FCH

01 : 2¹²/FCH 11 : 2¹⁸/FCH

and

clock

1 : Yes

0 : No

1 : Yes

0 : No

writable

0 : Dual

clock

P07

P06

P05

P04

P03

P02

P01

P00

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

3FF1H

3FF2^H

3FF3^H

P17

P16

P15

P14

P13

P12

P11

P10

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

P37

P36

P35

P34

P33

P32

P31

P30

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Vacancy Vacancy Vacancy Vacancy

Vacancy

3FF4^HReadable Readable Readable Readable

Readable Readable Readable Readable

and

writable

Vacancy Vacancy Vacancy Vacancy

Vacancy

3FF5^HReadable Readable Readable Readable

Readable Readable Readable Readable

and

writable

Vacancy Vacancy Vacancy Vacancy

Vacancy

3FF6^HReadable Readable Readable Readable

Readable Readable Readable Readable

and

writable

Note : Each bit is set to “1” as the initialized value, therefore the pull-up option is not selected.

14

MB89120/120A Series

■ HANDLING MB89P131/P133A/P135A

1. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure.

Program, verify

Aging

+150 °C, 48 h

Data verification

Assembly

2. Programming Yield

Due to its nature, bit programming test can’t be conducted as Fujitsu delivery test. For this reason, a programming

yeild of 100% cannot be assured at all times.

3. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer

Recommended programmer

manufacturer and programmer name

Compatible socket adapter

Part no.

Package

Sun Hayato Co., Ltd.

Minato Electronics Inc.

1890A

MB89P131PF

Recommended

QFP-48

ROM-48QF2-28DP-8L

MB89P133APFM

Inquiry : Sun Hayato Co., Ltd. : TEL : (81) -3-3986-0403

FAX : (81) -3-5396-9106

Minato Electronics Inc. : TEL : USA (1) -916-348-6066

JAPAN (81) -45-591-5611

15

MB89120/120A Series

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TVM

2. Programming Socket Adapter

To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer : Sun Hayato

Co., Ltd.) listed below :

Package

Adapter socket part number

LCC-32 (Square)

ROM-32LC-28DP-S

Inquiry : Sun Hayato Co., Ltd. : TEL (81) -3-3986-0403

FAX (81) -3-5396-9106

3. Memory Space

Memory space in each mode, such as 32-Kbyte PROM is diagrammed below.

Address

0000H

Single chip

Corresponding addresses on the EPROM programmer

I/O

0080H

0480H

RAM

Not available

8000H

0000H

PROM

32 KB

EPROM

32 KB

7FFFH

FFFFH

4. Programming to the EPROM

(1) Set the EPROM programmer for the MBM27C256A.

(2) Load program data into the EPROM programmer at 0000^Hto 7FFFH.

(3) Program with the EPROM programmer.

16

MB89120/120A Series

■ BLOCK DIAGRAM

X0

X1

Timebase timer

Reset circuit

Main clock oscillator

Clock controller

RST

(WDT)

X0A

X1A

Subclock oscillator

(32.768 kHz)

8-bit timer/counter

P34/TO/INT0

P33/EC/SCO

CMOS I/O port

P00/(INT20) to

P07/(INT27)

8

External interrupt

(Wake-up)

P30/SCK

P32/SI

8-bit serial I/O

P10 to P17

P31/SO

External interrupt

P35/INT1

P36/INT2

8

Remote control

transmission

frequency generator

P20 to P27

Buzzer output

CMOS I/O port

CMOS output port

P37/BZ/(RCO)

N-ch open-drain output port

RAM

4

P40 to P43

F²MC-8L

CPU

ROM

The other pins

MOD0, MOD1, VCC, VSS

AVCC, AVR, AVSS

* : Only the MB89120A series has wake-up interrupt inputs and remote control transmission.

Note : Parenthesized pins are available only with the MB89120A series.

17

MB89120/120A Series

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89120/A series offer 64 Kbytes of memory for storing all of I/O, data, and program

areas. The I/O area is allocated from the lowest address. The data area is allocated immediately above the I/

O area. The data area can be divided into register, stack, and direct areas according to the application. The

program area is allocated from exactly the opposite end of I/O area, that is, near the highest address. The tables

of interrupt reset vectors and vector call instructions are allocated from the highest address with the program

area. The memory space of the MB89120/A series is structured as illustrated below :

Memory Space

MB89123A

MB89125A

MB89P135A

MB89PV130A

MB89121

MB89P133A

MB89P131

0000

H

0000

H

0000

H

0000

H

0000

H

I/O

007F

0080

H

007F

0080

H

007F

0080

H

007F

0080

H

007F

0080

H

Not available

RAM

512 B

RAM

1 KB

00BF

00C0

0100

H

00FF

0100

H

00FF

0100

H

0100

H

0100

H

Register

01FF

0200

H

01FF

0200

H

013F

0140

H

017F

0180

H

017F

0180

H

027F

0280

H

047F

0480

H

Not available

Vacancy

Not available

Vacancy

7FFF

8000

H

BFFF

H

BFFF

C000

H

Not available

C000

DFFF

E000

H

External

ROM

32 KB

ROM

16 KB

EFFF

F000

H

ROM

H

ROM

FFFF

H

FFFF

H

FFFF

H

FFFF

H

FFFF

H

18

MB89120/120A Series

2. Registers

The F²MC-8L family has two types of registers; dedicated hardware registers and general-purpose memory

registers. The following dedicated registers are provided :

Program counter (PC) :

Accumulator (A) :

A 16-bit-long register for indicating the instruction storage positions

A 16-bit-long temporary register for arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T) : A 16-bit-long register which is used for arithmetic operations with the accumu-

lator When the instruction is an 8-bit data processing instruction, the lower

byte is used.

Index register (IX) :

Extra pointer (EP) :

Stack pointer (SP) :

Program status (PS) :

A 16-bit-long register for index modification

A 16-bit-long pointer for indicating a memory address

A 16-bit-long pointer for indicating a stack area

A 16-bit-long register for storing a register pointer, a condition code

Initial value

16 bits

PC

A

: Program counter

: Accumulator

FFFDH

Indeterminate

T

: Temporary accumulator Indeterminate

IX

: Index register

: Extra pointer

: Stack pointer

: Program status

Indeterminate

EP

SP

PS

I-flag = 0, IL1, 0 = 11

The other bit values are Indeterminate.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR) (see the diagram below) .

Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

Vacancy Vacancy Vacancy

PS

RP

H

IL1, 0

N

V

C

RP

CCR

19

MB89120/120A Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

Rule for Conversion of Actual Addresses of the General-purpose Register Area

RP

Lower OP codes

"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and

bits for control of CPU operations at the time of an interrupt.

H-flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.

Cleared “0” otherwise. This flag is for decimal adjustment instructions.

I-flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when the flag is cleared to “0”.

Cleared to “0” at the reset.

IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level

is higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low

N-flag : Set to “1” if the MSB becomes “1” as the result of an arithmetic operation. Cleared to “0” otherwise.

Z-flag : Set to “1” when an arithmetic operation results in 0. Cleared to “0” otherwise.

V-flag : Set to “1” if the complement on “2” overflows as a result of an arithmetic operation. Cleared to “0” if

the overflow does not occur.

C-flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to

“0” otherwise. Set to the shift-out value in the case of a shift instruction.

20

MB89120/120A Series

The following general-purpose registers are provided :

General-purpose registers : An 8-bit-long register for storing data

The general-purpose registers are of 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 8 banks can be used on the MB89121/P131, and a total of 16 banks can be

used on the MB89123A/125A/P133A and a total of 32 banks can be used on the MB89P135A/PV130A.

The bank currently in use is indicated by the register bank pointer (RP) .

Register Bank Configuration

This address = 0100H + 8 × (RP)

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

8 banks (MB89121/P131)

16 banks (MB89123A/125A/133A)

32 banks (MB89P135A/PV130A)

Memory area

21

MB89120/120A Series

■ I/O MAP

Address

00^H

01^H

02H

03^H

04^H

05H

06^H

07^H

08H

09^H

0AH

0B^H

0CH

0DH

0E^H

0FH

10^H

11H

12H

13^H

14H

15H

16^H

17H

18H

19H

1A^H

1BH

1CH

1D^H

1EH

1FH

Read/write

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

DDR0

Port 0 data direction register

Port 1 data register

Port 1 data direction register

Port 2 data register

Vacancy

(R/W)

(W)

PDR1

DDR1

(R/W)

PDR2

Vacancy

(R/W)

(W)

SYCC

STBC

WDTC

TBTC

WPCR

PDR3

DDR3

PDR4

BZCR

System clock control register

Standby control register

Watchdog control register

Time-base timer control register

Watch prescaler control register

Port 3 data register

Port 3 data direction register

Port 4 data register

Buzzer register

(R/W)

Vacancy

(R/W)

SCGC

Peripheral control clock register

Vacancy

(R/W)

RCR1

RCR2

Remote control transmission control register 1*

Remote control transmission control register 2*

Vacancy

(R/W)

T2CR

T1CR

T2DR

T1DR

SMR1

SDR1

Timer 2 control register

Timer 1 control register

Timer 2 data register

Timer 1 data register

Serial mode register

Serial data register

Vacancy

(Continued)

22

MB89120/120A Series

(Continued)

Address

Read/write

Register name

Register description

Vacancy

20^H

21^H

Vacancy

22H

Vacancy

23^H

(R/W)

EIC1

EIC2

External interrupt control register 1

External interrupt control register 2

Vacancy

24^H

25H

26^Hto 31H

32^H

Vacancy

(R/W)

EIE2

EIF2

External interrupt 2 enable register*

External interrupt 2 flag register*

Vacancy

33H

34^Hto 7BH

7CH

(W)

ILR1

ILR2

ILR3

Interrupt level register 1

Interrupt level register 2

Interrupt level register 3

Vacancy

7D^H

7EH

7FH

* : Only in the MB89120A series

Note : Do not use vacancies.

23

MB89120/120A Series

■ ELECTRICAL CARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

V^CC

AVCC

AVR

Use VCC, AVCC , and AVR

set to the same voltage.

Power supply voltage

VSS − 0.3

VSS + 7.2

V

MOD1 pin on the

MB89P131/P133A/P135A

Program voltage

V^PP

VSS − 0.6

VSS + 13.0

Input voltage

V^I

VO

I^OL

VSS − 0.3

VCC + 0.3

10

V

Output voltage

“L” level maximum output current

mA

Avarage value (operating

current × operating rate)

“L” level average output current

I^OLAV

4

mA

“L” level total maximum output cur-

rent

ΣI^OL

100

Avarage value (operating

current × operating rate)

“L” level total average output current

“H” level maximum output current

“H” level average output current

ΣI^OLAV

IOH

20

−10

−2

mA

Avarage value (operating

current × operating rate)

I^OHAV

“H” level total maximum output cur-

rent

ΣIOH

−30

−10

mA

Avarage value (operating

current × operating rate)

“H” level total average output current

ΣI^OHAV

Power consumption

Operating temperature

Storage temperature

PD

TA

200

+85

mW

°C

−40

−55

Tstg

+150

°C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

24

MB89120/120A Series

2. Recommended Operating Conditions

Value

(AVSS = VSS = 0.0 V)

Symbol

Unit

Remarks

Parameter

Min.

Max.

Normal operation assurance range

2.2*

6.0*

V

Applied to “MB89P131/P133A/P135A/PV130A,

and single-clock MB89121/123A/125A*”

Power supply voltage

Operating temperature

V^CC

Normal operation assurance range

Applied to “ Dual-clock MB89121/123A/125A*”

2.7*

6.0*

1.5

6.0

V

Retains the RAM state in stop mode

T^A

−40

+85

°C

* : These values vary with the operating conditions. See “ Operating Voltage vs. Main Clock Operating

Frequency.”

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

25

MB89120/120A Series

• Operating Voltage vs. Main Clock Operating Frequency

Dual-clock MB89121/123A/125A

6

5

4

Operation assurance range

3

2

1

2

3

4

Main clock operating frequency (Instruction cycle time of 4/F^CH) (MHz)

4.0

2.0

1.0

Minimum execution time (µs)

MB89P131/P133A/P135A/PV130A, and single-clock MB89121/123A/125A

6

5

Operation assurance range

4

3

2

1

2

3

4

Main clock oprating frequency (Instruction cycle time of 4/F^CH) (MHz)

4.0

2.0

1.0

Minimum execution time (µs)

Note : The shaded area is assured only for the MB89121/123A/125A (instruction cycle time of 4/FCH) .

26

MB89120/120A Series

3. DC Characteristics

(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Condition

Unit Remarks

Min.

Typ.

Max.

P00 to P07,

P10 to P17

VCC +

0.3

V^IH

0.7 VCC

V

INT20 to

INT27 are

available

only in the

MB89120A

series.

“H” level input

voltage

RST,

P30 to P37,

INT20 to INT27

VCC +

0.3

V^IHS

0.8 VCC

V

P00 to P07,

P10 to P17

VSS −

0.3

VIL

0.3 VCC

0.2 VCC

V

INT20 to

INT27 are

available

“L” level input

voltage

RST,

P30 to P37,

INT20 to INT27

VSS −

0.3

V^ILS

V

only in the

MB89120A

series.

Open-drain

output pin

applied voltage

VSS −

0.3

VCC +

0.3

VD

P40 to P43

V

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37

“H” level output

voltage

V^OH

I^OH= −2.0 mA

2.4

P00 to P07,

P10 to P17

P20 to P27,

P30 to P37,

P40 to P43

V^OL

I^OL= 1.8 mA

IOL = 4.0 mA

0.4

0.6

V

“L” level output

voltage

V^OL2

RST

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

P40 to P43,

MOD0, MOD1

Input leakage

current

(Hi-z output

leakage current)

Without

µA pull-up

resistor

ILI

0.45 V < V^I< VCC

±5

P00 to P07,

P10 to P17,

P30 to P37,

P40 to P43,

RST

Pull-up resistance

R^PULL

VI = 0.0 V

25

50

100

kΩ

(Continued)

27

MB89120/120A Series

(Continued)

(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Condition

Unit Remarks

Min.

Typ.

Max.

MB89121/

mA

4

7

123A/125A

V^CC= 5.0 V

ICC1

FCH = 4.00 MHz

MB89P131/

mA P133A/

P135A

tinst^*2= 1.0 µs

6

2

10

5

VCC = 5.0 V

FCH = 4.00 MHz

Main sleep mode

tinst^*2= 1.0 µs

I^CCS1

mA

MB89121/

µA

50

1

100

3

123A/125A

VCC = 3.0 V

FCL = 32.768 kHz

Subclock mode

I^CCL

MB89P131/

mA P133A/

P135A

VCC

Power supply

current^*1

(External clock

operation)

VCC = 3.0 V

FCL = 32.768 kHz

Subclock sleep

mode

I^CCLS

25

50

15

µA

VCC = 3.0 V

F^CL= 32.768 kHz

• Watch mode

• Main clock stop

mode at dual

clock system

I^CCT

µA

TA = +25 °C

• Subclock stop

mode

• Main clock stop

mode at single

clock system

I^CCH

1

µA

Other than

AVCC, AVSS,

VCC, and VSS

Input capacitance

CIN

f = 1 MHz

10

pF

*1 : The measurement conditions of power supply current is external clock. (V^CC= 5.0 V, VCC = 3.0 V)

*2 : For information on tinst, see “ (4) Instruction Cycle” in “4. AC Characteristics.”

28

MB89120/120A Series

4. AC Characteristics

(1) Reset Timing

(V^CC= +5.0 V ±10%, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Min.

Max.

RST “L” pulse width

tZLZH

48 tHCYL*

ns

* : t^HCYLis the oscillation cycle (1/FCH) input to the X0.

tZLZH

RST

0.8 VCC

0.2 VCC

(2) Power-on Reset

(AV^SS= VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Min.

Max.

Power-on reset

function only

Power supply rising time

Power supply cut-off time

t^R

50

ms

Due to repeated

operations

t^OFF

1

Note : Make sure that power supply rises within the oscillation stabilization time selected.

When the main clock is operating at F^CH= 3 MHz and the oscillation stabilization time select option has been

set to 2¹²/FCH, for example, the oscillation settling time is 1.4 ms and accordingly the maximum value of

power supply rising time is about 1.4 ms.

Keep in mind that rapid changes in power supply voltage may cause a power-on reset. If power supply

voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.

tR

tOFF

2.0 V

0.2 V

VCC

29

MB89120/120A Series

(3) Clock Timings

(V^SS= 0.0 V, TA = −40 °C to +85 °C)

Value

Typ.

Symbol

Unit

Remarks

Parameter

Min.

Max.

F^CH

FCL

X0, X1

X0A, X1A

X0, X1

1

4.2

MHz Main clock

kHz Subclock

ns Main clock

µs Subclock

Clock frequency

32.768

30.5

t^HCYL

t^LCYL

238

72

1000

24

Clock cycle time

X0A, X1A

PWH1

PWL1

Input clock pulse width

X0

ns External clock

t^CR1

tCF1

Input clock rising/falling time

X0, X1 Timings and Conditions of Applied Voltage

tHCYL

0.8 VCC

0.2 VCC

X0

PWH1

PWL1

tCF1

tCR1

Main Clock Conditions of Applied Voltage

When a crystal

or

ceramic resonator is used

When an external clock is used

X0

X1

X0

X1

FCH

C1

Open

C0

FCH

30

MB89120/120A Series

X0A, X1A Timings and Conditions of Applied Voltage

tLCYL

0.8 VCC

X0A

Subclock Conditions of Applied Voltage

When a crystal

or

ceramic resonator is used

Single-clock option is used

X0A

X1A

X0A

X1A

Open

Rd

FCL

C0

C1

(4) Instruction Cycles

Parameter

(V^SS= 0.0 V, TA = −40 °C to +85 °C)

Symbol

Value (typical)

Unit

Remarks

4/FCH, 8/FCH, 16/FCH,

64/FCH

(4/FCH) tinst = 1.0 µs when operating at

FCH = 4 MHz

µs

Instruction cycle

(minimum execution time)

t^inst

tinst = 61.036 µs when operating at FCL

= 32.768 kHz

2/F^CL

31

MB89120/120A Series

(5) Recommended Resonator Manufacturers

Sample Application of Piezoelectric Resonator (FAR Series) for Main Clock Oscillation Circuit

(Only in the MB89120A Series)

X0

X1

R

1

FAR

2

C1

C2

*1 : FUJITSU MEDIA DEVICE LIMITED

Temperature

characteristics of

FAR frequency

Initial deviation of

FAR frequency

(T^A= +25 °C)

Loading

FAR part number

(built-incapacitortype)

Frequency Dumping

(MHz)

resistor

capacitors*²

(T^A= −20°Cto+60°C)

1000

510

FAR-C4CC-02000-L00

2.00

±0.5%

Built-in

FAR-C4 A-03580- 01

FAR-C4CB-04000-M00

3.58

4.00

—

Inquiry : FUJITSU MEDIA DEVICES LIMITED

32

MB89120/120A Series

Sample Application of Ceramic Resonator for Main Clock Oscillation Circuit

X0

X1

R

C1

C2

• Mask ROM products

Frequency

(MHz)

Resonator manufacturer*

Resonator

C1 (pF)

33

C2 (pF)

33

R (kΩ)

Not required

1.5

Kyocera Corporation

KBR-4.0MKS

EFOV4004B

4.00

1.00

Matsushita Electronic Compo-

nents

Built-in

CSBF1000J

100

Built-in

100

Built-in

100

6.8

CSTCS4.00MG800

CSA4.00MG040

CST4.00MGW040

Not required

Murata Mfg. Co. Ltd.

4.00

Built-in

Inquiry : Kyocera Corporation

• AVX Corporation

North American Sales Headquarters : TEL (803) 448-9411

• AVX Limited

European Sales Headquarters : TEL (01252) 770000

• AVX/Kyocera H.K. Ltd.

Asian Sales Headquarters : TEL 363-3303

Matsushita Electronic Components Co., Ltd.

• Ceramic Division : TEL 81-6-908-1101

Murata Mfg Co., Ltd.

• Murata Electronics North America, Inc. : TEL 1-404-436-1300

• Murata Europe Management GmbH : TEL 49-911-66870

• Murata Electronics Singapore (Pte.) Ltd. : TEL 65-758-4233

33

MB89120/120A Series

Sample Application of Crystal Resonator for Subclock Oscillation Circuit

X0A

X1A

Rd

C1

C2

• Mask ROM product

Frequency

Resonator manufacturer*

Resonator

DS-VT-200

C1 (pF)

C2 (pF)

Rd (kΩ)

(kHz)

SII

32.768

24

680

Inquiry : SII

Seiko Instruments Inc. (Japan) : TEL 81-43-211-1219

Seiko Instruments U.S.A. Inc. : TEL 310-517-7770

Seiko Instruments GmbH :

TEL 49-6102-297-122

34

MB89120/120A Series

(6) Serial I/O Timings

Parameter

(V^CC= +5.0 V ±10%, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol

Condition

Unit Remarks

Min.

2 tinst*

−200

200

t^inst*

tinst*

0

Max.

Serial clock cycle time

SCK ↓ → SO time

t^SCYC

tSLOV

t^IVSH

t^SHIX

tSHSL

t^SLSH

t^SLOV

tIVSH

tSHIX

SCK

µs

ns

µs

ns

SCK, SO

SI, SCK

SCK, SI

200

Internal clock

operation

Valid SI → SCK ↑

SCK ↑ → Valid SI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK ↓ → SO time

SCK

External clock

operation

SCK, SO

SI, SCK

SCK, SI

200

Valid SI → SCK ↑

200

SCK ↑ → Valid SI hold time

* : For information on t^inst, see “ (4) Instruction Cycles.”

Internal Shift Clock Mode

tSCYC

SCK

2.4 V

0.8 V

tSLOV

2.4 V

SO

0.8 V

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

SI

0.2 VCC

External Shift Clock Mode

tSLSH

tSHSL

SCK

0.8 VCC

0.2 VCC

tSLOV

0.2 VCC

2.4 V

0.8 V

SO

SI

tIVSH

0.8 VCC

0.2 VCC

tSHIX

0.8 VCC

0.2 VCC

35

MB89120/120A Series

(7) Peripheral Input Timings

(V^CC= +5.0 V ±10%, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol

Unit Remarks

Parameter

Min.

2 t^inst*

2 tinst*

Max.

t^ILIH

µs

Peripheral input “H” pulse width

Peripheral input “L” pulse width

EC, INT0 to INT2

tIHIL

* : For information on t^inst, see “ (4) Instruction Cycle.”

tIHIL

tILIH

EC

INT0 to INT2

0.8 VCC

0.2 VCC

36

MB89120/120A Series

■ EXAMPLE CHARACTERISTICS

(1) “L” Level Output Voltage

VOL vs. IOL

(2) “H” Level Output Voltage

VCC − VOH vs. IOH

VCC − VOH (V)

VOL (V)

VCC = 2.5 V

VCC = 2.2 V

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

TA = +25 °C

VCC = 2.2 V

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

VCC = 2.5 V

TA = +25 °C

VCC = 3.0 V

VCC = 4.0 V

VCC = 3.0 V

VCC = 5.0 V

VCC = 6.0 V

VCC = 4.0 V

VCC = 5.0 V

VCC = 6.0 V

0.0

−.5

−1.0 −1.5 −2.0 −2.5 −3.0

IOH (mA)

0

1

2

3

4

5

6

7

8

9

10

IOL (mA)

(3) “H” Level Input Voltage/“L” Level Input

Voltage (CMOS Input)

(4) “H” Level Input Voltage/“L” Level Input

Voltage (Hysteresis Input)

VIN vs. VCC

VIN (V)

5.0

VIN vs. VCC

V^IN(V)

5.0

TA = +25 °C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

TA = +25 °C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

VIHS

VILS

.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00

V^CC(V)

.00

1.00 2.00 3.00 4.00 5.00 6.00 7.00

VCC (V)

V^IHS: Threshold when input voltage in hysteresis

characteristics is set to “H” level

VILS : Threshold when input voltage in hysteresis

characteristics is set to “L” level

(5) Pull-up Resistance

RPULL vs. VCC

RPULL (kΩ)

1000

TA = +25 °C

300

100

50

10

0

2

3

4

5

6

7

1

VCC (V)

37

MB89120/120A Series

(6) Power Supply Current

ICC1 vs. VCC

ICCS1 vs. VCC

ICC (mA)

5.0

ICCS (mA)

3.0

Divide by 4

4.5

4.0

3.5

3.0

2.5

2.0

1.5

FCH = 4.0 MHz

TA = +25 °C

(ICC1)

Divide by 4 (ICCS1)

Divide by 64

FCH = 4.0 MHz

TA = +25 °C

2.5

2.0

1.5

1.0

0.5

0.0

Divide by 64

1.0

0.5

0.0

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

6.5

VCC (V)

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

6.5

VCC (V)

ICCLS vs. VCC

ICCL vs. VCC

ICCL (µA)

ICCLS (µA)

50

200

180

160

TA = +25 °C

45

40

35

30

25

20

15

140

120

100

80

60

40

10

5

20

0

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

6.5

VCC (V)

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

VCC (V)

ICCH vs. VCC

ICCT vs. VCC

ICCH (µA)

2.0

ICCT (µA)

30

TA = +25 °C

1.8

1.6

25

20

15

10

5

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

VCC (V)

6.5

VCC (V)

38

MB89120/120A Series

■ INSTRUCTIONS (136 INSTRUCTIONS)

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

#vct

#d8

#d16

dir: b

rel

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

Register indirect (Example: @A, @IX, @EP)

@

A

AH

AL

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

Lower 8 bits of accumulator A (8 bits)

T

TH

TL

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

IX

EP

PC

SP

PS

dr

CCR

RP

Ri

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

Register bank pointer RP (5 bits)

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

( × )

(( × ))

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

Columns indicate the following:

Mnemonic: Assembler notation of an instruction

~:

#:

The number of instructions

The number of bytes

Operation: Operation of an instruction

TL, TH, AH:

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH prior to the instruction executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

39

MB89120/120A Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)

(A) ← (EP)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

–

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(EP) ← d16

(IX) ← (A)

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

AL

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

–

F0

Note: During byte transfer to A, T ← A is restricted to low bytes.

Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

40

MB89120/120A Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 to DF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

C

A

←

C

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

(A) − (Ri)

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

41

MB89120/120A Series

(Continued)

Mnemonic

~

#

Operation

(A) ← (AL) ( (EP) )

TL

TH AH NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

42

MB89120/120A Series

■ INSTRUCTION MAP

43

MB89120/120A Series

■ MASK OPTIONS

MB89121

MB89123A

MB89125A

MB89P131

MB89P133A

Part number

MB89P135A

MB89PV130A

No.

Specify when ordering

masking

Set with EPROM Specification

Specifying procedure

programmer

impossible

Pull-up resistors

Selectable by pin

All pins fixed to

1

2

• P00 to P07, P10 to P17,

• P30 to P37, P40 to P43

Selectable by pin (P40 to P43 must be set to without no pull-up resis-

a pull-up resistor.)

tor optional

Power-on reset

Power-on reset provided

No power-on reset

With power-on

reset

Selectable

Selection of oscillation stabiliza-

tion wait time

• The oscillation stabilization wait

time initial value is selectable

from 4 types given below.

0 : Oscillation stabilization 2²/FCH

1 : Oscillation stabilization 2¹²/FCH

2 : Oscillation stabilization 2¹⁶/FCH

3 : Oscillation stabilization 2¹⁸/FCH

Oscillation sta-

bilization

2¹⁸/FCH

3

Selectable

Reset pin output

• Reset output provided

• No reset output

With reset out-

put

4

5

6

Selectable

Clock mode selection

• Single-clock mode

• Dual-clock mode

Dual-clock

mode

Selectable

Main clock oscillation circuit type

• External clock input

Not required*¹

• Oscillation resonator

Peripheral control clock

output function*²

• Not used

7

Selectable

Not required*³

• Used

*1 : Both external clock and oscillation resonator is usable on the one-time product.

*2 : “Used” must be selected when P33 (39 pin) is used as SCO for the peripheral control clock output.

*3 : The peripheral control clock function can be used only by software.

44

MB89120/120A Series

■ MB89P131/P133A STANDARD OPTIONS

No.

1

Product option

Pull-up resistor

MB89P131-101

MB89P133A-201

Not provided for any port

Provided

Not provided for any port

Provided

2

Power-on reset

Selection of oscillation stabilization

time

3

2 : Oscillation stabilization 2¹⁶/FCH 2 : Oscillation stabilization 2¹⁶/FCH

4

5

Reset pin output

Provided

Clock mode selection

Dual-clock mode

■ ORDERING INFORMATION

Part number

Package

Remarks

MB89121PFM

MB89123APFM

MB89125APFM

48-pin Plastic QFP

(FPT-48P-M13)

MB89P131PFM-101

MB89P133APFM-201

MB89P135APFM

48-pin Ceramic MQFP

(MQP-48C-P01)

MB89PV130ACF-ES

45

MB89120/120A Series

■ PACKAGE DIMENSION

48-pin Plastic QFP

(FPT-48P-M13)

13.10±0.40 SQ

(.516±.016)

2.35(.093)MAX

(Mounting height)

10.00±0.20 SQ

(.394±.008)

0(0)MIN

(STAND OFF)

36

25

Details of "A" part

37

24

0.15(.006)

0.20(.008)

8.80

(.346)

REF

11.50±0.30

(.453±.012)

INDEX

"A"

0.18(.007)MAX

0.53(.021)MAX

48

13

Details of "B" part

1

12

LEAD No.

0.80(.0315)TYP

0.15±0.05

(.006±.002)

0.30±0.10

(.012±.004)

M

0.16(.006)

0~10°

"B"

0.80±0.30

(.031±.012)

0.10(.004)

C

1994 FUJITSU LIMITED F48023S-1C-1

Dimensions in mm (inches)

46

MB89120/120A Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3347

Fax: +81-3-5322-3386

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

http://www.fujitsu.co.jp/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The contents of this document may not be reproduced or copied

without the permission of FUJITSU LIMITED.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

FUJITSU semiconductor devices are intended for use in standard

applications (computers, office automation and other office

equipments, industrial, communications, and measurement

equipments, personal or household devices, etc.).

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

CAUTION:

Europe

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or

where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters,

vehicle operating controls, medical devices for life support, etc.)

are requested to consult with FUJITSU sales representatives before

such use. The company will not be responsible for damages arising

from such use without prior approval.

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

http://www.fmap.com.sg/

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0008

FUJITSU LIMITED Printed in Japan


型号：	MB89123
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器
文件：	总47页 (文件大小：551K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89123 [FUJITSU]

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