MB89628RPF_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12517-2E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89628R/629R/P629

MB89628R/629R/P629

■ DESCRIPTION

The MB89628R/629R/P629 have been developed as a general-purpose version of the F²MC*-8L family

consisting of proprietary 8-bit, single-chip microcontrollers.

In addition to the F²MC-8L CPU core which can operate at low voltage but at high speed, the microcontrollers

contain a variety of peripheral functions such as timers, serial interfaces, an A/D converter, and an external

interrupt.

The MB89628R/629R/P629 are applicable to a wide range of applications from welfare to industrial equipment,

including portable devices.

*: F²MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

• Large-size RAM

MB89P629: 4 Kbytes

MB89628R: 3 Kbytes

MB89629R: 3 Kbytes

• High-speed processing at low voltage

Minimum execution time: 0.4 µs/3.5 V, 0.8 µs/2.7 V

• F²MC-8L family CPU core

Multiplication and division instructions

16-bit arithmetic operations

Test and branch instructions

Instruction set optimized for controllers

(Continued)

Bit manipulation instructions, etc.

■ PACKAGE

64-pin Plastic SH-DIP

64-pin Plastic QFP

(DIP-64P-M01)

(FPT-64P-M06)

MB89628R/629R/P629

(Continued)

• Four types of timers

8-bit PWM timer (also usable as a reload timer)

8-bit pulse width count timer (Continuous measurement capable, applicable to remote control, etc.)

16-bit timer/counter

20-bit time-base timer

• Two serial interfaces

Swichable the transfer direction allows communication with various equipment.

• 8-bit A/D converter

Sense mode function enabling comparison at 5 µs

Activation by an external input capable

• External interrupt: 4 channels

Four channels are independent and capable of wake-up from low-power consumption modes (with an edge

detection function).

• Low-power consumption modes

Stop mode (Oscillation stops to reduce the current consumption.)

Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)

2

MB89628R/629R/P629

■ PRODUCT LINEUP

Part number

Parameter

MB89PV620^*1

MB89628R

MB89629R

MB89P629

One-time PROM

Piggyback/evaluation

Classification

Mass production products

(mask ROM products)

product for evaluation and product for evaluation and

development development

32 K × 8 bits

ROM size

(internal PROM, programming

with general-purpose EPROM

programmer)

32 K × 8 bits

(external ROM)

24 K × 8 bits

(internal mask ROM)

32 K × 8 bits

(internal mask ROM)

RAM size

3072 × 8 bits

4096 × 8 bits

1 K × 8 bits

CPU functions

Number of instructions:

Instruction bit length:

Instruction length:

Data bit length:

Minimum execution time:

Interrupt processing time:

136

8 bits

1 to 3 bytes

1, 8, 16 bits

0.4 µs/10 MHz

3.6 µs/10 MHz

Ports

Input ports:

5 (4 ports also serve as peripherals.)

8 (All also serve as peripherals.)

8 (4 ports also serve as peripherals.)

8

24

53

Output ports (N-ch open-drain):

I/O ports (N-ch open-drain):

Output ports (CMOS):

I/O ports (CMOS):

Total:

8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to 3.3 ms)

8-bit PWM timer

8-bit resolution PWM operation (conversion cycle: 102 µs to 839 ms)

8-bit pulse width count

timer

8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 µs)

8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 µs)

8-bit pulse width measurement operation (Continuous measurement “H” pulse width/“L”

pulse width/from ↑ to ↑/from ↓ to ↓ capable)

16-bit timer/counter

16-bit timer operation (operating clock cycle: 0.4 µs)

16-bit event counter operation (Rising/falling/both edges selectability)

8-bit serial I/O 1,

8-bit serial I/O 2

8-bits

LSB first/MSB first transfer selectability

One clock selectable from four transfer clocks

(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)

8-bit A/D converter

External interrupt

8-bit resolution × 8 channels

A/D conversion mode (conversion time: 18 µs)

Sense mode (conversion time: 5 µs)

Continuous activation by an external activation or an internal timer capable

Reference voltage input

4 independent channels (edge selection, interrupt vector, source flag)

Rising edge/falling edge selectability

Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)

Standby modes

Process

Sleep mode, stop mode

CMOS

Operating voltage^*2

2.2 V to 6.0 V

2.7 V to 6.0 V

MBM27C256A-20

EPROM for use

*1: The piggyback/evaluation product is applicable to the MB89620 series.

*2: Varies with conditions such as the operating frequency. (See section “■Electrical Characteristics.”) In the case

of the MB89PV620, the voltage varies with the restrictions of the EPROM for use.

3

MB89628R/629R/P629

■ PACKAGE AND CORRESPONDING PRODUCTS

MB89628R

MB89629R

MB89P629

Package

MB89PV620

DIP-64P-M01

FPT-64P-M06

MDP-64C-P02

MQP-64C-P01

×

: Available

× : Not available

Note: For more information about each package, see section “■ Package Dimensions.”

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the piggyback product, verify its differences from the product that will actually be used.

Take particular care on the following points:

• On the MB89P629, the program area starts from address 8007^Hbut on the MB89PV620, MB89628R, and

MB89629R starts from 8000^H. (On the MB89P629, addresses 8000H to 8006H comprise the option setting

area, option settings can be read by reading these addresses. On the MB89PV620, MB89628R, and

MB89629R, addresses 8000^Hto 8006H could also be used as a program ROM. However, do not use these

addresses in order to maintain compatibility of the MB89P629.)

2. Current Consumption

• In the case of the MB89PV620, add the current consumed by the EPROM which is connected to the top socket.

• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume

more current than the product with a mask ROM.

However, the current consumption in sleep/stop modes is the same. (For more information, see section

“■ Electrical Characteristics”.)

3. Mask Options

Functions that can be selected as options and how to designate these options vary by the product.

Before using options check section “■ Mask Options.”

Take particular care on the following points:

• A pull-up resistor cannot be set for P40 to P47 on the MB89P629.

• A pull-up resistor is not selected for P50 to P57 when the A/D converter is used.

• Options are fixed on the MB89PV620.

4

MB89628R/629R/P629

■ PIN ASSIGNMENT

(Top view)

1

VCC

P36/WTO

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

2

P35/PWC

P34/EC

P33/SI1

P32/SO1

P31/SCK1

P30/ADST/CLKO

V^SS

P37/PTO

P40

3

4

P41

5

P42

6

P43

7

P44/BZ

P45/SCK2

P46/SO2

P47/SI2

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AV^CC

8

9

P00

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

AVR

AV^SS

P14

P15

P60/INT0

P61/INT1

P62/INT2

P63/INT3

P64

P16

P17

P20

P21

P22

RST

P23

MOD0

MOD1

X0

P24

P25

P26

X1

V^SS

P27

(DIP-64P-M01)

(Top view)

P45/SCK2

P46/SO2

P47/SI2

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AV^CC

1

2

3

4

5

6

7

8

51

P30/ADST/CLKO

V^SS

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

9

10

11

12

13

14

15

16

17

18

19

AVR

AV^SS

P60/INT0

P61/INT1

P62/INT2

P63/INT3

P64

P17

P20

(FPT-64P-M06)

5

MB89628R/629R/P629

■ PIN DESCRIPTION

Pin no.

Circuit

Pin name

type

Function

SH-DIP^*1

QFP^*2

23

30

31

28

29

27

X0

A

B

C

Cystal oscillator pins

24

X1

21

MOD0

MOD1

RST

Operating mode selection pins

Connect directly to V^CCor VSS.

22

20

Reset I/O pin

This pin is an N-ch open-drain output type with a pull-up

resistor, and a hysteresis input type. “L” is output from this

pin by an internal reset source. The internal circuit is

initialized by the input of “L”.

56 to 49

48 to 41

49 to 42

41 to 34

P00 to P07

P10 to P17

D

F

General-purpose I/O ports

40,

39

33,

32

P20,

P21

General-purpose output-only ports

38,

37

31,

30

P22,

P23

D

36 to 33

58

29 to 26

51

P24 to P27

F

E

P30/ADST/

CLKO

General-purpose I/O port

Also serves as an A/D converter external activation and an

oscillation monitor clock output. This port is a hysteresis

input type.

59

60

61

62

63

1

52

53

54

55

56

58

P31/SCK1

P32/SO1

P33/SI1

E

General-purpose I/O port

Also serves as the clock I/O for the 8-bit serial I/O 1.

This port is a hysteresis input type.

General-purpose I/O port

Also serves as the data output for the 8-bit serial I/O 1. This

port is a hysteresis input type.

General-purpose I/O port

Also serves as the data input for the 8-bit serial I/O 1. This

port is a hysteresis input type.

P34/EC

General-purpose I/O port

Also serves as the external clock input for the 16-bit timer/

counter. This port is a hysteresis input type.

P35/PWC

P36/WTO

General-purpose I/O port

Also serves as the measured pulse input for the 8-bit pulse

width count timer. This port is a hysteresis input type.

General-purpose I/O port

Also serves as the toggle output for the 8-bit pulse width

count timer. This port is a hysteresis input type.

(Continued)

*1: DIP-64P-M01

*2: FPT-64P-M06

6

MB89628R/629R/P629

(Continued)

Pin no.

Circuit

type

Pin name

Function

SH-DIP^*1

QFP^*2

2

59

P37/PTO

E

General-purpose I/O port

Also serves as the toggle output for the 8-bit PWM timer.

This port is a hysteresis input type.

3 to 6

7

60 to 63 P40 to P43

G

N-ch open-drain I/O ports

These ports are a hysteresis input type.

64

P44/BZ

N-ch open-drain I/O port

Also serves as a buzzer output. This port is a hysteresis

input type.

8

9

1

P45/SCK2

P46/SO2

P47/SI2

G

N-ch open-drain I/O port

Also serves as the clock I/O for the 8-bit serial I/O 2. This

port is a hysteresis input type.

2

3

N-ch open-drain I/O port

Also serves as the data output for the 8-bit serial I/O 2. This

port is a hysteresis input type.

10

N-ch open-drain I/O port

Also serves as the data input for the 8-bit serial I/O 2. This

port is a hysteresis input type.

11 to 18

22 to 25

4 to 11

P50/AN0 to

P57/AN7

H

I

N-ch open-drain output-only port

Also serves as the analog input for the A/D converter.

15 to 18 P60/INT0 to

P63/INT2

General-purpose input-only ports

Also serve as an external interrupt input. These ports are a

hysteresis input type.

26

64

19

57

P64

I

General-purpose input-only port

This port is a hysteresis input type.

V^CC

V^SS

—

Power supply pin

32,

57

25,

50

Power supply (GND) pins

19

20

21

12

13

14

AVCC

AVR

AV^SS

—

A/D converter power supply pin

A/D converter reference voltage input pin

A/D converter power supply (GND) pin.

Use this pin at the same voltage as VSS.

*1: DIP-64P-M01

*2: FPT-64P-M06

7

MB89628R/629R/P629

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• At an oscillation feedback resistor of approximately

1 MΩ/5.0 V

X1

X0

Standby control signal

B

C

• At an output pull-up resistor (P-ch) of approximately

50 MΩ/5.0 V

R

• CMOS hysteresis input

P-ch

N-ch

D

E

F

• CMOS output

• CMOS input

R

P-ch

N-ch

• Pull-up resistor optional (except P22 and P23)

• CMOS output

• Hysteresis input

R

P-ch

N-ch

• Pull-up resistor optional

• CMOS output

P-ch

N-ch

(Continued)

8

MB89628R/629R/P629

(Continued)

Type

Circuit

P-ch

Remarks

G

• N-ch open-drain output

• Hysteresis input

R

P-ch

N-ch

• Pull-up resistor optional

(MB89628R and MB89629R only)

H

• N-ch open-drain output

• Analog input

R

P-ch

N-ch

Analog input

I

• Hysteresis input

R

• Pull-up resistor optional

9

MB89628R/629R/P629

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prevent the analog power supply (AV^CCand AVR) and analog input from exceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore

important. As stabilization guidelines, it is recommended to control power so that V^CCripple fluctuations (P-P

value) will be less than 10% of the standard V^CCvalue at the commercial frequency (50 to 60 Hz) and the transient

fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.

6. Precautions when Using an External Clock

Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and

wake-up from stop mode.

10

MB89628R/629R/P629

■ PROGRAMMING TO THE EPROM ON THE MB89P629

The MB89P629 is an OTPROM version of the MB89628R and MB89629R.

1. Features

• 16-Kbyte PROM on chip

• Options can be set using the EPROM programmer.

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in EPROM mode, option area is diagrammed below.

Single chip

I/O

EPROM mode

(Corresponding addresses on the EPROM programmer)

Address

0000H

0080^H

0100H

Register

RAM

0200H

1080^H

Not available

Option area

8000H

0000H

Option area

8007H

0007^H

Program area

(EPROM)

32 KB

PROM

32 KB

FFFFH

7FFF^H

3. Programming to the EPROM

In EPROM mode, the MB89P629 functions equivalent to the MBM27C256A. This allows the PROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter.

• Programming procedure

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0000^Hto 7FFFH (note that addresses 8000H to FFFFH

while operating as a single chip assign to 0000H to 7FFFH in EPROM mode. For information about each

corresponding option, see “7. Setting OTPROM Options.”)

(3) Program to 0000H to 7FFFH with the EPROM programmer.

11

MB89628R/629R/P629

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM microcomputer program.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

5. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

6. EPROM Programmer Socket Adapter

Package

Compatible socket adapter

ROM-64SD-28DP-8L

DIP-64P-M01

FPT-64P-M06

ROM-64QF-28DP-8L

Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760

12

MB89628R/629R/P629

7. Setting OTPROM Options

The programming procedure is the same as that for the PROM. Options can be set by programming values at

the addresses shown on the memory map. The relationship between bits and options is shown on the following

bit map:

• OTPROM option bit map

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Oscillation

stabilization time

Readable and Readable and Readable and 1: Crystal

Vacancy

Reset pin Power-on

8000^H

(0000H)

output

1: Yes

2: No

reset

1: Yes

0: No

Readable and Readable and

writable

0: Ceramic

writable

P07

P06

P05

P04

P03

P02

P01

P00

8001H Pull-up

(0001H) 1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P17

8002^HPull-up

(0002H) 1: No

0: Yes

P16

P15

P14

P13

P12

P11

P10

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P37

8003^HPull-up

(0003H) 1: No

0: Yes

P36

P35

P34

P33

P32

P31

P30

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P57

8004^HPull-up

(0004H) 1: No

0: Yes

P56

P55

P54

P53

P52

P51

P50

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Vacancy

P64

P63

P62

P61

P60

8005^H

(0005H)

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Readable and Readable and Readable and

writable

Vacancy

Reserved bit

8006H

(0006H)

Readable and Readable and Readable and Readable and Readable and Readable and Readable and Readable and

writable

Notes: • Set each bit to 1 to erase.

• Do not write 0 to the vacant bit.

The read value of the vacant bit is 1, unless 0 is written to it.

• Always write 0 to the reserved bit.

13

MB89628R/629R/P629

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TV, MBM27C256A-20CZ

2. Programming Socket Adapter

To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato

Co., Ltd.) listed below.

Package

Adapter socket part number

LCC-32 (Rectangle)

ROM-32LC-28DP-YG

Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760

3. Memory Space

Memory space in 32-Kbyte PROM on the EPROM programmer is diagrammed below.

Single chip

I/O

Address

0000H

Corresponding addresses on the EPROM programmer

0080H

RAM

0480H

8000H

Not available

0000H

Not available

0007H

8007H

EPROM

32 KB

PROM

32 KB

FFFFH

7FFFH

4. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0007^Hto 7FFFH.

(3) Program to 0000H to 7FFFH with the EPROM programmer.

14

MB89628R/629R/P629

■ BLOCK DIAGRAM

X0

X1

20-bit time-base timer

Oscillator

Clock controller

8-bit PWM timer

P37/PTO

Reset circuit

(WDT)

RST

P36/WTO

P35/PWC

8-bit pulse width

count timer

CMOS I/O port

8

P34/EC

16-bit timer/counter

8-bit serial I/O 1

P00 to P07

8

P33/SI1

P32/SO1

P31/SCK1

P10 to P17

MOD0

MOD1

External bus

interface

P30/ADST/CLKO

CMOS I/O port

8-bit serial I/O 2

Buzzer output

P47/SI2

P46/SO2

P45/SCK2

8

P20 to P27

CMOS output port

P44/BZ

4

P40 to P43

N-ch open-drain I/O port

N-ch open-drain output port

RAM

8

P50/AN0

to P57/AN7

F²MC-8L

CPU

8-bit A/D converter

AVR

AV^CC

AVSS

ROM

4

P60/INT0

to P63/INT3

External interrupt

P64

Input port

Other pins

VCC, VSS × 2

15

MB89628R/629R/P629

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89628R/629R/P629 offer a memory space of 64 Kbytes for storing all of I/O, data,

and program areas. The I/O area is located at the lowest address. The data area is provided immediately above

the I/O area. The data area can be divided into register, stack, and direct areas according to the application.

The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables

of interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89628R/629R/P629 is structured as illustrated below.

Memory Space

MB89629R

I/O

MB89P629

I/O

MB89PV620

I/O

MB89628R

I/O

0000^H

0080H

0000H

0080H

0100H

0000^H

0080H

0100H

0000H

0080H

RAM *¹

1 KB

RAM

3 KB

RAM

4 KB

RAM

3 KB

0100H

0200H

0100H

0200H

Register

0200H

0480H

0200H

0C80H

0C80^H

8000H

External area

1080^H

8000H

Not available

8000H

2

Not available

Option area

*

8007H

A000H

External ROM

32 KB

ROM

32 KB

ROM

32 KB

ROM

24 KB

FFFF^H

FFFFH

*1: The internal RAM of the MB89PV620 is 1 Kbyte. The RAM of a development tool can be substituted

for that RAM when the tool is connected. If the MB89PV620 is used as a piggyback product, however,

it runs out of RAM. Note, in addition, that some tools such as the MB2140 series cannot be used due

to mapping restrictions.

*2: Since addresses 8000^Hto 8006H for the MB89P629 comprise an option area, do not use this area for

the MB89PV620, MB89628R, and MB89629R.

16

MB89628R/629R/P629

3. Registers

The F²MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following dedicated registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit register for indicating instruction storage positions

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

Whenthe instructionisan8-bitdataprocessinginstruction,thelowerbyteisused.

Index register (IX):

Extra pointer (EP):

Stack pointer (SP):

Program status (PS):

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit register for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

Initial value

16 bits

PC

A

: Program counter

: Accumulator

FFFD^H

Undefined

T

: Temporary accumulator

: Index register

IX

EP

SP

PS

: Extra pointer

: Stack pointer

: Program status

I-flag = 0, IL1, 0 = 11

Other bits are undefined.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

PS

RP

Vacancy Vacancy Vacancy

H

IL1, 0

N

V

C

RP

CCR

17

MB89628R/629R/P629

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

Rule for Conversion of Actual Addresses of the General-purpose Register Area

RP

Lower OP codes

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0

when reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low = no interrupt

N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.

Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.

V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does

not occur.

C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.

Set to the shift-out value in the case of a shift instruction.

18

MB89628R/629R/P629

The following general-purpose registers are provided:

General-purpose registers: An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 32 banks can be used on the MB89628R and MB89629R. The bank currently

in use is indicated by the register bank pointer (RP).

Register Bank Configuration

This address = 0100H + 8 × (RP)

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

32 banks

Memory area

19

MB89628R/629R/P629

■ I/O MAP

Address

00^H

01^H

02^H

03H

04^H

05^H

06H

07^H

08H

09^H

0AH

0BH

0C^H

0DH

0EH

0F^H

10H

11^H

12H

13H

14^H

15H

16H

17^H

18^H

19H

1AH

1B^H

1CH

1DH

1E^H

1FH

Read/write

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

DDR0

Port 0 data direction register

Port 1 data register

(R/W)

(W)

PDR1

DDR1

Port 1 data direction register

Port 2 data register

(R/W)

PDR2

BCTR

External bus pin control register

Vacancy

(R/W)

STBC

WDTC

TBTC

Standby control register

Watchdog timer control register

Time-base timer control register

Vacancy

(R/W)

(W)

PDR3

DDR3

PDR4

BZCR

PDR5

PDR6

CNTR

COMR

PCR1

PCR2

RLBR

Port 3 data register

Port 3 data direction register

Port 4 data register

(R/W)

(R)

Buzzer register

Port 5 data register

Port 6 data register

(R/W)

(W)

PWM control register

PWM compare register

PWC pulse width control register 1

PWC pulse width control register 2

PWC reload buffer register

Vacancy

(R/W)

TMCR

TCHR

TCLR

16-bit timer control register

16-bit timer count register (H)

16-bit timer count register (L)

Vacancy

(R/W)

SMR1

SDR1

SMR2

SDR2

Serial I/O 1 mode register

Serial I/O 1 data register

Serial I/O 2 mode register

Serial I/O 2 data register

(Continued)

20

MB89628R/629R/P629

(Continued)

Address

Read/write

(R/W)

Register name

ADC1

Register description

A/D converter control register 1

A/D converter control register 2

A/D converter data register

Vacancy

20^H

21H

(R/W)

ADC2

22^H

(R/W)

ADCD

23^H

24H

(R/W)

EIC1

EIC2

CLKE

External interrupt control register 1

External interrupt control register 2

Clock output control register

Vacancy

25^H

26^H

27H to 7BH

7C^H

(W)

ILR1

ILR2

ILR3

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Vacancy

7DH

7E^H

7FH

Note: Do not use vacancies.

21

MB89628R/629R/P629

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

V^CC

AVCC

1

Power supply voltage

VSS – 0.3

V^SS– 0.3

VSS + 7.0

V

*

A/D converter reference input

voltage

AVR

VSS + 7.0

AVR must not exceed AVCC + 0.3 V.

V^I

VSS – 0.3

VCC + 0.3

VSS + 7.0

VCC + 0.3

VSS + 7.0

V

Except P40 to P47*²

P40 to P47

Input voltage

VI2

V^O

VO2

Except P40 to P47*²

P40 to P47

Output voltage

“L” level maximum output

current

I^OL

20

4

mA

Average value (operating

current × operating rate)

“L” level average output current

IOLAV

∑I^OL

∑I^OLAV

IOH

“L” level total maximum output

current

100

40

“L” level total average output

current

Average value (operating

current × operating rate)

“H” level maximum output

current

–20

–4

Average value (operating

current × operating rate)

“H” level average output current

I^OHAV

∑I^OH

∑I^OHAV

“H” level total maximum output

current

–50

–20

“H” level total average output

current

Average value (operating

current × operating rate)

Power consumption

Operating temperature

Storage temperature

P^D

300

+85

mW

°C

TA

–40

–55

Tstg

+150

°C

*1: Use AVCC and VCC set at the same voltage.

Take care so that AVCC does not exceed VCC, such as when power is turned on.

*2: VI and VO must not exceed VCC + 0.3 V.

Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.

Functional operation should be restricted to the conditions as detailed in the operational sections of

this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

22

MB89628R/629R/P629

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

Normal operation assurance range*

(MB89628R/629R)

2.2*

6.0*

V

V^CC

AVCC

Power supply voltage

Normal operation assurance range*

(MB89P629/PV620)

2.7*

1.5

6.0*

6.0

V

Retains the RAM state in stop mode

A/D converter reference input

voltage

AVR

T^A

0.0

AV^CC

+85

V

Operating temperature

–40

°C

* : These values vary with the operating frequency and analog assurance range. See Figure 1 and “5. A/D Converter

Electrical Characteristics.”

6

Analog accuracy

assured in the

5

AV^CC= VCC = 3.5 V to 6.0 V range

Operation assurance range

4

3

2

1

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

Clock operating frequency (at an instruction cycle of 4/Fc) (MHz)

4.0 2.0

0.8

0.4

Minimum execution time (instruction cycle) (µs)

Note:

The shaded area is assured only for the MB89628R/629R.

Figure 1 Operating Voltage vs. Clock Operating Frequency

Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/F^C.

23

MB89628R/629R/P629

3. DC Characteristics

(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Parameter

Condition

Unit

Remarks

Min.

Typ.

Max.

P00 to P07,

P10 to P17,

P22, P23

V^CC+ 0.3

V^IH

0.7 V^CC

V

“H” level input

voltage

RST, MOD0,

MOD1,

P30 to P37,

P60 to P64

V^CC+ 0.3

V^IHS

0.8 V^CC

V

V^SS+ 6.0

0.3 VCC

V^IHS2

V^IL

P40 to P47

0.8 VCC

V

P00 to P07,

P10 to P17,

P22, P23

V^SS− 0.3

“L” level input

voltage

RST, MOD0,

MOD1,

V^SS− 0.3

V^ILS

P30 to P37,

P40 to P47,

P60 to P64

—

0.2 VCC

V

V^SS− 0.3

V^SS+ 0.3

V^SS+ 6.0

Open-drain

output pin

application

voltage

V^D

P50 to P57

V

V^D2

P40 to P47

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37

“H” level output

voltage

V^OH

I^OH= –2.0 mA

I^OL= +4.0 mA

4.0

V

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

P40 to P47,

P50 to P57

V^OL

0.4

V

“L” level output

voltage

V^OL2

RST

—

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

P40 to P47,

P60 to P64,

MOD0, MOD1

Input leakage

current

(Hi-z output

leakage

Without pull-up

resistor

0.0 V < VI < VCC

I^LI1

±5

µA

kΩ

current)

P00 to P07,

P10 to P17,

P30 to P37,

P40 to P47,

P50 to P57,

P60 to P64,

RST

Pull-up

resistance

R^PULL

VI = 0.0 V

25

50

100

(Continued)

24

MB89628R/629R/P629

(Continued)

(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Parameter

Condition

Unit

Remarks

Min.

Typ.

Max.

FC = 10 MHz

Normal

operation

mode

(External clock)

MB89628R,

MB89629R

—

9

15

mA

I^CC

—

10

18

mA MB89P629

VCC

FC = 10 MHz

Sleep mode

(External clock)

I^CCS

—

3

4

1

mA

Stop mode

T^A= +25°C

I^CCH

—

µA

Power supply

current*

FC = 10 MHz,

when A/D

conversion

is activated

I^A

—

1

3

mA

AVCC

FC = 10 MHz,

TA = +25°C,

when A/D

I^AH

—

1

µA

conversion

is stopped

Other than

AVCC, AVSS,

VCC, and VSS

Input

capacitance

C^IN

f = 1 MHz

10

—

pF

* : In the case of the MB89PV620, the current consumed by the connected EPROM and ICE is not included.

The power supply current is measured at the external clock.

25

MB89628R/629R/P629

4. AC Characteristics

(1) Reset Timing

(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Min.

Max.

RST “L” pulse width

tZLZH

—

16 tXCYL

—

ns

Note: tXCYL is the oscillation cycle (1/FC) to input to the X0 pin.

tZLZH

RST

0.2 VCC

(2) Power-on Reset

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol Condition

Unit

Remarks

Parameter

Min.

—

Max.

Power supply rising time

Power supply cut-off time

t^R

50

—

ms

Power-on reset function only

Due to repeated operations

—

t^OFF

1

Note: Make sure that power supply rises within the selected oscillation stabilization time.

If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is

recommended.

tOFF

t^R

2.0 V

VCC

0.2 V

26

MB89628R/629R/P629

(3) Clock Timing

Parameter

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Min.

1

Max.

10

Clock frequency

Clock cycle time

F^C

X0, X1

MHz

ns

t^XCYL

100

1000

P^WH

PWL

—

Input clock pulse width

X0

20

—

ns

External clock

Input clock rising/falling

time

t^CR

tCF

10

X0 and X1 Timing and Conditions

tXCYL

PWH

PWL

tCR

tCF

0.8 VCC

X 0

0.2 VCC

Clock Conditions

When a crystal

or

ceramic resonator is used

When an external clock is used

X 0

X 1

X 0

X 1

Open

(4) Instruction Cycle

Parameter

Symbol

Value (typical)

Unit

Remarks

Instruction cycle

(minimum execution time)

t^inst= 0.4 µs when operating at

F^C= 10 MHz

t^inst

4/FC

µs

27

MB89628R/629R/P629

(5) Serial I/O Timing

(VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit Remarks

Parameter

Min.

Max.

Serial clock cycle time

t^SCYC

t^SLOV

t^IVSH

t^SHIX

SCK1, SCK2

2 t^inst*

—

µs

SCK1 ↓ → SO1 time

SCK2 ↓ → SO2 time

SCK1, SO1

SCK2, SO2

–200

200

—

ns

Internal shift

clock mode

Valid SI1 → SCK1 ↑

Valid SI2 → SCK2 ↑

SI1, SCK1

SI2, SCK2

1/2 t^inst*

µs

SCK1 ↑ → valid SI1 hold time

SCK2 ↑ → valid SI2 hold time

SCK1, SI1

SCK2, SI2

—

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

SCK1, SCK2

SCK1, SO1

1 tinst*

—

µs

tSLSH

SCK1 ↓ → SO1 time

SCK2 ↓ → SO2 time

t^SLOV

t^IVSH

t^SHIX

0

200

—

ns

µs

SCK2, SO2 External shift

clock mode

Valid SI1 → SCK1 ↑

Valid SI2 → SCK2 ↑

SI1, SCK1

SI2, SCK2

1/2 t^inst*

SCK1 ↑ → valid SI1 hold time

SCK2 ↑ → valid SI2 hold time

SCK1, SI1

SCK2, SI2

—

* : For information on tinst, see “(4) Instruction Cycle.”

28

MB89628R/629R/P629

Internal Shift Clock Mode

t^SCYC

2.4 V

SCK1

SCK2

0.8 V

tSLOV

2.4 V

0.8 V

SO1

SO2

tIVSH

0.8 VCC

0.2 VCC

tSHIX

0.8 VCC

0.2 VCC

SI1

SI2

External Shift Clock Mode

tSLSH

tSHSL

0.8 VCC

SCK1

SCK2

0.2 VCC

tSLOV

2.4 V

0.8 V

SO1

SO2

tIVSH

0.8 VCC

0.2 VCC

tSHIX

0.8 VCC

0.2 VCC

SI1

SI2

29

MB89628R/629R/P629

(6) Peripheral Input Timing

(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

PWC,

EC, INT0

to INT3

Condition

Unit Remarks

Parameter

Min. Max.

Peripheral input “H” pulse width 1

Peripheral input “L” pulse width 1

t^ILIH1

t^IHIL1

2 t^inst*

—

µs

—

2 tinst*

Peripheral input “H” pulse width 2

Peripheral input “L” pulse width 2

Peripheral input “H” pulse width 2

Peripheral input “L” pulse width 2

t^ILIH2

t^IHIL2

tILIH2

t^IHIL2

32 t^inst*

32 tinst*

8 t^inst*

—

µs

A/D mode

ADST

Sense mode

8 tinst*

* : For information on tinst, see “(4) Instruction Cycle.”

tIHIL1

tILIH1

0.8 VCC

PWC

EC

0.2 VCC

INT0 to INT3

tIHIL2

tILIH2

0.8 VCC

0.2 VCC

ADST

0.2 VCC

30

MB89628R/629R/P629

5. A/D Converter Electrical Characteristics

(AVCC = VCC = +3.5 V to +6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Remarks

Parameter

Resolution

Condition

Unit

Min.

—

Typ.

—

Max.

8

—

bit

Total error

—

±1.5

±1.0

±0.9

LSB

mV

—

Linearity error

—

Differential linearity error

Zero transition voltage

—

AVR = AVCC

AV^SS– 1.0 LSB AV^SS+ 0.5 LSB AV^SS+ 2.0 LSB

VOT

Full-scale transition

voltage

—

AVR – 3.0 LSB AVR – 1.5 LSB

V^FST

AVR

0.5

—

mV

LSB

µs

Interchannel disparity

—

A/D mode conversion

time

44 t^inst*

—

Sense mode conversion

time

—

12 tinst*

—

µs

—

Analog port input current

Analog input voltage

Reference voltage

IAIN

—

10

µA

V

AN0 to

AN7

0.0

AVR

AV^CC

V

AVR = 5.0 V,

when A/D

conversion

activated

I^R

—

100

—

µA

AVR

Reference voltage

supply current

AVR = 5.0 V,

when A/D

conversion

stopped

I^RH

1

* : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

(1) A/D Glossary

• Resolution

Analog changes that are identifiable with the A/D converter.

When the number of bits is 8, analog voltage can be divided into 2⁸= 256.

• Linearity error (unit: LSB)

The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the

full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics

• Differential linearity error (unit: LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error (unit: LSB)

The difference between theoretical and actual conversion values

31

MB89628R/629R/P629

Digital output

Theoretical conversion value

Actual conversion value

1111 1111

1111 1110

(1 LSB × N + V^OT)

AVR

256

1 LSB =

Linearity error =

VNT – (1 LSB × N + VOT)

1 LSB

V( N + 1 ) T – VNT

– 1

Differential linearity error =

Total error =

1 LSB

VNT – (1 LSB × N + 1 LSB)

1 LSB

0000 0010

0000 0001

0000 0000

VOT

VNT

V (N + 1)T

VFST

Analog input

(2) Precautions

• Input impedance of the analog input pins

The A/D converter contains a sample hold circuit as illustrated below to fetch analog input voltage into the

sample hold capacitor for eight instruction cycles after activating A/D conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output

impedance of the external circuit low (below 10 kΩ).

Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about

0.1 µF for the analog input pin.

Analog Input Equivalent Circuit

Sample hold circuit

C = 33 pF

Analog input pin

Comparator

If the analog input

impedance is

R = 6 kΩ

higher than 10 kΩ,

it is recommended

to connect an

external capacitor

of approx. 0.1 µF.

.

Close for 8 instruction cycles

.

after activating A/D conversion.

Analog channel selector

• Error

The smaller the | AVR – AV^SS|, the greater the error would become relatively.

32

MB89628R/629R/P629

■ INSTRUCTIONS

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

#vct

#d8

#d16

dir: b

rel

@

Register indirect (Example: @A, @IX, @EP)

A

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

AH

AL

Lower 8 bits of accumulator A (8 bits)

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the

instruction in use.)

T

TH

TL

IX

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

(Continued)

33

MB89628R/629R/P629

(Continued)

Symbol

Meaning

EP

PC

SP

PS

dr

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

Register bank pointer RP (5 bits)

CCR

RP

Ri

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × )

(( × ))

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

Columns indicate the following:

Mnemonic:

~:

Assembler notation of an instruction

Number of instructions

Number of bytes

#:

Operation:

TL, TH, AH:

Operation of an instruction

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH immediately before the instruction

is executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

34

MB89628R/629R/P629

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

–

AL

–

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

–

F0

Notes: • During byte transfer to A, T ← A is restricted to low bytes.

• Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

35

MB89628R/629R/P629

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 to DF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

A

C

←

C ← A

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

(A) − (Ri)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

36

MB89628R/629R/P629

(Continued)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

37

MB89628R/629R/P629

■ INSTRUCTION MAP

38

MB89628R/629R/P629

■ MASK OPTIONS

MB89628R/

MB89629R

Model

Specifying procedure

Pull-up resistors

MB89P629

MB89PV620

No.

Specify when

orderingmasking

Set with EPROM

programmer

Setting not

possible

Selectable per pin. Can be set per pin.

(P50 to P57 must be set (P40 to P47 are

P00 to P07, P10 to P17,

P30 to P37, P40 to P47,

P50 to P57, P60 to P64

Fixed to without

pull-up resistor

to without a pull-up

resistor when an A/D

converter is used.)

available only for

without a pull-up

resistor.)

1

Power-on reset

Fixed to with

power-on reset

2

3

4

With power-on reset

Without power-on reset

Selectable

Setting possible

Oscillation stabilization time selection

Fixed to crystal

Crystal oscillator: (2¹⁸/F^C) (26.2 ms/10 MHz)

oscillator of 2¹⁸/FC

Ceramic oscillator: (2¹⁴/F^C) (1.64 ms/10 MHz)

Reset pin output

With reset output

Without reset output

Fixed to with reset

output

■ ORDERING INFORMATION

Part number

Package

Remarks

MB89628RP-SH

MB89629RP-SH

MB89P629P-SH

64-pin Plastic SH-DIP

(DIP-64P-M01)

MB89628RPF

MB89629RPF

MB89P629PF

64-pin Plastic QFP

(FPT-64P-M06)

64-pin Ceramic MDIP

(MDP-64C-P02)

MB89PV620C-SH

MB89PV620CF

64-pin Ceramic MQFP

(MQP-64C-P01)

39

MB89628R/629R/P629

■ PACKAGE DIMENSIONS

64-pin Plastic SH-DIP

(DIP-64P-M01)

58.00⁺^–0⁰^.^.⁵²⁵²

+.008

2.283–.022

INDEX-1

INDEX-2

17.00±0.25

(.669±.010)

5.65(.222)MAX

3.00(.118)MIN

0.25±0.05

(.010±.002)

+0.50

1.00^–0

0.45±0.10

(.018±.004)

0.51(.020)MIN

19.05(.750)

TYP

+.020

15°MAX

.039^–0

1.778±0.18

(.070±.007)

1.778(.070)

MAX

55.118(2.170)REF

C

1994 FUJITSU LIMITED D64001S-3C-4

Dimensions in mm (inches)

40

MB89628R/629R/P629

64-pin Plastic QFP

(FPT-64P-M06)

24.70±0.40(.972±.016)

20.00±0.20(.787±.008)

3.35(.132)MAX

51

33

0.05(.002)MIN

(STAND OFF)

52

32

14.00±0.20 18.70±0.40

(.551±.008) (.736±.016)

12.00(.472)

REF

16.30±0.40

(.642±.016)

INDEX

64

20

"A"

1

19

LEAD No.

0.15±0.05(.006±.002)

Details of "B" part

1.00(.0394)

TYP

0.40±0.10

(.016±.004)

M

0.20(.008)

Details of "A" part

0.25(.010)

"B"

0.30(.012)

0.18(.007)MAX

0.63(.025)MAX

0.10(.004)

18.00(.709)REF

22.30±0.40(.878±.016)

0

10°

1.20±0.20

(.047±.008)

C

1994 FUJITSU LIMITED F64013S-3C-2

Dimensions in mm (inches)

41

MB89628R/629R/P629

64-pin Ceramic MDIP

(MDP-64C-P02)

0°~9°

56.90±0.64

(2.240±.025)

15.24(.600)

TYP

18.75±0.30

(.738±.012)

19.05±0.30

(.750±.012)

INDEX AREA

2.54±0.25

(.100±.010)

0.25±0.05

(.010±.002)

33.02(1.300)REF

1.27±0.25

(.050±.010)

10.16(.400)MAX

+0.13

3.43±0.38

(.135±.015)

1.778±0.25

(.070±.010)

0.46^–0.08

0.90±0.13

(.035±.005)

.018⁺^–.^.⁰⁰⁰⁰³⁵

55.12(2.170)REF

C

1994 FUJITSU LIMITED M64002SC-1-4

Dimensions in mm (inches)

42

MB89628R/629R/P629

64-pin Ceramic MQFP

(MQP-64C-P01)

18.70(.736)TYP

16.30±0.33

(.642±.013)

15.58±0.20

(.613±.008)

12.00(.472)TYP

1.00±0.25

INDEX AREA

1.20⁺^–0⁰^.^.²⁴⁰⁰

(.039±.010)

.047 ⁺^–.^.⁰⁰⁰¹⁸⁶

1.00±0.25

(.039±.010)

1.27±0.13

(.050±.005)

18.12±0.20

(.713±.008)

22.30±0.33

(.878±.013)

12.02(.473)

TYP

18.00(.709)

TYP

10.16(.400)

14.22(.560)

TYP

0.30(.012)

TYP

24.70(.972)

TYP

0.40±0.10

(.016±.004)

1.27±0.13

(.050±.005)

0.30(.012)TYP

7.62(.300)TYP

9.48(.373)TYP

11.68(.460)TYP

0.40±0.10

(.016±.004)

1.20^–⁺⁰⁰^.^.²⁴⁰⁰

.047^–⁺^.^.⁰⁰⁰¹⁸⁶

10.82(.426)

MAX

0.15±0.05

(.006±.002)

0.50(.020)TYP

C

1994 FUJITSU LIMITED M64004SC-1-3

Dimensions in mm (inches)

43

MB89628R/629R/P629

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 1015, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211, Japan

Tel: (044) 754-3753

Fax: (044) 754-3329

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, U.S.A.

Tel: (408) 922-9000

Fax: (408) 432-9044/9045

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

63303 Dreieich-Buchschlag

Germany

Circuit diagrams utilizing Fujitsu products are included as a

means of illustrating typical semiconductor applications. Com-

plete information sufficient for construction purposes is not nec-

essarily given.

Tel: (06103) 690-0

Fax: (06103) 690-122

The information contained in this document has been carefully

checked and is believed to be reliable. However, Fujitsu as-

sumes no responsibility for inaccuracies.

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LIMITED

No. 51 Bras Basah Road,

Plaza By The Park,

The information contained in this document does not convey any

license under the copyrights, patent rights or trademarks claimed

and owned by Fujitsu.

#06-04 to #06-07

Singapore 189554

Tel: 336-1600

Fujitsu reserves the right to change products or specifications

without notice.

Fax: 336-1609

No part of this publication may be copied or reproduced in any

form or by any means, or transferred to any third party without

prior written consent of Fujitsu.

The information contained in this document are not intended for

use with equipments which require extremely high reliability

such as aerospace equipments, undersea repeaters, nuclear con-

trol systems or medical equipments for life support.

F9606

FUJITSU LIMITED Printed in Japan

44


型号：	MB89628RPF
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器
文件：	总44页 (文件大小：583K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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