MB89P945PF_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12536-2E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89940 Series

MB89943/P945/PV940

■ OUTLINE

The MB89940 series is specially designed for automotive instrumentation applications. It features a combination

of two PWM pulse generators and four high-drive-current outputs for controlling a stepping motor. It also contains

two analog inputs, two PWM pulse generators and 10-digit LCD controller/driver for various sensor/indicator

devices. The MB89940 series is manufactured with high performance CMOS technologies and packaged in a

48-pin QFP.

■ FEATURES

• 8-bit core CPU; 4 MHz system clock (8 MHz external, 500 ns instruction cycle)

• 21-bit watchdog timer

• Clock generator/controller

• 16-bit interval timer

• Two PWM pulse generators with four high-drive-current outputs

• Two-channel 8-bit A/D converter

• Three external interrupt

• Low supply voltage reset

• External voltage monitor interrupt

• Two more PWM pulse generators for controlling indicator devices

• 4-common 17-segment LCD driver/controller

• Package; 48-pin plastic QFP, 48-pin ceramic MQFP

(Continued)

■ PACKAGE

48-pin Plastic QFP

48-pin Ceramic MQFP

(MQP-48C-P01)

(FPT-48P-M16)

MB89940 Series

(Continued)

• 5.0 V single power supply (VPP required for MB89P945)

• 0.8 µm CMOS technology (MB89PV940 and MB89P945)

• 0.5 µm CMOS technology (MB89943)

• On-chip voltage regulator for internal 3.0 V power supply (MB89943)

■ PRODUCT LINEUP

Part number

MB89943

MB89P945

MB89PV940

Item

Classification

Mass-produced products

(mask ROM products)

One-time PROM

Piggyback

ROM size

8 K × 8 bits

(internal mask ROM)

16 K × 8 bits

(internal PROM)

32 K × 8 bits

(external on piggyback)

RAM size

512 × 8 bits

The number of instructions: 136

1 K × 8 bits

CPU functions

Instruction cycle:

0.5 µs*¹@8 MHz

Interrupt response time:

Multiply instruction time:

Divide instruction time:

4.0 µs*¹@8 MHz

19 instruction cycles

21 instruction cycles

Direct addressing memory-to/from-register data transfer:

7 instruction cycles

Ports

Output:

Input/Output:

5-bit N-ch open-drain

Two 8-bit CMOS schmitt I/Os and 8-bit CMOS I/Os

Timebase timer

8-bit/16-bit timer

Watchdog Reset

21 bits

Interrupt interval: 1 ms, 4.1 ms, 32.8 ms or 524.3 ms

Can be used as two 8-bit timers or one 16-bit timer

Operation clock: 1 µs, 16 µs, 256 µs or external *¹

Reset interval: Approx. 524 ms to 1049 ms

Stepping motor

controller

Two 8-bit PWM pulse generators

Synchronized 4-channel high current output

Operation clock: 250 ns, 500 ns, 1 µs or 4 µs*¹

8-bit PWM timers

External interrupt

A/D converter

Two 8-bit PWM timers

3 channels, selective positive edge or negative edge trigger

8-bit resolution, two-channel input

Conversion time: 44 instruction cycles for A/D conversion, 12 instruction cycles

for sense mode operation

LCD controller

4-common and 17-segment outputs

Number of outputs programmable

Low supply voltage

reset

Autonomous reset when low supply voltage

Reset voltage: 3.3 V, 3.6 V, 4.0 V

External voltage

monitor interrupt

Interrupts when voltage at external pin is lower than the reference voltage

Standby modes

Stop mode and sleep mode

3.5 V to 5.5 V

Operating

voltage*²

(Continued)

2

MB89940 Series

(Continued)

Part number

MB89943

MB89P945

MB89PV940

Item

Process

CMOS

External EPROM

MBM27C256A-20TVM

*1: Execution times and clock cycle times are dependent on the use of MCU.

*2: Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”) In the case

of the MB89PV940, the voltage varies with the vestrictions of the EPROM for use.

■ PACKAGE AND CORRESPONDING PRODUCTS

MB89943

MB89P945

Package

MB89PV940

FPT-48P-M16

MQP-48C-P01

×

: Available

× : Not available

Note: For more information about each package, see section “■ Package Dimensions.”

3

MB89940 Series

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Prior to evaluating/developing the software for the MB89940 series, please check the differences between the

product types.

• RAM/ROM configurations are dependent on the product type.

• If the bottom address of the stack is set to the upper limit of the RAM address, it should be relocated when

changing the product type.

2. Power Dissipation

• For the piggyback product, add the power dissipation of the EEPROM on the piggyback.

• The power dissipation differs between the product types.

3. Technology

The mask ROM product is fabricated with a 0.5 µm CMOS technology whereas the other products with 0.8 µm

CMOS technology.

Also the mask ROM product contains the on-chip voltage regulator for the internal 3.0 power supply. For details,

refer to MB89940 Series Hardware Manual.

4. Mask Option

Functions that can be selected as options and how to designate these options vary by the product.

Before using options check section “■ Mask Options.”

• No options are available for the piggyback product.

• The power-on reset and reset output options are always activated with the mask ROM product.

• Pull-up option must not be specified with the pins used as LCD outputs.

4

MB89940 Series

■ PIN ASSIGNMENT

(Top view)

AV^CC

RST

P41/COM0

P42/COM1

X0

1

2

3

4

5

6

7

8

36

35

34

33

32

31

30

29

28

27

26

25

DV^CC

P30/FUELO

P00/SEG00

P01/SEG01

P02/SEG02

P03/SEG03

P04/SEG04

P05/SEG05

P06/SEG06

P07/SEG07

P10/SEG08

P11/SEG09

X1

V^CC

P43/COM2

P44/COM3

P27/INT2

P26/INT1

P25/INT0

9

10

11

12

(FPT-48P-M16)

5

MB89940 Series

(Top view)

AV^CC

1

2

3

4

5

6

7

8

36

35

34

33

32

31

30

29

28

27

26

25

DV^CC

RST

P41/COM0

P42/COM1

X0

P30/FUELO

P00/SEG00

P01/SEG01

P02/SEG02

P03/SEG03

P04/SEG04

P05/SEG05

P06/SEG06

P07/SEG07

P10/SEG08

P11/SEG09

69

70

71

72

73

74

75

76

60

59

58

57

56

55

54

53

X1

V^CC

P43/COM2

P44/COM3

P27/INT2

P26/INT1

P25/INT0

9

10

11

12

(MQP-48C-P01)

• Pin assignment on package top (MB89PV940 only)

Pin no.

49

Pin name

A15

A12

A7

Pin no.

57

Pin name

N.C.

A2

Pin no.

65

Pin name

Pin no.

73

Pin name

OE

O4

O5

50

58

66

74

N.C.

A11

A9

51

59

A1

67

O6

75

52

A6

60

A0

68

O7

76

53

A5

61

O1

69

O8

77

A8

54

A4

62

O2

70

CE

A10

N.C.

78

A13

A14

VCC

55

A3

63

O3

71

79

56

N.C.

64

V^SS

72

80

N.C.: Internally connected. Do not use.

6

MB89940 Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

Function

QFP*¹

MQFP*²

5

X0

X1

A

These pins are used for crystal oscillation.

X0 and X1 can be directly connected to a crystal

oscillator.

When the oscillation clock is provided to X0

externally, X1 should be left open.

6

48

MODE

RST

B

C

The mode input is used for entering the MPU into the

test mode.

In user applications, MODE is connected to V^SS.

2

Applying a reset pulse to this pin forces the MPU to

enter the initial state. RST is active low and drives

low state when an internal reset occurs.

Reset pulses of the duration less than the minimum

pulse width may cause the MCU to enter undefined

states.

34 to 27

P00/SEG00 to

P07/SEG07

H

J

These pins have two functions.

Their functions can be switched between Port 0 and

LCD segment signal outputs by setting the internal

registers of the LCD controller.

26 to 20,

18

26 to 20,

18

P10/SEG08 to

P17/SEG15

These pins have two functions.

Their functions can be switched between Port 1 and

LCD segment signal outputs by setting the internal

registers of the LCD controller.

17

16

15

17

16

15

P20/SEG15

P21/V0

I

This pin can be used as the bit 0 of Port 2 or an LCD

segment signal output by setting the internal register

of the LCD controller.

F

This pin is the bit 1 of Port 2.

This pin can also be used for an external LCD bias

voltage input.

P22/EC/V1

This pin can be used as the bit 2 of Port 2 or the

external clock input for the interval timer.

This pin can also be used for an external LCD bias

voltage input.

14

P23/TO/V2

F

This pin can be used as the bit 3 of Port 2 or the

output for the interval timer.

Its function can be switched by setting the internal

register of the interval timer.

This pin can also be used for an external LCD bias

voltage input.

13

12, 11, 10

35

13

P24/V3

F

E

D

This pin can be used as the bit 4 of Port 2 or an

external LCD bias voltage input.

12, 11, 10 P25/INT0 to

P27/INT2

These pins are used for Port 2.

They can also be used for external interrupt inputs.

35

P30/FUELO

This pin can be used for the bit 0 of Port 3 or the

output from PWM3.

The function of this pin can be switched by setting

the internal register of PWM3.

(Continued)

*1: FPT-48P-M16

*2: MQP-48C-P01

7

MB89940 Series

(Continued)

Pin no.

Circuit

type

Pin name

Function

QFP*¹

MQFP*²

37

P31/TEMPO

G

This pin can be used for the bit 1 of Port 3 or the

output from PWM4.

The function of this pin can be switched by setting

the internal register of PWM4. This output has a high

drive-current capability.

38,

39

38,

39

P32/PWM1P,

P33/PWM1M

These pins are the pair of high-current driver outputs

for one of two motor coils.

They can be also used for the bits 2 and 3 of Port 3

by setting the internal register of the stepper motor

controller.

40,

41

40,

41

P34/PWM2P,

P35/PWM2M

These pins are the pair of high-current driver outputs

for one of two motor coils.

They can be also used for the bits 4 and 5 of Port 3

by setting the internal register of the stepper motor

controller.

44

45

46

44

45

46

P36/TEMPI

P37/FUELI

P40/PW

M

L

This analog input is connected to channel 1 of the

A/D converter.

It can also be used for the bit 6 of Port 3 when this A/

D input enable register bit is set to ‘0’.

This analog input is connected to channel 0 of the

A/D converter.

It can also be used for the bit 7 of Port 3 when this A/

D input enable register bit is set to ‘0’.

This pin has two functions.

When this pin is used as an open-drain output of

Port 4, the external voltage monitor reset should be

in the power down mode.

When it is used as the PW input of external voltage

monitor reset, the corresponding bit of the port data

register should be set to ‘1’.

3, 4

8, 9

3, 4

8, 9

P41/COM0 to

P44/COM3

K

These pins are the LCD common signal outputs.

When LCD is not used, these pins can be also used

for Port 4.

47

VINT

—

An external capacitor should be connected to this

pin for stabilizing the internal 3.0 V power supply.

For MB89PV940 and MB89P945, this pin should be

left open.

7

19

1

7

19

1

V^CC

—

VCC

VSS

AVCC

The power supply pin for the analog circuit

The same voltage should be applied as VCC.

The power supply pin for the analog circuit

The same voltage should be applied as V^SS.

43

36

43

36

AV^SS

—

DVCC

The dedicated power supply pin for the high-current

driver output

The same voltage should be applied as VCC.

42

DV^SS

—

The dedicated power supply pin for the high-current

driver output

The same voltage should be applied as VSS.

*1: FPT-48P-M16

*2: MQP-48C-P01

8

MB89940 Series

• External EPROM pins (MB89PV940 only)

Pin no.

Pin name

A15

I/O

Function

49

50

51

52

53

54

55

58

59

60

O

Address output pins

A12

A7

A6

A5

A4

A3

A2

A1

A0

61

62

63

65

66

67

68

69

O1

O2

O3

O4

O5

O6

O7

O8

I

Data input pins

70

CE

O

ROM chip enable pin

Outputs “H” during standby.

71

73

A10

OE

O

Address output pin

ROM output enable pin

Outputs “L” at all times.

75

76

77

78

79

A11

A9

A8

A13

A14

O

Address output pin

80

64

V^CC

VSS

O

EPROM power supply pin

Power supply (GND) pin

Internally connected pins

56

57

72

74

N.C.

—

Be sure to leave them open.

9

MB89940 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• Oscillator I/O

With feedback resistor of approx. 2 MΩ.

X1

X0

Standby control signal

B

C

• Schmitt-trigger input

(Pull-down resistance only for MB89943)

R

• Open-drain output with pull-up resistor

(Approx. 50 kΩ).

R

P-ch

• Schmitt-trigger input

• Hysteresis input

N-ch

D

• CMOS I/O

P-ch

N-ch

E

• CMOS I/O (Schmitt trigger)

• Pull-up resistor optional

R

P-ch

N-ch

Mask Option

(Continued)

10

MB89940 Series

Type

Circuit

Remarks

F

• CMOS I/O (Schmitt trigger)

• External bias input

R

P-ch

• Pull-up resistor optional

Mask Option

N-ch

P-ch

N-ch

G

• CMOS I/O (High output current)

P-ch

N-ch

H

• CMOS I/O

• LCD controller/driver output

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch

I

• CMOS I/O

• LCD controller/driver output

• Pull-up resistor optional

• Hysteresis input

R

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch

(Continued)

11

MB89940 Series

(Continued)

Type

Circuit

Remarks

J

• CMOS I/O

• LCD controller/driver output

• Pull-up resistor optional

(Except P11/SEG09, P10/SEG08)

R

P-ch

Mask Option

N-ch

P-ch

N-ch

P-ch

N-ch

K

• N-ch open-drain output

• LCD controller/driver output

N-ch

P-ch

N-ch

P-ch

N-ch

L

• N-ch open-drain output

• Analog input

N-ch

M

• CMOS I/O

• Analog input

P-ch

N-ch

12

MB89940 Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prevent the analog power supply (AV^CCand AVR) and analog input from exceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

The VINT pin of MB89PV940 and MB89P945 is the only exception.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is

therefore important. As stabilization guidelines, it is recommended to control power so that V^CCripple fluctuations

(P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the

transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power

is switched.

13

MB89940 Series

■ PROGRAMMING TO THE EPROM ON THE MB89P945

1. Programming MB89P945

Using the EPROM adapter (provided by Fujitsu) and a standard EPROM programmer, user-defined data can

be written into the OTPROM and option PROM. The EPROM programmer should be set to MB27C256A-20TVM

andelectro-signaturemodeshouldnotbeused. Whenprogrammingthedata, theinternaladdressesaremapped

as follows.

2. Memory Space

Address

0000H

Single chip

EPROM mode

(Corresponding addresses on the EPROM programmer)

8000H

C000H

0000H

3FF0H

4000H

Option PROM

One Time PROM

16 KB

One Time PROM

16 KB

7FFFH

FFFF^H

3. EPROM Programmer Socket Adapter

Please contact Fujitsu for socket adapters for the MB89P945 and the EPROM on the MB89PV940.

4. Screening MB89P945

It is recommended that high-temperature aging is performed on the MB89P945 prior to the assembly.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

14

MB89940 Series

5. Setting OTPROM Options

For MB89P945, mask options are described in the internal option PROM area. The table below shows the bit

map of the option PROM. The option data can be written by a standard EPROM programmer.

• OTPROM option bit map

PROM

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

3FF0^HUnused

Unused

Reserved Reset

output

Power-on

reset

1: Active

Oscillation stabilization

time

11: 2¹⁸TOSC 10: 2¹⁷TOSC

01: 2¹⁴TOSC

1: Active

0: Inactive 0: Inactive

3FF1H P17

Pull-up

P16

Pull-up

P15

Pull-up

P14

Pull-up

P13

Pull-up

P12

Pull-up

Unused

1: Inactive 1: Inactive 1: Inactive 1: Inactive 1: Inactive 1: Inactive

0: Active

3FF2H P27

P26

Pull-up

P25

Pull-up

P24

Pull-up

P23

Pull-up

P22

Pull-up

P21

Pull-up

P20

Pull-up

1: Inactive 1: Inactive 1: Inactive 1: Inactive 1: Inactive 1: Inactive 1: Inactive 1: Inactive

0: Active

3FF3^HUnused

Unused

Low volt.

PDX bit

Low volt.

S1 bit

Low volt.

S0 bit

Low volt.

LVE bit

Low volt.

1: Register

active

0: Option

active

3FF4^HUnused

3FF5^HUnused

3FF6^HUnused

Unused

Notes: Default values are all ‘1’.

T^OSC: One oscillation clock cycle time

When the bit 0 of “3FF3^H” is “0”, it activates the option setting for the Low Voltage Reset Control register.

When this option is activated, software setting in the register has no effect.

15

MB89940 Series

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TVM

2. Programming Socket Adapter

Please consult Fujitsu.

3. Memory Space

The memory space of the piggyback EPROM is mapped onto the internal memory space as shown in the figure

below.

Address

0000H

Single chip

Corresponding addresses on the EPROM programmer

8000H

0000H

Piggy Back

EPROM

32 KB

7FFFH

FFFF^H

For EPROM devices suitable for MB89PV940, please consult Fujitsu.

4. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256A-20TVM.

(2) Load program data into the EPROM programmer at 0000^Hto 7FFFH.

(3) Program to 0000^Hto 7FFFH with the EPROM programmer.

16

MB89940 Series

■ BLOCK DIAGRAM

X0

X1

Interrupt

controller

Oscillator

Clock controller

Timebase timer

Reset circuit

Low supply

voltage reset

RST

Port 4

4

P41/COM0 to

P44/COM3

External voltage

monitor interrupt

Port 0, 1 and 4

P40/PW

8

P10/SEG08 to

P17/SEG15

8

P00/SEG00 to

P37/FUELI

P36/TEMPI

P07/SEG07

LCD

controller driver

8-bit A/D

converter

P20/SEG16

P21/V0

DVCC

DVSS

High-drive-current

P22/EC/V1

P23/TO/V2

P24/V3

Stepper motor

macro

P32/PWM1P

Interval timer

P33/PWM1M

P34/PWM2P

P35/PWM2M

PWM1

PWM2

3

P25/INT0 to

P27/INT2

MODE

Port 2

RAM

P30/FUELO

High-drive-current

P31/TEMPO

PWM3

PWM4

F²MC-8L

core CPU

ROM

Port 3

Other pins

VCC, VSS

AVCC, AVSS

VINT

17

MB89940 Series

■ CPU CORE

1. Memory Space

The MB89940 Series has a memory space of 64 Kbytes. All peripheral registers, RAM and ROM areas are

mapped onto the 0000H to FFFFH range. The peripheral registers address below 007FH and the RAM addresses

the range 0080H to 027FH (0080H to 047FH for MB89PV940). A part of this RAM area is also assigned as the

general-purpose registers. The ROM addresses above E000^H. The One-Time PROM addresses the range above

C000H. The external ROM for the piggy sample addresses the range above 8000H. The reset vector, interrupt

vectors and vectors for vector-call instructions are stored in the highest addresses of the memory space.

Memory Space

MB89943

MB89P945

MB89PV940

0000H

Peripheral

registers

Peripheral

registers

Peripheral

registers

007FH

0100H

007FH

0100H

007FH

0100H

General-

purpose

registers

RAM

purpose

registers

RAM

purpose

registers

RAM

017FH

027FH

017FH

027FH

017FH

512 B

1 KB

047FH

8000^H

C000^H

External

ROM

E000^H

FFFF^H

One-time

PROM

ROM

8 KB

16 KB

32 KB

FFFF^H

18

MB89940 Series

2. Registers

The F²MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following dedicated registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit register for indicating instruction storage positions

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

Whenthe instructionisan8-bitdataprocessinginstruction,thelowerbyteisused.

Index register (IX):

Extra pointer (EP):

Stack pointer (SP):

Program status (PS):

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit register for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

16 bits

Initial value

FFFD^H

PC

A

: Program counter

: Accumulator

Indeterminate

T

: Temporary accumulator Indeterminate

IX

: Index register

: Extra pointer

: Stack pointer

: Program status

Indeterminate

EP

SP

PS

I-flag = 0, IL1, 0 = 11

The other bit values are indeterminate.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

PS

RP

Vacancy Vacancy Vacancy

H

IL1, 0

N

V

C

RP

CCR

19

MB89940 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

Rule for Conversion of Actual Addresses of the General-purpose Register Area

Lower OP codes

RP

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared

to ‘0’ at the reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low

N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ otherwise.

Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise.

V-flag: Set to ‘1’ if the complement on ‘2’ overflows as a result of an arithmetic operation. Cleared to ‘0’ if the

overflow does not occur.

C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to

‘0’ otherwise. Set to ‘1’ to the shift-out value in the case of a shift instruction.

20

MB89940 Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 16 banks can be used on the MB89943 (RAM 512 × 8 bits). The bank currently

in use is indicated by the register bank pointer (RP).

Note: The number of register banks that can be used varies with the RAM size. Up to a total of 32 banks can

be used on other than the MB89943.

Register Bank Configuration

This address = 0100H + 8 × (RP)

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

16 banks

Memory area

21

MB89940 Series

■ I/O MAP

Address

00^H

Read/write

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

01^H

PDD0

Port 0 data direction register

Port 1 data register

02^H

(R/W)

(W)

PDR1

03H

PDD1

Port 1 data direction register

Vacancy

04^Hto 06H

07^H

(R/W)

(W)

SCC

SMC

System clock control register

Standby mode control register

Watchdog timer control register

Timebase timer control register

Low voltage reset control

Port 2 data register

08H

09^H

WDTC

TBTC

LVRC

PDR2

PDD2

PDR3

PDD3

PDR4

ADE

0AH

0B^H

0CH

0DH

Port 2 data direction register

Port 3 data register

0E^H

(R/W)

(W)

0FH

Port 3 data direction register

Port 4 data register

10H

(R/W)

11^H

Port 3 A/D input enable register

Vacancy

12H to 17H

18^H

(R/W)

T2CR

T1CR

T2DR

T1DR

Timer 2 control register

Timer 1 control register

Timer 2 data register

19H

1AH

1B^H

Timer 1 data register

1CH to 1FH

20H

Vacancy

(R/W)

(W)

ADC1

ADC2

A/D converter control register 1

A/D converter control register 2

A/D converter data register

PWM control register

PWM1 compare register

Vacancy

21^H

22^H

ADCD

CNTR

COMP1

23H

24H

25^H

26H

(W)

COMP2

SELR1

SELR2

CNTR3

COMP3

CNTR4

PWM2 compare register

PWM1 select register

PWM2 select register

PWM3 control register

PWM3 compare register

PWM4 control register

27H

(R/W)

(W)

28^H

29H

2AH

2B^H

(R/W)

(Continued)

22

MB89940 Series

(Continued)

Address

Read/write

(W)

Register name

COMP4

SELT

Register description

2C^H

2DH

PWM4 compare register

(R/W)

Selector test register

2E^H

PFC

Power fail control register

External interrupt control 1 register

External interrupt control 2 register

Vacancy

2F^H

EIR1

30H

EIR2

31^Hto 5FH

60^Hto 68H

69H to 71H

72^H

(R/W)

VRAM

Display data RAM

Vacancy

(R/W)

LCR1

LCR2

LCD controller/driver register

LCD controller/driver 2 register

Vacancy

73H

74^Hto 7BH

7CH

(W)

ILR1

ILR2

ILR3

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Vacancy

7DH

7E^H

7FH

23

MB89940 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

V^CC

AV^CC

DVCC

V^I1

VSS – 0.3

VSS + 6.5

VCC + 0.3

DVCC + 0.3

V

Power supply voltage

Should not exceed VCC

Except P31 to P35 and P41 to P44

P31 to P35

V^I2

P41 to P44

MB89PV940/945

Input voltage

V^I3

V^I4

VSS – 0.3

VSS + 6.5

VCC + 0.3

V

P41 to P44

MB89943

V^O1

V^O2

VSS – 0.3

VCC + 0.3

V

Except P31 to P35 and P41 to P44

P31 to P35

DVCC + 0.3

P41 to P44

MB89PV940/945

Output voltage

V^O3

V^O4

VSS – 0.3

VSS + 6.5

VCC + 0.3

V

P41 to P44

MB89943

—

–40

–55

20

50

mA Except P31 to P35

mA P31 to P35

mA Except P31 to P35

mA P31 to P35

mA Except P31 to P35

mA P31 to P35

mA Except P31 to P35

mA P31 to P35

mA Except P31 to P35

mA P31 to P35

mA Except P31 to P35

mA P31 to P35

mA Except P31 to P35

mA P31 to P35

mA Except P31 to P35

mA P31 to P35

mW

“L” level maximum output

current

V^OL

4

“L” level average output

current

V^OLAV

40

100

200

40

“L” level total maximum

output current

V^OLTOTALMAX

V^OLTOTALAV

V^OH

“L” level total average

output current

100

–20

–50

–4

“H” level maximum output

current

“H” level average output

current

V^OHAV

–40

–50

–200

–20

–100

300

+85

+150

“H” level total maximum

output current

V^OHTOTALMAX

“H” level total average

output current

V^OHTOTALAV

Power consumption

Operating temperature

Storage temperature

P^D

T^A

°C

Tstg

°C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

24

MB89940 Series

2. Recommended Operating Conditions

Parameter

(AVCC = VCC = DVCC = 5.0 V, VSS = AVSS = DVSS = 0.0 V)

Value

Symbol

Unit

Remarks

Min.

Typ.

Max.

V^CC

AVCC

DVCC

Operating supply voltage range

3.5

—

5.5

V

V^CC

AVCC

DVCC

RAM data retention supply voltage range

Operating temperature range

3.0

—

5.5

V

TA

–40

+85

°C

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the

device’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

3. DC Characteristics

(AVCC = VCC = DVCC = 5.0 V, VSS = AVSS = DVSS = 0.0 V)

Value

Symbol

Parameter

Pin name

Condition

Unit Remarks

Min.

Typ.

Max.

P00 to P07, P10 to P17

P30 to P37, P40 to P47

V^CC+ 0.3

0.3 VCC

0.2 VCC

VIH

—

0.7 VCC

0.8 VCC

V^SS− 0.3

—

V

“H” level input voltage

RST, MODE, P20 to P27

V^IHS

VIL

—

P00 to P07, P10 to P17

P30 to P37, P40 to P47

—

“L” level input voltage

RST, MODE, P20 to P27

V^ILS

—

V^SS− 0.3

V^CC+ 0.3

V^SS+ 5.5

V^CC+ 0.3

—

VD

—

V

P40

MB89PV940/

945

Open-drain output

pin application voltage

V^D2

VD3

V^OH

V^OH2

—

V

P41 to P44

V^SS− 0.3

4.0

V

MB89943

P10 to P17, P20 to

P27, P30, P36, P37

I^OH= –2.0 mA

“H” level output

voltage

I^OH= –30

VCC = DVCC

V^CC− 0.5

P31 to P36

—

P10 to P17, P20 to P27,

P30, P36, P37,

P40 to P44

V^OL

IOL = 4.0 mA

—

0.4

0.5

V

“L” level output

voltage

I^OL= 30 mA

VSS = DVSS

V^OL2

P31 to P36

(Continued)

25

MB89940 Series

(Continued)

(AVCC = VCC = DVCC = 5.0 V, VSS = AVSS = DVSS = 0.0 V)

Value

Symbol

Parameter

Input leakage current

Pull-up resistance

Pin name

Condition

Unit Remarks

Min.

Typ.

Max.

MODE, P10 to P17,

P20 to P27, P30 to P37,

P40 to P44

0.0 V< VI < VCC,

VCC = DVCC

Without

pull-up option

IIL1

–5

—

+5

µA

RST, P12 to P17,

P20 to P27

With pull-up

option

RPULL

—

25

50

—

50

100

12

100

200

20

kΩ

LCD internal bias

voltage resister

V0-V1, V1-V2, V2-V3

R^LCD

FC = 8 MHz,

tinst* = 0.5 µs

ICC = I(VCC)

+ I(DV^CC)

MB89PV940

mA

ICC

MB89943,

MB89P945

12

20

FC = 8 MHz

t^inst* = 0.5 µs

I^CCS= I(VCC)

+ I(DVCC)

ICCS

VCC

—

3

5

7

mA

in Sleep mode

Power supply current

In Stop mode

T^A= 25°C

ICCH = I(VCC)

+ I(DV^CC)

I^CCH

10

µA

FC = 8 MHz

I^A= I(AVCC)

A/D in operation

I^A

—

6

5

8

mA

AVCC

FC = 8 MHz

I^AH= I(AVCC)

A/D stopped

I^AH

10

µA

Input capacitance

CIN

—

f = 1 MHz

—

10

—

pF

External capacitor

at VINT

MB89943 only

CVINT

—

0.1

µF

* : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

4. AC Characteristics

(1) Reset Timing

(AVSS = VSS = DVSS, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Min.

Max.

RST “L” pulse width

tZLZH

—

16 tHCYL

—

ns

tHCYL: One oscillation clock cycle time

26

MB89940 Series

tZLZH

RST

0.8 VCC

0.2 VCC

If power-on reset option is not activated, the external reset signal must be kept asserted until the oscillation is

stabilized.

(2) Power-on Profile

(AVSS = VSS = DVSS, TA = –40°C to +85°C)

Value

Symbol

t^R

Condition

Unit

Remarks

Parameter

Min.

Max.

MB89PV940,

MB89P945

Power supply voltage rising time

—

50

ms

2¹⁹tHCYL

Power supply voltage rising time

Power-off minimum period

t^R

—

1

ns

MB89943

t^OFF

—

ms

tHCYL: One oscillation clock cycle time

Note: Power supply voltage should reach the minimum operation voltage within the specified default duration of

the oscillation stabilization time.

tOFF

t^R

3.5 V

0.2 V

V

CC

(3) Clock Timing

Parameter

(AVSS = VSS = DVSS, TA = –40°C to +85°C)

Value

Symbol

F^C

Condition

Unit

Remarks

Min.

1

Max.

8

Clock frequency

Clock cycle time

MHz

ns

t^CYC

1000

125

tWH

tWL

—

Input clock pulse width

20

—

ns

t^CR

tCF

Input clock rising/falling time

10

27

MB89940 Series

X0 and X1 Timing and Conditions

t^CYC

tWL

t^CR

tCF

0.8 VCC

X0

0.2 VCC

Clock Conditions

When a crystal

or

ceramic resonator is used

When an external clock is used

X0

X1

X0

X1

Open

(4) Instruction Cycle

Parameter

Symbol

Value (typical)

Unit

Remarks

Instruction cycle

(minimum execution time)

(4/F^C) tinst = 0.5 µs when operating at

FC = 8 MHz

t^inst

4/FC, 8/FC, 16/FC, 64/FC

µs

Note: When operating at 8 MHz, the cycle varies with the set execution time.

(5) Peripheral Input Timing

(AVSS = VSS= DVSS, TA = –40°C to +85°C)

Value

Symbol

t^WH

Pin name

Unit

Remarks

Parameter

Min.

Max.

INT0, INT1,

INT2, EC

Peripheral input “H” pulse width

Peripheral input “L” pulse width

2 t^inst*

—

µs

INT0, INT1,

INT2, EC

tWL

2 t^inst*

—

* : For information on tinst, see “(4) Instruction Cycle.”

28

MB89940 Series

tWL

0.8 VCC

INT0, INT1,

INT2, EC

0.2 VCC

5. A/D Converter Electrical Characteristics

(AVSS = VSS = DVSS, TA = –40°C to +85°C)

Value

Typ.

—

name

Symbol

Condition

Parameter

Resolution

Unit

Remarks

Min.

Max.

8

—

bit

LSB

V

Total error

—

±1.5

—

Linearlity error

Differential linearlity error

—

±1.0

—

±0.9

AV^SS– 1.0 LSB

AV^SS+ 5/8 LSB

AV^SS+ 0.5 LSB

AV^SS+ 2.0 LSB

MB89PV940/P945

MB89943

Zero transition voltage

VOT

AV^SS+ 7/8 LSB AV^SS+ 11/8 LSB

V

AV^CC– 3.0 LSB AV^CC– 1.5 LSB

AV^CC– 13/8 LSB AV^CC– 9/8 LSB

MB89PV940/P945

MB89943

AVCC

AV^CC– 7/8 LSB

0.5

V

Full-scale transition

voltage

—

V^FST

V

Interchannel disparity

—

LSB

µs

MB89PV940/P945

—

44 t^inst*

52 tinst*

10

A/D mode

conversion time

µs MB89943

µA

Analog input current I^AIN

Analog input voltage

—

0

—

AV^CC

V

range

* : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

6. A/D Converter Glossary

• Resolution

Analog changes that are identifiable with the A/D converter

When the number of bits is 8, analog voltage can be divided into 2⁸= 256.

• Linearity error (unit: LSB)

The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the

full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics

• Differential linearity error (unit: LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error (unit: LSB)

The difference between theoretical and actual conversion values

29

MB89940 Series

Digital output

Theoretical conversion value

1111 1111

1111 1110

•

Actual conversion value

•

(1 LSB × N + V^OT)

AVR

256

•

1 LSB =

•

V^NT– (1 LSB × N + VOT)

•

Linearity error =

•

1 LSB

•

V( N + 1 ) T – VNT

•

– 1

Differential linearity error =

Total error =

•

1 LSB

Linearity error

•

VNT – (1 LSB × N + 1 LSB)

•

1 LSB

•

0000 0010

0000 0001

0000 0000

VOT

VNT

V(N + 1)T

VFST

Analog input

7. Notes on Using A/D Converter

• Input impedance of the analog input pins

The A/D converter used for the MB89940 series contains a sample hold circuit as illustrated below to fetch

analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output

impedance of the external circuit low (below 10 kΩ).

Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about

0.1 µF for the analog input pin.

Analog Input Equivalent Circuit

Sample hold circuit

.

C = 33 pF

.

Analog input pin

Comparator

If the analog input

impedance is higher

than 10 kΩ, it is

recommended to

connect an external

capacitor of approx.

0.1 µF.

.

R = 6 kΩ

.

Close for 8 instruction cycles after activating

A/D conversion.

Analog channel selector

• Error

The smaller the | AV^CC– AVSS |, the greater the error would become relatively.

30

MB89940 Series

8. Low Supply Voltage Reset Electrical Characteristics

Value

Symbol

Unit

Remarks

Parameter

Min.

3.0

Max.

3.6

V^DL1

V^DL2

V^DL3

V

When the voltage is

dropping.

Refer to the register

definition.

Reset voltage

3.3

3.9

3.7

4.3

When the voltage is

recovering.

Hysteresis of reset voltage

V^HYS

0.1

—

V

Delay time to reset

t^D

—

2.0

0.1

µs

Supply voltage slew rate

dV/dt

V/µs

9. External Voltage Monitor Interrupt Electrical Characteristics

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

Reference voltage

V^REF

T^D

1.18

1.38

V

µs

Refer to the register

definition.

Delay time to interrupt

Input slew rate

—

2.0

0.1

dV/dt

V/µs

31

MB89940 Series

■ INSTRUCTIONS (136 INSTRUCTIONS)

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

#vct

#d8

#d16

dir: b

rel

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

Register indirect (Example: @A, @IX, @EP)

@

A

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

AH

AL

Lower 8 bits of accumulator A (8 bits)

T

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

TH

TL

IX

EP

PC

SP

PS

dr

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

CCR

RP

Ri

Register bank pointer RP (5 bits)

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × )

(( × ))

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

32

MB89940 Series

Columns indicate the following:

Mnemonic:

~:

Assembler notation of an instruction

The number of instructions

The number of bytes

#:

Operation:

TL, TH, AH:

Operation of an instruction

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH prior to the instruction executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

33

MB89940 Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

–

AL

–

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

–

F0

Notes: • During byte transfer to A, T ← A is restricted to low bytes.

• Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

34

MB89940 Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 to DF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

C

A

←

C

A

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

(A) − (Ri)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

35

MB89940 Series

(Continued)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

36

MB89940 Series

■ MASK OPTIONS

Part number

MB89943

MB89P945

MB89PV940

Specify when

ordering

No.

Set with EPROM

Programmer

Setting not

possible

Specifying procedure

masking

Selectable per pin

(P20 and P12 to

P17 must be set to

without pull-up

resistor when they

are used as LCD

outputs.)

Pull-up resistors

Fixed to without

pull-up resistor

1

P12 to P17,

P20 to P27

Can be set per pin

Power-on reset

Fixed to with

power-on reset

Fixed to with

power-on reset

2

3

4

With power-on reset

Without power-on reset

Setting possible

Main clock oscillation stabilization time

selection (when operating at 8 MHz)

Approx. 2¹⁸/FC (Approx. 32.8 ms)

Approx. 2¹⁷/FC (Approx. 16.4 ms)

Approx. 2¹⁴/FC (Approx. 2.0 ms)

Fixed to

approx. 2¹⁸/FC

(Approx. 32.8 ms)

Selectable

Reset pin output

With reset output

Without reset output

Fixed to with reset

output

Fixed to with reset

output

■ ORDERING INFORMATION

Part number

Package

Remarks

MB89943PF

MB89P945PF

48-pin Plastic QFP

(FPT-40P-M16)

48-pin Ceramic MQFP

(MQP-48C-P01)

MB89PV940CF

38

MB89940 Series

■ PACKAGE DIMENSION

48-pin Plastic QFP

(FPT-48P-M16)

17.20±0.40 SQ

2.70(.106)MAX

(Mounting height)

(.677±.016)

12.00 ⁺^–0⁰^.^.¹³⁰⁰SQ

0.05(.002)MIN

(STAND OFF)

.472 –⁺.^.0⁰0¹4²

36

25

Details of "A" part

0.15(.006)

37

24

8.80

(.346)

REF

13.60±0.40

(.535±.016)

0.20(.008)

0.15(.006)MAX

0.50(.020)MAX

INDEX

48

13

"A"

Details of "B" part

1

12

LEAD No.

0.15 –⁺0⁰.^.0⁰1⁵

.006 ⁺^–.^.⁰⁰⁰⁰⁰²⁴

0.80(.0315)TYP

0.30±0.06

(.012±.002)

M

0.16(.006)

0~10°

"B"

1.80±0.30

(.071±.012)

0.15(.006)

C

1994 FUJITSU LIMITED F48026S-1C-1

Dimensions in mm (inches)

48-pin Ceramic MQFP

(MQP-48C-P01)

17.20(.677)TYP

15.00±0.25

(.591±.010)

1.50(.059)TYP

1.00(.040)TYP

8.80(.346)REF

PIN No.1 INDEX

14.82±0.35

(.583±.014)

0.80±0.22

(.0315±.0087)

PIN No.1 INDEX

1.02±0.13

(.040±.005)

10.92 –⁺0⁰.^.0¹³

.430 –⁺0^.005

8.71(.343)

TYP

7.14(.281)

TYP

PAD No.1 INDEX

4.50(.177)TYP

1.10 ⁺^–0⁰^.^.²⁴⁵⁵

.043 ⁺^–.^.⁰⁰¹¹⁰⁸

0.40±0.08

(.016±.003)

0.60(.024)TYP

0.30(.012)TYP

8.50(.335)MAX

0.15±0.05

(.006±.002)

C

Dimensions in mm (inches)

1994 FUJITSU LIMITED M48001SC-4-2

39


型号：	MB89P945PF
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器外围集成电路可编程只读存储器时钟
文件：	总40页 (文件大小：521K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89P945PF [FUJITSU]

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