MB89PV490 [FUJITSU]
8-bit Proprietary Microcontroller; 8位微控制器专有
| 型号： | MB89PV490 |
| 厂家： | 
FUJITSU |
| 描述： | 8-bit Proprietary Microcontroller |
| 文件： | 总45页 (文件大小：545K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
Revision 1.5
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89490 Series
MB89497/498/F499/PV490
■ DESCRIPTION
The MB89490 series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit single-chip microcontrollers.
In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as
21-bit timebase timer, watch prescaler, PWM timer, 8/16-bit timer/counter, remote receiver control, LCD
controller/driver, external interrupt 0 (edge), external interrupt 1 (level), 10-bit A/D converter, UART/SIO, SIO,
I2C and watchdog timer reset.
The MB89490 series is designed suitable for compact disc/cassette tape/radio receiver controller as well as in
a wide range of applications for consumer product.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• Package used
QFP package for MB89F499, MB89497,MB89498
MQFP package for MB89PV490
• High speed operating capability at low voltage
• Minimum execution time: 0.32 µs/12.5MHz
(Continued)
■ PACKAGE
100-pin Plastic QFP
100-pin Ceramic MQFP
(FTP-100P-M06)
(MQP-100C-P01)
1
MB89490 Series
(Continued)
• F2MC-8L family CPU core
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Instruction set optimized for controllers
Bit manipulation instructions, etc.
• Clock
Embedded PLL clock multiplication circuit for sub-clock
Operating clock (PLL for sub-clock) can be selected four times of the sub-clock oscillation
• Six timers
PWM timer x 2
8/16-bit timer/counter x 2
21-bit timebase timer
Watch prescaler
• External interrupt
Edge detection (selectable edge) : 8 channels
Low level interrupt (wake-up function) : 8 channels
• 10-bit A/D converter (8 channels)
10-bit successive approximation type
• UART/SIO
Synchronous/asynchronous data transfer capability
• SIO
Synchronous data transfer capability
• LCD controller/driver
Max. 32 segments output x 4 commons
• I2C interface circuit
• Remote receiver circuit
• Low-power consumption mode
Stop mode (oscillation stops so as to minimize the current consumption.)
Sleep mode (CPU stops so as to reduce the current consumption to approx. 1/3 of normal.)
Watch mode (everything except the watch prescaler stops so as to reduce the power comsumption to an
extremely low level.)
Sub-clock mode
• Watchdog timer reset
• I/O ports: max. 66channels
■ PRODUCT LINEUP
Part number
MB89497
MB89498
MB89F499
MB89PV490
Parameter
Classification
Mass production products
(mask ROM product)
FLASH
Piggy-back
60K x 8-bit (external ROM)*1
ROM size
RAM size
32K x 8-bit
(internal ROM) (internal ROM)
48K x 8-bit
60K x 8-bit (internal FLASH)
1K x 8-bit 2K x 8-bit
2K x 8-bit
2K × 8-bit
*1 : Use MBM27C512 as the external ROM.
2
MB89490 Series
Part number
Parameter
CPU functions
MB89497
MB89498
MB89F499
MB89PV490
Number of instructions
Instruction bit length
: 136
: 8 bits
Instruction length
Data bit length
Minimum execution time
Minimum interrupt processing time
: 1 to 3 bytes
: 1, 8, 16 bits
: 0.32 µs/12.5 MHz
: 2.88 µs/12.5 MHz
I/O ports (CMOS)
Input ports (CMOS)
N-channel open drain I/O ports
Total
: 56 pins
: 2 pins
: 8 pins
: 66 pins
Ports
21-bit timebase
timer
Interrupt period (0.66 ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz
Watchdog timer
Reset period (167.8 ms to 335.5 ms) at 12.5 MHz.
8-bit reload timer operation (supports square wave output, operating clock period: 1, 8, 16, 64
PWM timer 0,1
tinst,)
8-bit resolution PWM operation
Can be operated either as a 2-channel 8-bit timer/counter (timer 00 and timer 01, each with its
own independent operating clock cycle), or as one 16-bit timer/counter
In timer 00 or 16-bit timer/counter operation, event counter operation (external clock-triggered)
and square wave output capability
8/16-bit timer/
counter 00, 01
Can be operated either as a 2-channel 8-bit timer/counter (timer 10 and timer 11, each with its
own independent operating clock cycle), or as one 16-bit timer/counter
In timer 10 or 16-bit timer/counter operation, event counter operation (external clock-triggered)
and square wave output capability
8/16-bit timer/
counter 10, 11
External interrupt 0
(edge)
8 independent channels (selectable edge, interrupt vector, request flag)
8 channels (low level interrupt)
External interrupt 1
(level)
10-bit resolution × 8 channels
A/D converter
A/D conversion function (conversion time: 38 tinst )
Supports repeated activation by internal clock
Common output
Segment output
Bias power supply pins
LCD display RAM size
: 4 (max.)
: 32 (max.)
: 3
LCD controller/driver
: 32 × 4 bits
Synchronous/asynchronous data transfer capability
(Max. baud rate: 97.656 Kbps at 12.5 MHz)
(7 and 8 bits with parity bit; 8 and 9 bits without parity bit)
UART/SIO
SIO
8-bit serial I/O with LSB first/MSB first selectability
One clock selectable from four operation clock (one external shift clock, three internal shift
clock: 0.64µs, 2.56µs, 10.24µs at 12.5MHz)
I2C*1
1 channel
Use a 2-wire protocol to communicate with other device
Selectable maximum noise width removal
Reversible input polarity
Remote receiver
Sleep mode, stop mode, watch mode, sub-clock mode
CMOS
Standby mode
Process
2.2V ~ 3.6V
2.7V ~ 3.6V
2.7V ~ 3.6V
Operating voltage
*1 : I2C is complied to Philips I2C specification.
3
MB89490 Series
■ PACKAGE AND CORRESPONDING PRODUCTS
Part number
MB89497/498
MB89F499
MB89PV490
Package
FPT-100P-M06
MQP-100C-P01
O
X
O
X
X
O
O : Availabe
X : Not available
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following point:
• The stack area is set at the upper limit of the RAM.
2. Current Consumption
• For the MB89PV490 the current consumed by the EPROM mounted in the piggy-back socket is needed to be
included.
• When operating at low speed, the current consumed by the FLASH product is greater than that for the mask
ROM product. However, the current consumption is roughly the same in sleep and stop mode.
• For more information, see “■ Electrical Characteristics.”
3. Oscillation Stabilization Time after Power-on Reset
• For MB89PV490 and MB89F499, the power-on stabilization time cannot be selected.
• For MB89497 and MB89498, the power-on stabilization time can be selected.
• For more information, please refer to “■ Mask Option”.
4
MB89490 Series
■ PIN ASSIGNMENT
(TOP VIEW)
Vcc
*P00
*P01
*P02
*P03
*P04
*P05
*P06
*P07
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P65/SEG21
P64/SEG20
P63/SEG19
P62/SEG18
P61/SEG17
P60/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
9
P10/INT00
P11/INT01
P12/INT02
P13/INT03
P14/INT04
P15/INT05
P16/INT06
P17/INT07
P20/TO0
P21/RMC
P22/EC0
P23
P24/TO1
P25/EC1
P26/PWM0
P27/PWM1
P50/SI0
P51/SO0
P52/SCK0
AVR
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SEG0
P54/COM3
P53/COM2
COM1
COM0
V1
V2
V3
Vcc
AVcc
* High current pins
(FPT-100P-M06)
5
MB89490 Series
(TOP VIEW)
Vcc
*P00
*P01
*P02
*P03
*P04
*P05
*P06
*P07
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P65/SEG21
P64/SEG20
P63/SEG19
P62/SEG18
P61/SEG17
P60/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
9
121
122
123
124
125
126
127
128
129
113
112
111
110
109
108
107
106
105
P10/INT00
P11/INT01
P12/INT02
P13/INT03
P14/INT04
P15/INT05
P16/INT06
P17/INT07
P20/TO0
P21/RMC
P22/EC0
P23
P24/TO1
P25/EC1
P26/PWM0
P27/PWM1
P50/SI0
P51/SO0
P52/SCK0
AVR
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SEG0
P54/COM3
P53/COM2
COM1
COM0
V1
V2
V3
Vcc
AVcc
* High current pins
(MQP-100C-P01)
Pin assignment on package top (MB89PV490 only)
Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name
101
102
103
104
105
106
107
108
N.C.
A15
A12
A7
109
110
111
112
113
114
115
116
A2
A1
117
118
119
120
121
122
123
124
N.C.
O4
125
126
127
128
129
130
131
132
OE
N.C.
A11
A9
A0
O5
N.C.
O1
O2
O3
VSS
O6
A6
O7
A8
A5
O8
A13
A14
VCC
A4
CE
A10
A3
N.C.: As connected internally, do not use.
6
MB89490 Series
■ PIN DESCRIPTION
Pin number
I/O circuit
type
Pin name
Function
MQFP*1/QFP*2
99
98
49
48
X0
X1
Connection pins for a crystal or other oscillator.
An external clock can be connected to X0. In this case, leave X1 open.
A
A
Connection pins for a crystal or other oscillator.
An external clock can be connected to X0A. In this case, leave X1A
open.
X0A
X1A
Input pin for setting the memory access mode.
Connect directly to VSS.
97
MOD0
B
J
95, 94
P84,P83
General-purpose CMOS Input port.
Reset I/O pin. The pin is an N-ch open-drain type with pull-up resistor
and a hysteresis input. The pin outputs an “L” level when an internal
reset request is present. Inputting an “L” level initializes internal
circuits.
96
RST
C
2~9
P00 ~ P07
D
E
General-purpose CMOS I/O port.
P10/INT00
~
P17/INT07
General-purpose CMOS I/O port.
The pin is shared with external interrupt 0 input.
10~17
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 00, 01 output.
18
19
P20/TO0
P21/RMC
F
E
General-purpose CMOS I/O port.
The pin is shared with remote receiver input.
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 00, 01 input.
20
21
22
P22/EC0
P23
E
F
F
General-purpose CMOS I/O port.
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 10, 11 output.
P24/TO1
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 10,11 input.
23
24
25
P25/EC1
P26/PWM0
P27/PWM1
E
F
F
General-purpose CMOS I/O port.
The pin is shared with PWM0 output.
General-purpose CMOS I/O port.
The pin is shared with PWM1 output.
P30/AN0/INT10
~
P37/AN7/INT17
General-purpose CMOS I/O port.
The pin is shared with external interrupt 1 input and A/D converter
input.
32 ~ 39
G
40 ~ 45
46
P40~P45
P46/SCL
H
H
General-purpose N-ch open-drain I/O port.
General-purpose N-ch open-drain I/O port.
The pin is shared with I2C clock I/O.
General-purpose N-ch open-drain I/O port.
The pin is shared with I2C data I/O.
47
26
27
28
P47/SDA
P50/SI0
H
E
F
E
General-purpose CMOS I/O port.
The pin is shared with SIO data input.
General-purpose CMOS I/O port.
The pin is shared with SIO data output.
P51/SO0
P52/SCK0
General-purpose CMOS I/O port.
The pin is shared with SIO clock I/O.
7
MB89490 Series
(Continued)
Pin number
I/O circuit
type
Pin name
Function
General-purpose CMOS I/O port.
MQFP*1/QFP*2
57
58
P53/COM2
P54/COM3
F / I
F / I
The pin is shared with the LCD common output.
General-purpose CMOS I/O port.
The pin is shared with the LCD common output.
P60/SEG16
~
P67/SEG23
General-purpose CMOS I/O port.
The pin is shared with LCD segment output.
75 ~ 82
83 ~ 90
F / I
F / I
P70/SEG24
~
P77/SEG31
General-purpose CMOS I/O port.
The pin is shared with LCD segment output.
General-purpose CMOS I/O port.
The pin is shared with UART/SIO data input.
91
92
P80/SI1
P81/SO1
P82/SCK1
E
F
E
I
General-purpose CMOS I/O port.
The pin is shared with UART/SIO data output.
General-purpose CMOS I/O port.
The pin is shared with UART/SIO clock I/O.
93
SEG0 ~
SEG15
59 ~ 74
LCD segment output-only pin.
LCD common output-only pin.
COM0 ~
COM1
55 ~ 56
I
54, 53, 52
1,51
V1 to V3
VCC
—
—
—
—
—
LCD driving power supply pin.
Power supply pin.
50,100
30
VSS
Power supply pin (GND).
AVCC
AVR
A/D converter power supply pin.
A/D converter reference voltage input pin.
29
A/D converter power supply pin.
Use at the same voltage level as VSS.
31
AVSS
—
*1: MQP-100C-P01
*2: FPT-100P-M06
8
MB89490 Series
• External EPROM Socket (MB89PV490 only)
Pin
number
Pin
name
I/O
Function
MQFP*1
102
131
130
103
127
124
128
129
104
105
106
107
108
109
110
111
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
O
Address output pins.
A4
A3
A2
A1
A0
122
121
120
119
118
115
114
113
O8
O7
O6
O5
O4
O3
O2
O1
I
Data input pins.
101
112
117
126
N.C.
—
Internally connected pins. Always leave open.
116
123
125
132
VSS
CE
OE
VCC
O
O
O
O
Power supply pin (GND).
Chip enable pin for the EPROM. Outputs “H” in standby mode.
Output enable pin for the EPROM. Always outputs “L”.
Power supply pin for the EPROM.
*1: MQP-100C-P01
9
MB89490 Series
■ I/O CIRCUIT TYPE
Circuit
Class
Circuit
Remarks
X1 (X1A)
X0 (X0A)
N-ch P-ch
P-ch
A
B
C
• Main/Sub-clock circuit
N-ch
N-ch
Stop mode control signal
• Hysteresis input (CMOS input in
MB89F499)
• The pull-down resistor (not
available in MB89F499)
Approx. 50kΩ
R
R
P-ch
N-ch
• The pull-up resistor (P-channel)
Approx. 50 kΩ
• Hysteresis input
pull-up
resistor register
R
• CMOS output
• IOH=-4mA, IOL=12mA
• CMOS input
P-ch
P-ch
D
• Selectable pull-up resistor
Approx. 50 kΩ
N-ch
port
pull-up
resistor register
R
P-ch
N-ch
• CMOS output
• IOH=-2mA, IOL=4mA
• CMOS port input
• Hysteresis resource input
• Selectable pull-up resistor
Approx. 50 kΩ
P-ch
E
port
resource
(Continued)
10
MB89490 Series
(Continued)
pull-up
resistor register
R
• CMOS output
• IOH=-2mA, IOL=4mA
• CMOS input
• Selectable pull-up resistor
Approx. 50 kΩ
P-ch
N-ch
P-ch
F
port
pull-up
resistor register
R
• CMOS output
• IOH=-2mA, IOL=4mA
• CMOS port input
P-ch
P-ch
• Automotive (VIH=0.85Vcc, VIL=0.5Vcc)
resource input
G
N-ch
• Analog input
• Selectable pull-up resistor
Approx. 50 kΩ
port
resource
analog
• N-ch open-drain output
• IOL=15mA
• CMOS port input
• CMOS resource input
• 5V tolerance
N-ch
H
port / resource
P-ch
N-ch
I
• LCD segment output
P-ch
N-ch
J
• CMOS input
11
MB89490 Series
■ HANDLING DEVICES
1. Preventing Latch-up
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output
pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in “■ Electrical Characteristics” is applied between VCC and VSS.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC andAVR), and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D is not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is
therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations
(P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the
transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power
is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up
from stop mode.
7. Treatment of Unused dedicated LCD pins
When dedicated LCD pins are not in use, keep them open.
12
MB89490 Series
■ PROGRAMMING AND ERASING FLASH MEMORY ON THE MB89F499
1. Flash Memory
The flash memory is located between 1000H and FFFFH in the CPU memory map and incorporates a flash
memory interface circuit that allows read access and program access from the CPU to be performed in the same
way as mask ROM. Programming and erasing flash memory is also performed via the flash memory interface
circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the
control of the CPU, providing an efficient method of updating program and data.
2. Flash Memory Features
• 60 K byte × 8-bit configuration (16 K + 8 K + 8 K + 28 K sectors)
• Automatic programming algorithm (Embedded algorithm* : Equivalent to MBM29LV200)
• Includes an erase pause and restart function
• Data polling and toggle bit for detection of program/erase completion
• Detection of program/erase completion via CPU interrupt
• Compatible with JEDEC-standard commands
• Sector Protection (sectors can be combined in any combination)
• No. of program/erase cycles : 10,000 (Min)
*: Embedded Algorithm is a trademark of Advanced Micro Devices.
3. Procedure for Programming and Erasing Flash Memory
Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or
erase flash memory, the program must first be copied from flash memory to RAM so that programming can be
performed without program access from flash memory.
4. Flash Memory Register
• Control status register (FMCS)
Address
007AH
Bit 7
INTE
R/W
Bit 6
Bit 5
WE
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Initial value
000X00-0B
RDYINT
RDY Reserved Reserved
Reserved
—
R/W
R/W
R
R/W
R/W
—
R/W
5. Sector Configuration
The table below shows the sector configuration of flash memory and lists the addresses of each sector for both
during CPU access a flash memory programming.
• Sector configuration of flash memory
Flash Memory
16 K bytes
8 K bytes
CPU Address
FFFFH to C000H
BFFFH to A000H
9FFFH to 8000H
7FFFH to 1000H
Programmer Address*
1FFFFH to 1C000H
1BFFFH to 1A000H
19FFFH to 18000H
17FFFH to 11000H
8 K bytes
28 K bytes
13
MB89490 Series
* : Programmer address
The programmer address is the address to be used instead of the CPU address when programming data
from a parallel flash memory programmer. Use the programmer address on programming or erasing using
a general purpose parallel programmer.
6. ROM Programmer Adaptor and Recommended ROM Programmers
Recommended Programmer
Adaptor Part No.
Manufacturer and Model
Ando Denki Co. Ltd.
Part number
Package
Sun Hayato Co. Ltd.
AF9708 (ver 1.60 or later)
AF9709 (ver 1.60 or later)
MB89F499PF
FPT-100P-M06
TBD
* Enquiries
Sunhayato Co. Ltd. : FAX +81-3-5396-9106
Ando Denki Co. Ltd. : TEL +81-44-549-7300
14
MB89490 Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C512-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
Adapter socket part number
LCC-32 (Rectangle)
ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3986-0403
3. Memory Space
Memory space in each mode is shown in the diagram below.
Address
0000H
Corresponding addresses on the EPROM programmer
Normal operating mode
I/O
0080H
RAM
0880H
1000H
Not available
1000H
PROM
60KB
EPROM
60KB
FFFFH
FFFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C512.
(2) Load program data into the EPROM programmer at 1000H to FFFFH.
(3) Program to 1000H to FFFFH with the EPROM programmer.
15
MB89490 Series
■ Block Diagram
X0
X1
Main clock
oscillator
21-bit timebase
timer
AVcc
AVss
AVR
Clock controller
Sub-clock
oscillator
(PLL x 1,2,4)
X0A
X1A
8
10-bit
A/D converter
P37/AN7/INT17
to
P30/AN0/INT10
Reset circuit
(Watchdog timer)
8
CMOS I/O port
RST
8
External interrupt 1
Watch prescaler
CMOS I/O port
(level)
P23
P47/SDA
P46/SCL
I2C
P26/PWM0
8-bit PWM timer 0
8-bit PWM timer 1
6
P45 to P40
P27/PWM1
P21/RMC
N-ch open-drain I/O port
CMOS I/O port
P84
P83
Remote receiver
P82/SCK1
P81/SO1
P80/SI1
8/16-bit
P22/EC0
P20/TO0
P25/EC1
P24/TO1
timer/counter 00,01
UART/SIO
SIO
8/16-bit
timer/counter 10,11
P52/SCK0
P51/SO0
P50/SI0
8
8
8
P17/INT07 to
P10/INT00
External interrupt 0
(edge)
CMOS I/O port
2
2
P54/COM3
to P53/COM2
CMOS I/O port
16
2
SEG0
t0 SEG15
P07 to P00
Port 0*1
CMOS I/O port
LCD controller/driver
COM0
to COM1
RAM (1K bytes / 2K bytes)
3
V1
32 × 4-bit display
RAM (16 bytes)
to V3
F2MC-8L
CPU
8
8
P67/SEG23
to P60/SEG16
16
P77/SEG31
to P70/SEG24
ROM (32K bytes / 48K bytes)
CMOS I/O port
Other pins
Vcc x 2, Vss x 2, MOD0
*1: High current I/O port.
16
MB89490 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89490 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89490 series is structured as illustrated below.
Memory Space
MB89498
MB89F499
MB89497
MB89PV490
I/O
0000
H
H
0000
0080
H
H
0000
0080
H
H
0000
0080
H
H
I/O
I/O
I/O
0080
RAM
RAM
RAM
RAM
0100
H
0100
H
0100
H
0100
H
General-
purpose
registers
General-
purpose
registers
H
General-
purpose
registers
H
General-
purpose
registers
0200
H
H
0200
0880
0200
0880
0200
H
H
H
H
0880
0480
Vacant
Vacant
1000
H
1000
H
Vacant
Vacant
FLASH
(60K)
External
ROM
(60K)
4000
H
8000
H
ROM
ROM
FFC0
FFFFH
FFC0
FFFFH
FFC0
FFFFH
FFC0
FFFFH
H
H
H
H
Vector table (reset, interrupt, vector call instruction)
17
MB89490 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following registers are provided:
Program counter (PC):
Accumulator (A):
A 16-bit register for indicating instruction storage positions.
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register for performing arithmetic operations with the accumulator.
Whenthe instruction is an 8-bitdata processing instruction, thelower byte is used.
Index register (IX):
Extra pointer (EP):
Stack pointer (SP):
Program status (PS):
A 16-bit register for index modification.
A 16-bit pointer for indicating a memory address.
A 16-bit register for indicating a stack area.
A 16-bit register for storing a register pointer, a condition code.
Initial value
16 bits
PC
A
: Program counter
: Accumulator
FFFDH
Undefined
Undefined
Undefined
Undefined
Undefined
T
: Temporary accumulator
: Index register
IX
EP
SP
PS
: Extra pointer
: Stack pointer
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
Z
1
0
PS
RP
Vacancy Vacancy Vacancy
H
IL1, 0
N
V
C
RP
CCR
18
MB89490 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set to "1" when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Clear
to "0" otherwise. This flag is for decimal adjustment instructions.
I-flag: Interrupt isallowed whenthis flag isset to "1". Interrupt isprohibited when theflag is setto"0". Clear to "0"
when reset.
IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
0
IL0
0
Interrupt level
Priority
High
1
0
1
1
0
2
3
1
1
Low = no interrupt
N-flag: Set to "1" if the MSB is set to "1" as the result of an arithmetic operation. Clear to "0" otherwise.
Z-flag: Set to "1" when an arithmetic operation results in "0". Clear to "0" otherwise.
V-flag: Set to "1" if a signed numeric value overflows because of an arithmetic calculation. Clear to "0" if the
overflow does not occur.
C-flag: Set to "1" when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Clear to
"0" otherwise. Set to the shift-out value in the case of a shift instruction.
19
MB89490 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers. Up to a total of 32 banks can be used on the MB89490 series. The bank currently in use is
indicated by the register bank pointer (RP).
Register Bank Configuration
This address = 0100H + 8 × (RP)
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
32 banks
Memory area
20
MB89490 Series
■ I/O MAP
Address
00H
Register name
PDR0
Register description
Port 0 data register
Read/Write
R/W
Initial value
XXXXXXXXB
00000000B
XXXXXXXXB
00000000B
00000000B
01H
DDR0
Port 0 data direction register
Port 1 data register
W*
02H
PDR1
R/W
03H
DDR1
Port 1 data direction register
Port 2 data register
W*
04H
PDR2
R/W
05H
(Reserved)
06H
DDR2
SYCC
STBC
WDTC
TBTC
Port 2 data direction register
System clock control register
Standby control register
R/W
R/W
R/W
W*
00000000B
X-1MM100B
00010XXXB
0---XXXXB
00---000B
07H
08H
09H
Watchdog timer control register
0AH
R/W
Timebase timer control register
Watch prescaler control register
0BH
WPCR
R/W
00--0000B
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
PDR3
DDR3
RSFR
PDR4
PDR5
DDR5
PDR6
DDR6
PDR7
DDR7
PDR8
DDR8
EIC0
R/W
R/W
R
XXXXXXXXB
00000000B
XXXX----B
Port 3 data register
Port 3 data direction register
Reset flag register
Port 4 data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
11111111B
---XXXXXB
---00000B
Port 5 data register
Port 5 data direction register
XXXXXXXXB
00000000B
XXXXXXXXB
00000000B
---XXXXXB
---00000B
Port 6 data register
Port 6 data direction register
Port 7 data register
Port 7 data direction register
Port 8 data register
Port 8 data direction register
External interrupt 0 control register 0
External interrupt 0 control register 1
External interrupt 0 control register 2
External interrupt 0 control register 3
External interrupt 1 enable register
External interrupt 1 flag register
Serial mode register
00000000B
00000000B
00000000B
00000000B
00000000B
-------0B
EIC1
EIC2
EIC3
EIE1
EIF1
SMR
00000000B
XXXXXXXXB
000000X0B
000000X0B
XXXXXXXXB
XXXXXXXXB
000000X0B
000000X0B
SDR
Serial data register
T01CR
T00CR
T01DR
T00DR
T11CR
T10CR
Timer 01 control register
Timer 00 control register
Timer 01 data register
Timer 00 data register
Timer 11 control register
Timer 10 control register
(Continued)
21
MB89490 Series
(Continued)
Address
26H
Register name
T11DR
T10DR
ADER
Register description
Timer 11 data register
Read/Write
R/W
R/W
R/W
R/W
R/W
R
Initial value
XXXXXXXXB
XXXXXXXXB
11111111B
-00000X0B
-0000001B
------XXB
27H
Timer 10 data register
28H
A/D input enable register
29H
ADC0
A/D control register 0
2AH
ADC1
A/D control register 1
2BH
ADDH
ADDL
A/D data register (Upper byte)
A/D data register (Lower byte)
PWM 0 timer control register
PWM 0 timer compare register
UART/SIO serial mode control register
UART/SIO serial mode control register
UART/SIO serial status/data register
UART/SIO serial data register
UART/SIO serial rate control register
PWM 1 timer control register
PWM 1 timer compare register
I2C bus status register
2CH
2DH
2EH
R
XXXXXXXXB
0-000000B
CNTR0
COMR0
SMC0
R/W
W*
XXXXXXXXB
00000000B
00000000B
00001---B
2FH
R/W
R/W
R/W
R/W
R/W
R/W
W*
30H
SMC1
31H
SSD
32H
SIDR/SODR
SRC
XXXXXXXXB
XXXXXXXXB
0-000000B
33H
34H
CNTR1
COMR1
IBSR
35H
XXXXXXXXB
00000000B
00000000B
000XXXXXB
XXXXXXXXB
XXXXXXXXB
----0000B
36H
R
I2C bus control register
I2C clock control register
I2C address register
I2C data register
37H
IBCR
R/W
R/W
R/W
R/W
R/W
38H
ICCR
39H
IADR
3AH
IDAR
3BH
PLLCR
Sub PLL control register
3CH to 3FH
40H
(Reserved)
RMN
RMC
Remote control counter register
Remote control control register
Remote control status register
Remote control FIFO data register
Remote control compare register 0
Remote control compare register 1
Remote control compare register 2
Remote control compare register 3
Remote control compare register 4
Remote control compare register 5
Remote interrupt register
R
XXXXXXXXB
00000000B
0X000001B
X----XXXB
41H
R/W
R/W
R
42H
RMS
43H
RMD
44H
RMCD0
RMCD1
RMCD2
RMCD3
RMCD4
RMCD5
RMCI
R/W
R/W
R/W
R/W
R/W
R/W
R/W
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
-110-000B
45H
46H
47H
48H
49H
4AH
4BH to 5DH
5EH
(Reserved)
LOCR
LCD
LCD controller output control register
LCD controller control register
LCD data RAM
R/W
R/W
R/W
R/W
R/W
-0000000B
00010000B
XXXXXXXXB
11111111B
11111111B
5FH
60H to 6FH
70H
VRAM
PURC0
PURC1
Port 0 pull up resistor control register
Port 1 pull up resistor control register
71H
(Continued)
22
MB89490 Series
(Continued)
Address
72H
Register name
PURC2
Register description
Port 2 pull up resistor control register
Port 3 pull up resistor control register
Port 5 pull up resistor control register
Port 6 pull up resistor control register
Port 7 pull up resistor control register
Port 8 pull up resistor control register
(Reserved)
Read/Write
R/W
Initial value
11111111B
11111111B
---11111B
73H
PURC3
R/W
74H
PURC5
R/W
75H
PURC6
R/W
11111111B
11111111B
-----111B
76H
PURC7
R/W
77H
PURC8
R/W
78H to 79H
7AH
FMCS
ILR1
ILR2
ILR3
ILR4
Flash memory control status registger
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Interrupt level setting register 4
(Reserved)
R/W
W*
W*
W*
W*
000X00-0B
11111111B
11111111B
11111111B
11111111B
7BH
7CH
7DH
7EH
7FH
* Bit manipulation instruction cannot be used.
■ Read/write access symbols
R/W : Readable and writable
R : Read-only
W : Write-only
■ Initial value symbols
0: The initial value of this bit is “0”.
1: The initial value of this bit is “1”.
X: The initial value of this bit is undefined.
- : Unused bit.
M: The initial value of this bit is determined by mask option.
23
MB89490 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
VCC
AVCC
VSS – 0.3
VSS + 4.0
V
AVCC must be equal to VCC
Power supply voltage
AVR
VSS – 0.3
VSS + 4.0
VCC
V
V
V
LCD power supply voltage
V1 to V3 VSS – 0.3
VSS – 0.3 VCC + 0.3
other than P40~P47
P40~P47 in MB89PV490,
MB89497/498
Input voltage
VI
VSS – 0.3
VSS – 0.3
VSS + 6.0
VSS + 5.5
V
V
V
P40~P47 in MB89F499
Output voltage
VO
VSS – 0.3 VCC + 0.3
15
“L” level maximum output current IOL
mA
Average value (operating current
× operating rate)
“L” level average output current
IOLAV
4
mA
mA
“L” level total maximum output
current
IOL
100
“L” level total average output
current
Average value (operating current
× operating rate)
IOLAV
40
–15
–4
mA
mA
mA
“H” level maximum output current IOH
Average value (operating current
× operating rate)
“H” level average output current
IOHAV
“H” level total maximum output
current
IOH
–50
mA
mA
“H” level total average output
current
Average value (operating current
× operating rate)
IOHAV
–20
300
Power consumption
Operating temperature
Storage temperature
PD
mW
°C
TA
–40
–55
+85
Tstg
+150
°C
Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
24
MB89490 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
Operation assurance
range
MB89PV490,
MB89F499
2.7*
2.2*
1.5
3.6
V
V
V
VCC
Operation assurance
range
MB89497,
MB89498
3.6
3.6
AVCC
Power supply voltage
Retains the RAM state in
stop mode
AVR
2.7
Vss
–40
3.6
Vcc
+85
V
V
LCD power supply voltage V1 to V3
Operating temperature TA
°C
* : These values depend on the operating conditions and the analog assurance range. See Figure 1, 2 and
“5. A/D Converter Electrical Characteristics.”
Operating
voltage (V)
3.6
Analog accuracy
assurance range :
Vcc = AVcc = 2.7V~3.6V
3.0
2.7
2.2
2.0
Main clock
operating freq. (MHz)
11.0 12.0 12.5
1.0
4.0
2.0
3.0
4.0
1.0
5.0
0.8
6.0
7.0
8.0
9.0 10.0
Min execution
2.0 1.33
0.66 0.57 0.50 0.44 0.4 0.36 0.33
0.32
time (inst. cycle) (µs)
Note : The shaded area is not assured for MB89F499
Figure 1 Operating Voltage vs. Main Clock Operating Frequency (MB89F499/497/498)
25
MB89490 Series
Operating
voltage (V)
3.6
3.5
Analog accuracy
assurance range :
Vcc = AVcc = 2.7V~3.6V
3.0
2.7
Main clock
operating Freq. (MHz)
11.0 12.0 12.5
1.0
4.0
2.0
3.0
4.0
1.0
5.0
0.8
6.0
7.0
8.0
9.0 10.0
Min execution
2.0 1.33
0.66 0.57 0.50 0.44 0.4
0.36 0.33
0.32
time (inst. cycle) (µs)
Figure 2 Operating Voltage vs. Main Clock Operating Frequency (MB89PV490)
Figure 1 and 2 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating
speed is switched using a gear.
26
MB89490 Series
3. DC Characteristics
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
Pin
P00 ~ P07,
Condition
Unit
Remarks
Min.
Typ.
Max.
P10 ~ P17,
P20 ~ P27,
P30 ~ P37,
P50 ~ P54,
P60 ~ P67,
P70 ~ P77,
P80 ~ P84,
SCL, SDA,
MOD1, MOD2
—
0.7 VCC
—
VCC + 0.3
V
VIH
“H” level
input voltage
MB89PV490,
MB89497/498
—
—
0.7 VCC
0.7 VCC
—
—
VSS + 6.0
VSS + 5.5
V
V
P40 ~ P47
MB89F499
RST, MOD0, EC0,
EC1, SCK0, SI0,
SCK1, SI1, RMC,
INT00 ~ INT07
VIHS
—
—
0.8 VCC
—
—
VCC + 0.3
VCC + 0.3
V
V
VIHA
INT10 ~ INT17
0.85 VCC
P00 ~ P07,
P10 ~ P17,
P20 ~ P27,
P30 ~ P37,
P40 ~ P47,
P50 ~ P54,
P60 ~ P67,
P70 ~ P77,
P80 ~ P84,
SCL, SDA,
MOD1, MOD2
VIL
—
VSS − 0.3
—
0.3 VCC
V
“L” level
input voltage
RST, MOD0, EC0,
EC1, SCK0, SI0,
SCK1, SI1, RMC,
INT00 ~ INT07
VILS
VILA
VD
—
VSS − 0.3
—
0.2 VCC
V
INT10 ~ INT17
—
—
—
VSS − 0.3
VSS − 0.3
VSS − 0.3
—
—
—
0.5 VCC
VSS + 6.0
VSS + 5.5
V
V
V
Open-drain
output pin
application
voltage
MB89PV490,
MB89497/498
P40 ~ P47
MB89F499
P10 ~ P17,
P20 ~ P27,
P30 ~ P37,
P50 ~ P54,
P60 ~ P67,
P70 ~ P77,
P80 ~ P82
IOH = -2.0 mA
IOH = -4.0 mA
2.2
2.2
—
—
—
—
V
V
“H” level
output voltage
VOH
P00 ~ P07
(Continued)
27
MB89490 Series
(Continued)
Value
Typ.
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min.
Max.
P10 ~ P17,
P20 ~ P27,
P30 ~ P37,
P50 ~ P54,
P60 ~ P67,
P70 ~ P77,
P80 ~ P82, RST
IOL = 4.0 mA
—
—
0.4
V
“L” level
output voltage
VOL
P00 ~ P07
P40 ~ P47
IOL = 12.0 mA
IOL = 15.0 mA
—
—
—
—
0.4
0.4
V
V
P00 ~ P07,
P10 ~ P17,
P20 ~ P27,
P30 ~ P37,
P40 ~ P47,
P50 ~ P54,
P60 ~ P67,
P70 ~ P77,
P80 ~ P84
Without
pull-up
resistor
Input leakage
current
ILI
0.45 V < VI < VCC
−5
—
+5
µA
Open-drain
outputleakage ILOD
current
P40 ~ P47
MOD0
0.0 V < VI < VCC
VI = VCC
−5
—
+5
µA
kΩ
Pull-down
Except
MB89F499
RDOWN
25
50
100
resistance
P00 ~ P07,
P10 ~ P17,
P20 ~ P27,
P30 ~ P37,
P50 ~ P54,
P60 ~ P67,
P70 ~ P77,
P80 ~ P82,
RST
When pull-up
resistor is
selected
(except RST)
Pull-up
resistance
RPULL
VI = 0.0 V
25
50
100
kΩ
Common
output
impedance
RVCOM
COM0 to COM3 V1 to V3 = +3.0 V
SEG0 to SEG31 V1 to V3 = +3.0 V
—
—
2.5
kΩ
Segment
output
impedance
RVSEG
—
—
15
kΩ
kΩ
LCD divided
resistance
Between VCC and
—
RLCD
300
500
750
V
SS
LCD
controller/
driver
leakage
current
V1 to V3,
COM0 to COM3,
SEG0 to SEG31
ILCDL
—
-1
—
+1
µA
(Continued)
28
MB89490 Series
(Continued)
Value
Typ.
Parameter
Symbol
Pin
Condition
FCH = 10 MHz
tinst = 0.4 µs
Main clock run mode
Unit
Remarks
Min.
—
—
—
—
—
—
—
—
—
—
—
Max.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MB89PV490,
MB89497/498
3.5
6.0
mA
ICC1
mA MB89F499
MB89PV490,
mA
FCH = 10 MHz
tinst = 6.4 µs
Main clock run mode
0.4
MB89497/498
ICC2
1.5
mA MB89F499
MB89PV490,
mA
FCH = 10 MHz
tinst = 0.4 µs
Main clock sleep mode
1.2
MB89497/498
ICCS1
ICCS2
ICCL
2.0
mA MB89F499
MB89PV490,
mA
FCH = 10 MHz
tinst = 6.4 µs
Main clock sleep mode
0.4
MB89497/498
1.0
mA MB89F499
MB89PV490,
µA
FCL = 32.768 kHz
Sub-clock mode
TA = +250C
22.0
35.0
120.0
MB89497/498
VCC
µA MB89F499
Power supply
current
FCL = 32.768 kHz
Sub-clock mode
TA = +250C
MB89PV490,
µA
MB89497/498
ICCLPLL
ICCLS
ICCT
—
150.0
TBD
µA MB89F499
sub PLL x 4
MB89PV490,
µA
FCL = 32.768 kHz
Sub-clock sleep mode
TA = +250C
—
—
—
7.0
15.0
1.0
TBD
TBD
TBD
MB89497/498
MB89F499
µA
µA
FCL = 32.768 kHz
Watch mode
MB89PV490,
MB89497/498
Main clock stop mode
TA = +250C
—
—
5.0
0.8
TBD
TBD
MB89F499
µA
MB89PV490,
MB89497/498
µA
µA
TA = +250C
Sub-clock stop mode
ICCH
—
—
—
1.0
1.0
0.8
TBD
3.0
MB89F499
IA
AVcc = 3.0 V, TA = +250C
TA = +250C
mA A/D converting
AVcc
IAH
4.0
µA A/D stop
Other than
VCC, VSS, AVCC, f = 1 MHz
AVSS, AVR
Input
capacitance
CIN
—
10.0
—
pF
29
MB89490 Series
4. AC Characteristics
(1) Reset Timing
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Condition
Unit
Remarks
Parameter
Min.
Max.
RST “L” pulse width
tZLZH
—
48 tHCYL
—
ns
Note: tHCYL is the oscillation cycle (1/FCH) to input to the X0 pin.
The MCU operation is not guaranteed when the "L" pulse width is shorter than tZLZH.
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Condition
Unit
Remarks
Parameter
Min.
—
Max.
Power supply rising time
Power supply cut-off time
tR
50
—
ms
ms
—
tOFF
1
Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time.
Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to
be varied in the course of operation, a smooth voltage rise is recommended.
tOFF
tR
1.5 V
0.2 V
0.2 V
0.2 V
V
CC
30
MB89490 Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Typ.
—
Symbol
Pin
Unit
Remarks
Parameter
Clock frequency
Clock cycle time
Min.
1
Max.
FCH
X0, X1
12.5 MHz
FCL
X0A, X1A
X0, X1
—
32.768
—
75
1000
—
kHz
ns
tHCYL
tLCYL
80
X0A, X1A 13.3
30.5
µs
PWH
PWL
X0
20
—
—
—
15.2
—
—
—
10
ns
µs
ns
Input clock pulse width
PWHL
PWLL
X0A
External clock
tCR
tCF
Input clock rising/falling time
X0, X0A
X0 and X1 Timing and Conditions
t
HCYL
P
WH
P
WL
t
CR
t
CF
0.8 VCC
0.8 VCC
X 0
0.2 VCC
0.2 VCC
0.2 VCC
Main Clock Conditions
When a crystal
or
When an external clock is used
ceramic reasonator is used
X0
X1
X0
X1
Open
F
CH
F
CH
C1
C2
31
MB89490 Series
Sub-clock Timing and Conditions
t
LCYL
0.8 VCC
0.2 VCC
X0A
PWHL
PWLL
t
CR
t
CF
Sub-clock Conditions
When a crystal
or
ceramic oscillator is used
When an external clock is used
When subclock is not used
X0A
X1A
X0A
X1A
X0A
X1A
FCL
Rd
Open
Open
FCL
C0
C1
(4) Instruction Cycle
Symbol
Value
Unit
Remarks
Parameter
(4/FCH)tinst = 0.32 µs when operating
at FCH = 12.5 MHz
4/FCH, 8/FCH, 16/FCH, 64/FCH
2/FCL, 1/2FCL
µs
µs
Instruction cycle
(minimum execution time)
tinst
(2/FCL)tinst = 61.036 µs when
operating at FCL = 32.768 kHz
32
MB89490 Series
PLL operation guarantee range
(subPLL x 4)
Relationship between internal operating clock frequency and power supply voltage
Operating
voltage (V)
subPLL operating guarantee range
3.6
3.0
2.7
2.5
2.0
Internal operating clock freq. (kHz)
131.072
15.625
300
Min execution
time (inst. cycle) (µs)
6.67
Not assured for MB89F499, MB89PV490.
Relationship between subclock oscillating frequency and instruction cycle when
subPLL is enabled
15.625
Multiplied-
by-4
6.67
32.768
75
Oscillation clock FCL (kHz)
33
MB89490 Series
(5) Serial I/O Timing
(AVCC = VCC = 3.0 V, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Condition
Unit
Parameter
Min.
2 tinst*
–200
Max.
—
Serial clock cycle time
SCK ↓ → SO time
tSCYC
tSLOV
tIVSH
tSHIX
SCK0, SCK1
µs
ns
µs
µs
µs
µs
ns
µs
µs
Internal
shift clock
mode
SCK0, SCK1, SO0, SO1
SI0, SI1, SCK0, SCK1
SCK0, SCK1, SI0, SI1
200
—
Valid SI → SCK ↑
1/2 tinst*
1/2 tinst*
1 tinst*
1 tinst*
0
SCK ↑ → valid SI hold time
—
Serial clock “H” pulse width tSHSL
—
SCK0, SCK1
Serial clock “L” pulse width
SCK ↓ → SO time
tSLSH
tSLOV
tIVSH
—
External
shift clock
mode
SCK0, SCK1, SO0, SO1
SI0, SI1, SCK0, SCK1
SCK0, SCK1, SI0, SI1
200
—
Valid SI → SCK ↑
1/2 tinst*
1/2 tinst*
SCK ↑ → valid SI hold time tSHIX
—
* : For information on tinst, see “(4) Instruction Cycle.”
Internal Clock Operation
t
SCYC
SCK0, SCK1
2.4 V
0.8 V
0.8 V
tSLOV
SO0, SO1
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SI0, SI1
External Clock Operation
t
SLSH
t
SHSL
SCK0, SCK1
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
SO0, SO1
2.4 V
0.8 V
t
IVSH
t
SHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SI0, SI1
34
MB89490 Series
(6) I2C Timing
(Vcc = 3.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin Condition
Unit Remarks
Parameter
Min.
Max.
1/4tinst*1 x
M x N - 20
SCL
SDA
1/4tinst x
M x N + 20
master
mode
Start condition output tSTA
Stop condition output tSTO
Start condition detect tSTA
ns
ns
1/4tinst x
(M*2 x N*3 + 8) +
20
SCL
SDA
1/4tinst x
(M x N + 8) - 20
master
mode
SCL
SDA
1/4tinst x 6 + 40
—
ns
ns
ns
ns
ns
SCL
SDA
Stop condition detect tSTO
Re-start condition
1/4tinst x 6 + 40
—
SCL
SDA
1/4tinst x
1/4tinst x
master
mode
tSTASU
tSTASU
tLOW
output
(M x N + 8) - 20 (M x N + 8) + 20
Re-start condition
detect
SCL
SDA
1/4tinst x 4 + 40
—
SCL output LOW
width
1/4tinst x
M x N - 20
1/4tinst x
M x N + 20
master
mode
SCL
SCL output HIGH
width
1/4tinst x
1/4tinst x
master
mode
tHIGH
tDO
SCL
SDA
SDA
ns
ns
ns
(M x N + 8) - 20 (M x N + 8) + 20
SDA output delay
1/4tinst x 4 - 20
1/4tinst x 4 + 20
SDA output setup
time after interrupt
4
tDOSU
1/4tinst x 4 - 20
—
*
SCL input LOW
pulse width
tLOW
tHIGH
SCL
SCL
1/4tinst x 6 + 40
1/4 tinst x 2 + 40
—
—
ns
ns
SCL input HIGH
pulse width
SDA input setup time tSU
SDA hold time tHO
SDA
SDA
40
0
—
—
ns
ns
*1: For information in tinst, see "(4) Instruction Cycle".
*2: M is defined in the ICCR CS4 and CS3 (bit 4 to bit 3). For details, please refer to the H/W manual register
explanation.
*3: N is defined in the ICCR CS2 to CS0 (bit 2 to bit 0)
*4: When the interrupt period is grater than SCL "L" width, SDA and SCL output (Standard) value is based on
hypothesis when rising time is 0 ns.
Data transmit (master/slave)
tSU
tHO
tDO
tDO
tDOSU
SDA
ACK
tSTASU
tSTA
tLOW
tHO
SCL
1
9
Data receive (master/slave)
tSU
tHO
tDO
tDO
tDOSU
SDA
SCL
ACK
9
tLOW
t
HIGH
tSTO
6
7
8
35
MB89490 Series
(7) Peripheral Input Timing
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Unit
Remarks
Parameter
Min.
2 tinst*
2 tinst*
Max.
—
Peripheral input “H” pulse width 1
Peripheral input “L” pulse width 1
tILIH1
tIHIL1
µs
µs
EC0, EC1, RMC, INT00 ~
INT07, INT10 ~ INT17
—
* : For information on tinst, see “(4) Instruction Cycle.”
t IHIL1
t ILIH1
EC0, EC1, RMC,
INT00 ~ INT07
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
t IHIL1
t ILIH1
INT10 to INT17
0.85 VCC
0.85 VCC
0.5 VCC
0.5 VCC
36
MB89490 Series
5. A/D Converter Electrical Characteristics
(1) A/D Converter Electrical Characteristics
(AVCC = VCC = 2.7 V ~ 3.6 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Resolution
Symbol
Pin
Unit
Remarks
Min.
—
Typ.
10
Max.
—
bit
Total error
—
—
±3.0
±2.5
±1.9
LSB
LSB
LSB
—
Linearity error
—
—
Differential linearity error
Zero transition voltage
—
—
—
VOT
AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB mV
Full-scale transition
voltage
VFST
AVCC – 3.5 LSB AVCC – 1.5 LSB AVCC - 0.5 LSB
mV
A/D mode conversion time
Analog port input current
Analog input voltage
Reference voltage
—
IAIN
VAIN
—
—
—
—
—
—
38 tinst*
µs
µA
V
—
10
AN0 to
AN7
AVSS
AVR
AVCC
AVSS + 2.7
V
A/D is
activated
IR
—
—
200
—
TBD
5
µA
µA
AVR
Reference voltage supply
current
A/D is
stopped
IRH
* : For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics".
(2) A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
The deviation of the straight line connecting the zero transition point ("00 0000 0000" ↔ "00 0000 0001") with
the full-scale transition point ("11 1111 1111" ↔ "11 1111 1110") from actual conversion characteristics.
• Differential linearity error (unit: LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value.
• Total error (unit: LSB)
The difference between theoretical and actual conversion values.
37
MB89490 Series
Theoretical I/O characteristics
Total error
3FF
3FE
3FD
3FF
3FE
3FD
V
FST
Actual conversion
value
1.5 LSB
{1 LSB × N + VOT
}
004
003
002
001
004
003
002
001
V
NT
VOT
Actual conversion
value
1 LSB
Theoretical value
0.5 LSB
AVCC
AVCC
AVSS
AVSS
Analog input
Analog input
V
NT – {1 LSB × N + 0.5 LSB}
1 LSB
V
FST – VOT
1022
Total error =
1 LSB =
(V)
Zero transition error
Full-scale transition error
Theoretical value
004
Actual conversion
value
3FF
3FE
3FD
3FC
Actual conversion
value
003
002
001
V
(Actual
measurement)
FST
Actual conversion
value
Actual conversion value
V
OT (Actual measurement)
Analog input
AVCC
AVSS
Analog input
Differential linearity error
Theoretical value
Linearity error
3FF
3FE
3FD
Actual conversion
value
N + 1
Actual conversion
value
{1 LSB × N + VOT
}
V
(N + 1)T
V
(Actual
FST
N
V
NT
measurement)
004
003
002
001
N – 1
N – 2
V
NT
Actual conversion value
Actual conversion value
Theoretical value
V
OT (Actual measurement)
AVCC
AVSS
AVCC
AVSS
Analog input
Analog input
VNT – {1 LSB × N + VOT}
1 LSB
V
(N + 1)T – VNT
1 LSB
Linearity error =
– 1
Differential linearity error =
38
MB89490 Series
(3) Notes on Using A/D Converter
• Input impedance of the analog input pins
The A/D converter used for the MB89490 series contains a sample and hold circuit as illustrated below to fetch
analog inputvoltage into the sample and hold capacitor for 16 instruction cycles after activation A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low.
Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about
0.1 µF for the analog input pin.
Sample hold circuit
Analog Input Circuit Model
Analog input pin
Comparator
If the analog input
impedance is higher
R
C
than 10 kΩ, it is
recommended to
connect an external
capacitor of approx.
0.1 µF.
Close for 16 instruction cycles after
activating A/D conversion.
Analog channel selector
MB89F499
2.4 kΩ
MB89PV490/MB89497/MB89498
R: analog input equivalent resistance
C: analog input equivalent capacitance
2.4 kΩ
52 pF
53 pF
39
MB89490 Series
■ MASK OPTIONS
Part number
MB89497
MB89498
MB89F499
MB89PV490
No.
Specify when
ordering mask
Specifying procedure
Setting not possible
Selection of oscillation
stabilization time (OSC)
• The initial value of the
oscillationstabilization
time for the main clock
can be set by
selecting the values of
the WTM1 and WTM0
bit on the right.
Selectable
OSC
Fixed to oscillation
1
1
2
3
: 210/FCH
: 214/FCH
: 218/FCH
stabilization time of 218/FCH
40
MB89490 Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89497PF
MB89498PF
MB89F499PF
100-pin Plastic QFP
(FPT-100P-M06)
100-pin Ceramic MQFP
(MQP-100C-P01)
MB89PV490CF
41
MB89490 Series
■ PACKAGE DIMENSIONS
100-pin Plastic QFP
FPT-100P-M06
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00 +–00..2305
.118 +–..000184
(Mounting height)
0~8°
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.17±0.06
(.007±.002)
M
0.13(.005)
0.25±0.20
(.010±.008)
(Stand off)
0.80±0.20
(.031±.008)
"A"
0.88±0.15
(.035±.006)
Dimensions in mm (inches)
C
2001 FUJITSU LIMITED F100008S-c-4-4
(Continued)
42
MB89490 Series
(Continued)
100-pin ceramic MQFP
MQP-100C-P01
18.70(.736)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.35(.486)TYP
0.65±0.15
INDEX AREA
1.20 –+00..2400
.047 –+..000186
(.0256±.0060)
0.65±0.15
(.0256±.0060)
1.27±0.13
(.050±.005)
18.12±0.20
(.713±.008)
22.30±0.33
(.878±.013)
12.02(.473)
TYP
18.85(.742)
TYP
10.16(.400)
14.22(.560)
TYP
0.30(.012)
TYP
24.70(.972)
TYP
TYP
0.30±0.08
(.012±.003)
1.27±0.13
(.050±.005)
0.30(.012)TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
0.30±0.08
(.012±.003)
1.20 –+00..2400
.047 –+..000186
10.82(.426)
MAX
0.15±0.05
(.006±.002)
C
1994 FUJITSU LIMITED M100001SC-1-2
43
MB89490 Series
MEMO
44
MB89490 Series
FUJITSU LIMITED
For further information please contact:
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The contents of this document are subject to change
without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
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presented as examples of semiconductor device
applications, and are not intended to be incorporated in
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F0208
FUJITSU LIMITED Printed in Japan
45
相关型号：
MB89PV530-101C
Microcontroller, 8-Bit, 12.5MHz, CMOS, CDIP64, 1.778 MM PITCH, CERAMIC, DIP-64
FUJITSU
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