MB90224PF [FUJITSU]
16-bit Proprietary Microcontroller; 16位微控制器专有
| 型号： | MB90224PF |
| 厂家： | 
FUJITSU |
| 描述： | 16-bit Proprietary Microcontroller |
| 文件： | 总105页 (文件大小：1602K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13502-5E
16-bit Proprietary Microcontroller
CMOS
F2MC-16F MB90220 Series
MB90223/224/P224A/W224A
MB90P224B/W224B/V220
■ OUTLINE
The MB90220 series of general-purpose high-performance 16-bit microcontrollers has been developed primarily
for applications that demand high-speed real-time processing and is suited for industrial applications, office
automation equipment, process control, and other applications. The F2MC-16F CPU is based on the F2MC*-16
Family with improved high-level language support functions and task switching functions, as well as additional
addressing modes.
On-chip peripheral resources include a 4-channel PWC timer, a 4-channel ICU (Input Capture Unit), a 1-channel
24-bit timer counter, an 8-channel OCU (Output Compare Unit), a 6-channel 16-bit reload timer, a 2-channel
16-bit PPG timer, a 10-bit A/D converter with 16 inputs, and a 4-channel serial port with a UART function (one
channel includes the CTS function).
The MB90P224B, MB90W224B, MB90224 is under development.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ PACKAGE
120-pin Plastic QFP
120-pin Ceramic QFP
(FPT-120P-M03)
(FPT-120C-C02)
MB90220 Series
■ FEATURES
F2MC-16F CPU
• Minimum execution time: 62.5 ns/16 MHz oscillation (using a duty control system)
• Instruction sets optimized for controllers
Upward object-compatible with the F2MC-16(H)
Various data types (bit, byte, word, and long-word)
Instruction cycle improved to speed up operation
Extended addressing modes: 25 types
High coding efficiency
Access method (bank access with linear pointer)
Enhanced multiplication and division instructions (with signed instructions added)
Higher-precision operation using a 32-bit accumulator
• Extended intelligent I/O service (automatic transfer function independent of instructions)
Access area expanded to 64 Kbytes
• Enhanced instruction set applicable to high-level language (C) and multitasking
System stack pointer
Enhanced pointer-indirect instructions
Barrel shift instruction
Stack check function
• Increased execution speed: 8-byte instruction queue
• Powerful interrupt functions: 8 levels and 28 sources
Peripheral resources
• Mask ROM
: 64 Kbytes (MB90223)
96 Kbytes (MB90224)
EPROM
: 96 Kbytes (MB90W224A/W224B)
• One-time PROM : 96 Kbytes (MB90P224A/P224B)
• RAM: 3 Kbytes (MB90223)
4.5 Kbytes (MB90224/MB90W224A/P224A/W224B/P224B)
5 Kbytes (MB90V220)
• General-purpose ports: max. 102 channels
• ICU (Input Capture Unit): 4 channels
• 24-bit timer counter: 1 channel
• OCU (Output Compare Unit): 8 channels
• PWC timer with time measurement function: 4 channels
• 10-bit A/D converter: 16 channels
• UART: 4 channels (one channel includes CTS function)
• 16-bit reload timer
Toggled output, external clock, and gate functions: 6 channels
• 16-bit PPG timer: 2 channels
• DTP/External-interrupt inputs: 8 channels (of which five have edge detection function only)
• Write-inhibit RAM: 0.5 Kbytes (1 Kbyte for MB90V220)
• Timebase counter: 18 bits
• Clock gear function
• Low-power consumption mode
Sleep mode
Stop mode
Hardware standby mode
2
MB90220 Series
Product description
• MB90223/224 are mask ROM product.
• MB90P224A/P224B are one-time PROM products.
• MB90W224A/W224B are EPROM products. ES only.
• Operating temperature of MB90P224A/W224A is –40°C to +85°C.
(However, the AC characteristics is assured in –40°C to +70°C)
• Operation clock cycle of MB90223 is 10 MHz to 12 MHz.
• MB90V220 is a evaluation device for the program development. ES only.
■ PRODUCT LINEUP
Part number
MB90P224A
MB90P224B
MB90W224A
MB90V220
MB90223
MB90224
MB90W224B
Item
Classification
Mask ROM
product
Mask ROM
product
One-time
PROM product
EPROM
product
Evaluation
device
ROM size
64 Kbytes
3 Kbytes
96 Kbytes
4.5 Kbytes
96 Kbytes
4.5 Kbytes
96 Kbytes
4.5 Kbytes
None
RAM size
5 Kbytes
CPU functions
The number of instructions:
Instruction bit length:
Instruction length:
412
8 or 16 bits
1 to 7 bytes
Data bit length:
Minimum execution time:
Interrupt processing time:
1, 4, 8, 16, or 32 bits
62.5 ns/16 MHz
1.0 µs/16 MHz (min.)
Ports
I/O ports (N-ch open-drain):
I/O ports (CMOS):
Total:
16
86
102
ICU
Number of channels: 4
Rising edge/falling edge/both edges selectable
(Input Capture Unit)
24-bit timer
counter
Number of channels: 1
Overflow interrupt, intermediate bit interrupt
OCU
(Output Compare Unit)
Number of channels: 8
Pin change source (match signal causes register value transfer/general-purpose port)
PWC timer
Number of channels: 4
16-bit reload timer operation (operation clock cycle: 0.25 µs to 1.31 ms)
16-bit pulse-width count operation (Allowing continuous/one-shot measurement, H/L width
measurement, inter-edge measurement, and divided-frequency measurement)
10-bit
A/D converter
Resolution: 10 bits
Number of inputs: 16
Single conversion mode (conversion of each channel)
Scan conversion mode (continuous conversion for up to 16 consecutive channels)
Continuous conversion mode (repeated conversion of specified channel)
Stop conversion mode (conversion every fixed cycle)
UART
Number of channels: 4 (1 channel with CTS function)
Clock-synchronous transfer mode
(full-duplex double buffering, 7 to 9-bit data length, 2400 to 62500 bps)
Asynchronous transfer mode
(full-duplex double buffering, 7 to 9-bit data length, 2400 to 62500 bps)
16-bit reload
timer
Number of channels: 6
16-bit reload timer operation (operation clock cycle: 0.25 µs to 1.05 s)
(Continued)
3
MB90220 Series
(Continued)
Part number
MB90223
Item
MB90P224A
MB90P224B
MB90W224A
MB90W224B
MB90224
MB90V220
16-bit PPG timer
Number of channels: 2
16-bit PPG operation (operation clock cycle: 0.25 µs to 6 s)
DTP/External
interrupts
Number of inputs: 8 (of which five have edge detection function only)
External interrupt mode (allowing interrupts to activate at four different request levels)
Simple DMA transfer mode (allowing extended I2OS to activate at two different request levels)
Write-inhibited
RAM
RAM size: 512 bytes (1 Kbyte for MB90V220)
RAM write-protectable with WI pin
Standby mode
Gear function
stop mode (activated by software or hardware) and sleep mode
Machine clock operation frequency switching: 16 MHz, 8 MHz, 4 MHz, 1 MHz (at
16-MHz oscillation)
Package
FPT-120P-M03
FPT-120C-C02 PGA-256C-A02
Note: MB90V220 is a evaluation device, therefore, the electrical characteristics are not assured.
■ DIFFERENCES BETWEEN MB90223/224 (MASK ROM PRODUCT) AND MB90P224A/
W224A/P224B/W224B
Part number
MB90P224A
MB90P224B
MB90W224A
MB90W224B
MB90223
MB90224
Item
ROM
Mask ROM
64 Kbytes
Mask ROM
96 Kbytes
OTPROM
96 Kbytes
EPROM
96 Kbytes
Pin functions: pin 87
MD2 pin
MD2/VPP pin
4
MB90220 Series
■ PIN ASSIGNMENT
(Top view)
VSS
X0 92
X1 93
91
60 PA5/INT0
59 PA4/PWC3/POT3/ASR3
58 PA3/PWC2/POT2/ASR2
57 PA2/PWC1/POT1/ASR1
56 PA1/PWC0/POT0
55 PA0/ASR0
54 VCC
53 P67/AN07
52 P66/AN06
51 P65/AN05
50 P64/AN04
49 P63/AN03
48 P62/AN02
47 P61/AN01
46 P60/AN00
45 AVSS
VCC
94
P00/D00 95
P01/D01 96
P02/D02 97
P03/D03 98
P04/D04 99
P05/D05 100
P06/D06 101
P07/D07 102
P10/D08 103
P11/D09 104
P12/D10 105
P13/D11 106
P14/D12 107
P15/D13 108
P16/D14 109
P17/D15 110
P20/A00 111
P21/A01 112
P22/A02 113
P23/A03 114
P24/A04 115
P25/A05 116
P26/A06 117
P27/A07 118
VSS 119
44 AVRL
43 AVRH
42 AVCC
41 P97/AN15
40 P96/AN14
39 P95/AN13
38 P94/AN12
37 P93/AN11
36 P92/AN10
35 P91/AN09
34 P90/AN08
33 VSS
32 P87/PPG1
31 P86/PPG0
P30/A08 120
(FPT-120P-M03)
(FPT-120C-C02)
5
MB90220 Series
■ PIN DESCRIPTION
Pin no.
Circuit
Pin name
Function
Crystal oscillation pins (16 MHz)
type
QFP*
92,
93
X0,
X1
A
89 to 87
MD0 to MD2
D
Operation mode specification input pins
Connect directly to VCC or VSS.
90
86
RST
HST
G
E
C
External reset request input
Hardware standby input pin
95 to 102 P00 to P07
General-purpose I/O ports
This function is valid only in single-chip mode.
D00 to D07
Output pins for low-order 8 bits of the external address bus.
This function is valid only in modes where the external bus is
enabled.
103 to 110 P10 to P17
D08 to D15
C
General-purpose I/O ports
This function is valid only in single-chip mode or when the external bus
is enabled and the 8-bit data bus specification has been made.
I/O pins for higher-order 8 bits of the external data bus
This function is valid only when the external bus is enabled and the
16-bit bus specification has been made.
111 to 118 P20 to P27
A00 to A07
C
C
General-purpose I/O ports
This function is valid only in single-chip mode.
Output pins for lower-order 8 bits of the external address bus
This function is valid only in modes where the external bus is
enabled.
120,
P30,
General-purpose I/O ports
1 to 7
P31 to P37
This function is valid either in single-chip mode or when the address
mid-order control register specification is “port”.
A08,
A09 to A15
Output pins for mid-order 8 bits of the external address bus
This function is valid in modes where the external bus is enabled and
the address mid-order control register specification is “address”.
9 to 11
P40 to P42
A16 to A18
P43 to P47
C
C
General-purpose I/O ports
This function is valid either in single-chip mode or when the address
high-order control register specification is “port”.
Output pins for higher-order 8 bits of the external address bus
This function is valid in modes where the external bus is enabled and
the address high-order control register specification is “address”.
12 to 16
General-purpose I/O ports
This function is valid when either single-chip mode is enabled or the
address higher-order control register specification is “port”.
A19 to A23
Output pins for higher-order 8 bits of the external address bus
This function is valid in modes where the external bus is enabled and
the address higher-order control register specification is “address”.
TIN1 to TIN5
16-bit reload timer input pins
This function is valid when the timer input specification is “enabled”.
The data on the pins is read as timer input (TIN1 to TIN5).
* : FPT-120P-M03, FPT-120C-C02
6
(Continued)
MB90220 Series
Pin no.
QFP*
Circuit
type
Pin name
Function
External interrupt request input pins
12 to 16
INT3 to INT7
C
When external interrupts are enabled, these inputs may be used
suddenly at any time; therefore, it is necessary to stop output by other
functions on these pins, except when using them for output
deliberately.
78
P50
C
General-purpose I/O port
This function is valid in single-chip mode and when the CLK output
specification is disabled.
CLK
P51
RDY
P52
HAK
P53
HRQ
CLK output pin
This function is valid in modes where the external bus is enabled and
the CLK output specification is enabled.
79
80
81
C
C
C
General-purpose I/O port
This function is valid in single-chip mode or when the ready function
is disabled.
Ready input pin
This function is valid in modes where the external bus is enabled and
the ready function is enabled.
General-purpose I/O port
This function is valid in single-chip mode or when the hold function is
disabled.
Hold acknowledge output pin
This function is valid in modes where the external bus is enabled and
the hold function is enabled.
General-purpose I/O port
This function is valid in single-chip mode or external bus mode and
when the hold function is disabled.
Hold request input pin
This function is valid in modes where the external bus is enabled and
the hold function is enabled.
During this operation, the input may be used suddenly at any time;
therefore, it is necessary to stop output by other fuctions on this pin,
except when using it for output deliberately.
82
83
P54
C
C
General-purpose I/O port
This function is valid in single-chip mode, when the external bus is in
8-bit mode, or when WRH pin output is disabled.
WRH
P55
Write strobe output pin for the high-order 8 bits of the data bus
This function is valid in modes where the external bus is enabled, the
external bus is in 16-bit mode, and WRH pin output is enabled.
General-purpose I/O port
This function is valid in single-chip mode or when WRL pin output is
disabled.
WRL
Write strobe output pin for the low-order 8 bits of the data bus
This function is valid in modes where the external bus is enabled and
WRL pin output is enabled.
* : FPT-120P-M03, FPT-120C-C02
(Continued)
7
MB90220 Series
Pin no.
Circuit
Pin name
P56
Function
type
QFP*
84
C
General-purpose I/O port
This function is valid in single-chip mode. This function is valid in
modes where the external bus is valid.
RD
Read strobe output pin for the data bus
This function is valid in modes where the external bus is enabled.
85
P57
B
General-purpose I/O port
This function is always valid.
When these pins are open in input mode, through current may leak in
stop mode/reset mode, be sure to fix these pins to VCC/VSS level to
use these pins in input mode.
WI
RAM write disable request input
During this operation, the input may be used suddenly at any time;
therefore, it is necessary to stop output by other fuctions on this pin,
except when using it for output deliberately.
46 to 53
P60 to P67
AN00 to AN07
P70 to P77
F
Open-drain I/O ports
This function is valid when the analog input enable register
specification is “port”.
10-bit A/D converter analog input pins
This function is valid when the analog input enable register
specification is “analog input”.
17 to 24
25 to 30
C
General-purpose I/O ports
This function is valid when the output specification for DOT0 to DOT7
is “disabled”.
DOT0 to DOT7
P80 to P85
This function is valid when OCU (output compare unit) output is
enabled.
C
C
General-purpose I/O ports
This function is valid when the output specification for TOT0 to TOT5
is “disabled”.
TOT0 to TOT5
16-bit reload timer output pins (TOT0 to TOT5)
31,
32
P86,
P87
General-purpose I/O ports
This function is valid when the PPG0, and PPG1 output specification
is “disabled”.
PPG0,
PPG1
16-bit PPG timer output pins
This function is valid when the PPG control/status register
specification is “PPG output pins”.
34 to 41
P90 to P97
F
Open-drain I/O ports
This function is valid when the analog input enable register
specification is “port”.
AN08 to AN15
10-bit A/D converter analog input pins
This function is valid when the analog input enable register
specification is “analog input”.
* : FPT-120P-M03, FPT-120C-C02
(Continued)
8
MB90220 Series
Pin no.
QFP*
55
Circuit
type
Pin name
PA0
Function
C
General-purpose I/O port
This function is always valid.
ASR0
PA1
ICU (input capture unit) input pin
This function is valid during ICU (input capture unit) input operations.
56
C
General-purpose I/O port
This function is always valid.
PWC0
PWC input pin
During PWC0 input operations, this input may be used suddenly at
any time; therefore, it is necessary to stop output by other functions
on this pin, except when using it for output deliberately.
POT0
PWC output pin
This function is valid during PWC output operations.
57 to 59
PA2 to PA4
PWC1 to PWC3
C
General-purpose I/O ports
This function is always valid.
PWC input pins
This function is valid during PWC input operations.
During PWC1 to PWC3 input operations, this input may be used
suddenly at any time; therefore, it is necessary to stop output by other
functions on this pin, except when using it for output deliberately.
POT1 to POT3
ASR1 to ASR3
PWC output pins
This function is valid during PWC output operations.
ICU (input capture unit) input pins
This function is valid during ICU (input capture unit) input operations.
60,
61
PA5,
PA6
B
General-purpose I/O ports
This function is always valid.
When these pins are open in input mode, through current may leak in
stop mode/reset mode, be sure to fix these pins to VCC/VSS level to
use these pins in input mode.
INT0,
INT1
DTP/External interrupt request input pins
When DTP/external interrupts are enabled, these inputs may be used
suddenly at any time; therefore, it is necessary to stop output by other
functions on these pins, except when using them for output
deliberately.
When these pins are open in input mode, through current may leak in
stop mode/reset mode, be sure to fix these pins to VCC/VSS level to
use these pins in input mode.
62
PA7
B
General-purpose I/O port
This function is always valid.
When these pins are open in input mode, through current may leak in
stop mode/reset mode, be sure to fix these pins to VCC/VSS level to
use these pins in input mode.
* : FPT-120P-M03, FPT-120C-C02
(Continued)
9
MB90220 Series
Pin no.
Circuit
Pin name
INT2
Function
type
QFP*
62
B
DTP/External interrupt request input pin
When DTP/external interrupts are enabled, these inputs may be used
suddenly at any time; therefore, it is necessary to stop output by other
functions on these pins, except when using them for output
deliberately.
When these pins are open in input mode, through current may leak in
stop mode/reset mode, be sure to fix these pins to VCC/VSS level to
use these pins in input mode.
ATG
10-bit A/D converter external trigger input pin
When these pins are open in input mode, through current may leak in
stop mode/reset mode, be sure to fix these pins to VCC/VSS level to
use these pins in input mode.
64
65
66
PB0
C
C
C
General-purpose I/O port
This function is valid when the UART0 (ch.0) serial data output
specification is “disabled”.
SOD0
UART0 (ch.0) serial data output
This function is valid when the UART0 (ch.0) serial data output
specification is “enabled”.
PB1
General-purpose I/O port
This function is always valid.
SID0
UART0 (ch.0) serial data input pin
During UART0 (ch.0) input operations, this input may be used
suddenly at any time; therefore, it is necessary to stop output by other
functions on this pin, except when using it for output deliberately.
PB2
General-purpose output port
This function is valid when the UART0 (ch.0) clock output
specification is “disabled”.
SCK0
UART0 (ch.0) clock output pin
The clock output function is valid when the UART0 (ch.0) clock output
specification is “enabled”.
UART0 (ch.0) external clock input pin. This function is valid when the
port is in input mode and the UART0 (ch.0) specification is external
clock mode.
67
68
PB3
C
C
General-purpose I/O port
This function is valid when the UART0 (ch.1) serial data output
specification is “disabled”.
SOD1
UART0 (ch.1) serial data output pin
This function is valid when the UART0 (ch.1) serial data output
specification is “enabled”.
PB4
General-purpose I/O port
This function is always valid.
SID1
UART0 (ch.1) serial data input pin
During UART0 (ch.1) input operations, this input may be used
suddenly at any time; therefore, it is necessary to stop output by other
functions on this pin, except when using it for output deliberately.
* : FPT-120P-M03, FPT-120C-C02
(Continued)
10
MB90220 Series
Pin no.
QFP*
69
Circuit
type
Pin name
PB5
Function
C
General-purpose I/O port
This function is valid when the UART0 (ch.1) clock output specification
is “disabled”.
SCK1
UART0 (ch.1) clock output pin
The clock output function is valid when the UART0 (ch.1) clock output
specification is “enabled”.
UART0 (ch.1) external clock input pin
This function is valid when the port is in input mode and the UART0
(ch.1) specification is external clock mode.
70
71
72
PB6
C
C
C
General-purpose I/O port
This function is valid when the UART0 (ch.2) serial data output
specification is “disabled”.
SOD2
UART0 (ch.2) serial data output pin
This function is valid when the UART0 (ch.2) serial data output
specification is “enabled”.
PB7
General-purpose I/O port
This function is always valid.
SID2
UART0 (ch.2) serial data input pin
During UART0 (ch.2) input operations, this input may be used
suddenly at any time; therefore, it is necessary to stop output by other
functions on this pin, except when using it for output deliberately.
PC0
General-purpose I/O port
This function is valid when the UART0 (ch.2) clock output
specification is “disabled”.
SCK2
UART0 (ch.2) clock output pin
The clock output function is valid when the UART0 (ch.2) clock output
specification is “enabled”.
UART0 (ch.2) external clock input pin
This function is valid when the port is in input mode and the UART0
(ch.2) specification is external clock mode.
73
74
PC1
C
C
General-purpose I/O port
This function is valid when the UART1 serial data output specification
is “disabled”.
SOD3
UART1 serial data output pin
This function is valid when the UART1 serial data output specification
is “enabled”.
PC2
General-purpose I/O port
This function is always valid.
SID3
UART1 serial data input pin
During UART1 input operations, this input may be used suddenly at
any time; therefore, it is necessary to stop output by other functions
on this pin, except when using it for output deliberately.
* : FPT-120P-M03, FPT-120C-C02
(Continued)
11
MB90220 Series
(Continued)
Pin no.
Circuit
Pin name
PC3
Function
type
QFP*
75
C
General-purpose I/O port
This function is valid when the UART1 clock output specification is
“disabled”.
SCK3
UART1 clock output pin
The clock output function is valid when the UART1 clock output
specification is “enabled”.
UART1 external clock input pin
This function is valid when the port is in input mode and the UART1
specification is external clock mode.
76
77
PC4
C
C
General-purpose I/O port
This function is always valid.
CTS0
UART0 (ch.0) Clear To Send input pin
When the UART0 (ch.0) CTS function is enabled, this input may be
used suddenly at any time; therefore, it is necessary to stop output by
other functions on this pin, except when using it for output
deliberately.
PC5
General-purpose I/O port
This function is always valid.
TRG0
16-bit PPG timer trigger input pin
This function is valid when the 16-bit PPG timer trigger input
specification is enabled.
The data on this pin is read as 16-bit PPG timer trigger input (TRG0).
During this operation, the input may be used suddenly at any time;
therefore, it is necessary to stop output by other functions on this pin,
except when using it for output deliberately.
8,
54,
94
VCC
Power Power supply for digital circuitry
supply
33,
63,
VSS
Power Ground level for digital circuitry
supply
91,
119
42
AVCC
Power Power supply for analog circuitry
supply When turning this power supply on or off, always be sure to first apply
electric potential equal to or greater than AVCC to VCC.
During normal operation AVCC should be equal to VCC.
43
AVRH
Power Reference voltage input for analog circuitry
supply When turning this pin on or off, always be sure to first apply electric
potential equal to or greater than AVRH to AVCC.
44
45
AVRL
AVSS
Power Reference voltage input for analog circuitry
supply
Power Ground level for analog circuitry
supply
* : FPT-120P-M03, FPT-120C-C02
(Continued)
12
MB90220 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• Oscillation feedback resistor: Approx. 1 MΩ
MB90223
MB90224
MB90P224B
MB90W224B
X1
X0
Standby control signal
• Oscillation feedback resistor: Approx. 1 MΩ
MB90P224A
MB90W224A
X1
X0
Standby control signal
B
• CMOS-level output
• CMOS-level hysteresis input with no standby
control
Digital output
Digital output
R
Digital input
Note: The pull-up and pull-down resistors are always connected, regardless of the state.
(Continued)
13
MB90220 Series
Type
Circuit
Remarks
• CMOS-level output
C
• CMOS-level hysteresis input with standby
control
Digital output
Digital output
R
Digital input
D
• CMOS-level input with no standby control
Mask ROM products only:
MD2: with pull-down resistor
MD1: with pull-up resistor
MD0: with pull-down resistor
R
Digital input
• CMOS-level input with no standby control
MD2 of OTPROM products/EPROM products
only
R
Digital input
VPP power supply
E
• CMOS-level hysteresis input with no standby
control
• With input analog filter (40 ns Typ.)
R
Analog filter
Digital input
Note: The pull-up and pull-down resistors are always connected, regardless of the state.
(Continued)
14
MB90220 Series
(Continued)
Type
Circuit
Remarks
F
• N-channel open-drain output
• CMOS-level hysteresis input with A/D
control and with standby control
Digital output
R
A/D input
Digital input
G
• CMOS-level hysteresis input with no
standby control and with pull-up resistor
• With input analog filter (40 ns Typ.)
Pull-up
resistor
R
MB90223, MB90224: RST pin can be set
to with or without a pull-up resistor by a
mask option.
MB90P224A: With pull-up resistor
MB90W224A: With pull-up resistor
MB90P224B: With no pull-up resistor
MB90W224B: With no pull-up resistor
R
Digital input
Analog filter
: P-type transistor
: N-type transistor
Note: The pull-up and pull-down resistors are always connected, regardless of the state.
15
MB90220 Series
■ HANDLING DEVICES
1. Preventing Latchup
CMOS ICs may cause latchup when a voltage higher than VCC or lower than VSS is applied to input or output
pins other than medium-and high-voltage pins, or when a voltage exceeding the rating is applied between VCC
and VSS.
If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the
device. Use meticulous care not to let any voltage exceed the maximum rating.
Also, take care to prevent the analog power supply (AVCC and AVRH) and analog input from exceeding the
digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Pins when A/D is not Used
Connect to be AVCC = AVRH = VCC and AVSS = AVRL = VSS even if the A/D converter is not in use.
4. Precautions when Using an External Input
To reset the internal circuit properly by the “L” level input to the RST pin, the “L” level input to the RST pin must
be maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.
5. VCC and VSS Pins
Apply equal potential to the VCC and VSS pins.
6. Supply Voltage Variation
The operation assurance range for the VCC supply voltage is as given in the ratings. However, sudden changes
in the supply voltage can cause misoperation, even if the voltage remains within the rated range. Therefore, it
is important to supply a stable voltage to the IC. The recommended power supply control guidelines are that
the commercial frequency (50 to 60 Hz) ripple variation (P-P value) on VCC should be less than 10% of the
standard VCC value and that the transient rate of change during sudden changes, such as during power supply
switching, should be less than 0.1 V/ms.
7. Notes on Using an External Clock
When using an external clock, drive the X0 pin as illustrated below. When an external clock is used, oscillation
stabilization time is required even for power-on reset and wake-up from stop mode.
• Use of External Clock
MB90220
X0
X1
Note: When using an external clock, be sure to input external clock more than 6 machine cycles after
setting the HST pin to “L” to transfer to the hardware standby mode.
16
MB90220 Series
8. Power-on Sequence for A/D Converter Power Supplies and Analog Inputs
Be sure to turn on the digital power supply (VCC) before applying voltage to the A/D converter power supplies
(AVCC, AVRH, and AVRL) and analog inputs (AN00 to AN15).
When turning power supplies off, turn off the A/D converter power supplies (AVCC, AVRH, and AVRL) and analog
inputs (AN00 to AN15) first, then the digital power supply (VCC).
When turning AVRH on or off, be careful not to let it exceed AVCC.
17
MB90220 Series
■ PROGRAMMING FOR MB90P224A/P224B/W224A/W224B
In EPROM mode, the MB90P224A/P224B/W224A/W224B functions equivalent to the MBM27C1000. This
allows the EPROM to be programmed with a general-purpose EPROM programmer by using the dedicated
socket adapter (do not use the electronic signature mode).
1. Program Mode
When shipped from Fujitsu, and after each erasure, all bits (96 K × 8 bits) in the MB90P224A/P224B/W224A/
W224B are in the “1” state. Data is written to the ROM by selectively programming “0’s” into the desired bit
locations. Bits cannot be set to “1” electrically.
2. Programming Procedure
(1) Set the EPROM programmer to MBM27C1000.
(2) Load program data into the EPROM programmer at 08000H to 1FFFFH.
Note that ROM addresses FE8000H to FFFFFFH in the operation mode in the MB90P224A/P224B/W224A/
W224B series assign to 08000H to 1FFFFH in the EPROM mode (on the EPROM programmer).
FFFFFFH
1FFFFH *
FE8000H
08000H *
Operation mode
EPROM mode
(Corresponding addresses on the EPROM mode)
* : Be sure to set the programming, the start address and the stop address on the EPROM programmer to 08000H/1FFFFH.
(3) Mount the MB90P224A/P224B/W224A/W224B on the adapter socket, then fit the adapter socket onto the
EPROM programmer. When mounting the device and the adapter socket, pay attention to their mounting
orientations.
(4) Start programming the program data to the device.
(5) If programming has not successfully resulted, connect a capacitor of approx. 0.1 µF between VCC and GND,
between VPP and GND.
Note: The mask ROM products (MB90223, MB90224) does not support EPROM mode. Data cannot, therefore, be
read by the EPROM programmer.
18
MB90220 Series
3. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer
Part No.
Package
MB90P224B
QFP-120
Compatible socket adapter
Sun Hayato Co., Ltd.
ROM-120QF-32DP-16F
Recommended
programmer
manufacturer
and
programmer
name
R4945A
(main unit)
+
R49451A
(adapter)
Advantest corp.
Recommended
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
Advantest Corp.:
TEL: Except JAPAN (81)-3-3930-4111
4. Erase Procedure
Data written in the MB90W224A/W224B is erased (from “0” to “1”) by exposing the chip to ultraviolet rays with
a wavelength of 2,537 Å through the translucent cover.
Recommended irradiation dosage for exposure is 10 Wsec/cm2. This amount is reached in 15 to 20 minutes
with a commercial ultraviolet lamp positioned 2 to 3 cm above the package(when the package surface illuminance
is 1200 µW/cm2).
If the ultraviolet lamp has a filter, remove the filter before exposure. Attaching a mirrored plate to the lamp
increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. If the translucent
part of the package is stained with oil or adhesive, transmission of ultraviolet rays is degraded, resulting in a
longer erasure time. In that case, clean the translucent part using alcohol (or other solvent not affecting the
package).
The above recommended dosage is a value which takes the guard band into consideration and is a multiple of
the time in which all bits can be evaluated to have been erased. Observe the recommended dosage for erasure;
the purpose of the guard band is to ensure erasure in all temperature and supply voltage ranges. In addition,
check the life span of the lamp and control the illuminance appropriately.
Data in the MB90W224A/W224B is erased by exposure to light with a wavelength of 4,000 Å or less.
Data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure
results in a much lower erasure rate than exposure to 2,537 Å ultraviolet rays. Note that exposure to such lights
for an extended period will therefore affect system reliability. If the chip is used where it is exposed to any light
with a wavelength of 4,000 Å or less, cover the translucent part, for example, with a protective seal to prevent
the chip from being exposed to the light.
Exposure to light with a wavelength of 4,000 to 5,000 Å or more will not erase data in the device. If the light
applied to the chip has a very high illuminance, however, the device may cause malfunction in the circuit for
reasons of general semiconductor characteristics. Although the circuit will recover normal operation when
exposure is stopped, the device requires proper countermeasures for use in a place exposed continuously to
such light even though the wavelength is 4,000 Å or more.
19
MB90220 Series
5. Recommended Screening Conditions
High temperature aging is recommended as the pre-assembly screening procedure.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
6. Programming Yeild
MB90P224A/P224B cannot be write-tested for all bits due to their nature. Therefore the write yield cannot always
be guaranteed to be 100%.
7. Pin Assignments in EPROM Mode
(1) Pins Compatible with MBM27C1000
MB90P224A/P224B/
MB90W224A/W224B
MB90P224A/P224B/
MB90W224A/W224B
MBM27C1000
MBM27C1000
Pin no. Pin name
Pin no.
Pin name
VPP
Pin no.
87
Pin name
MD2 (VPP)
P55
Pin no.
Pin name
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
8, 54, 94
VCC
2
3
OE
83
PGM
N.C.
A14
A13
A08
A09
A11
A16
A10
CE
84
—
6
P56
—
A15
A12
A07
A06
A05
A04
A03
A02
A01
A00
D00
D01
D02
GND
7
P37
4
4
P34
P36
P35
P30
P31
P33
P40
P32
P54
P07
P06
P05
P04
P03
5
118
117
116
115
114
113
112
111
95
P27
5
6
P26
120
1
7
P25
8
P24
3
9
P23
9
10
11
12
13
14
15
16
P22
2
P21
82
102
101
100
99
98
P20
D07
D06
D05
D04
D03
P00
96
P01
97
P02
33, 63, 91,119 VSS
20
MB90220 Series
(2) Power Supply and GND Connection Pins
Type
Pin no.
Pin name
Power supply
89
88
86
MD0
MD1
HST
VCC
8, 54, 94
GND
33, 63, 91, 119
VSS
AVRL
AVSS
P52
P53
RST
44
45
80
81
90
(3) Pins other than MBM27C1000-compatible Pins
Pin no. Pin name
Treatment
92
93
X0
X1
Pull up with 4.7 KΩ resistor
OPEN
109
110
10 to 16
P16
P17
P41 to P47
42
43
AVCC
AVRH
46
47
P60
P61
48 to 53
17 to 24
25 to 32
34 to 41
55 to 61
63 to 70
71 to 76
78
P62 to P67
P70 to P77
P80 to P82
P90 to P97
PA0 to PA7
PB0 to PB7
PC0 to PC5
P50
Connect pull-up resistor of about 1 MΩ to each pin
79
P51
85
P57
P10 to P15
103 to 108
21
MB90220 Series
■ BLOCK DIAGRAM
4
4
PWC0 to PWC3
POT0 to POT3
X1
X0
RST
Clock controller
5
PWC timer × 4
HST
MD0 to MD2
Write-inhibit
RAM
WI
4
ASR0 to ASR3
ICU (Input
Capture Unit)
× 4
4
CTS0
SID0 to SID2
3
UART0 × 3
SOD0 to SOD2
SCK0 to SCK2
24-bit timer counter
3
SID3
SOD3
SCK3
UART1
8
OCU (Output
Compare Unit)
× 4
DOT0 to DOT7
INT0 to INT7
8
16-bit reload timer
× 6
DTP/External
interrupt
× 8
6
5
TOT0 to TOT5
TIN1 to TIN5
16
D00 to D15
ATG
AN00 to AN15
AVCC
AVRH
AVRL
AVSS
2
External bus
interface
RDY
HRQ
10-bit
A/D converter
16 channels
21
29
A00 to A23
CLK
HAK
WRH
WRL
F2MC-16F CPU
RD
102
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
I/O ports
RAM
ROM
P70 to P77
P80 to P87
P90 to P97
PA0 to PA7
PB0 to PB7
PC0 to PC5
16-bit PPG timer
2
× 2
PPG0
PPG1
TRG0
22
MB90220 Series
■ PROGRAMMING MODEL
Dedicated Registers
AL
Accumulator
AH
USP
SSP
User stack pointer
System stack pointer
Processor status
PS
PC
Program counter
USPCU
SSPCU
USPCL
SSPCL
User stack upper register
System stack upper register
User stack lower register
System stack lower register
DPR
Direct page register
PCB
DTB
USB
SSB
ADB
8 bit
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional bank register
16 bit
32 bit
General-purpose Registers
Max.32 banks
Upper
R 7
R 5
R 3
R 1
R 6
R 4
R 2
R 0
RW 7
RW 6
RL 3
RL 2
RL 1
RL 0
RW 5
RW 4
RW3
RW 2
RW 1
RW 0
Lower
000180H + RP × 10H
16 bit
MSB
LSB
Processor Status (PS)
ILM
—
I
S
T
N
Z
V
C
RP
C C R
23
MB90220 Series
■ MEMORY MAP
Single chip
Internal ROM
External ROM
and external bus
and external bus
FFFFFFH
Address #1
010000H
ROM area
ROM area
ROM area
ROM area
FF bank
image
FF bank
image
Address #2
002000H
Internal
Internal
Internal
register area
register area
register area
001F00H
Address #3
Write-inhibit
RAM
Write-inhibit
RAM
Write-inhibit
RAM
Address #4
000380H
: Internal
RAM
RAM
RAM
Registers
Registers
Registers
000180H
000100H
: External
0000C0H
Peripherals
Peripherals
Peripherals
: No access
000000H
Type
MB90223
MB90224
Address #1
Address #2
004000H
Address #3
000F00H
Address #4
000D00H
001300H
FF0000H
FE8000H
001500H
004000H
MB90P224A/P224B
MB90W224A/W224B
004000H
MB90V220
001500H
(FE0000H)
001900H
24
MB90220 Series
■ I/O MAP
Register
name
Resouce
Initial value
name
Address
Register
Port 0 data register
Access
*3
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
1 1 1 1 1 1 1 1
X X X X X X X X
X X X X X X X X
1 1 1 1 1 1 1 1
X X X X X X X X
X X X X X X X X
– – X X X X X X
000000H
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
PDRB
PDRC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
*3
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Port 5 data register
Port 6 data register
Port 7 data register
Port 8 data register
Port 9 data register
Port A data register
Port B data register
Port C data register
000001H
*3
000002H
*3
000003H
*3
000004H
*3
000005H
000006H
000007H
000008H
000009H
00000AH
00000BH
00000CH
R/W
R/W
R/W
R/W
R/W
00000DH
to 0FH
(Reserved area)*1
*3
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
––0 0 0 0 0 0
000010H
Port 0 data direction register
Port 1 data direction register
Port 2 data direction register
Port 3 data direction register
Port 4 data direction register
Port 5 data direction register
Port 6 analog input enable register
Port 7 data direction register
Port 8 data direction register
Port 9 analog input enable register
Port A data direction register
Port B data direction register
Port C data direction register
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
ADER0
DDR7
DDR8
ADER1
DDRA
DDRB
DDRC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
*3
000011H
*3
000012H
*3
000013H
*3
000014H
*3
000015H
000016H
000017H
000018H
000019H
00001AH
00001BH
00001CH
00001DH
to 1FH
(Reserved area)*1
000020H
000021H
Mode control register 0
Status register 0
UMC0
USR0
R/W
R/W
0 0 0 0 0 1 0 0
0 0 0 1 0 0 0 0
UART 0 (ch.0)
Input data register 0
/output data register 0
UIDR0
/UODR0
000022H
R/W
X X X X X X X X
(Continued)
25
MB90220 Series
Register
name
Resouce
name
Address
Register
Access
Initial value
000023H
000024H
000025H
Rate and data register 0
Mode control register 1
Status register 1
URD0
UMC1
USR1
R/W
R/W
R/W
R/W
UART0 (ch.0)
0 0 0 0 0 0 0 X
0 0 0 0 0 1 0 0
0 0 0 1 0 0 0 0
UART0 (ch.1)
Input data register 1
/output data register 1
UIDR1
/UODR1
000026H
X X X X X X X X
000027H
000028H
000029H
Rate and data register 1
Mode control register 2
Status register 2
URD1
UMC2
USR2
R/W
R/W
R/W
R/W
0 0 0 0 0 0 0 X
0 0 0 0 0 1 0 0
0 0 0 1 0 0 0 0
UART0 (ch.2)
UART0 (ch.0)
Input data register 2
/output data register 2
UIDR2
/UODR2
00002AH
X X X X X X X X
00002BH
00002CH
00002DH
00002EH
00002FH
Rate and data register 2
URD2
UCCR
R/W
R/W
0 0 0 0 0 0 0 X
– – – 0 0 0 – –
UART CTS control register
(Reserved area)*1
Mode register
SMR
SCR
R/W
R/W
R/W
0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 0
Control register
UART1
Input data register
/output data register
SIDR
/SODR
000030H
X X X X X X X X
000031H
000032H
000033H
000034H
000035H
000036H
000037H
000038H
000039H
00003AH
00003BH
00003CH
00003DH
Status register
SSR
R/W
R/W
R/W
R/W
0 0 0 0 1 – 0 0
0 0 0 0 0 0 0 0
– – – X 0 0 0 0
0 0 0 0 – – 0 0
A/D channel setting register
A/D mode register
ADCH
ADMD
ADCS
10-bit A/D
converter
A/D control status register
(Reserved area)*1
X X X X X X X X
0 0 0 0 0 0 X X
10-bit A/D
converter
A/D data register
ADCD
R
(Reserved area)*1
DTP/interrupt enable register
DTP/interrupt source register
ENIR
EIRR
R/W
R/W
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
DTP/external
interrupt
Request level setting register
ELVR
R/W
00003EH
to 3FH
(Reserved area)*1
TMCSR0 R/W
000040H
000041H
0 0 0 0 0 0 0 0
– – – – 0 0 0 0
(Continued)
16-bit reload
timer 0
Timer control status register 0
26
MB90220 Series
Register
name
Resouce
Initial value
name
Address
Register
Access
000042H
000043H
000044H
000045H
000046H
000047H
000048H
000049H
00004AH
00004BH
00004CH
00004DH
00004EH
00004FH
000050H
000051H
000052H
000053H
000054H
000055H
000056H
000057H
0 0 0 0 0 0 0 0
16-bit reload
Timer control status register 1
TMCSR1
TMCSR2
TMCSR3
TMCSR4
TMCSR5
PCNT0
R/W
timer 1
– – – – 0 0 0 0
0 0 0 0 0 0 0 0
16-bit reload
Timer control status register 2
Timer control status register 3
Timer control status register 4
Timer control status register 5
PPG control status register 0
PPG control status register 1
PWC control status register 0
PWC control status register 1
PWC control status register 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
timer 2
– – – – 0 0 0 0
0 0 0 0 0 0 0 0
16-bit reload
timer 3
– – – – 0 0 0 0
0 0 0 0 0 0 0 0
16-bit reload
timer 4
– – – – 0 0 0 0
0 0 0 0 0 0 0 0
16-bit reload
timer 5
– – – – 0 0 0 0
0 0 0 0 0 0 0 0
16-bit PPG
timer 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
16-bit PPG
PCNT1
timer 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PWC timer 0
PWCSR0
PWCSR1
PWCSR2
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PWC timer 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PWC timer 2
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PWC timer 3
PWC control status register 3
ICU control register 0
PWCSR3
ICC0
R/W
R/W
0 0 0 0 0 0 0 0
ICU (Input
000058H
000059H
00005AH
0 0 0 0 0 0 0 0
Capture Unit)
(Reserved area)*1
ICC1 R/W
ICU (Input
Input capture control register 1
0 0 0 0 0 0 0 0
Capture Unit)
00005BH
00005CH
00005DH
00005EH
00005FH
000060H
000061H
(Reserved area)*1
1 1 1 1 0 0 0 0
OCU (Output
OCU control register 00
CCR00
R/W
Compare Unit)
– – – – 0 0 0 0
(Continued)
27
MB90220 Series
Register
name
Resouce
name
Address
Register
Access
Initial value
000062H
000063H
000064H
000065H
000066H
000067H
000068H
000069H
00006AH
00006BH
00006CH
00006DH
00006EH
00006FH
000070H
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
000080H
1 1 1 1 0 0 0 0
– – – – 0 0 0 0
OCU (Output
Compare Unit)
OCU0 control register 01
CCR01
R/W
(Reserved area)*1
– – – – 0 0 0 0
0 0 0 0 0 0 0 0
– – – – 0 0 0 0
0 0 0 0 0 0 0 0
OCU0 control register 10
OCU0 control register 11
CCR10
CCR11
R/W
R/W
OCU (Output
Compare Unit)
(Reserved area)*1
1 1 0 0 0 0 0 0
– – 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Free-run timer control register
TCCR
TCRL
TCRH
R/W
R
Free-run timer lower-order data
register
24-bit timer
counter
Free-run timer upper-order data
register
(Reserved area)*1
PWC divider ratio control register 0
Reserved area*1
DIVR0
DIVR1
DIVR2
DIVR3
R/W
R/W
R/W
R/W
PWC timer 0
PWC timer 1
PWC timer 2
PWC timer 3
– – – – – – 0 0
– – – – – – 0 0
– – – – – – 0 0
– – – – – – 0 0
PWC divider ratio control register 1
Reserved area*1
PWC divider ratio control register 2
Reserved area*1
PWC divider ratio control register 3
000081H
to 8DH
(Reserved area)*1
(Continued)
28
MB90220 Series
Register
name
Resouce
Initial value
name
Address
Register
WI control register
Access
Write-inhibit
– – – X – – – –
RAM
00008EH
00008FH
WICR
R/W
(Reserved area)*1
000090H
to 9EH
Delay interrupt
generation
module
Delay interrupt source generation
/release register
00009FH
DIRR
R/W
– – – – – – – 0
Low power
consumption
0000A0H
0000A3H
0000A4H
0000A5H
0000A8H
Standby control register
STBYC
MACR
HACR
EPCR
WDTC
R/W
W
0 0 0 1 * * * *
# # # # # # # #
# # # # # # # #
# # 0 – 0 # 0 0
X X X X X X X X
Address mid-order control register
External pin
External pin
External pin
Address higher-order control
register
W
External pin control register
W
Watchdog
timer
Watchdog timer control register
R/W
Timebase
timer
0000A9H
Timebase timer control register
TBTC
R/W
– – – 0 0 0 0 0
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
0000BDH
0000BEH
0000BFH
Interrupt control register 00
Interrupt control register 01
Interrupt control register 02
Interrupt control register 03
Interrupt control register 04
Interrupt control register 05
Interrupt control register 06
Interrupt control register 07
Interrupt control register 08
Interrupt control register 09
Interrupt control register 10
Interrupt control register 11
Interrupt control register 12
Interrupt control register 13
Interrupt control register 14
Interrupt control register 15
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
Interrupt
controller
0000C0H
to FFH
(External area)*2
001F00H
001F01H
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
(Continued)
PWC data buffer register 0
PWCR0 R/W
PWC timer 0
29
MB90220 Series
Register
name
Resouce
name
Address
Register
Access
Initial value
001F02H
001F03H
001F04H
001F05H
001F06H
001F07H
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PWC data buffer register 1
PWCR1
PWCR2
PWCR3
R/W
PWC timer 1
PWC timer 2
PWC timer 3
PWC data buffer register 2
PWC data buffer register 3
R/W
R/W
001F08H
to 1F0FH
(Reserved area)*1
001F10H
001F11H
001F12H
001F13H
001F14H
001F15H
001F16H
001F17H
001F18H
001F19H
001F1AH
001F1BH
001F1CH
001F1DH
001F1EH
001F1FH
001F20H
001F21H
001F22H
001F23H
001F24H
001F25H
001F26H
001F27H
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
(Continued)
OCU compare lower-order data
register 00
CPR00L
R/W
Output
compare 00
OCU compare higher-order data
register 00
CPR00
OCU compare lower-order data
register 01
CPR01L
R/W
Output
compare 01
OCU compare higher-order data
register 01
CPR01
OCU compare lower-order data
register 02
CPR02L
R/W
Output
compare 02
OCU compare higher-order data
register 02
CPR02
OCU compare lower-order data
register 03
CPR03L
R/W
Output
compare 03
OCU compare higher-order data
register 03
CPR03
OCU compare lower-order data
register 04
CPR04L
R/W
Output
compare 10
OCU compare higher-order data
register 04
CPR04
OCU compare lower-order data
register 05
CPR05L
R/W
Output
compare 11
OCU compare higher-order data
register 05
CPR05
30
MB90220 Series
Register
name
Resouce
Initial value
name
Address
Register
Access
001F28H
001F29H
001F2AH
001F2BH
001F2CH
001F2DH
001F2EH
001F2FH
001F30H
001F31H
001F32H
001F33H
001F34H
001F35H
001F36H
001F37H
001F38H
001F39H
001F3AH
001F3BH
001F3CH
001F3DH
001F3EH
001F3FH
001F40H
001F41H
001F42H
001F43H
001F44H
001F45H
001F46H
001F47H
0 0 0 0 0 0 0 0
OCU compare lower-order data
register 06
CPR06L
CPR06
CPR07L
CPR07
TMR0
0 0 0 0 0 0 0 0
Output
R/W
compare 12
0 0 0 0 0 0 0 0
OCU compare higher-order data
register 06
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
OCU compare lower-order data
register 07
0 0 0 0 0 0 0 0
Output
R/W
compare 13
0 0 0 0 0 0 0 0
OCU compare higher-order data
register 07
0 0 0 0 0 0 0 0
X X X X X X X X
16-bit timer register 0
R
W
R
X X X X X X X X
16-bit reload
timer 0
X X X X X X X X
16-bit reload register 0
16-bit timer register 1
TMRLR0
TMR1
X X X X X X X X
X X X X X X X X
X X X X X X X X
16-bit reload
timer 1
X X X X X X X X
16-bit timer reload register 1
16-bit timer register 2
TMRLR1
TMR2
W
R
X X X X X X X X
X X X X X X X X
X X X X X X X X
16-bit reload
timer 2
X X X X X X X X
16-bit timer reload register 2
16-bit timer register 3
TMRLR2
TMR3
W
R
X X X X X X X X
X X X X X X X X
X X X X X X X X
16-bit reload
timer 3
X X X X X X X X
16-bit timer reload register 3
16-bit timer register 4
TMRLR3
TMR4
W
R
X X X X X X X X
X X X X X X X X
X X X X X X X X
16-bit reload
timer 4
X X X X X X X X
16-bit timer reload register 4
16-bit timer register 5
TMRLR4
TMR5
W
R
X X X X X X X X
X X X X X X X X
X X X X X X X X
16-bit reload
timer 0
X X X X X X X X
16-bit timer reload register 5
TMRLR5
W
X X X X X X X X
(Continued)
31
MB90220 Series
(Continued)
Register
name
Resouce
name
Address
Register
Access
Initial value
001F48H
001F49H
001F4AH
001F4BH
001F4CH
001F4DH
001F4EH
001F4FH
001F50H
001F51H
001F52H
001F53H
001F54H
001F55H
001F56H
001F57H
001F58H
001F59H
001F5AH
001F5BH
001F5CH
001F5DH
001F5EH
001F5FH
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
0 0 0 0 0 0 0 0
X X X X X X X X
X X X X X X X X
X X X X X X X X
0 0 0 0 0 0 0 0
X X X X X X X X
X X X X X X X X
X X X X X X X X
0 0 0 0 0 0 0 0
X X X X X X X X
X X X X X X X X
X X X X X X X X
0 0 0 0 0 0 0 0
PPG cycle setting register 0
PCSR0
PDUT0
PCSR1
PDUT1
ICRL0
ICRH0
ICRL1
ICRH1
ICRL2
ICRH2
ICRL3
ICRH3
W
16-bit PPG
timer 0
PPG duty setting register 0
W
W
W
R
R
R
R
R
R
R
R
PPG cycle setting register 1
PPG duty setting register 1
16-bit PPG
timer 1
ICU lower-order data register 0
ICU higher-order data register 0
ICU lower-order data register 1
ICU higher-order data register 1
ICU lower-order data register 2
ICU higher-order data register 2
ICU lower-order data register 3
ICU higher-order data register 3
Input capture 0
Input capture 1
Input capture 2
Input capture 3
001F60H
to 1FFFH
(Reserved area)*1
Initial value
0: The initial value of this bit is “0”.
1: The initial value of this bit is “1”.
X: The initial value of this bit is undefined.
–: This bit is not used. The initial value is undefined.
*: The initial value of this bit varies with the reset source.
#: The initial value of this bit varies with the operation mode.
*1: Access prohibited
*2: Only this area is open to external access in the area below address 0000FFH (inclusive). All addresses which
are not described in the table are reserved areas, and accesses to these areas are handled in the same
manner as for internal areas. The access signal for the external bus is not generated.
*3: When an external bus is enable mode, never access to resisters which are not used as general ports in areas
address 000000H to 000005H or 000010H to 000015H.
32
MB90220 Series
■ INTERRUPT SOURCES AND INTERRUPT VECTORS/INTERRUPT CONTROL
REGISTERS
Interrupt control
register
Interrupt vector
No. Address
EI2OS
Interrupt source
support
ICR
—
Address
Reset
×
×
×
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
08H
09H
FFFFDCH
FFFFD8H
—
—
—
INT9 instruction
—
Exception
0AH FFFFD4H
0BH FFFFD0H
—
External interrupt #0
ICR00
ICR01
ICR02
ICR03
0000B0H
0000B1H
0000B2H
0000B3H
External interrupt #1
0CH FFFFCCH
0DH FFFFC8H
0EH FFFFC4H
External interrupt #2
Input capture 0
PWC0 count completed/overflow
PWC1 count completed/overflow/input capture 1
PWC2 count completed/overflow/input capture 2
PWC3 count completed/overflow/input capture 3
24-bit timer, overflow
0FH
10H
11H
12H
13H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
ICR04
0000B4H
24-bit timer, intermediate bit/timebase timer,
interval interrupt
#20
14H
FFFFACH
Compare 0
#21
#22
#23
#24
#25
#26
#27
#28
#29
#31
#32
#33
#34
#35
#36
#37
15H
16H
17H
18H
19H
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
ICR05
ICR06
ICR07
0000B5H
0000B6H
0000B7H
Compare 1
Compare 2
Compare 3
Compare 4/6
Compare 5/7
1AH FFFF94H
1BH FFFF90H
1CH FFFF8CH
1DH FFFF88H
16-bit timer 0/1/2, overflow/PPG0
16-bit timer 3/4/5, overflow/PPG1
10-bit A/D converter count completed
UART1 transmission completed
UART1 reception completed
UART0 (ch.1) transmission completed
UART0 (ch.2) transmission completed
UART0 (ch.1) reception completed
UART0 (ch.2) reception completed
UART0 (ch.0) transmission completed
ICR08
ICR09
ICR10
0000B8H
0000B9H
0000BAH
1FH
20H
21H
22H
23H
24H
25H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
ICR11
0000BBH
0000BCH
ICR12
ICR13
0000BDH
(Continued)
33
MB90220 Series
(Continued)
Interrupt control
register
Interrupt vector
EI2OS
Interrupt source
support
No.
27H
2AH FFFF54H
Address
ICR
ICR14
ICR15
—
Address
0000BEH
0000BFH
—
UART0 (ch.0) reception completed
Delay interrupt generation module
Stack fault
#39
#42
FFFF60H
×
×
#255 FFH FFFC00H
: EI2OS is supported (with stop request).
: EI2OS is supported (without stop request).
: EI2OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI2OS is used
for one of the two, EI2OS and ordinary interrupt are not both available for the other (with stop request).
: EI2OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI2OS is used
for one of the two, EI2OS and ordinary interrupt are not both available for the other (without stop request).
: EI2OS is not supported.
Note: Since the interrupt sources having interrupt vector Nos. 15 to 18, 20, and 25 to 28 are OR’ed, respectively,
select them by means of the interrupt enable bits of each resource.
If EI2OS is used with the above-mentioned interrupt sources OR’ed with the interrupt vector Nos. 15 to 18,
20, and 25 to 28, be sure to activate one of the interrupt sources.
Also in this case, a request flag in the same series as the one interrupt source is likely to be cleared
automatically by EI2OS.
Assume for example that an interrupt for compare 4 of the interrupt vector No. 25 is activated at this time by
ICR07, so that the compare 6 is disabled. If EI2OS is activated at this time by ICR07, so that the compare 6
interrupt takes place during generation of or simultaneously with the compare 4 interrupt, not only the interrupt
flag for the compare 4 but also that for the compare 6 will be automatically cleared after EI2OS is automatically
transferred due to the compare 4 interrupt.
34
MB90220 Series
■ PERIPHERAL RESOURCES
1. Parallel Ports
The MB90220 series has 86 I/O pins and 16 open-drain I/O pins.
(1) Register Configuration
• Port 0 to C Data Register (PDR0 to PDRC)
Register name Address
000001 H
000003 H
000005 H
000007 H
000009 H
00000B H
PDR1
PDR3
PDR5
PDR7
PDR9
PDRB
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
PD x 7 PD x 6 PD x 5 PD x 4 PD x 3 PD x 2 PD x 1 PD x 0
XXXXXXXX B
(PDR9 only: 11111111)
(R/W)
PDR7 only: (R)
(R/W) (R/W)
(R) (R)
(R/W) (R/W)
(R) (R)
(R/W) (R/W) (R/W)
(R) (R) (R)
Register name Address
PDR0
PDR2
PDR4
PDR6
PDR8
PDRA
PDRC
000000 H
000002 H
000004 H
000006 H
000008 H
00000A H
00000C H
bit7
bit6
bit5
bit 4
bit3
bit2
bit1
bit0
Initial value
PD x 7 PD x 6 PD x 5 PD x 4 PD x 3 PD x 2 PD x 1 PD x 0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
XXXXXXXX B
(PDR6 only: 11111111)
Note: There are no register bits for bits 7 and 6 of port C.
• Port 0 to C Data Register (PDR0 to PDRC)
Register name Address
DDR1
DDR3
DDR5
DDR7
DDRB
000011 H
000013 H
000015 H
000017 H
00001B H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
DD x 7 DD x 6 DD x 5 DD x 4 DD x 3 DD x 2 DD x 1 DD x 0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
00000000 B
(PDR7 only: 11111111)
Register name Address
DDR0
DDR2
DDR4
DDR8
DDRA
DDRC
000010 H
000012 H
000014 H
000018 H
00001A H
00001C H
bit7
bit6
bit5
bit 4
bit3
bit2
bit1
bit0
Initial value
00000000 B
DD x 7 DD x 6 DD x 5 DD x 4 DD x 3 DD x 2 DD x 1 DD x 0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Note: There are no register bits for bits 7 and 6 of port C.
• Port 6, 9 Analog Input Enable Register (ADER0, ADER1)
Register name Address
bit7
bit6
bit5
bit 4
bit3
bit2
bit1
bit0
Initial value
000016 H
ADER0
AE07
AE06
AE05
AE04
AE03
AE02
AE01
AE00
11111111 B
(R/W)
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
Register name Address
ADER1 000019 H
Initial value
11111111 B
bit7
bit6
bit5
bit 4
bit3
bit2
bit1
bit0
AE15
AE14
AE13
AE12
AE11
AE10
AE09
AE08
(R/W)
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
35
MB90220 Series
(2) Block Diagram
• I/O Port (Port 0 to 5, 8, and A to C)
Data register read
Data register
Pin
Data register write
Direction register
Direction register write
Direction register read
• I/O Ports with an Open-drain output (Port 6, and 9)
RMW
(read-modify-write instruction)
Data register read
Data register write
Pin
Data register
ADER
ADER register write
ADER register read
• I/O Port (Port 7)
DOT0 to DOT3 (OCU)
4
4
Data register read
Pin
Direction register
Direction register write
4
Direction register read
Port 7
Note: Port 7 is input port. This pin also usable as I/O port for OCU internal function.
36
MB90220 Series
2. 16-bit Reload Timer (with Event Count Function)
The 16-bit reload timer 1 consists of a 16-bit down counter, a 16-bit reload register, an input pin (TIN), an output
pin (TOT), and a control register. The input clock can be selected from among three internal clocks and one
external clock. At the output pin (TOT), the pulses in the toggled output waveform are output in the reload mode;
the rectangular pulses indicating that the timer is counting are in the single-shot mode. The input pin (TIN) can
be used for event input in the event count mode, and for trigger input or gate input in the internal clock mode.
The MB90220 series has six channels for this timer.
(1) Register Configuration
• Timer Control Status Register 0 to 5 (TMCSR0 to TMCSR5)
Register name Address
000041 H
000043 H
000045 H
000047 H
000049 H
00004B H
TMCSR0
TMCSR1
TMCSR2
TMCSR3
TMCSR4
TMCSR5
Initial value
- - - - 0000 B
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
—
—
—
—
CSL1 CSL0 MOD2 MOD1
(—)
(—)
(—)
(—)
(R/W)
(R/W) (R/W) (R/W)
Register name Address
000040 H
000042 H
000044H
000046 H
000048 H
00004A H
TMCSR0
TMCSR1
TMCSR2
TMCSR3
TMCSR4
TMCSR5
Initial value
00000000 B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOD0 OUTE OUTL RELD
INTE
UF
CNTE
TRG
(R/W) (R/W) (R/W) (R/W) (R/W)
(R/W) (R/W) (R/W)
• 16-bit Timer Register 0 to 5 (TMR0 to TMR5)
Register name Address
001F31 H
001F35 H
001F39H
001F3D H
001F41 H
001F45H
TMR0
TMR1
TMR2
TMR3
TMR4
TMR5
Initial value
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
XXXXXXXX B
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
Register name Address
TMR0
TMR1
TMR2
TMR3
TMR4
TMR5
001F30 H
001F34 H
001F38H
001F3C H
001F40H
001F44 H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
XXXXXXXX B
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
• 16-bit Timer Reload Register 0 to 5 (TMRLR0 to TMRLR5)
Register name Address
TMRLR0
TMRLR1
TMRLR2
TMRLR3
TMRLR4
TMRLR5
001F33 H
001F37 H
001F3BH
001F3F H
001F43 H
001F47 H
Initial value
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
XXXXXXXX B
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
37
MB90220 Series
Register name Address
TMRLR0
TMRLR1
TMRLR2
TMRLR3
TMRLR4
TMRLR5
001F32 H
001F36 H
001F3A H
001F3E H
001F42 H
001F46 H
Initial value
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
XXXXXXXX B
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(2) Block Diagram
16
8
16-bit reload register
Reload
RELD
OUTE
OUTL
INTE
UF
UF
16-bit down counter
2
16
OUT
CTL.
GATE
IRQ
EI2OS clear
2
CSL1
CSL0
CNTE
TRG
Clock selector
Retrigger
2
Port (TIN)
IN
CTL.
EXCK
3
Port (TOT)
φ
21
φ
23
φ
25
Prescaler clear
MOD2
MOD1
MOD0
A/D (timer ch3 output)
UART0 (timer ch5 output)
UART1 (timer ch4 output)
Internal clock
3
38
MB90220 Series
3. UART0
UART0 is a serial I/O port for synchronous or asynchronous communication with external resources. It has the
following features:
• Full duplex double buffer
• CLK synchronous and CLK asynchronous data transfers capable
• Multiprocessor mode support (Mode 2)
• Built-in dedicated baud-rate generator (12 rates)
• Arbitrary baud-rate setting from external clock input or internal timer
• Variable data length (7 to 9 bits (without parity bit); 6 to 8 bits (with parity bit))
• Error detection function (Framing, overrun, parity)
• Interrupt function (Two sources for transmission and reception)
• Transfer in NRZ format
The MB90220 has three of these modules on chip.
(1) Register Configuration
• Mode Control Register 0 to 2 (UMC0 to UMC2)
Serial mode control register
Register name Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000100 B
000020 H
000024 H
000028 H
UMC0
UMC1
UMC2
PEN
SBL
MC1
MC0 SMDE
(R/W) (R/W)
RFC
SCKE
SOE
(R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
• Status Register 0 to 2 (USR0 to USR2)
Register name Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00001000 B
USR0
USR1
USR2
000021 H
000025 H
000029 H
RDRF ORFE
(R) (R)
PE
(R)
TDRE
(R)
RIE
(R/W)
TIE
(R/W)
RBF
(R)
TBF
(R)
• Input Data Register 0 to 2 (UIDR0 to UIDR2)/Ouput Data Register 0 to 2 (UODR0 to UODR2)
Register name Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000022 H
000026 H
00002A H
UIDR0/UODR0
UIDR1/UODR1
UIDR2/UODR2
XXXXXXXX B
D7
(R/W)
D6
D5
D4
D3
D2
D1
D0
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
• Rate and Data Register 0 to 2 (URD0 to URD2)
Register name Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0000000X B
000023 H
000027 H
00002B H
URD0
URD1
URD2
BCH
(R/W)
RC3
RC2
RC1
RC0
BCH0
P
D8
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
• UART CTS Control Register (UCCR)
Register name Address
bit7
—
bit6
—
bit5
—
bit4
CTE
bit3
bit2
bit1
—
bit0
—
Initial value
- - - 000 - - B
00002C H
UCCR
CSP
CTSE
(—)
(—)
(—)
(R/W) (R/W) (R/W)
(—)
(—)
39
MB90220 Series
(2) Block Diagram
CONTROL BUS
Receiving interrupt
(to CPU)
Dedicated baud rate clock
16-bit reload timer 5
SCK
Transmission interrupt
(to CPU)
Transmitting clock
(internally connected)
Clock selector
Receiving clock
External clock
Receiving controller
Transmission controller
Transmission
start circuit
SID
Start bit detector
Transmitted bit counter
Received bit counter
Received
parity counter
Transmission
parity counter
SOD
Received status
determination circuit
Receiving shifter
Transmitting shifter
Start of
End of
reception
transmission
UIDR
UODR
Signal indicating occurrence
of receiving error for EI2OS (to CPU)
Internal data bus
PEN
SBL
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
BCH
RC3
RC2
RC1
RC0
BCH
P
MC1
MC0
SMDE
RFC
SCKE
SOE
UMC
register
USR
register
URD
register
D8
CONTROL BUS
40
MB90220 Series
4. UART1
The UART1 is a serial I/O port for asynchronous communications (start-stop synchronization) or CLK
synchronized communications. It has the following features:
• Full-duplex double buffering
• Permits asynchronous (start-stop synchronization) and CLK synchronous communications
• Multiprocessor mode support
• Built-in dedicated baud rate generator
Asynchronous:
9615, 31250, 4808, 2404, and 1202 bps
CLK synchronization: 1 M, 500 K, 250 K bps
• Arbitray baud-rate setting from external clock input or internal timer
• Error detection function (parity errors, framing errors, and overrun errors)
• Transfer in format NRZ
• Extended supports intelligent I/O service
(1) Register Configuration
• Mode Register (SMR)
bit7
MD1
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000000B
Register name Address
00002E H
SMR
MD0
CS2
CS1
CS0
BCH
SCKE
SOE
(R/W)
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
• SCR (Control Register)
bit15
PEN
bit14
P
bit13
SBL
bit12
CL
bit11
A/D
bit10
REC
(R)
bit9
bit8
Register name Address
Initial value
00000100B
00002F H
SCR
RXE
TXE
(R/W)
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W)
• Input Data Register (SIDR)/Serial Output Data Register (SODR)
Initial value
bit7
D7
bit6
D6
bit5
D5
bit4
D4
bit3
D3
bit2
D2
bit1
D1
bit0
D0
Register name Address
000030 H
SIDR
XXXXXXXXB
(R)
bit7
D7
(R)
bit6
D6
(R)
bit5
D5
(R)
bit4
D4
(R)
bit3
D3
(R)
bit2
D2
(R)
bit1
D1
(R)
bit0
D0
Register name Address
000030 H
SODR
XXXXXXXXB
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
• SSR (Status Register)
Register name Address
bit15
PE
bit14
ORE
(R)
bit13
FRE
(R)
bit12
bit11
bit10
—
bit9
RIE
bit8
TIE
Initial value
00001-00B
000031 H
SSR
RDRF TDRE
(R) (R)
(R)
(R/W) (R/W)
41
MB90220 Series
(2) Block Diagram
Control signals
Receiving interrupt
(to CPU)
Dedicated baud rate generator
SCK3
16-bit reload timer 4
(internally connected)
Clock selector
Transmission interrupt
(to CPU)
Transmitting clock
Receiving clock
External clock
Receiving controller
Transmission controller
SID3
Transmission
start circuit
Start bit detector
Transmitted
bit counter
Received
bit counter
Received
parity counter
Transmission
parity counter
SOD3
Received status
determination circuit
Receiving shifter
Transmitting shifter
Start of
End of
reception
transmission
SIDR
SODR
Signal indicating occurrence
of receiving error for EI2OS (to CPU)
Internal data bus
MD1
MD0
CS2
CS1
CS0
BCH
SCKE
SOE
PEN
P
SBL
CL
A/D
REC
RXE
TXE
PE
ORE
FRE
RDRF
TDRE
SMR
register
SCR
register
SSR
register
RIE
TIE
Control signals
42
MB90220 Series
5. 10-bit A/D Converter
The 10-bit A/D converter converts analog input voltage into a digital value. The features of this module are
described below:
• Conversion time: 6.125 µs/channel (min.) (with machine clock running at 16 MHz)
• Uses RC-type sequential comparison and conversion method with built-in sample and hold circuit
• 10-bit resolution
• Analog input can be selected by software from among 16 channels
Single-conversion mode:
Scan conversion mode:
One-shot mode:
Selects and converts one channel.
Converts several consecutive channels (up to 16 can be programmed).
Converts the specified channel once and terminates.
Continuous conversion mode: Repeatedly converts the specified channel.
Stop conversion mode: Pauses after converting one channel and waits until the next startup (permits
synchronization of start of conversion).
• When A/D conversion is completed, an “A/D conversion complete” interrupt request can be issued to the CPU.
Because the generation of this interrupt can be used to start up the EI2OS and transfer the A/D conversion
results to memory, this function is suitable for continuous processing.
• Startup triggers can be selected from among software, an external trigger (falling edge), and a timer (rising
edge).
(1) Register Configuration
• A/D Channel Setting Register (ADCH)
This register specfies the A/D converter conversion channel.
bit7
ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Register name Address
000032H
Initial value
00000000 B
ADCH
• A/D Mode Register (ADMD)
This register specfies the A/D converter operation mode and the startup source.
bit15
—
bit14
—
bit13
—
bit12
bit11
MOD1 MOD0 STS1 STS0
(R/W) (R/W) (R/W) (R/W)
bit10
bit9
bit8
Register name Address
000033H
Initial value
- - - X0000 B
ADMD
Reserved
(—)
(—)
(—)
(W)
Note: Program “0” to bit 12 when write. Read value is indeterminated.
• A/D Control Status Register (ADCS)
This register is the A/D converter control and status register.
Register name Address
000034H
bit7
bit6
INT
bit5
bit4
bit3
—
bit2
—
bit1
bit0
Initial value
0000 - - 00 B
ADCS
Reserved
BUSY
INTE PAUS
STRT
(R/W) (R/W) (R/W) (R/W)
(—)
(—)
(W)
(R/W)
• A/D Data Register (ADCD)
This register stores the A/D converter conversion data.
Initial value
bit7
D7
bit6
D6
bit5
D5
bit4
D4
bit3
D3
bit2
D2
bit1
D1
bit0
D0
Register name Address
000036H
ADCD
XXXXXXXX B
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
43
MB90220 Series
Register name Address
bit15
bit14
—
bit13
—
bit12
—
bit11
—
bit10
—
bit9
D9
bit8
D8
Initial value
000000XX B
000037H
ADCD
—
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(2) Block Diagram
AVCC
AVRH/AVRL
AVSS
MPX
AN0
AN1
AN2
AN3
AN4
D/A converter
AN5
AN6
Sequential
comparison register
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
Comparator
Sample and hold circuit
A/D data register
ADCD
Decoder
A/D channel setting register
A/D mode register
ADCH
ADMD
ADCS
A/D control status register
Trigger startup
Timer
ATG
Timer startup
Operation clock
(16-bit reload timer 3 output)
φ
Prescaler
Machine clock
44
MB90220 Series
6. PWC (Pulse Width Count) Timer
The PWC (pulse width count) timer is a 16-bit multifunction up-count timer with an input-signal pulse-width count
function and a reload timer function. The hardware configuration of this module is a 16-bit up-count timer, an
input pulse divider with divide ratio control register, four count input pins, and a 16-bit control register. Using
these components, the PWC timer provides the following features:
• Timer functions:
An interrupt request can be generated at set time intervals.
Pulse signals synchronized with the timer cycle can be output.
Thereference internalclockcanbeselectedfromamongthreeinternalclocks.
The time between arbitrary pulse input events can be counted.
The reference internal clock can be selected from among three internalclocks.
Various count modes:
• Pulse-width count functions:
“H” pulse width (↑ to ↓)/“L” pulse width (↓ to ↑)
Rising-edge cycle (↑ to ↑/Falling-edge cycle (↓ to ↓)
Count between edges (↑ or ↓ to ↓ or ↑)
Cycle count can be performed by 22n division (n = 1, 2, 3, 4) of the input
pulse, with an 8 bit input divider.
An interrupt request can be generated once counting has been performed.
The number of times counting is to be performed (once or subsequently) can
be selected.
The MB90220 series has four channels for this module.
(1) Register Configuration
• PWC Control Status Register 0 to 3 (PWCSR0 to PWCSR3)
Register name Address
bit15
bit14
bit13
bit12
EDIE
bit11
bit10
bit9
bit8
000051 H
000053 H
000055 H
000057 H
PWCSR0
PWCSR1
PWCSR2
PWCSR3
Initial value
00000000B
STRT STOP EDIR
OVIR
OVIE
ERR
POUT
(R/W)
(R/W)
(R)
(R/W) (R/W)
(R/W)
(R)
(R/W)
Register name Address
bit7
bit6
bit5
PIS1
(R/W) (R/W)
bit4
bit3
S/C
bit2
bit1
bit0
PWCSR0
PWCSR1
PWCSR2
PWCSR3
000050 H
000052 H
000054 H
000056 H
Initial value
00000000B
CKS1 CKS0
(R/W)
PIS0
MOD1 MOD1 MOD0
(R/W) (R/W) (R/W)
(R/W) (R/W)
• PWC Data Buffer Register 0 to 3 (PWCR0 to PWCR3)
Register name Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
PWCR0
PWCR1
PWCR2
PWCR3
001F01 H
001F03 H
001F05 H
001F07 H
Initial value
00000000B
(R/W)
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
Register name Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000000B
PWCR0
PWCR1
PWCR2
PWCR3
001F00 H
001F02 H
001F04 H
001F06 H
(R/W)
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
45
MB90220 Series
• PWC Division Ratio Control Register 0 to 3 (DIVR0 to DIVR3)
Register name Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
- - - - - - 00B
00007A H
00007C H
00007E H
000080 H
DIVR0
DIVR1
DIVR2
DIVR3
—
—
—
—
—
—
MOD1 MOD0
(R/W) (R/W)
(—)
(—)
(—)
(—)
(—)
(—)
(2) Block Diagram
PWCR read
16
ERR
Error detector
PWCR
16
16
Internal clock
(machine clock/4)
Reload
Data transfer
16
22
Clock
Overflow
16-bit up-count timer
Clock divider
23
Timer clear
CKS 1
CKS 0
Count enable
Controller
Divider clear
Start edge
select
End edge Division on/off
select
*
PWC 0
PWC 1
PWC 2
PWC 3
Count
start edge
Edge
detector
Count end edge
Count end interrupt request
8-bit
divider
PIS 1 CKS 1
ERR PIS 0 CKS 0
PIS 1
PIS 0
Overflow interrupt
request
15
PWCSR
Divider
selection
2
Overflow
F.F.
POT
DIVR
*: In the MB90220 series, only the module input PWC 0 of each channel is connected to the respective external pins.
POT pin
Channel
PWC ch. 0
PWC ch. 1
PWC ch. 2
PWC ch. 3
PA 1/PWC 0/POT 0
PA 2/PWC 1/POT 1/ASR 1
PA 3/PWC 2/POT 2/ASR 2
PA 4/PWC 3POT 3/ASR 3
46
MB90220 Series
7. DTP/External Interrupts
DTP (Data Transfer Peripheral) is located between external peripherals and the F2MC-16F CPU. It receives a
DMA request or an interrupt request generated by the external peripherals and reports it to the F2MC-16F CPU
to activate the extended intelligent I/O service or interrupt handler. The user can select two request levels of “H”
and “L” for extended intelligent I/O service or, and four request levels of “H,” “L,” rising edge and falling edge for
external interrupt requests. In MB90220, only parts corresponding to INT2 to INT0 are usable as external
interrupt/DTP request.
Parts corresponding to INT7 to INT3 cannot be used as external interrupt/DTP request, but only for edge
detection at external terminals.
Note: INT7 to INT3 are not usable as DTP/external interrupts.
(1) Register Configuration
• DTP/Interrupt Enable Register (ENIR)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Register name Address
Initial value
00000000B
00003A H
ENIR
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
(R/W)
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
• DTP/Interrupt Source Register (EIRR)
Register name Address
00003B H
bit15
ER7
bit14
ER6
bit13
ER5
bit12
ER4
bit11
ER3
bit10
ER2
bit9
bit8
Initial value
00000000B
EIRR
ER1
ER0
(R/W)
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
• Request Level Setting Register (ELVR)
bit15
LB7
bit14
LA7
bit13
LB6
bit12
LA6
bit11
LB5
bit10
LA5
bit9
bit8
Initial value
00000000B
Register name Address
00003D H
ELVR
LB4
LA4
(R/W)
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000000B
Register name Address
00003C H
ELVR
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
(R/W)
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
(2) Block Diagram
4
Interrupt/DTP enable register
4
4
8
Gate
Source F/F
Edge detector
INT
Interrupt/DTP source register
8
Request level setting register
47
MB90220 Series
8. 24-bit Timer Counter
The 24-bit timer counter consists of a 24-bit up-counter, an 8-bit output buffer register, and a control register.
The count value output by this timer counter is used to generate the base time used for input capture and output
compare.
The interrupt functions provided are timer overflow interrupts and timer intermediate bit interrupts. The
intermediate bit interrupt permits four time settings.
The 24-bit timer counter value is cleared to all zeroes by a reset.
(1) Register Configuration
• Free-run Timer Control Register (TCCR)
Register name Address
000071 H
bit15
—
bit14
—
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
- - 111111B
TCCR
Reserved Reserved Reserved Reserved Reserved
PR0
(—)
(—)
(W)
(W)
(R/W)
(R/W) (R/W) (R/W)
Register name Address
000070 H
bit7
bit6
bit5
IVF
bit4
bit3
TIM
bit2
bit1
bit0
Initial value
11000000B
TCCR
CLR2
CLR
IVFE
TIME
TIS1
TIS0
(W)
(W)
(R/W) (R/W) (R/W)
(R/W) (R/W) (R/W)
• Free-run Timer Low-order Data Register (TCRL)
bit15
bit0
Register name Address
Initial value
00000000 B
Access
R
000072 H
000073 H
TCRL
TCRL
• Free-run Timer High-order Data Register (TCRH)
bit15
bit8 bit7
bit0
Register name Address
Initial value Access
000074 H
000075 H
TCRH
—
TCRH
R
00000000 B
48
MB90220 Series
(2) Block Diagram
Timer counter clocks
CK0
CK1
2
2
Internal
φ/3
φ/4
basic
clock
CLR (prescaler clear)
CLR2 (prescaler clear, 24-bit timer counter STOP bit)
PR0
2
Clear bit
CLR/CLR2
CLR
2
2
CLR2
CK0, CK1
Higher-order 8-bit counter
CK0
CK1
Lower-order 16-bit counter
Timer counter bit output
8
2
Carry
T23 to T16
4
16
T0 to T15
8
“0”
Output buffer
16
16
16
2
10th bit
11th bit
12th bit
13th bit
TIS1
TIS0
23rd bit
Intermediate bit interrupt
cycle setting
Interrupt enable
Interrupt flag
4
IVF
IVFE
TIM
TIME
Intermediate bit interrupt request
Overflow interrupt request
TIM
IVF
49
MB90220 Series
9. OCU (Output Compare Unit)
The OCU (Output Compare Unit) consists of a 24-bit output compare register, a comparator, and a control
register.
The match detection signal is output when the contents of the output compare register match the contents of
the 24-bit timer counter. This match detection signal can be used to change the output value of the corresponding
pin, or can be used to generate an interrupt. One block consists of four output compare units, and the four
output compare registers use one comparator to perform time division comparisons.
(1) Register Configuration
• OCUO Control Register 00, 01 (CCR00, CCR01)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Register name Address
Initial value
- - - - 0000
000061 H
CCR00
CCR02
000063 H
—
—
—
—
MD3
MD2
MD1
MD0
(—)
(—)
(—)
(—)
(R/W) (R/W) (R/W) (R/W)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Register name Address
Initial value
11110000
000060 H
000062 H
CCR00
CCR02
SEL3
(R/W)
SEL2
SEL1
SEL0 CPE3 CPE2 CPE1 CPE0
(R/W) (R/W) (R/W) (R/W) (R/W)
(R/W) (R/W)
• OCUO Control Register 10, 11 (CCR10, CCR11)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Register name Address
Initial value
00000000
CCR10
CCR11
000069 H
00006B H
ICE3
ICE2
ICE1
ICE0
IC3
IC2
IC1
IC0
(R/W)
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
Register name Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CCR10
CCR11
000068 H
00006A H
Initial value
- - - - 0000
—
—
—
—
DOT3 DOT2 DOT1 DOT0
(R/W) (R/W) (R/W) (R/W)
(—)
(—)
(—)
(—)
• OCU Compare Low-order Data Register 00 to 07 (CPR00L to CPR07L)
Register name Address
CPR00L
CPR01L
CPR02L
CPR03L
CPR04L
CPR05L
CPR06L
CPR07L
001F11 H
001F15 H
001F19 H
001F1D H
001F21 H
001F25 H
001F29 H
001F2D H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00000000
(R/W)
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
Register name Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CPR00L
CPR01L
CPR02L
CPR03L
CPR04L
CPR05L
CPR06L
CPR07L
001F10 H
001F14 H
001F18 H
001F1C H
001F20 H
001F24 H
001F28 H
001F2C H
Initial value
00000000
—
—
(R/W)
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
50
MB90220 Series
• Output Compare High-order Data Register 00 to 07 (CPR00H to CPR07H)
Register name Address
CPR00
CPR01
CPR02
CPR03
CPR04
CPR05
CPR06
CPR07
001F13 H
001F17 H
001F1B H
001F1F H
001F23 H
001F27 H
001F2B H
001F2F H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00000000
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
Register name Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CPR00
CPR01
CPR02
CPR03
CPR04
CPR05
CPR06
CPR07
001F12 H
001F16 H
001F1A H
001F1E H
001F22 H
001F26 H
001F2A H
001F2E H
Initial value
00000000
—
—
(R/W)
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
51
MB90220 Series
(2) Block Diagram
24-bit timer counter
Compare unit*
4
T2 to T23
22
Match signal
Comparator controller
MATCH0 to 3
Interrupt enable ICE0 to 3
8
14
ICE3
ICE2
ICE1
ICE0
IC3
Output latch
Output latch
14
8
24
24
24
24
CPR03
CPR02
CPR01
CPR03L
CPR02L
CPR01L
Interrupt
request signals
4
ICMP0 to 3
IC2
CPR00
Output
CPR00L
Output
IC1
compare register compare register
higher-order 8 bits lower-order 16 bits
IC0
Interrupt flags IC0 to 3
8
4
4
Source
selector
4
Match source signals
EXT0 to 3
4
Match detection signal selection
Match operation enable
8
SEL3 SEL2 SEL1
SEL0
CPE3 CPE2
CPE1 CPE0
24-bit timer counter
data T0
Port general purpose/compare dedicated switching
Clock
selector
4
MD3
MD2
MD1
MD0
DOT pin data output
(also serves as general-purpose port data register)
4
4
DOT0 to 3
4
DOT3 DOT2 DOT1 DOT0
4
Pin
Data register read
4
4
Direction register
Direction register write
Direction register read
Port 7
(Continued)
52
MB90220 Series
(Continued)
*: There are two compare units drawn as below.
Internal data bus
timer count data
Compare unit
4
23
MATCH 0 to 3
T1 to T23
RB15 to 0
Interrupt request ICOMP 0 to 3
ICOMP 0 to 3
Compare 00 to 03
DOT 0 to 3
16
16
4
Pin output
DOT 0 to 3
EXT 0 to 3
ICOMP 0, 2
Interrupt request
ICOMP 4/6
MATCH 0 to 3
T1 to T23
RB15 to 0
OPEN
2
4
4
ICOMP 0 to 3
Compare 10 to 13
DOT 0 to 3
OR
Pin output
DOT 4 to 7
2
OR
ICOMP 5/7
EXT 0 to 3
ICOMP 1, 3
53
MB90220 Series
10. ICU (Input Capture Unit)
This module detects either the rising edge, falling edge, or both edges of an externally input waveform and holds
the value of the 24-bit timer counter at that time, while at the same time the module generates an interrupt
request for the CPU. The module consists of a 24-bit input capture data register and a control register. There
are four external input pins (ASR0 to ASR3); the operation of each input is described below.
ASR0 to ASR3: Each of these input pinshasa corresponding inputcaptureregister. When the specified
valid edge (↑ or ↓ or ↑ ↓) is detected, the register can be used to store the 24-bit timer
counter value.
(1) Register Configuration
• ICU Control Register 0 (ICC0)
bit7
EG3B EG3A EG2B EG2A EG1B EG1A EG0B EG0A
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Register name Address
Initial value
00000000B
000058 H
ICCO
• ICU Control Register 1 (ICC1)
bit7
bit6
bit5
bit4
bit3
IR3
bit2
IR2
bit1
IR1
bit0
IR0
Register name Address
Initial value
00000000B
ICCI
00005A H
IRE3
IRE2
IRE1
IRE0
(R/W)
(R/W) (R/W)
(R/W) (R/W)
(R/W) (R/W) (R/W)
• ICU Low-order Data Register (ICRL0 to ICRL3)
bit15
bit14
bit13
bit12
bit11
D11
bit10
D10
bit9
bit8
Register name Address
Initial value
XXXXXXXXB
001F50 H
001F54 H
001F58 H
001F5C H
ICRL0
ICRL1
ICRL2
ICRL3
D15
(R)
D14
D13
D12
D09
(R)
D08
(R)
(R)
(R)
(R)
(R)
(R)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Register name Address
Initial value
XXXXXXXXB
001F51 H
001F55 H
001F59 H
001F5D H
ICRL0
ICRL1
ICRL2
ICRL3
D07
(R)
D06
(R)
D05
(R)
D04
(R)
D03
(R)
D02
(R)
D01
(R)
D00
(R)
• ICU High-order Data Register (ICRH0 to ICRH3)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Register name Address
Initial value
XXXXXXXXB
001F52 H
001F56 H
001F5A H
001F5E H
ICRH0
ICRH1
ICRH2
ICRH3
—
—
—
—
—
—
—
—
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Register name Address
Initial value
00000000B
001F53 H
001F57 H
001F5B H
001F5F H
ICRH0
ICRH1
ICRH2
ICRH3
D23
(R)
D22
(R)
D21
(R)
D20
(R)
D19
(R)
D18
(R)
D17
(R)
D16
(R)
54
MB90220 Series
(2) Block Diagram
8
EG3B EG3A EG2B EG2A EG1B EG1A EG0B EG0A Edge detection
polarity (ICC0)
24-bit timer counter input
T23
to T0
8
16
24
8
T23 to
T16
T15 to T00
ASR0
ASR2
ICRH0
ICRH1
ICRH2
ICRH3
ICRL0
ICRL1
ICRL2
ICRL3
Edge detection 0
Edge detection 1
Edge detection 2
Edge detection 3
ASR1
ASR3
Edge detection 0 to 3:
↑ or ↓ or ↑↓
Output latch
8
4
4
EGO0 to EGO3
EGI0 to EGI3
16
Interrupt request flags (ICC1)
IR0
IR1
IR2
IR3
4
IRQ0 to IRQ3
4
4
IRE3
IRE2
IRE1
IRE0 Interrupt enable
(ICC1)
Capture
55
MB90220 Series
11. 16-bit PPG Timer
This module can output a pulse synchronized with an external trigger or a software trigger. In addition, the cycle
and duty ratio of the output pulse can be changed as desired by overwriting the two 16-bit register values.
PWM function:
Synchronizes pulse with trigger, and permits programming of the pulse output by
overwriting the register values mentioned above.
This function permits use as a D/A converter with the addition of external circuits.
One-shot function: Detects the edge of trigger input, and permits single-pulse output. There is no
trigger input for PPG1.
This module consists of a 16-bit down-counter, a prescaler, a 16-bit synchronization setting register, a 16-bit
duty register, a 16-bit control register, one external trigger input pin, and one PPG output pin.
(1) Register Configuration
• PPG Control Status Register (PCNT0, PCNT1)
bit15
CNTE STGR MDSE RTRG CKS1 CKS0 PGMS
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
bit14
bit13
bit12
bit11
bit10
bit9
bit8
—
Register name Address
Initial value
00000000B
0004D H
PCNT0
PCNT1
0004F H
Overwrite during operation→
Register name Address
bit7
EGS1 EGS0 IREN
(R/W) (R/W) (R/W)
bit6
bit5
bit4
bit3
IRS1
bit2
bit1
bit0
Initial value
00000000B
0004C H
PCNT0
IRQF
IRS0
POEN OSEL
0004E H
PCNT1
(R/W) (R/W)
(R/W) (R/W) (R/W)
Overwrite during operation→
• PPG0, PPG1 Cycle Setting Register (PCSP0, PCSP1)
bit15
(W)
bit14
(W)
bit13
(W)
bit12
(W)
bit11
(W)
bit10
(W)
bit9
(W)
bit8
(W)
Register name Address
Initial value
001F49 H
001F4D H
PCSP0
PCSP1
XXXXXXXXB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Register name Address
Initial value
XXXXXXXXB
PCSP0
PCSP1
001F48 H
001F4C H
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
• PPG0, PPG1 Duty Setting Register (PDUT0, PDUT1)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Register name Address
Initial value
XXXXXXXXB
001F4B H
001F4F H
PDUT0
PDUT1
(W)
(W)
(W)
(W)
(W)
(W)
bit2
(W)
bit1
(W)
bit0
Register name Address
bit7
bit6
bit5
bit4
bit3
Initial value
XXXXXXXXB
001F4A H
001F4E H
PDUT0
PDUT1
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
56
MB90220 Series
(2) Block Diagram
PCSR
PDUT
Prescaler
1/1
cmp
1/4
ck
Load
16-bit down-counter
1/16
1/64
Start
Borrow
PPG mask
S
Q
Oscillation clock
PPG output
R
Reverse bit
Enable
IRQ
Interrupt
selector
TRG input
Edge detection
Software trigger
57
MB90220 Series
12. Watchdog Timer and Timebase Timer Functions
The watchdog timer consists of a 2-bit watchdog counter using carry from an 18-bit timebase timer as the clock
source, a control register, and a watchdog reset control section. The timebase timer consists of an 18-bit timer
and an interval interrupt control circuit.
(1) Register Configuration
• Watchdog Timer Control Register (WDTC)
Register name Address
0000A8 H
bit7
bit6
bit5
bit4
bit3
bit2
WTE
(W)
bit1
WT1
(W)
bit0
WT0
(W)
Initial value
WDTC
PONR STBR WRST ERST SRST
XXXXXXXX
(R)
(R)
(R)
(R)
(R)
• Timebase Timer Control Register (TBTC)
Register name Address
0000A9 H
bit15
—
bit14
—
bit13
—
bit12
TBIE
bit11
bit10
TBR
bit9
bit8
Initial value
- - - XXXXX
TBTC
TBOF
TBC1 TBC0
(R/W) (R/W)
(—)
(—)
(—)
(R/W) (R/W)
(R)
(2) Block Diagram
Oscillation clock
Clock input
Timebase timer
212
TBTC
TBC1
214
216
218
Selector
TBC0
TBR
TBTRES
214 216 217 218
S
R
TBIE
Q
AND
TBOF
Timebase
interrupt
WDTC
WT1
2-bit counter
Watchdog reset
signal generator
WDGRST
Selector
OF
To internal reset signal generator
CLR
CLR
WT0
WTE
PONR
STBR
WRST
ERST
SRST
From power-on signal generator
From hardware standby controller
RST pin
From RST bit of STBYC register
58
MB90220 Series
13. Delay Interruupt Generation Module
The delayed interrupt generation module is used to generate an interrupt task switching. Using this module
allows an interrupt request to the F2MC-16F CPU to generated or cancel by software.
(1) Register Configuration
• Delay Interrupt Source Generation/Cancel Register (DIRR)
Register name Address
bit15
—
bit14
—
bit13
—
bit12
—
bit11
—
bit10
—
bit9
—
bit8
R0
Initial value
- - - - - - - 0
DIRR
00009F H
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R/W)
(2) Block Diagram
Delay interrupt source generation/cancel decoder
Source latch
59
MB90220 Series
14. Write-inhibit RAM
The write-inhibit RAM is write-protectable with the WI pin input. Maintaining the “L” level input to the WI pin
prevents a certain area of RAM from being written. The WI pin has a 4-machine-cycle filter.
(1) Register Configuration
• WI Control Register (WICR)
Register name Address
00008E H
bit7
—
bit6
—
bit5
—
bit4
WI
bit3
—
bit2
—
bit1
—
bit0
—
Initial value
- - - X - - - -
WICR
(—)
(—)
(—)
(R/W)
(—)
(—)
(—)
(—)
(2) Write-inhibit RAM Areas
Write-inhibit RAM areas: 000D00H to 000EFFH (MB90223)
001300H to 0014FFH (MB90224/P224A/P224B/W224A/W224B)
001500H to 0018FFH (MB90V220)
(3) Block Diagram
Other area access
Write-inhibit
circuit
WR
Write-inhibit
RAM
Priority
Q
Select
4-machine cycle smoothing circuit
4-machine cycle smoothing circuit
S
R
Q
S
R
L
WI
H
RAM
decoder
Internal data bus
60
MB90220 Series
15. Low-power Consumption Modes, Oscillation Stabilization Delay Time, and Gear Function
The MB90220 series has three low-power consumption modes: the sleep mode, the stop mode, the hardware
standby mode, and gear function.
Sleep mode is used to suspend only the CPU operation clock; the other components remain in operation. Stop
mode and hardware standby mode stop oscillation, minimizing the power consumption while holding data.
The gear function divides the external clock frequency, which is used usually as it is, to provide a lower machine
clock frequency. This function can therefore lower the overall operation speed without changing the oscillation
frequency. The function can select the machine clock as a division of the frequency of crystal oscillation or
external clock input by 1, 2, 4, or 16.
The OSC1 and OSC0 bits can be used to set the oscillation stabilization delay time for wake-up from stop mode
or hardware standby mode.
(1) Register Configuration
• Standby Control Register (STBYC)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Register name Address
0000A0 H
Initial value
0001* * * *
STBYC
STP
SLP
SPL
RST
OSC1 OSC0 CLK1 CLK0
(W)
(W)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Note: The initial value (*) of bit0 to bit3 is changed by reset source.
61
MB90220 Series
(2) Block Diagram
Oscillation clock
CPU clock
Gear divider
1/1 1/2 1/4 1/16
CPU clock
generator
STBYC
CLK1
Selector
CLK0
Peripheral clock
generator
Peripheral clock
SLP
STP
Standby controller
RST Release HST start
HST pin
Interrupt request or RST
Clock input
20
216
217
218
OSC1
OSC0
Timebase timer
214 216 217 218
Selector
SPL
RST
Pin Hi-Z
Pin high impedance controller
RST pin
Internal reset
signal generator
Internal RST
To watchdog timer
WDGRST
62
MB90220 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
Value
Symbol
Pin name
Unit
Remarks
Parameter
Min.
Max.
Power supply voltage
Program voltage
VCC
VPP
VCC
VSS – 0.3
VSS + 7.0
V
V
MB90P224A/P224B
MB90W224A/W224B
VPP
VSS – 0.3
13.0
Power supply voltage
for A/D converter
AVCC
AVCC
VSS – 0.3
VSS – 0.3
VCC + 0.3
V
V
Analog power supply
voltage
Reference voltage for
A/D converter
AVRH
AVRL
AVRH
AVRL
AVCC
Input voltage
VI*1
VO
—
VSS – 0.3
VSS – 0.3
—
VCC + 0.3
VCC + 0.3
20
V
V
2
Output voltage
*
3
“L” level output current
IOL
*
mA Rush current
mA Total output current
mA Rush current
mA Total output current
mW
“L” level total output
current
3
ΣIOL
IOH
*
—
—
50
–10
–48
650
+105
2
“H” level output current
*
“H” level total output
current
2
ΣIOH
PD
—
*
Power consumption
Operating temperature
Storage temperature
—
—
—
—
MB90223/224/P224B
/W224B
–40
°C
TA
–40
–55
+85
°C MB90P224A/W224A
°C
Tstg
+150
*1: V1 must not exceed VCC + 0.3 V.
*2: Output pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77, P80 to
P87, PA0 to PA7, PB0 to PB7, PC0 to PC5
*3: Output pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to
P77, P80 to P87, P90 to P97, PA0 to PA7, PB0 to PB7, PC0 to PC5
WARNING:Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
63
MB90220 Series
2. Recommended Operating Condition
(VSS = AVSS = 0.0 V)
Value
Pin
name
Symbol
Unit
Remarks
Parameter
Min.
Max.
4.5
5.5
V
V
When operating
Power supply voltage
VCC
VCC
Retains the RAM state in
stop mode
3.0
4.5
5.5
Power supply voltage for
A/D converter
AVCC
AVCC
VCC + 0.3
V
Analog power supply
voltage
AVRH
AVRL
AVRH
AVRL
AVRL
AVSS
AVCC
V
V
Reference voltage for A/D
converter
AVRH
MB90224/P224A/W224A
MB90P224B/W224B
10
10
16
12
MHz
Clock frequency
FC
—
MHz MB90223
Single-chip mode
–40
+105
°C
MB90223/224/P224B/
W224B
Operating temperature
TA*
—
Single-chip mode
MB90P224A/W224A
–40
–40
+85
+70
°C
°C
External bus mode
* : Excluding the temperature rise due to the heat produced.
WARNING:Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
64
MB90220 Series
3. DC Characteristics
Single-chip mode MB90223/224/P224B/W224B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P224A/W224A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
External bus mode
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Parameter
Symbol Pin name
Condition
Unit
Remarks
Min.
Typ. Max.
VIH
X0
—
—
—
—
—
—
0.7 VCC
0.8 VCC
VCC – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
—
—
—
—
—
—
VCC + 0.3
VCC + 0.3
VCC + 0.3
0.3 VCC
V
V
V
V
V
V
CMOS level input
Hysteresis input
“H” level input
voltage
1
VIHS
VIHM
VIL
*
MD0 to MD2
X0
CMOS level input
Hysteresis input
“L” level input
voltage
1
VILS
VILM
0.2 VCC
*
MD0 to MD2
VSS + 0.3
VCC = 4.5 V
IOH = –4.0 mA
2
VOH
VOH1
VOL
VCC – 0.5
—
—
—
—
VCC
VCC
V
V
V
V
*
“H” level
output voltage
VCC = 4.5 V
IOH = –2.0 mA
X1
VCC – 2.5
VCC = 4.5 V
IOL = 4.0 mA
3
0
0
0.4
*
“L” level
output voltage
VCC = 4.5 V
IOL = 2.0 mA
VOL1
X1
VCC – 2.5
Hysteresis input
Except pins with
µA pull-up/pull-
down resistor
and RST pin
VCC = 5.5 V
0.2 VCC < VI < 0.8 VCC
1
II
*
—
—
±10
Input leackage
current
VCC = 5.5 V
0.2 VCC < VI2 < 0.8 VCC
II2
X0
—
—
±20
µA
4
*
MB90223/224
MB90P224A/
RST
—
22
50
110
kΩ
Pull-up resistor RpulU
W224A
4
*
MD1
—
—
22
22
50
50
150
150
kΩ
MB90223/224
4
Pull-down
RpulD
MD0
MD2
*
kΩ
resistor
MB90223/224
70*5
70*5
FC = 12 MHz
FC = 16 MHz
—
—
100
100
mA MB90223
mA MB90224
MB90P224A/
ICC
VCC
P224B
MB90W224A/
W224B
FC = 16 MHz
fC = 16 MHz*9
—
—
—
—
90*5
—
125
60
mA
Power supply
voltage*8
ICCS
VCC
VCC
mA At sleep mode
In stop mode
TA = +25°C
At hardware
ICCH
5
10
µA
standby
(Continued)
65
MB90220 Series
(Continued)
Value
Parameter
Symbol Pin name
Condition
fC = 16 MHz*9
Unit
Remarks
Min.
—
Typ. Max.
IA
3
7
mA
Analog power
supply voltage
AVCC
IAH
—
—
—
—
5*6
µA At stop mode
Input
capacitance
7
CIN
*
—
10
—
pF
*1: Hysteresis input pins
RST, HST, P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P80 to P87,
P90 to P97, PA0 to PA7, PB0 to PB7, PC0 to PC5
*2: Ouput pins
P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77, P80 to P87, PA0 to
PA7, PB0 to PB7, PC0 to PC5
*3: Output pins
P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to
P87, P90 to P97, PA0 to PA7, PB0 to PB7, PC0 to PC5
*4: A list of availabilities of pull-up/pull-down resistors
Pin name
RST
MB90223/224
MB90P224A/W224A
MB90P224B/W224B
Availability of pull-up resistors is optionally
defined.
Pull-up resistors
available
Unavailable
MD1
Pull-up resistors available
Pull-up resistors available
Unavailable
Unavailable
Unavailable
Unavailable
MD0, MD2
*5: VCC = +5.0 V, VSS = 0.0 V, TA = +25°C, FC = 16 MHz
*6: The current value applies to the CPU stop mode with A/D converter inactive (VCC = AVCC = AVRH = +5.5 V).
*7: Other than VCC, VSS, AVCC and AVSS
*8: Measurement condition of power supply current; external clock pin and output pin are open.
Measurement condition of VCC; see the table above mentioned.
*9: FC = 12 MHz for MB90223
66
MB90220 Series
4. AC Characteristics
(1) Clock Timing Standards
Single-chip mode MB90223/224/P224B/W224B : (VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P224A/W224A
: (VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
External bus mode
: (VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
Symbol
Condition
Unit
Remarks
Parameter
name
Min.
10
Typ.
Max.
16
MB90224/
P224A/P224B
MB90W224A/
W224B
—
MHz
Clock frequency
FC
X0, X1
X0, X1
—
10
—
12
MHz MB90223
MB90224/
P224A/P224B
MB90W224A/
W224B
62.5
—
100
ns
Clock cycle time
tC
—
83.4
—
—
100
ns
ns
MB90223
PWH
PWL
Equivalent to
60% duty ratio
Input clock pulse width
X0
X0
—
—
0.4 tc
0.6 tc
Input clock rising/falling
times
tcr
tcf
—
—
8
ns
tcr + tcf
tC = 1/fC
• Clock Input Timings
tc
0.7 VCC
0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
PWH
PWL
tcr
tcf
• Clock Conditions
When a crystal
or
When an external clock is used
ceramic resonator is used
X0
X1
X0
X1
Open
C1
C2
C1 = C2 = 10 pF
Select the optimum capacity value for the resonator
67
MB90220 Series
• Relationship between Clock Frequency and Supply Voltage
Single-chip mode
(MB90224/P224B/W224B) : TA = –40°C to +105°C, Fc = 10 to 16 MHz
VCC
[V]
(MB90223)
(MB90P224A/W224A)
External bus mode
: TA = –40°C to +105°C, Fc = 10 to 12 MHz
: TA = –40°C to +85°C, Fc = 10 to 16 MHz
: TA = –40°C to +70°C, Fc = 10 to 16 MHz
(Fc = 10 to 12 MHz, only for MB90223)
5.5
4.5
Operation assurance range
Fc
[MHz]
0
10
12
16
68
MB90220 Series
(2) Clock Output Timing
(External bus mode: VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
name
Symbol
Condition
Unit
Remarks
Parameter
Min.
Typ.
Max.
MB90224/
P224A/P224B
MB90W224A/
224B
62.5
—
1600
ns
Load
condition:
80 pF
Machine cycle time
tCYC
CLK
CLK
83.4
—
—
1600
ns MB90223
ns
CLK ↑ → CLK↓
tCHCL
tCYC/2 – 20
tCYC/2
tCYC = n/FC, n gear ratio (1, 2, 4, 16)
tCYC
tCHCL
CLK
1/2 VCC
(3) Reset and Hardware Standby Input Standards
Single-chip mode MB90223/224/P224B/W224B: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P224A/W224A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
External bus mode
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
Symbol
Condition
Unit Remarks
Parameter
name
Min.
5 tCYC
5 tCYC
Typ.
—
Max.
—
Reset input time
Hardware standby input time
tRSTL
tHSTL
RST
HST
ns
—
—
—
ns
*
*: The machine cycle time (tCYC) at hardware standby is set to 1/16 divided oscillation.
tRSTL, tHSTL
RST
HST
0.2 VCC
0.2 VCC
69
MB90220 Series
(4) Power on Supply Specifications (Power-on Reset)
Single-chip mode MB90223/224/P224B/W224B: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P224A/W224A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
External bus mode
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Symbol Pin name Condition
Unit
Remarks
Parameter
Min.
—
Typ.
—
Max.
30
Power supply rising time
Power supply cut-off time
tR
VCC
VCC
—
—
ms
ms
*
tOFF
1
—
—
* : Before power supply rising, it is required to be VCC < 0.2 V.
Notes: • Power-on reset assumes the above values.
• Whether the power-on reset is required or not, turn the power on according to these characteristics and
trigger the power-on reset.
• There are internal registers (STBYC, etc.) which is initialized only by the power-on reset in the device.
• Power-on Reset
tR
VCC
4.5 V
0.2 V
0.2 VCC
0.2 VCC
tOFF
Note: Note on changing power supply
Even if above characteristics are not insufficient, abrupt changes in power supply voltage may cause a power-
on reset. Therefore, at the time of a momentary changes such as when power is turned on, rise the power
smoothly as shown below.
• Changing Power Supply
Main power supply voltage
This rising edge should be
Subpower supply voltage
50 mV/ms or less
Vss
70
MB90220 Series
(5) Bus Read Timing
Parameter
(VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Symbol Pin name Condition
Unit Remarks
Min.
tCYC/2 – 20
tCYC – 25
—
Max.
Valid address → RD ↓ time
RD pulse width
tAVRL
tRLRH
tRLDV
tRHDX
A23 to A00
RD
—
—
ns
ns
ns
ns
ns
ns
RD ↓ → Valid data input
RD ↑ → Data hold time
tCYC – 30
—
D15 to D00
0
Load
condition:
80 pF
Valid address → Valid data input tAVDV
—
3 tCYC/2 – 40
—
RD ↑ → Address valid time
Valid address → CLK ↑ time
RD ↓ → CLK ↓ time
tRHAX
tAVCH
tRLCL
A23 to A00
tCYC/2 – 20
A23 to A00
CLK
tCYC/2 – 25
tCYC/2 – 25
—
—
ns
ns
RD, CLK
tAVCH
tRLCL
0.7 VCC
0.3 VCC
CLK
RD
tAVRL
tRLRH
0.7 VCC
0.3 VCC
tRHAX
0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
A23 to A00
D15 to D00
tRHDX
tRLDV
tAVDV
0.8 VCC
0.2 VCC
0.8 VCC
Read data
0.2 VCC
71
MB90220 Series
(6) Bus Write Timing
(VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Symbol Pin name Condition
Unit Remarks
Parameter
Min.
Max.
—
Valid address → WR ↓ time
tAVWL
tWLWH
A23 to A00
WRL, WRH
D15 to D00
D15 to D00
A23 to A00
tCYC/2 – 20
tCYC – 25
tCYC – 40
tCYC/2 – 20
tCYC/2 – 20
ns
ns
ns
ns
ns
WR pulse width
—
Valid data output → WR ↑ time tDVWH
—
Load
condition:
80 pF
WR ↑ → Data hold time
tWHDX
tWHAX
—
WR ↑ → Address valid time
—
WRL,
WRH, CLK
WR ↓ → CLK ↓ time
tWLCL
tCYC/2 – 25
—
ns
tWLCL
0.3 VCC
CLK
tWLWH
WR
0.7 VCC
(WRL, WRH)
0.3 VCC
tAVWL
tWHAX
0.7 VCC
0.3 VCC
0.7 VCC
A23 to A00
D15 to D00
0.3 VCC
tDVWH
tWHDX
0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
Indeter-
minate
Read data
72
MB90220 Series
(7) Ready Input Timing
Parameter
(VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
Symbol
Condition
Unit
Remarks
name
Min.
40
Max.
—
RDY setup time
RDY hold time
tRYHS
tRYHH
RDY
RDY
ns
ns
Load condition:
80 pF
0
—
Note: Use the auto-ready function if the RDY setup time is insufficient.
CLK
0.7 VCC
0.7 VCC
A23 to A00
RD/WR
(WRL, WRH)
tRYHH
tRYHH
tRYHS
tRYHS
RDY
0.8 VCC
0.8 VCC
No wait
One wait
0.8 VCC
0.8 VCC
0.2 VCC
(8) Hold Timing
Parameter
(VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
Symbol
Condition
Unit
Remarks
name
Min.
30
Max.
tCYC
Pin floating → HAK ↓ time
HAK ↑ time → pin valid time
tXHAL
tHAHV
HAK
HAK
ns
ns
Load condition:
80 pF
tCYC
2 tCYC
Note: It takes at least one machine cycle for HAK to vary after HRQ is fetched.
0.8 VCC
HRQ
0.2 VCC
0.7 VCC
HAK
0.3 VCC
tHAHV
tXHAL
Each pin
High impedance
73
MB90220 Series
(9) UART Timing
Single-chip mode MB90223/224/P224B/W224B: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P224A/W224A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
External bus mode
Value
Pin
Symbol
Condition
Unit Remarks
Parameter
name
Min.
8 tCYC
–80
100
60
Max.
—
Serial clock cycle time
SCLK ↓ → SOUT delay time
Valid SIN → SCLK ↑
tSCYC
tSLOV
tIVSH
—
—
—
—
—
—
—
—
—
ns
Internal
clock
80
—
ns
Load condition:
80 pF
operation
output pin
ns
ns
SCLK ↑ → Valid SIN hold time tSHIX
—
Serial clock “H” pulse width
Serial clock “L” pulse width
SCLK ↓ → SOUT delay time
Valid SIN → SCLK ↑
tSHSL
tSLSH
tSLOV
tIVSH
4 tCYC
4 tCYC
—
—
ns
—
ns
ns
ns
ns
External
clock
operation
output pin
Load condition:
80 pF
150
—
60
SCLK ↑ → valid SIN hold time tSHIX
60
—
Notes: • These AC characteristics assume in CLK synchronization mode.
• “tCYC” is the machine cycle (unit: ns).
74
MB90220 Series
• Internal Shift Clock Mode
tSCYC
0.7 VCC
SCK
0.3 VCC
0.3 VCC
tSLOV
0.7 VCC
0.3 VCC
SOD
SID
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• External Shift Clock Input Mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
tSLOV
0.7 VCC
0.3 VCC
SOD
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SID
75
MB90220 Series
(10) Resourse Input Timing
Single-chip mode MB90223/224/P224B/W224B: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P224A/W224A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
External bus mode
Parameter
Symbol
Pin name
Condition
Unit
Remarks
Min.
Typ.
Max.
External event
count input mode
4 tCYC
—
—
ns
TIN1 to TIN5
Triggerinput/gate
input mode
2 tCYC
—
—
ns
tTIWH
tTIWL
Load
condition:
80 pF
PWC0 to PWC3
ASR0 to ASR3
INT0 to INT7
TRG0
2 tCYC
2 tCYC
3 tCYC
2 tCYC
2 tCYC
4 tCYC
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Input pulse width
ATG
tWIWL
WI
0.8 VCC
0.8 VCC
0.2 VCC
TIN1 to TIN5
0.2 VCC
PWC0 to PWC3
ASR0 to ASR3
INT0 to INT7
WI
tTIWL, tWIWL
tTIWH
TRG0
ATG
(11) Resourse Output Timing
Single-chip mode MB90223/224/P224B/W224B: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P224A/W224A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
External bus mode
Parameter
Symbol
Pin name
Condition
Unit
Remarks
Min.
Typ.
Max.
TOT0 to TOT5
PPG0 to PPG1
POT0 to POT3
DOT0 to DOT7
Load
condition:
80 pF
CLK ↑ → TOUT
tTO
—
—
30
ns
transition time
0.7 VCC
CLK
TOUT
0.7 VCC
0.3 VCC
tTO
76
MB90220 Series
5. A/D Converter Electrical Characteristics
Single-chip mode MB90223/224/P224B/W224B
: (AVCC = VCC = +4.5 V to +5.5 V, AVSS =VSS = 0.0 V, TA = –40°C to +105°C, +4.5 V ≤ AVRH – AVRL)
MB90P224A/W224A
: (AVCC = VCC = +4.5 V to +5.5 V, AVSS = VSS =0.0 V, TA = –40°C to +85°C, +4.5 V ≤ AVRH – AVRL)
: (AVCC = VCC = +4.5 V to +5.5 V, AVSS = VSS =0.0 V, TA = –40°C to +70°C, +4.5 V ≤ AVRH – AVRL)
External bus mode
Value
Pin
Parameter
Symbol
Condition
Unit Remarks
name
Min.
—
Typ.
—
Max.
10
Resolution
n
—
—
—
—
—
—
—
—
—
bit
Total error
—
—
—
V0T
—
—
±3.0
±2.0
±1.5
LSB
LSB
LSB
Linearity error
—
—
Differential linearity error
Zero transition voltage
—
—
AVRL – 1.5 AVRL + 0.5 AVRL + 2.5 LSB
AN00to
AN15
Full-scale transition
voltage
VFST
—
AVRH – 3.5 AVRH – 1.5 AVRH + 0.5 LSB
98 machine
cycles
Conversion time*1
Sampling period
TCONV
TSAMP
—
—
6.125
3.75
—
—
—
—
µs
µs
tCYC
= 62.5 ns
60 machine
cycles
Analog port input current
Analog input voltage
IAIN
—
—
—
—
—
—
—
AVRL
AVRL
AVSS
—
—
—
±0.1
AVRH
AVCC
AVRH
500
µA
V
AN00to
AN15
VAIN
AVRH
AVRL
—
V
Analog reference voltage
—
—
V
IR
200
—
µA
µA
Reference voltage supply
current
AVRH
IRH
—
5*2
Variation between
channels
AN00to
AN15
—
—
—
—
4
LSB
*1: These standards in this table are for MB90224/P224A/P224B/W224A/W224B.
MB90223: Minimum conversion time is 8.17 µs and minimum sampling time is 5 µs at tCYC = 83.4 ns.
*2: The current value applies to the CPU stop mode with the A/D converter inactive (VCC = AVCC = AVRH = +5.5 V).
Notes: (1) The error becomes larger as | AVRH – AVRL | becomes smaller.
(2) Use the output impedance of the external circuit for analog input under the following conditions:
External circuit output impedance < approx. 10 kΩ (Sampling time approx. 3.75 µs, tCYC = 62.5 ns)
(3) Precision values are standard values applicable to sleep mode.
(4) If VCC/AVCC or VSS/AVSS is caused by a noise to drop to below the analog input volgtage, the analog
input current is likely to increase. In such cases, a bypass capacitor or the like should be provided in
the external circuit to suppress the noise.
77
MB90220 Series
• Analog Input Circuit Mode
C0
Analog input
Comparator
RON2
RON1
RON1: Approx. 1.5 kΩ
RON2: Approx. 1.5 kΩ
C0: Approx. 60 pF
C1
C1: Approx. 4 pF
Note: The values shown here are reference values.
6. A/D Converter Glossary
Resolution:
Analog changes that are identifiable with the A/D converter
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
Difference betweenactualandlogicalvalues. Thiserroriscausedbyazerotransition
error, full-scale transition error, linearity error, differential linearity error, or by noise.
The deviation of the straight line connecting the zero transition point (“00 0000 0000”
↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1111” ↔ “11 1111
1110”) from actual conversion characteristics
Total error:
Linearity error:
Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Digital output
11 1111 1111
11 1111 1110
11 1111 1101
Theoretical value (VNT
Total error
)
•
•
•
•
Theoretical value
Actual conversion value
N + 1
N
N – 1
•
•
•
•
•
Linearity error
00 0000 0010
00 0000 0001
00 0000 0000
N × 1LSB + V0T
AVRL
AVRH (V)
V
(N – 1)T
NT
V(N + 1)T
V
V
FST
V
0T
V
1T
V
2T
AVRH – AVRL
1022
V
FST – V0T
1022
=
=
1 LSB theoretical value
1 LSB
,
N = 0 to 1022
V
NT– (N × 1 LSB + V0T)
=
=
=
V
V
NT (N = 0) = V0T
NT (N = 1022) = VFST
Linearity error
1 LSB
V
NT – V(N–1)T
N = 1 to 1022
– 1
Differential linearity error
Total error
1 LSB
V
NT – {(N + 0.5) × 1 LSB theoretical value}
N = 0 to 1022
1 LSB theoretical value
78
MB90220 Series
■ EXAMPLE CHARACTERISTICS
(1) Power Supply Current
ICCH vs. TA example characteristics
ICCH (µA)
ICC vs. TA example characteristics
ICC (mA)
120
40
30
20
10
0
Fc = 16 MHz
110
VCC = 5 V
External clock input
VCC = 5.0 V
100
90
MB90P224A
80
70
MB90223
60
50
40
–10
–50
0
50
100
150
–50
0
50
100
150
TA (°C)
TA (°C)
Note: These are not assured value of characteristics but example characteristics.
(2) Output Voltage
VOL (V)
2.0
VOL vs. IOL example characteristics
VOH (V)
5.5
VOH vs. IOH example characteristics
TA = +25°C
VCC = 5.0 V
TA = +25°C
VCC = 5.0 V
1.5
1.0
5.0
4.5
4.0
3.5
3.0
0.5
0.0
–0.5
–5
0
5
10
15
20
25
–15
–10
–5
0
5
IOH (mA)
IOL (mA)
Note: These are not assured value of characteristics but example characteristics.
79
MB90220 Series
(3) Pull-up/Pull-down Resistor
Pull-down resistor example characteristics
Pull-up resistor example characteristics
RpulD (kΩ)
100
RpulU (kΩ)
100
90
80
70
60
50
40
30
20
VCC = 4.5 V
90
80
70
60
50
40
30
VCC = 5.0 V
VCC = 5.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
20
–50
0
50
100
150
–50
0
50
100
150
TA (°C)
TA (°C)
Note: These are not assured value of characteristics but example characteristics.
(4) Analog Filter
Analog filter example characteristics
Input pulse width (ns)
80
TA = +25°C
70
60
50
40
30
Filtering enable
20
10
4.0
4.5
5.0
5.5
6.0
VCC (V)
Note: These are not assured value of characteristics but example characteristics.
80
MB90220 Series
■ INSTRUCTION SET (412 INSTRUCTIONS)
Table 1 Explanation of Items in Table of Instructions
Explanation
Item
Mnemonic
Upper-case letters and symbols: Represented as they appear in assembler
Lower-case letters: Replaced when described in assembler.
Numbers after lower-case letters: Indicate the bit width within the instruction.
#
~
Indicates the number of bytes.
Indicates the number of cycles.
See Table 4 for details about meanings of letters in items.
B
Indicates the correction value for calculating the number of actual cycles during
execution of instruction.
The number of actual cycles during execution of instruction is summed with the value in
the “cycles” column.
Operation
LH
Indicates operation of instruction.
Indicates special operations involving the bits 15 through 08 of the accumulator.
Z: Transfers “0”.
X: Extends before transferring.
—: Transfers nothing.
AH
Indicates special operations involving the high-order 16 bits in the accumulator.
*: Transfers from AL to AH.
—: No transfer.
Z: Transfers 00H to AH.
X: Transfers 00H or FFH to AH by extending AL.
I
S
Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky
bit), N (negative), Z (zero), V (overflow), and C (carry).
*: Changes due to execution of instruction.
—: No change.
T
S: Set by execution of instruction.
R: Reset by execution of instruction.
N
Z
V
C
RMW
Indicates whether the instruction is a read-modify-write instruction (a single instruction
that reads data from memory, etc., processes the data, and then writes the result to
memory.).
*: Instruction is a read-modify-write instruction
—: Instruction is not a read-modify-write instruction
Note: Cannot be used for addresses that have different meanings depending on
whether they are read or written.
81
MB90220 Series
Table 2 Explanation of Symbols in Table of Instructions
Explanation
Symbol
A
32-bit accumulator
The number of bits used varies according to the instruction.
Byte: Low order 8 bits of AL
Word: 16 bits of AL
Long: 32 bits of AL, AH
AH
AL
High-order 16 bits of A
Low-order 16 bits of A
SP
Stack pointer (USP or SSP)
Program counter
PC
SPCU
SPCL
PCB
DTB
ADB
SSB
USB
SPB
DPR
brg1
brg2
Ri
Stack pointer upper limit register
Stack pointer lower limit register
Program bank register
Data bank register
Additional data bank register
System stack bank register
User stack bank register
Current stack bank register (SSB or USB)
Direct page register
DTB, ADB, SSB, USB, DPR, PCB, SPB
DTB, ADB, SSB, USB, DPR, SPB
R0, R1, R2, R3, R4, R5, R6, R7
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RW0, RW1, RW2, RW3
RWi
RWj
RLi
RL0, RL1, RL2, RL3
dir
addr16
Compact direct addressing
Direct addressing
addr24
addr24 0 to 15
addr24 16 to 23
Physical direct addressing
Bits 0 to 15 of addr24
Bits 16 to 23 of addr24
io
I/O area (000000H to 0000FFH)
(Continued)
82
MB90220 Series
(Continued)
Symbol
Explanation
#imm4
#imm8
#imm16
#imm32
ext (imm8)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
disp8
disp16
8-bit displacement
16-bit displacement
bp
Bit offset value
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
Bit address
rel
ear
eam
Branch specification relative to PC
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
rlst
Register list
83
MB90220 Series
Table 3 Effective Address Fields
Address format
Number of bytes in
address extemsion*
Code
Notation
00
01
02
03
04
05
06
07
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
RL0 Register direct
(RL0) “ea” corresponds to byte, word, and
RL1 long-word types, starting from the
(RL1) left
RL2
(RL2)
RL3
(RL3)
—
08
09
0A
0B
@RW0
Register indirect
0
0
1
@RW1
@RW2
@RW3
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacemen
2
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + dip16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
* : The number of bytes for address extension is indicated by the “+” symbol in the “#” (number of bytes) column in
the Table of Instructions.
84
MB90220 Series
Table 4 Number of Execution Cycles for Each Form of Addressing
(a)*
Code
Operand
Number of execution cycles for each from of addressing
Listed in Table of Instructions
00 to 07
Ri
RWi
RLi
08 to 0B
0C to 0F
10 to 17
18 to 1B
@RWj
1
4
1
1
@RWj +
@RWi + disp8
@RWj + disp16
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + dip16
@addr16
2
2
2
1
* : “(a)” is used in the “cycles” (number of cycles) column and column B (correction value) in the Table of Instructions.
Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles
(b)*
(c)*
(d)*
Operand
byte
word
long
Internal register
+
+
+
+
+
+
0
0
0
1
1
1
+
+
+
+
+
+
0
0
1
1
3
3
+
+
+
+
+
+
0
0
2
2
6
6
Internal RAM even address
Internal RAM odd address
Even address not in internal RAM
Odd address not in internal RAM
External data bus (8 bits)
* : “(b)”, “(c)”, and “(d)” are used in the “cycles” (number of cycles) column and column B (correction value) in the
Table of Instructions.
85
MB90220 Series
Table 6 Transfer Instructions (Byte) [50 Instructions]
cycles
LH AH
RMW
Mnemonic
#
B
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi))+disp8)
byte (A) ← ((SP)+disp8)
byte (A) ←(addr24)
byte (A) ← ((A))
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
–
*
*
*
–
*
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
(b)
(b)
0
2
2
1
1
2
3
1
2
2+
2
2
2
3
3
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RLi+disp8
A, @SP+disp8
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
2+ (a)
2
2
2
6
3
3
2
1
5
2
1
MOVP A, addr24
MOVP A, @A
MOVN A, #imm4
byte (A) ← imm4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
–
*
*
*
*
–
X
X
X
X
X
X
X
X
X
X
X
X
X
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
(b)
(b)
0
2
2
1
1
2
3
2
2
2+
2
2
2
2
3
MOVX A, dir
MOVX A, addr16
MOVX A, Ri
MOVX A, ear
MOVX A, eam
MOVX A, io
MOVX A, #imm8
MOVX A, @A
MOVX A,@RWi+disp8
MOVX A, @RLi+disp8
MOVX A, @SP+disp8
MOVPX A, addr24
MOVPX A, @A
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
(b)
2+ (a)
2
2
2
3
6
3
3
2
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi))+disp8)
byte (A) ← ((RLi))+disp8)
byte (A) ← ((SP)+disp8)
byte (A) ←(addr24)
byte (A) ← ((A))
3
5
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)) +disp8) ← (A)
byte ((SP)+disp8) ← (A)
byte (addr24) ← (A)
(b)
(b)
0
2
2
1
2
2
3
1
2
2+
2
3
3
5
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi+disp8, A
@SP+disp8, A
0
(b)
(b)
(b)
(b)
(b)
2+ (a)
2
6
3
3
MOVP addr24, A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte ((A)) ← (Ri)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
0
2
2
2+
2
2
2+
2
3
3
3
3+
MOV
MOV
MOVP @A, Ri
MOV
MOV
MOV
MOV
MOV
MOV
MOV
Ri, ear
Ri, eam
(b)
(b)
0
(b)
0
(b)
(b)
0
3+ (a)
3
3
ear, Ri
eam, Ri
3+ (a)
*
*
2
3
3
2
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
–
–
*
–
–
*
–
–
(b)
2+ (a)
–
–
–
*
*
–
–
–
–
–
byte ((A)) ← (AH)
(b)
2
2
MOV
@AL, AH
(Continued)
86
MB90220 Series
(Continued)
Mnemonic
cycles
LH AH
RMW
#
B
Operation
I
S
T
N
Z
V
C
XCH
XCH
XCH
XCH
A, ear
2
3
0
byte (A) ↔ (ear)
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A, eam
Ri, ear
Ri, eam
2+ 3+ (a) 2× (b) byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
2+ 5+ (a) 2× (b) byte (Ri) ↔ (eam)
2
4
0
For an explanation of “(a)” and “(b)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
87
MB90220 Series
Table 7 Transfer Instructions (Word) [40 Instructions]
cycles
LH AH
RMW
Mnemonic
MOVW A, dir
MOVW A, addr16
MOVW A, SP
MOVW A, RWi
MOVW A, ear
MOVW A, eam
MOVW A, io
MOVW A, @A
MOVW A, #imm16
MOVW A, @RWi+disp8
MOVW A, @RLi+disp8
MOVW A, @SP+disp8
MOVPW A, addr24
MOVPW A, @A
#
B
Operation
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
–
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
2
1
1
(c)
(c)
0
0
0
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
–
–
–
–
–
–
–
–
–
2
3
1
1
2
2+
2
2
3
2
3
3
5
2+ (a) (c)
2
2
2
3
6
3
3
2
(c)
(c)
0
(c)
(c)
(c)
(c)
(c)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi) +disp8) –
word (A) ← ((RLi) +disp8)
word (A) ← ((SP) +disp8
word (A) ← (addr24)
word (A) ← ((A))
–
–
–
–
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(c)
(c)
0
0
0
word (dir) ← (A)
2
3
4
1
1
2
2+
2
2
3
3
5
2
2
2+
2
2+
3
4
2
2
2
2
1
2
MOVW dir, A
word (addr16) ← (A)
word (SP) ← imm16
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
MOVW addr16, A
MOVW SP, # imm16
MOVW SP, A
MOVW RWi, A
MOVW ear, A
MOVW eam, A
MOVW io, A
MOVW @RWi+disp8, A
MOVW @RLi+disp8, A
MOVW @SP+disp8, A
MOVPW addr24, A
MOVPW @A, RWi
MOVW RWi, ear
MOVW RWi, eam
MOVW ear, RWi
MOVW eam, RWi
MOVW RWi, #imm16
MOVW io, #imm16
MOVW ear, #imm16
MOVW eam, #imm16
0
2+ (a) (c)
2
3
6
3
3
3
2
(c)
(c)
(c)
(c)
(c)
(c)
0
word ((RWi) +disp8) ← (A) –
word ((RLi) +disp8) ← (A)
word ((SP) +disp8) ← (A)
word (addr24) ← (A)
word ((A)) ← (RWi)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
3+ (a) (c)
3
0
3+ (a) (c)
2
3
2
0
(c)
0
word (ear) ← imm16
word (eam) ← imm16
4
4+
2+ (a) (c)
–
–
–
*
*
–
–
–
–
word ((A)) ← (AH)
–
2
(c)
MOVW @AL, AH
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
word (A) ↔ (ear)
2
2+
2
3
XCHW A, ear
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
5+ (a) 2× (c)
3+ (a) 2× (c)
XCHW A, eam
XCHW RWi, ear
XCHW RWi, eam
4
0
2+
Note: For an explanation of “(a)” and “(c)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual
Cycles.”
88
MB90220 Series
Table 8 Transfer Instructions (Long Word) [11 Instructions]
cycles
LH AH
RMW
Mnemonic
MOVL A, ear
#
B
Operation
I
S
T
N
Z
V
C
1
0
long (A) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
MOVL A, eam
2+ 3+ (a) (d) long (A) ← (eam)
MOVL A, # imm32
MOVL A, @SP + disp8
MOVPL A, addr24
MOVPL A, @A
5
3
5
2
3
4
4
3
0
long (A) ← imm32
(d) long (A) ← ((SP) +disp8)
(d) long (A) ← (addr24)
(d) long (A) ← ((A))
–
–
–
–
*
*
–
–
MOVPL @A, RLi
2
5
(d) long ((A)) ← (RLi)
–
–
(d) long ((SP) + disp8) ← (A)
(d) long (addr24) ← (A)
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
MOVL @SP + disp8, A
MOVPL addr24, A
MOVL ear, A
3
5
2
4
4
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
0
long (ear) ← (A)
MOVL eam, A
2+ 3+ (a) (d) long (eam) ← (A)
For an explanation of “(a)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
89
MB90220 Series
Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
cycles
LH AH
RMW
Mnemonic
ADD A, #imm8
#
B
Operation
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
Z
Z
Z
Z
–
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
2
2
2
2
3
2
0
byte (A) ← (A) +imm8
(b) byte (A) ← (A) +(dir)
byte (A) ← (A) +(ear)
(b) byte (A) ← (A) +(eam)
byte (ear) ← (ear) + (A)
2× (b) byte (eam) ← (eam) + (A)
ADD
ADD
ADD
ADD
ADD
ADDC
A, dir
A, ear
A, eam
ear, A
eam, A
A
0
2+ 3+ (a)
2
2
0
*
2+ 3+ (a)
–
–
–
–
2
2
0
0
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear) + (C)
1
2
ADDC A, ear
ADDC A, eam
ADDDC A
2+ 3+ (a)
(b) byte (A) ← (A) + (eam) + (C)
byte (A) ← (AH) + (AL) + (C) (Decimal) Z
1
3
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
Z
Z
Z
Z
–
–
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
2
3
2
byte (A) ← (A) –imm8
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
A, #imm8
A, dir
2
2
2
(b) byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
(b) byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
2× (b) byte (eam) ← (eam) – (A)
0
A, ear
A, eam
ear, A
eam, A
A
2+ 3+ (a)
2
2
0
*
2+ 3+ (a)
–
–
–
–
2
2
0
0
byte (A) ← (AH) – (AL) – (C)
byte (A) ← (A) – (ear) – (C)
1
2
SUBC A, ear
SUBC A, eam
SUBDC A
2+ 3+ (a)
(b) byte (A) ← (A) – (eam) – (C)
0
byte (A) ← (AH) – (AL) – (C) (Decimal) Z
1
3
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
2
2
word (A) ← (AH) + (AL)
word (A) ← (A) +(ear)
(c) word (A) ← (A) +(eam)
word (A) ← (A) +imm16
word (ear) ← (ear) + (A)
2× (c) word (eam) ← (eam) + (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
2
0
0
ADDW A
ADDW A, ear
ADDW A, eam
ADDW A, #imm16
ADDW ear, A
ADDW eam, A
ADDCW A, ear
ADDCW A, eam
2+ 3+ (a)
3
2
2
2
0
0
2+ 3+ (a)
2
0
word (A) ← (A) + (ear) + (C)
(c) word (A) ← (A) + (eam) + (C)
2
2+ 3+ (a)
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
2
2
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
(c) word (A) ← (A) – (eam)
word (A) ← (A) –imm16
word (ear) ← (ear) – (A)
2× (c) word (eam) ← (eam) – (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
2
0
0
SUBW A
SUBW A, ear
SUBW A, eam
SUBW A, #imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
2+ 3+ (a)
3
2
2
2
0
0
2+ 3+ (a)
2
0
word (A) ← (A) – (ear) – (C)
(c) word (A) ← (A) – (eam) – (C)
2
2+ 3+ (a)
0
long (A) ← (A) + (ear)
2+ 6+ (a) (d) long (A) ← (A) + (eam)
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
ADDL A, ear
ADDL A, eam
ADDL A, #imm32
2
5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
5
4
0
long (A) ← (A) +imm32
–
–
–
SUBL A, ear
SUBL A, eam
SUBL A, #imm32
2
5
0
long (A) ← (A) – (ear)
2+ 6+ (a) (d) long (A) ← (A) – (eam)
long (A) ← (A) –imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
5
4
0
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
90
MB90220 Series
Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
cycles
LH AH
RMW
Mnemonic
#
B
Operation
I
S
T
N
Z
V
C
INC
INC
ear
eam
2
2
0
byte (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2+ 3+ (a) 2× (b) byte (eam) ← (eam) +1
DEC
DEC
ear
eam
2
2
0
byte (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2+ 3+ (a) 2× (b) byte (eam) ← (eam) –1
INCW ear
INCW eam
2
2
0
word (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2+ 3+ (a) 2× (c) word (eam) ← (eam) +1
DECW ear
DECW eam
2
2
0
word (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2+ 3+ (a) 2× (c) word (eam) ← (eam) –1
INCL ear
INCL eam
2
4
0
long (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2+ 5+ (a) 2× (d) long (eam) ← (eam) +1
DECL ear
DECL eam
2
4
0
long (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2+ 5+ (a) 2× (d) long (eam) ← (eam) –1
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 11 Compare Instructions (Byte/Word/Long Word) [11 Instructions]
Mnemonic
#
cycles
LH AH
RMW
B
Operation
byte (AH) – (AL)
I
S
T
N
Z
V
C
CMP
A
1
2
2
2
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMP A, ear
CMP A, eam
CMP A, #imm8
byte (A) – (ear)
2+ 2+ (a) (b) byte (A) – (eam)
2
2
0
byte (A) – imm8
CMPW A
1
2
2
2
0
0
word (AH) – (AL)
word (A) – (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW A, ear
CMPW A, eam
CMPW A, #imm16
2+ 2+ (a) (c) word (A) – (eam)
3
2
0
word (A) – imm16
CMPL A, ear
CMPL A, eam
CMPL A, #imm32
2
3
0
long (A) – (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
2+ 4+ (a) (d) long (A) – (eam)
long (A) – imm32
5
3
0
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
91
MB90220 Series
Table 12 Unsigned Multiplication and Division Instructions (Word/Long Word) [11 Instructions]
cycles
LH AH
RMW
S T N Z V C
Mnemonic
#
B
Operation
I
1
–
–
DIVU A
1
0 word (AH) /byte (AL)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
Quotient → byte (AL) Remainder → byte (AH)
word (A)/byte (ear)
2
0
–
–
–
–
–
–
–
–
DIVU A, ear
2
*
Quotient → byte (A) Remainder → byte (ear)
word (A)/byte (eam)
3
6
DIVU A, eam 2+
*
*
Quotient → byte (A) Remainder → byte (eam)
long (A)/word (ear)
4
DIVUW A, ear
2
0
*
Quotient → word (A) Remainder → word (ear)
long (A)/word (eam)
5
7
DIVUW A, eam
2+
*
*
Quotient → word (A) Remainder → word (eam)
8
MULU A
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0 byte (AH) × byte (AL) → word (A)
*
0
MULU A, ear
2
9
byte (A) × byte (ear) → word (A)
*
MULU A, eam
2+
(b)
10
byte (A) × byte (eam) → word (A)
word (AH) × word (AL) → long (A)
word (A) × word (ear) → long (A)
word (A) × word (eam) → long (A)
*
MULUW A
1
0
0
(c)
11
*
MULUW A, ear
2
12
*
13
MULUW A, eam
2+
*
For an explanation of “(b)” and “(c), refer to Table 5, “Correction Values for Number of Cycle Used to Calculate
Number of Actual Cycles.”
*1: 3 when dividing into zero, 6 when an overflow occurs, and 14 normally.
*2: 3 when dividing into zero, 5 when an overflow occurs, and 13 normally.
*3: 5 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 17 + (a) normally.
*4: 3 when dividing into zero, 5 when an overflow occurs, and 21 normally.
*5: 4 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 25 + (a) normally.
*6: (b) when dividing into zero or when an overflow occurs, and 2 × (b) normally.
*7: (c) when dividing into zero or when an overflow occurs, and 2 × (c) normally.
*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not 0.
*9: 3 when byte (ear) is zero, and 7 when byte (ear) is not 0.
*10: 4 + (a) when byte (eam) is zero, and 8 + (a) when byte (eam) is not 0.
*11: 3 when word (AH) is zero, and 11 when word (AH) is not 0.
*12: 3 when word (ear) is zero, and 11 when word (ear) is not 0.
*13: 4 + (a) when word (eam) is zero, and 12 + (a) when word (eam) is not 0.
92
MB90220 Series
Table 13 Signed Multiplication and Division Instructions (Word/Long Word) [11 Insturctions]
cycles
LH AH
RMW
Mnemonic
#
B
Operation
I
S
T
N
Z
V
C
1
DIV
A
2
0 word (AH) /byte (AL)
Quotient → byte (AL) Remainder → byte (AH)
0 word (A)/byte (ear)
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
2
DIV A, ear
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
Quotient → byte (A) Remainder → byte (ear)
word (A)/byte (eam)
3
6
DIV A, eam 2+
DIVWA, ear
DIVWA, eam 2+
*
*
Quotient → byte (A) Remainder → byte (eam)
4
2
0 long (A)/word (ear)
*
Quotient → word (A) Remainder → word (ear)
long (A)/word (eam)
7
5
*
*
Quotient → word (A) Remainder → word (eam)
8
–
–
–
–
–
–
–
–
–
–
–
–
MUL A
MUL A, ear
2
2
0 byte (AH) × byte (AL) → word (A)
0 byte (A) × byte (ear) → word (A)
(b) byte (A) × byte (eam) → word (A)
0 word (AH) × word (AL) → long (A)
0 word (A) × word (ear) → long (A)
(b) word (A) × word (eam) → long (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
9
*
10
MUL A, eam 2+
*
*
*
*
11
MULW A
2
12
MULW A, ear
2
13
MULW A, eam
2+
For an explanation of “(b)” and “(c)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate
Number of Actual Cycles.”
*1: 3 when dividing into zero, 8 or 18 when an overflow occurs, and 18 normally.
*2: 3 when dividing into zero, 10 or 21 when an overflow occurs, and 22 normally.
*3: 4 + (a) when dividing into zero, 11 + (a) or 22 + (a) when an overflow occurs, and 23 + (a) normally.
*4: When the dividend is positive: 4 when dividing into zero, 10 or 29 when an overflow occurs, and 30 normally.
When the dividend is negative: 4 when dividing into zero, 11 or 30 when an overflow occurs, and 31 normally.
*5: When the dividend is positive: 4 + (a) when dividing into zero, 11 + (a) or 30 + (a) when an overflow occurs,
and 31 + (a) normally.
When the dividend is negative: 4 + (a) when dividing into zero, 12 + (a) or 31 + (a) when an overflow occurs,
and 32 + (a) normally.
*6: (b) when dividing into zero or when an overflow occurs, and 2 × (b) normally.
*7: (c) when dividing into zero or when an overflow occurs, and 2 × (c) normally.
*8: 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
*10: 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative.
*11: 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12: 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13: 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative.
Note: Which of the two values given for the number of execution cycles applies when an overflow error occurs in
a DIV or DIVW instruction depends on whether the overflow was detected before or after the operation.
93
MB90220 Series
Table 14 Logical 1 Instructions (Byte, Word) [39 Instructions]
cycles
LH AH
RMW
Mnemonic
#
B
Operation
I
S
T
N
Z
V
C
*
*
*
*
*
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
R
R
R
R
R
2
2
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
(b) byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
2+ 3+ (a)
2× (b) byte (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
0
0
AND
A, #imm8
A, ear
A, eam
ear, A
eam, A
AND
AND
AND
AND
2+ 3+ (a)
2
3
0
*
*
*
*
*
*
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
R
R
R
R
R
2
2
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
(b) byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
2+ 3+ (a)
2× (b) byte (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
0
0
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2+ 3+ (a)
2
3
0
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
2
2
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
(b) byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
2× (b) byte (eam) ← (eam) xor (A)
byte (A) ← not (A)
byte (ear) ← not (ear)
2× (b) byte (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
0
0
XOR A, #imm8
XOR A, ear
XOR A, eam
XOR ear, A
XOR eam, A
2+ 3+ (a)
2
3
0
2+ 3+ (a)
1
2
2
2
0
0
NOT
NOT
NOT
A
ear
eam
*
*
2+ 3+ (a)
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
R
R
R
2
2
2
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
3
2
0
0
0
ANDW A
ANDW A, #imm16
ANDW A, ear
ANDW A, eam
ANDW ear, A
ANDW eam, A
2+ 3+ (a)
(c) word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
2× (c) word (eam) ← (eam) and (A)
2
3
0
*
2+ 3+ (a)
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
R
R
R
2
2
2
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
3
2
0
0
0
ORW
A
ORW A, #imm16
ORW A, ear
ORW A, eam
ORW ear, A
2+ 3+ (a)
(c) word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
2+ 3+ (a)
2× (c) word (eam) ← (eam) or (A)
2
3
0
*
ORW eam, A
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
R
2
2
2
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
3
2
0
0
0
XORW A
XORW A, #imm16
XORW A, ear
XORW A, eam
XORW ear, A
XORW eam, A
NOTW A
2+ 3+ (a)
(c) word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
2× (c) word (eam) ← (eam) xor (A)
2
3
0
2+ 3+ (a)
2
2
0
0
word (A) ← not (A)
word (ear) ← not (ear)
2+ 3+ (a)
2× (c) word (eam) ← not (eam)
1
2
NOTW ear
NOTW eam
*
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
94
MB90220 Series
Table 15 Logical 2 Instructions (Long Word) [6 Instructions]
cycles
LH AH
RMW
Mnemonic
#
B
Operation
I
S
T
N
Z
V
C
ANDL A, ear
ANDL A, eam
2
5
0
long (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 6+ (a) (d) long (A) ← (A) and (eam)
ORL
ORL
A, ear
A, eam
2
5
0
long (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 6+ (a) (d) long (A) ← (A) or (eam)
XORL A, ear
XORL A, eam
2
5
0
long (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 6+ (a) (d) long (A) ← (A) xor (eam)
For an explanation of “(a)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 16 Sign Inversion Instructions (Byte/Word) [6 Instructions]
Mnemonic
#
cycles
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
NEG
A
1
2
0
byte (A) ← 0 – (A)
X
–
–
–
–
*
*
*
*
–
NEG ear
NEG eam
2
2
0
byte (ear) ← 0 – (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
2+ 3+ (a) 2× (b) byte (eam) ← 0 – (eam)
NEGW A
1
2
0
word (A) ← 0 – (A)
–
–
–
–
–
*
*
*
*
–
NEGW ear
NEGW eam
2
2
0
word (ear) ← 0 – (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
2+ 3+ (a) 2× (c) word (eam) ← 0 – (eam)
For an explanation of “(a)”, “(b)” and “(c)” and refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 17 Absolute Value Instructions (Byte/Word/Long Word) [3 Insturctions]
cycles
LH AH
RMW
Mnemonic
#
B
Operation
I
S
T
N
Z
V
C
ABS
ABSW A
ABSL
A
2
2
2
2
2
4
0
0
0
byte (A) ← absolute value (A)
word (A) ← absolute value (A)
long (A) ← absolute value (A)
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
A
Table 18 Normalize Instructions (Long Word) [1 Instruction]
Mnemonic
#
cycles
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
NRML A, R0
2
*
0
long (A) ← Shifts to the position at
which “1” was set first
–
–
–
–
*
–
–
–
–
–
byte (R0) ← current shift count
* : 5 when the contents of the accumulator are all zeroes, 5 + (R0) in all other cases.
95
MB90220 Series
Table 19 Shift Instructions (Byte/Word/Long Word) [27 Instructions]
cycles
LH AH
RMW
Mnemonic
RORC A
#
B
Operation
I
S
T
N
Z
V
C
2
2
2
2
0
0
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
–
–
ROLC A
–
–
–
–
*
*
*
*
–
–
–
–
*
*
*
*
*
*
*
*
RORC ear
RORC eam
ROLC ear
ROLC eam
2
2
0
byte (ear) ← Right rotation with carry
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
2+ 3+ (a) 2× (b) byte (eam) ← Right rotation with carry
byte (ear) ← Left rotation with carry
2
2
0
2+ 3+ (a) 2× (b) byte (eam) ← Left rotation with carry
1
*
*
–
–
–
–
*
*
*
–
–
–
ASR A, R0
LSR A, R0
LSL A, R0
2
2
2
0
0
0
byte (A) ← Arithmetic right barrel shift (A, R0) –
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
1
1
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
–
–
3
3
3
*
*
–
–
–
–
*
*
*
–
–
–
ASR A, #imm8
LSR A, #imm8
LSL A, #imm8
3
3
3
0
0
0
byte (A) ← Arithmetic rightbarrel shift(A, imm8) –
byte (A) ← Logical right barrel shift (A, imm8) –
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
byte (A) ← Logical left barrel shift (A, imm8)
–
ASRW A
*
*
*
–
–
–
1
1
1
2
2
2
0
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
R
*
*
*
*
–
–
–
LSRW A/SHRW A
LSLW A/SHLW A
1
*
*
*
–
–
–
ASRW A, R0
LSRW A, R0
LSLW A, R0
2
2
2
0
0
0
word (A) ← Arithmetic right barrel shift (A, R0)
word (A) ← Logical right barrel shift (A, R0)
word (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
1
*
1
*
3
ASRW A, #imm8
LSRW A, #imm8
LSLW A, #imm8
word (A) ← Arithmetic right barrel shift (A, imm8)
word (A) ← Logical right barrel shift (A, imm8)
word (A) ← Logical left barrel shift (A, imm8)
*
*
*
–
–
–
3
3
3
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
3
*
3
*
2
ASRL A, R0
LSRL A, R0
LSLL A, R0
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
2
2
2
0
0
0
long (A) ← Arithmetic right shift (A, R0)
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0)
–
–
–
*
2
*
2
*
4
ASRL A, #imm8
LSRL A, #imm8
LSLL A, #imm8
*
*
–
*
*
*
–
–
–
3
3
3
0
0
0
long (A) ← Arithmetic right shift (A, imm8) –
long (A) ← Logical right barrel shift (A, imm8) –
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
*
*
*
*
4
*
4
long (A) ← Logical left barrel shift (A, imm8)
–
*
For an explanation of “(a)” and “(b)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
*1: 3 when R0 is 0, 3 + (R0) in all other cases.
*2: 3 when R0 is 0, 4 + (R0) in all other cases.
*3: 3 when imm8 is 0, 3 + (imm8) in all other cases.
*4: 3 when imm8 is 0, 4 + (imm8) in all other cases.
96
MB90220 Series
Table 20 Branch 1 Instructions [31 Instructions]
LH AH
RMW
Mnemonic
#
cycles
B
Operation
I
S
T
N
Z
V
C
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
BZ/BEQ
BNZ/BNE rel
BC/BLO
BNC/BHS rel
rel
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Branch when (Z) = 1
Branch when (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
1
*
1
rel
*
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
1
*
1
*
BN
BP
BV
BNV
BT
BNT
BLT
BGE
BLE
BGT
BLS
BHI
BRA
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
1
*
1
*
1
*
1
*
1
*
Branch when (T) = 0
1
*
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
( (V) xor (N) ) or (Z) = 1
( (V) xor (N) ) or (Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
1
*
1
*
1
*
1
*
1
*
1
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← (ear), (PCB) ← (ear +2)
word (PC) ← (eam), (PCB) ← (eam +2)
word (PC) ← ad24 0 to 15
(PCB) ← ad24 16 to 23
word (PC) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
JMP
JMP
JMP
JMP
@A
1
3
2
2+
2
2+
0
0
0
(c)
0
(d)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
addr16
@ear
@eam
3
4+ (a)
3
JMPP @ear *3
JMPP @eam *3
JMPP addr24
4+ (a)
3
4
0
CALL @ear *4
CALL @eam *4
CALL addr16 *5
CALLV #vct4 *5
CALLP @ear *6
2
2+
3
1
2
(c)
2× (c)
(c)
2× (c)
2× (c)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (PC) ← (eam)
word (PC) ← addr16
5+ (a)
5
5
7
Vector call linstruction
word (PC) ← (ear) 0 to 15,
(PCB) ← (ear) 16 to 23
word (PC) ← (eam) 0 to 15,
(PCB) ← (eam) 16 to 23
word (PC) ← addr 0 to 15,
(PCB) ← addr 16 to 23
2
CALLP @eam *6
CALLP addr24 *7
–
–
–
–
–
–
–
–
8+ (a)
7
–
–
–
–
–
–
–
–
2+
4
–
–
–
–
*
2× (c)
For an explanation of “(a)”, “(c)”and “(d)”, refer to Table 4, “Number of Execution Cyclesfor Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
*1: 3 when branching, 2 when not branching.
*2: 3 × (c) + (b)
*3: Read (word) branch address.
*4: W: Save (word) to stack; R: Read (word) branch address.
*5: Save (word) to stack.
*6: W: Save (long word) to W stack; R: Read (long word) branch address.
*7: Save (long word) to stack.
97
MB90220 Series
Table 21 Branch 2 Instructions [20 Instructions]
cycles
LH AH
RMW
Mnemonic
#
B
Operation
I
S
T
N
Z
V
C
1
–
–
*
*
*
*
–
–
CBNE A, #imm8, rel
CWBNE A, #imm16, rel
3
4
0
0
Branch when byte (A) ≠ imm8
–
–
–
–
–
–
–
*
*
*
*
*
1
*
Branch when byte (A) ≠ imm16 –
1
*
CBNE ear, #imm8, rel
CBNE eam, #imm8, rel
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel
*
*
*
*
–
–
–
–
4
4+
5
0
Branch when byte (ear) ≠ imm8 –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
3
*
1
(b) Branch when byte (eam) ≠ imm8
Branch when word (ear) ≠ imm16
–
–
*
3
*
0
5+
(c) Branch when word (eam) ≠ imm16 –
2
*
DBNZ ear, rel
DBNZ eam, rel
DWBNZ ear, rel
DWBNZ eam, rel
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
3
3+
3
0
Branch when byte (ear) =
(ear) – 1, and (ear) ≠ 0
4
*
2
2× (b) Branch when byte (ear) =
(eam) – 1, and (eam) ≠ 0
*
4
–
*
0
Branch when word (ear) =
(ear) – 1, and (ear) ≠ 0
*
3+
2× (c) Branch when word (eam) =
14
12
13
14
9
(eam) – 1, and (eam) ≠ 0
INT
INT
INTP
INT9
RETI
#vct8
addr16
addr24
–
–
–
–
–
–
–
–
–
–
–
–
R
R
R
R
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
–
–
S
S
S
S
*
2
3
4
1
1
2
8× (c) Software interrupt
6× (c) Software interrupt
6× (c) Software interrupt
8× (c) Software interrupt
11
6× (c) Return from interrupt
RETIQ *6
5
6
*
*
*
*
*
*
*
Return from interrupt
*
LINK
#imm8
(c)
–
–
–
–
–
–
–
–
–
At constant entry, save old
frame pointer to stack, set new
frame pointer, and allocate
local pointer area
At constant entry, retrieve old
frame pointer from stack.
–
2
5
UNLINK
(c)
–
–
–
–
–
–
–
–
–
–
1
4
5
RET *7
(c)
(d)
Return from subroutine
Return from subroutine
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
1
RETP *8
For an explanation of “(b)”, “(c)” and “(d)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate
Number of Actual Cycles.”
*1: 4 when branching, 3 when not branching
*2: 5 when branching, 4 when not branching
*3: 5 + (a) when branching, 4 + (a) when not branching
*4: 6 + (a) when branching, 5 + (a) when not branching
*5: 3 × (b) + 2 × (c) when an interrupt request is generated, 6 × (c) when returning from the interrupt.
*6: High-speed interrupt return instruction. When an interrupt request is detected during this instruction, the
instruction branches to the interrupt vector without performing stack operations when the interrupt is generated.
*7: Return from stack (word)
*8: Return from stack (long word)
98
MB90220 Series
Table 22 Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
cycles
LH AH
RMW
Mnemonic
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
#
B
Operation
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
3
3
word (SP) ← (SP) –2, ((SP)) ← (A)
word (SP) ← (SP) –2, ((SP)) ← (AH)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(SP) ← (SP) –2n, ((SP)) ← (rlst)
–
–
–
–
–
–
–
–
–
–
–
–
1
1
1
2
(c)
(c)
(c)
–
–
–
–
3
4
*
*
–
–
*
–
–
*
–
–
–
–
–
–
*
–
–
*
–
–
*
–
–
*
POPW A
1
1
1
2
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2 –
–
–
*
–
–
*
3
3
3
(c)
(c)
(c)
POPW AH
POPW PS
POPW rlst
–
–
–
2
4
–
–
–
–
–
–
–
(rlst) ← ((SP)) , (SP) ← (SP)
–
*
*
–
*
*
*
*
*
*
*
JCTX @A
1
Context switch instruction
–
–
9
6× (c)
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
AND
OR
CCR, #imm8 2
CCR, #imm8 2
byte (CCR) ← (CCR) and imm8 –
–
–
3
3
0
0
byte (CCR) ← (CCR) or imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV RP, #imm8
MOV ILM, #imm8
2
2
byte (RP) ←imm8
byte (ILM) ←imm8
–
–
–
–
2
2
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2+
2
word (RWi) ←ear
word (RWi) ←eam
word(A) ←ear
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
3
0
0
0
0
2+ (a)
2
1+ (a)
MOVEA A, eam
2+
word (A) ←eam
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADDSP #imm8
ADDSP #imm16
2
3
word (SP) ← ext (imm8)
word (SP) ← imm16
–
–
–
–
3
3
0
0
1
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
2
2
3
byte (A) ← (brgl)
byte (brg2) ← (A)
byte (brg2) ← imm8
Z
–
–
*
–
–
–
–
–
MOV A, brgl
MOV brg2, A
MOV brg2, #imm8
0
0
0
*
1
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
NOP
ADB
DTB
PCB
SPB
NCC
CMR
1
1
1
1
1
1
1
No operation
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
1
1
1
1
1
1
1
–
–
–
–
–
–
Prefix code for AD space access
Prefix code for DT space access
Prefix code for PC space access
Prefix code for SP space access
Prefix code for no flag change
Prefix code for the common
register bank
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
4
word (SPCU) ← (imm16)
word (SPCL) ← (imm16)
Stack check ooperation enable
Stack check ooperation disable
–
–
–
–
–
–
–
–
–
–
–
–
MOVW SPCU, #imm16
–
–
–
–
0
0
0
0
2
2
2
2
MOVW SPCL, #imm16 4
SETSPC
CLRSPC
2
2
5
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
byte (A)← position of “1” bit in word (A) Z
–
–
–
–
–
–
BTSCN
BTSCNS A
BTSCND A
A
2
2
2
–
–
–
0
0
0
*
6
byte (A)← position of “1” bit in word (A) × 2
Z
*
7
Z
byte (A)← position of “1” bit in word (A) × 4
*
For an explanation of “(a)” and “(c)”, refer to Tables 4 and 5.
*1: PCB, ADB, SSB, USB, and SPB: 1 cycle
DTB: 2 cycles
DPR: 3 cycles
*2: 3 + 4 × (pop count)
*4: Pop count × (c), or push count × (c)
*5: 3 when AL is 0, 5 when AL is not 0.
*6: 4 when AL is 0, 6 when AL is not 0.
*7: 5 when AL is 0, 7 when AL is not 0.
*3: 3 + 4 × (push count)
99
MB90220 Series
Table 23 Bit Manipulation Instructions [21 Instructions]
cycles
LH AH
RMW
Mnemonic
#
B
Operation
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
3
4
3
3
3
3
(b) byte (A) ← (dir:bp) b
(b) byte (A) ← (addr16:bp) b
(b) byte (A) ← (io:bp) b
Z
Z
Z
*
*
*
–
–
–
–
–
–
*
*
*
–
–
–
*
*
*
–
–
–
–
–
–
*
*
*
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
3
4
3
4
4
4
2× (b) bit (dir:bp) b ← (A)
2× (b) bit (addr16:bp) b ← (A)
2× (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
SETB dir:bp
SETB addr16:bp
SETB io:bp
3
4
3
4
4
4
2× (b) bit (dir:bp) b ← 1
2× (b) bit (addr16:bp) b ← 1
2× (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
3
4
3
4
4
4
2× (b) bit (dir:bp) b ← 0
2× (b) bit (addr16:bp) b ← 0
2× (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
BBC
BBC
BBC
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
(b) Branch when (dir:bp) b = 0
(b) Branch when (addr16:bp) b = 0
(b) Branch when (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
1
*
1
*
1
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
BBS
BBS
BBS
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
(b) Branch when (dir:bp) b = 1
(b) Branch when (addr16:bp) b = 1
(b) Branch when (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
1
*
1
*
2
*
–
–
–
–
–
–
*
SBBS addr16:bp, rel
WBTS io:bp
5
3
3
2× (b)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Branch when (addr16:bp) b = 1, bit = 1
Wait until (io:bp) b = 1
*
4
3
–
–
–
–
*
*
3
4
WBTC io:bp
*
Wait until (io:bp) b = 0
*
For an explanation of “(b)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate Number of
Actual Cycles.”
*1: 5 when branching, 4 when not branching
*2: 7 when condition is satisfied, 6 when not satisfied
*3: Undefined count
*4: Until condition is satisfied
100
MB90220 Series
Table 24 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
cycles
LH AH
RMW
Mnemonic
SWAP
SWAPW
EXT
EXTW
ZEXT
ZEXTW
#
B
Operation
I
S
T
N
Z
V
C
1
1
1
1
1
1
3
2
1
2
1
2
0 byte (A) 0 to 7 ← → (A) 8 to 15
0 word (AH) ← → (AL)
0 Byte code extension
0 Word code extension
0 Byte zero extension
–
–
X
–
Z
–
–
*
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
0 Word zero extension
Table 25 String Instructions [10 Instructions]
Mnemonic
# cycles B
Operation
LH AH
RMW
I
S
T
N
Z
V
C
2
2
3
3
Byte transfer @AH+ ← @AL+, counter = RW0
Byte transfer @AH– ← @AL–, counter = RW0
MOVS/MOVSI
MOVSD
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
1
1
4
4
Byte retrieval @AH+ – AL, counter = RW0
Byte retrieval @AH– – AL, counter = RW0
SCEQ/SCEQI
SCEQD
2
2
*
*
*
*
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
5
5m +3
Byte filling @AH+ ← AL, counter = RW0
FILS/FILSI
2
–
–
–
–
–
*
*
–
–
–
*
2
6
6
MOVSW/MOVSWI
MOVSWD
Word transfer @AH+ ← @AL+, counter = RW0
Word transfer @AH– ← @AL–, counter = RW0
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
2
*
1
7
7
SCWEQ/SCWEQI
SCWEQD
Word retrieval @AH+ – AL, counter = RW0
Word retrieval @AH– – AL, counter = RW0
2
2
*
*
*
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
1
*
8
5m +3
Word filling @AH+ ← AL, counter = RW0
FILSW/FILSWI
2
–
–
–
–
–
*
*
–
–
–
*
m: RW0 value (counter value)
*1: 3 when RW0 is 0, 2 + 6 × (RW0) for count out, and 6n + 4 when match occurs
*2: 4 when RW0 is 0, 2 + 6 × (RW0) in any other case
*3: (b) × (RW0)
*4: (b) × n
*5: (b) × (RW0)
*6: (c) × (RW0)
*7: (c) × n
*8: (c) × (RW0)
101
MB90220 Series
Table 26 Multiple Data Transfer Instructions [18 Instructions]
cycles
LH AH
RMW
V C
Mnemonic
#
B
Operation
I
S
T N
Z
1
3
MOVM @A, @RLi, #imm8
MOVM @A, eam, #imm8
MOVM addr16, @RLi, #imm8
MOVM addr16, eam, #imm8
MOVMW @A, @RLi, #imm8
MOVMW @A, eam, #imm8
MOVMWaddr16, @RLi, #imm8
MOVMWaddr16, eam, #imm8
MOVM @RLi, @A, #imm8
MOVM eam, @A, #imm8
MOVM @RLi, addr16, #imm8
MOVM eam, addr16, #imm8
MOVMW @RLi, @A, #imm8
MOVMW eam, @A, #imm8
MOVMW@RLi, addr16, #imm8
MOVMWeam, addr16, #imm8
MOVM bnk : addr16, *5
←
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Multiple data trasfer byte ((A)) ((RLi))
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
3+
5
5+
3
3+
5
5+
3
3+
5
5+
3
3+
5
5+
7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
2
3
Multiple data trasfer byte ((A)) (eam)
←
1
3
Multiple data trasfer byte (addr16) ((RLi))
←
2
3
Multiple data trasfer byte (addr16) (eam)
←
4
1
Multiple data trasfer word ((A)) ((RLi))
←
4
2
Multiple data trasfer word ((A)) (eam)
←
4
1
Multiple data trasfer word (addr16) ((RLi))
←
4
2
Multiple data trasfer word (addr16) (eam)
←
3
1
Multiple data trasfer byte ((RLi)) ((A))
←
3
2
Multiple data trasfer byte (eam)
←
((A))
3
1
Multiple data transfer byte ((RLi)) (addr16)
←
3
2
Multiple data transfer byte (eam) (addr16)
←
4
1
Multiple data trasfer word ((RLi)) ((A))
←
4
2
Multiple data trasfer word (eam) ((A))
←
4
1
Multiple data transfer word ((RLi)) (addr16)
←
4
2
Multiple data transfer word (eam) (addr16)
←
3
1
Multiple data transfer
*
*
bnk : addr16, #imm8
MOVMW bnk : addr16, *5
bnk : addr16, #imm8
byte (bnk:addr16) ← (bnk:addr16)
Multiple data transfer
4
1
–
–
–
–
–
–
–
7
*
–
–
–
*
word (bnk:addr16) ← (bnk:addr16)
*1: 5 + imm8 × 5, 256 times when imm8 is zero.
*2: 5 + imm8 × 5 + (a), 256 times when imm8 is zero.
*3: Number of transfers × (b) × 2
*4: Number of transfers × (c) × 2
*5: The bank register specified by “bnk” is the same as for the MOVS instruction.
102
MB90220 Series
■ ORDERING INFORMATION
Part number
Type
MB90224PF
Package
Remarks
MB90224
MB90223
MB90P224A
MB90223PF
MB90P224PF
120-pin Plastic QFP
(FPT-120P-M03)
MB90P224B
MB90P224BPF
MB90W224A
MB90W224B
MB90W224ZF
MB90W224BZF
120-pin Ceramic QFP
(FPT-120C-C02)
ES level only
For evaluation
256-pin Ceramic PGA
(PGA-256C-A02)
MB90V220
MB90V220CR
101
MB90220 Series
■ PACKAGE DIMENSIONS
120-pin Plastic QFP
(FPT-120P-M03)
32.00±0.40(1.260±.016)SQ
28.00±0.20(1.102±.008)SQ
3.85(.152)MAX
0(0)MIN
(STAND OFF)
90
91
61
60
Details of "A" part
0.25(.010)
23.20
(.913)
REF
30.40±0.40
(1.197±.016)
0.20(.008)
0.18(.007)MAX
0.58(.023)MAX
INDEX
Details of "B" part
"A"
31
120
30
1
LEAD No.
0.80(.0315)TYP
0.35±0.10
(.014±.004)
0.15±0.05
(.006±.002)
M
0.16(.006)
"B"
0
10°
0.80±0.20(.031±.008)
0.10(.004)
Dimensions in mm (inches)
C
1994 FUJITSU LIMITED F120004S-3C-2
120-pin Ceramic QFP
(FPT-120C-C02)
32.00±0.30(1.260±.012)SQ
28.00–+00..3600 1.102–+..001223 SQ
23.20(.9135)REF
3.55(.140)MAX
0.80±0.20
(.0315±.008)
0.05(.002)MIN
(STAND OFF)
Ø12.70(.0500)REF
30.40±0.25
(1.197±.010)
SQ
Details of "A" part
0.10(.004)
"A"
INDEX AREA
0°~10°
0.80(.0315)TYP
0.35±0.10
(.0138±.0040)
0.15±0.05(.006±.002)
1.45±0.20(.057±.008)
0°
C
Dimensions in mm (inches)
1994 FUJITSU LIMITED F120023SC-1-1
Note: See to the latest version of Package Data Book for official package dimensions.
104
MB90220 Series
FUJITSU LIMITED
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F9710
FUJITSU LIMITED Printed in Japan
105
相关型号：
MB90233PFV-XXX
Microcontroller, 16-Bit, MROM, F2MC-16F CPU, 16MHz, CMOS, PQFP100, PLASTIC, LQFP-100
FUJITSU
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