MB90F574APFV_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13701-7E

16-bit Proprietary Microcontroller

CMOS

F²MC-16LX MB90570 Series

MB90573/574/574C/F574/F574A/V570/V570A

■ DESCRIPTION

The MB90570 series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process

control applications in consumer products that require high-speed real time processing. It contains an I²C*²bus

interface that allows inter-equipment communication to be implemented readily. This product is well adapted to

car audio equipment, VTR systems, and other equipment and systems.

The instruction set of F²MC-16LX CPU core inherits AT architecture of F²MC*¹family with additional instruction

sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and

enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word

data.

The MB90570 series has peripheral resources of an 8/10-bit A/D converter, an 8-bit D/A converter, UART (SCI),

an extended I/O serial interface, an 8/16-bit up/down counter/timer, an 8/16-bit PPG timer, I/O timer (a 16-bit

free run timer, an input capture (ICU), an output compare (OCU)).

*1: F²MC stands for FUJITSU Flexible Microcontroller.

*2: Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use these

components in an I²C system, provided that the system conforms to the I²C Standard Specification as

defined by Philips.

■ PACKAGE

120-pin plastic LQFP

120-pin plastic QFP

120-pin plastic LQFP

(FPT-120P-M13)

(FPT-120P-M21)

(FPT-120P-M05)

MB90570 Series

■ FEATURES

• Clock

Embedded PLL clock multiplication circuit

Operating clock (PLL clock) can be selected from 1/2 to 4× oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz).

Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, 4× PLL clock, operation at VCC of 5.0 V)

• Maximum memory space

16 Mbytes

• Instruction set optimized for controller applications

Rich data types (bit, byte, word, long word)

Rich addressing mode (23 types)

Enhanced signed multiplication/division instruction and RETI instruction functions

Enhanced precision calculation realized by the 32-bit accumulator

• Instruction set designed for high level language (C) and multi-task operations

Adoption of system stack pointer

Enhanced pointer indirect instructions

Barrel shift instructions

• Program patch function (for two address pointers)

• Enhanced execution speed

4-byte instruction queue

• Enhanced interrupt function

8 levels, 34 factors

• Automatic data transmission function independent of CPU operation

Extended intelligent I/O service function (EI²OS): Up to 16 channels

• Embedded ROM size and types

Mask ROM: 128 kbytes/256 kbytes

Flash ROM: 256 kbytes

Embedded RAM size: 6 kbytes/10 kbytes (mask ROM)

10 kbytes (flash memory)

10 kbytes (evaluation device)

• Low-power consumption (standby) mode

Sleep mode (mode in which CPU operating clock is stopped)

Stop mode (mode in which oscillation is stopped)

CPU intermittent operation mode

Hardware standby mode

• Process

CMOS technology

• I/O port

General-purpose I/O ports (CMOS): 63 ports

General-purpose I/O ports (with pull-up resistors): 24 ports

General-purpose I/O ports (open-drain): 10 ports

Total: 97 ports

(Continued)

2

MB90570 Series

(Continued)

• Timer

Timebase timer/watchdog timer: 1 channel

8/16-bit PPG timer: 8-bit × 2 channels or 16-bit × 1 channel

• 8/16-bit up/down counter/timer: 1 channel (8-bit × 2 channels)

• 16-bit I/O timer

16-bit free run timer: 1 channel

Input capture (ICU): Generates an interrupt request by latching a 16-bit free run timer counter value upon

detection of an edge input to the pin.

Output compare (OCU):Generates an interrupt request and reverse the output level upon detection of a match

between the 16-bit free run timer counter value and the compare setting value.

• Extended I/O serial interface: 3 channels

• I²C interface (1 channel)

Serial I/O port for supporting Inter IC BUS

• UART0 (SCI), UART1 (SCI)

With full-duplex double buffer

Clock asynchronized or clock synchronized transmission can be selectively used.

• DTP/external interrupt circuit (8 channels)

A module for starting extended intelligent I/O service (EI²OS) and generating an external interrupt triggered

by an external input.

• Delayed interrupt generation module

Generates an interrupt request for switching tasks.

• 8/10-bit A/D converter (8 channels)

8/10-bit resolution

Starting by an external trigger input.

Conversion time: 26.3 µs

• 8-bit D/A converter (based on the R-2R system)

8-bit resolution: 2 channels (independent)

Setup time: 12.5 µs

• Clock timer: 1 channel

• Chip select output (8 channels)

An active level can be set.

• Clock output function

3

MB90570 Series

■ PRODUCT LINEUP

Part number

MB90573

MB90574/C

MB90F574/A

MB90V570/A

Item

Classification

ROM size

RAM size

Mask ROM products

128 kbytes

6 kbytes

Flash ROM products Evaluation product

256 kbytes None

10 kbytes

The number of instructions: 340

Instruction bit length: 8 bits, 16 bits

Instruction length: 1 byte to 7 bytes

Data bit length: 1 bit, 8 bits, 16 bits

CPU functions

Minimum execution time: 62.5 ns (at machine clock of 16 MHz)

Interrupt processing time: 1.5 µs (at machine clock of 16 MHz, minimum value)

General-purpose I/O ports (CMOS output): 63

General-purpose I/O ports (with pull-up resistor): 24

General-purpose I/O ports (N-ch open-drain output): 10

Total: 97

Ports

Clock synchronized transmission (62.5 kbps to 1 Mbps)

Clock asynchronized transmission (1202 bps to 9615 bps)

Transmission can be performed by bi-directional serial transmission or by

master/slave connection.

UART0 (SCI), UART1 (SCI)

Resolution: 8/10-bit

Number of inputs: 8

One-shot conversion mode (converts selected channel only once)

Scan conversion mode (converts two or more successive channels and can

program up to 8 channels.)

8/10-bit A/D converter

8/16-bit PPG timer

Continuous conversion mode (converts selected channel continuously)

Stop conversion mode (converts selected channel and stop operation repeatedly)

Number of channels: 1 (or 8-bit × 2 channels)

PPG operation of 8-bit or 16-bit

A pulse wave of given intervals and given duty ratios can be output.

Pulse interval: 62.5 ns to 1 µs (at oscillation of 4 MHz, machine clock of 16 MHz)

Number of channels: 1 (or 8-bit × 2 channels)

Event input: 6 channels

8-bit up/down counter/timer used: 2 channels

8-bit re-load/compare function supported: 1 channel

8/16-bit up/down counter/

timer

16-bit

free run timer

Number of channel: 1

Overflow interrupts

Output

16-bit

Number of channels: 4

Pin input factor: A match signal of compare register

compare

I/O timer

(OCU)

Input capture

(ICU)

Number of channels: 2

Rewriting a register value upon a pin input (rising, falling, or both edges)

(Continued)

4

MB90570 Series

(Continued)

Part number

MB90573

MB90574/C

MB90F574/A

MB90V570/A

Item

Number of inputs: 8

Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.

External interrupt circuit or extended intelligent I/O service (EI²OS) can be used.

DTP/external interrupt circuit

Delayed interrupt generation

module

An interrupt generation module for switching tasks used in real time operating

systems.

Clock synchronized transmission (3125 bps to 1 Mbps)

LSB first/MSB first

Extended I/O serial interface

I²C interface

Serial I/O port for supporting Inter IC BUS

18-bit counter

Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms

(at oscillation of 4 MHz)

Timebase timer

8-bit resolution

Number of channels: 2 channels

Based on the R-2R system

8-bit D/A converter

Watchdog timer

Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms

(at oscillation of 4 MHz, minimum value)

Low-power consumption

(standby) mode

Sleep/stop/CPU intermittent operation/clock timer/hardware standby

Process

CMOS

Power supply voltage for

operation*

4.5 V to 5.5 V

* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

Assurance for the MB90V570/A is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an

operating temperature of 0 to +25°C, and an operating frequency of 1 MHz to 16 MHz.

■ PACKAGE AND CORRESPONDING PRODUCTS

Package

FPT-120P-M05

MB90573

MB90574

MB90F574/A

MB90574C

×

FPT-120P-M13

FPT-120P-M21

×

: Available ×: Not available

Note: For more information about each package, see section “■ Package Dimensions.”

5

MB90570 Series

■ DIFFERENCES AMONG PRODUCTS

Memory Size

In evaluation with an evaluation product, note the difference between the evaluation product and the product

actually used. The following items must be taken into consideration.

• The MB90V570/A does not have an internal ROM, however, operations equivalent to chips with an internal

ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of

the development tool.

• In the MB90V570/A, images from FF4000^Hto FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to

mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.)

• In the MB90F574/574/573/F574A/574C, images from FF4000^Hto FFFFFFH are mapped to bank 00, and

FF0000H to FF3FFFH to bank FF only.

• The products designated with /A or /C are different from those without /A or /C in that they are DTP/externally-

interrupted types which return from standby mode at the ch.0 to ch.1 edge request.

6

MB90570 Series

■ PIN ASSIGNMENT

(Top view)

1

2

3

4

5

6

7

8

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

P31/RD

RST

MD0

MD1

MD2

HST

PC3

PC2

PC1

P32/WRL

P33/WRH

P34/HRQ

P35/HAK

P36/RDY

P37/CLK

V^CC

P40/SIN0

P41/SOT0

P42/SCK0

P43/SIN1

P44/SOT1

P45/SCK1

P46/PPG0

P47/PPG1

P50/SIN2

P51/SOT2

P52/SCK2

P53/SIN3

P54/SOT3

P55/SCK3

P56/IN0

9

PC0

PB7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

PB6/ADTG

PB5/IRQ5

PB4/IRQ4

PB3/IRQ3

PB2/IRQ2

PB1/IRQ1

X0A

X1A

PB0/IRQ0

PA7/SCL

PA6/SDA

PA5/ZIN1

PA4/BIN1

PA3/AIN1/IRQ7

PA2/ZIN0

PA1/BIN0

PA0/AIN0/IRQ6

V^SS

P57/IN1

P60/SIN4

P61/SOT4

P62/SCK4

P63/CKOT

P64/OUT0

P65/OUT1

P97/CS7

P96/CS6

(FPT-120P-M05)

(FPT-120P-M13)

(FPT-120P-M21)

7

MB90570 Series

■ PIN DESCRIPTION

Pin no.

Pin name

X0,X1

Circuit type

Function

LQFP-120 *¹

QFP-120 *²

High speed oscillator input pins

Low speed oscillator input pins

92,93

74,73

A

B

C

X0A,X1A

These are input pins used to designate the operating mode. They should

be connected directly to Vcc or Vss.

89 to 87

MD0 to MD2

Reset input pin

90

86

RST

C

D

Hardware standby input pin

HST

In single chip mode, these are general purpose I/O pins. When set for

input, they can be set by the pull-up resistance setting register (RDR0).

When set for output, this setting will be invalid.

95 to 102

P00 to P07

In external bus mode, these pins function as address low output/data low

I/O pins.

AD00 to AD07

In single chip mode, these are general purpose I/O pins. When set for

input, they can be set by the pull-up resistance setting register (RDR1).

When set for output, the setting will be invalid.

103 to 110 P10 to P17

AD08 to AD15

D

In external bus mode, these pins function as address middle output/data

high I/O pins.

In single chip mode this is a general-purpose I/O port.

111 to 118 P20 to P27

A16 to A23

E

In external bus mode, these pins function as address high output pins.

In single chip mode this is a general-purpose I/O port.

120

P30

ALE

In external bus mode, this pin functions as the address latch enable signal

output pin.

In single chip mode this is a general-purpose I/O port.

1

P31

RD

E

In external bus mode, this pin functions as the read strobe signal output

pin.

In single chip mode this is a general-purpose I/O port.

2

P32

In external bus mode, this pin functions as the data bus lower 8-bit write

strobe signal output pin.

WRL

In single chip mode this is a general-purpose I/O port.

3

P33

In external bus mode, this pin functions as the data bus upper 8-bit write

strobe signal output pin.

WRH

In single chip mode this is a general-purpose I/O port.

4

P34

In external bus mode, this pin functions as the hold request signal input

pin.

HRQ

In single chip mode this is a general-purpose I/O port.

5

P35

In external bus mode, this pin functions as the hold acknowledge signal

output pin.

HAK

In single chip mode this is a general-purpose I/O port.

6

P36

In external bus mode, this pin functions as the ready signal input pin.

RDY

*1: FPT-120P-M05

*2: FPT-120P-M13,FPT-120P-M21

(Continued)

8

MB90570 Series

Pin no.

Pin name Circuit type

Function

LQFP-120 *¹

QFP-120 *²

In single chip mode this is a general-purpose I/O port.

7

9

P37

E

F

In external bus mode, this pin functions as the clock (CLK) signal output

pin.

CLK

In single chip mode this is a general-purpose I/O port. It can be set to open

drain by the ODR4 register.

P40

This is also the UART ch.0 serial data input pin. While UART ch.0 is in

input operation, this input signal is in continuous use, and therefore the

output function should only be used when needed. If shared by output

from other functions, this pin should be output disabled during SIN

operation.

SIN0

In single chip mode this is a general-purpose I/O port. It can be set to open

drain by the ODR4 register.

10

11

12

P41

F

This is also the UART ch.0 serial data output pin. This function is valid

when UART ch.0 is enabled for data output.

SOT0

P42

In single chip mode this is a general-purpose I/O port. It can be set to open

drain by the ODR4 register.

This is also the UART ch.0 serial clock I/O pin. This function is valid when

UART ch.0 is enabled for clock output.

SCK0

P43

In single chip mode this is a general-purpose I/O port. It can be set to

open-drain by the ODR4 register.

This is also the UART ch.1 serial data input pin. While UART ch.1 is in

input operation, this input signal is in continuous use, and therefore the

output function should only be used when needed. If shared by output

from other functions, this pin should be output disabled during SIN

operation.

SIN1

In single chip mode this is a general-purpose I/O port. It can be set to

opendrain by the ODR4 register.

13

14

P44

F

E

This is also the UART ch.1 serial data output pin. This function is valid

when UART ch.1 is enabled for data output.

SOT1

In single chip mode this is a general-purpose I/O port. It can be set to open

drain by the ODR4 register.

P45

This is also the UART ch.1 serial clock I/O pin. This function is valid when

UART ch.1 is enabled for clock output.

SCK1

In single chip mode this is a general-purpose I/O port. It can be set to open

drain by the ODR4 register.

15,16

17

P46,P47

PPG0,PPG1

These are also the PPG0, 1 output pins. This function is valid when PPG0,

1 output is enabled.

In single chip mode this is a general-purpose I/O port.

P50

This is also the I/O serial ch.0 data input pin. During serial data input, this

input signal is in continuous use, and therefore the output function should

only be used when needed.

SIN2

(Continued)

*1: FPT-120P-M05

*2: FPT-120P-M13,FPT-120P-M21

9

MB90570 Series

Pin no.

Pin name

P51

Circuit type

Function

LQFP-120 *¹

QFP-120 *²

In single chip mode this is a general-purpose I/O port.

18

19

20

E

This is also the I/O serial ch.0 data output pin. This function is valid when

serial ch.0 is enabled for serial data output.

SOT2

In single chip mode this is a general-purpose I/O port.

P52

E

This is also the I/O serial ch.0 clock I/O pin. This function is valid when

serial ch.0 is enabled for serial data output.

SCK2

In single chip mode this is a general-purpose I/O port.

P53

This is also the I/O serial ch.1 data input pin. During serial data input, this

input signal is in continuous use, and therefore the output function should

only be used when needed.

SIN3

In single chip mode this is a general-purpose I/O port.

21

22

P54

E

This is also the I/O serial ch.1 data output pin. This function is valid when

serial ch.1 is enabled for serial data output.

SOT3

In single chip mode this is a general-purpose I/O port.

P55

This is also the I/O serial ch.1 clock I/O pin. This function is valid when

serial ch.1 is enabled for serial data output.

SCK3

In single chip mode this is a general-purpose I/O port.

23,24

P56,P57

IN0,IN1

These are also the input capture ch.0/1 trigger input pins. During input

capture signal input on ch.0/1 this function is in continuous use, and

therefore the output function should only be used when needed.

In single chip mode this is a general-purpose I/O port. When set for input

it can be set by the pull-up resistance register (RDR6). When set for

output this setting will be invalid.

25

P60

SIN4

P61

F

This is also the I/O serial ch.2 data input pin. During serial data input this

function is in continuous use, and therefore the output function should

only be used when needed.

In single chip mode this is a general-purpose I/O port. When set for input

it can be set by the pull-up resistance register (RDR6). When set for

output this setting will be invalid.

26

27

28

F

This is also the I/O serial ch.2 data output pin. This function is valid when

serial ch.2 is enabled for serial data output.

SOT4

P62

In single chip mode this is a general-purpose I/O port. When set for input

it can be set by the pull-up resistance register (RDR6). When set for

output this setting will be invalid.

This is also the I/O serial ch.2 serial clock I/O pin. This function is valid

when serial ch.2 is enabled for serial data output.

SCK4

P63

In single chip mode this is a general-purpose I/O port. When set for input

it can be set by the pull-up resistance register (RDR6). When set for

output this setting will be invalid.

This is also the clock monitor output pin. This function is valid when clock

monitor output is enabled.

CKOT

(Continued)

*1: FPT-120P-M05

*2: FPT-120P-M13,FPT-120P-M21

10

MB90570 Series

Pin no.

LQFP-120 *¹

Pin name

Circuit type

Function

QFP-120 *²

In single chip mode these are general-purpose I/O ports. When set for

input they can be set by the pull-up resistance register (RDR6). When set

for output this setting will be invalid.

29 to 32

P64 to P67

F

These are also the output compare ch.0 to ch.3 event output pins. This

function is valid when the respective channel(s) are enabled for output.

OUT0 to

OUT3

These are general purpose I/O ports.

35 to 37

40,41

P70 to P72

P73,P74

E

I

These are general purpose I/O ports.

These are also the D/A converter ch.0,1 analog signal output pins.

These are general purpose I/O ports.

DA0,DA1

46 to 53

55 to 62

P80 to P87

AN0 to AN7

K

E

These are also A/D converter analog input pins. This function is valid

when analog input is enabled.

These are general purpose I/O ports.

P90 to P97

CS0 to CS7

These are also chip select signal output pins. This function is valid when

chip select signal output is enabled.

This is the power supply stabilization capacitor pin. It should be

connected externally to an 0.1 µF ceramic capacitor. Note that this is

not required on the FLASH model (MB90F574/A) and MB90574C.

34

64

C

G

E

This is a general purpose I/O port.

PA0

This pin is also used as count clock A input for 8/16-bit up-down counter

ch.0.

AIN0

This pin can also be used as interrupt request input ch. 6.

This is a general purpose I/O port.

IRQ6

PA1

65

66

67

E

This pin is also used as count clock B input for 8/16-bit up-down counter

ch.0.

BIN0

This is a general purpose I/O port.

PA2

This pin is also used as count clock Z input for 8/16-bit up-down counter

ch.0.

ZIN0

This is a general purpose I/O port.

PA3

This pin is also used as count clock A input for 8/16-bit up-down counter

ch.1.

AIN1

This pin can also be used as interrupt request input ch.7.

This is a general purpose I/O port.

IRQ7

PA4

68

69

E

This pin is also used as count clock B input for 8/16-bit up-down counter

ch.1.

BIN1

This is a general purpose I/O port.

PA5

This pin is also used as count clock Z input for 8/16-bit up-down counter

ch.1.

ZIN1

*1: FPT-120P-M05

*2: FPT-120P-M13,FPT-120P-M21

(Continued)

11

MB90570 Series

(Continued)

Pin no.

Pin name

PA6

Circuit type

Function

This is a general purpose I/O port.

LQFP-120 *¹

QFP-120 *²

70

71

L

This pin is also used as the data I/O pin for the I²C interface. This

function is valid when the I²C interface is enabled for operation. While the

I²C interface is operating, this port should be set to the input level

(DDRA: bit6 = 0).

SDA

This is a general purpose I/O port.

PA7

SCL

L

This pin is also used as the clock I/O pin for the I²C interface. This

function is valid when the I²C interface is enabled for operation. While the

I²C interface is operating, this port should be set to the input level

(DDRA: bit7 = 0).

These are general-purpose I/O ports.

72,

PB0,

E

75 to 79

PB1 to PB5

These pins are also the external interrupt input pins. IRQ0, 1 are

enabled for both rising and falling edge detection, and therefore cannot

be used for recovery from STOP status for MB90V570, MB90F574,

MB90573 and MB90574. However, IRQ0, 1 can be used for recovery

from STOP status for MB90V570A, MB90F574A and MB90574C.

IRQ0,

IRQ1 to IRQ5

This is a general purpose I/O port.

80

PB6

E

This is also the A/D converter external trigger input pin. While the A/D

converter is in input operation, this input signal is in continuous use, and

therefore the output function should only be used when needed.

ADTG

This is a general purpose I/O port.

These are general purpose I/O ports.

These are power supply (5V) input pins.

81

PB7

E

82 to 85

8,54,94

PC0 to PC3

VCC

Power

supply

These are power supply (0V) input pins.

33,63,

91,119

VSS

Power

supply

This is the analog macro (D/A, A/D etc.) Vcc power supply input pin.

42

43

AVCC

H

J

This is the A/D converter Vref+ input pin. The input voltage should not

exceed Vcc.

AVRH

This is the A/D converter Vref-input pin. The input voltage should not

less than Vss.

44

AVRL

H

This is the analog macro (D/A, A/D etc.) Vss power supply input pin.

45

38

AVSS

DVCC

H

This is the D/A converter Vref input pin. The input voltage should not

exceed Vcc.

This is the D/A converter GND power supply pin. It should be set to Vss

equivalent potential.

39

DVSS

H

*1: FPT-120P-M05

*2: FPT-120P-M13,FPT-120P-M21

12

MB90570 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• Oscillator circuit

Oscillator recovery resistance for high

X1

speed = approx. 1 MΩ

X0

Standby control signal

B

• Oscillator circuit

Oscillator recovery resistance for low

speed = approx. 1 MΩ

X1A

X0A

Standby control signal

C

• Hysteresis input pin

Resistance value = approx. 50 kΩ (typ.)

R

Hysteresis input

D

• CMOS hysteresis input pin with input pull-

up control

• CMOS level output.

• CMOS hysteresis input

(Includes input shut down standby control

function)

V^CC

Selective signal either

with a pull-up resistor or

without it.

V^CC

P-ch

N-ch

• Pull-up resistance value =

approx. 50 kΩ(typ.)

R

IOL = 4mA

Hysteresis input

Standby control for input interruption

I^OL= 4 mA

(Continued)

13

MB90570 Series

Type

Circuit

Remarks

E

• CMOS hysteresis input/output pin.

• CMOS level output

V^CC

• CMOS hysteresis input

(Includes input shut down standby control

function)

P-ch

I^OL= 4 mA

N-ch

R

Hysteresis input

Standby control for input interruption

I^OL= 4 mA

F

• CMOS hysteresis input/output pin.

• CMOS level output

V^CC

• CMOS hysteresis input

(Includes input shut down standby control

function)

P-ch

I^OL= 10 mA (Large current port)

N-ch

R

Hysteresis input

Standby control for input interruption

I^OL= 10 mA

G

• C pin output

V^CC

(capacitance connector pin).

On the MB90F574 this pin is not

connected (NC).

P-ch

N-ch

H

• Analog power supply protector

circuit.

V^CC

P-ch

AVP

N-ch

I

• CMOS hysteresis input/output

• Analog output/CMOS output

dual-function pin (CMOS output is not

available during analog output.)

(Analog output priority: DAE = 1)

• Includes input shout down standby

control function.

V^CC

P-ch

N-ch

R

I^OL= 4mA

Hysteresis input

Standby control for input interruption

DAO

I^OL= 4 mA

(Continued)

14

MB90570 Series

Type

Circuit

Remarks

J

• A/D converter ref+ power supply input

pin(AVRH), with power supply

protector circuit.

V^CC

P-ch

ANE

AVR

ANE

P-ch

N-ch

K

CC

• CMOS hysteresis input /analog input

dual-function pin.

V

P-ch

• CMOS output

• Includes input shut down function at input

shut down standby.

N-ch

R

Hysteresis input

Standby control for input interruption

Analog input

I^OL= 4 mA

V^CC

L

• Hysteresis input

N-ch

• N-ch open-drain output

• Includes input shut down standby control

function.

I^OL= 4mA

N-ch

R

Hysteresis input

Standby control for input interruption

I^OL= 4 mA

15

MB90570 Series

■ HANDLING DEVICES

1. Preventing Latchup

CMOS ICs may cause latchup in the following situations:

• When a voltage higher than Vcc or lower than Vss is applied to input or output pins.

• When a voltage exceeding the rating is applied between Vcc and Vss.

• When AVcc power is supplied prior to the Vcc voltage.

In turning on/turning off the analog power supply, make sure the analog power voltage (AV^CC, AVRH, DVCC)and

analog input voltages not exceed the digital voltage (VCC).

2. Treatment of unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the

device. Therefor they must be tied to VCC or Ground through resistors. In this case those resistors should be

more than 2 k<Symbol>W.

Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above

described connection.

3. Notes on Using External Clock

In using the external clock, drive X0 pin only and leave X1 pin unconnected.

• Using external clock

MB90570 series

X0

X1

Open

4. Unused Sub Clock Mode

If sub clock modes are not used, the oscillator should be connected to the X01A pin and X1A pin

5. Power Supply Pins (V^CC/V^SS)

In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to

avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to

lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise

in the ground level, and to conform to the total current rating.

Make sure to connect V^CCand VSS pins via lowest impedance to power lines.

16

MB90570 Series

It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pin near the device.

• Using power supply pins

VCC

VSS

VCC

VSS

VCC

MB90570 series

VCC

VSS

VCC

VSS

6. Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass

capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and

make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand

area for stabilizing the operation.

7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL,

DVCC,DVSS) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC).

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure

that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simulta-

neously is acceptable).

8. Connection of Unused Pins of A/D Converter

Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = DVCC = VSS.

9. N.C. Pins

The N.C. (internally connected) pins must be opened for use.

10. Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50

or more µs (0.2 V to 2.7 V).

11. Indeterminate outputs from ports 0 and 1

The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during

a power-on reset) after the power is turned on. (MB90573, MB90574, MB90V570, MB90V570A)

17

MB90570 Series

The series without built-in step-down circuit have no oscillation setting time of step-down circuit, so outputs

should not become indeterminate. (MB90F574,MB90F574A,MB90574C)

Timing chart of indeterminate outputs from ports 0 and 1

Oscillation setting time *²

Step-down circuit setting time *¹

VCC (power-supply pin)

PONR (power-on reset) signal

RST (external asynchronous reset) signal

RST (internal reset) signal

Oscillation clock signal

KA (internal operating clock A) signal

KB (internal operating clock B) signal

Period of indeterminate

PORT (port output) signal

*1: Step-down circuit setting time 2¹⁷/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms)

*2: Oscillation setting time

2¹⁸/oscillation clock frequency (oscillation clock frequency of 16 MHz: 16.38 ms)

12. Initialization

In the device, there are internal registers which are initialized only by a power-on reset. Turn on the power again

to initialize these registers.

13. Return from standby state

If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may

fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal

state.

14. Precautions for Use of ’DIV A, Ri,’ and ’DIVW A, Ri’ Instructions

The signed multiplication-division instructions ’DIV A, Ri,’ and ’DIVW A, RWi’ should be used when the corre-

sponding bank registers (DTB, ADB, USB, SSB) are set to value ’00h.’ If the corresponding bank registers (DTB,

ADB, USB, SSB) are set to a value other than ’00h,’ then the remainder obtained after the execution of the

instruction will not be placed in the instruction operand register.

15. Precautions for Use of REALOS

Extended intelligent I/O service (EI²OS) cannot be used, when REALOS is used.

18

MB90570 Series

■ BLOCK DIAGRAM

Interrupt controller

F²MC–16LX

CPU

3

P70 to P72

Port 7

Main clock

Sub clock

2

P73/DA0

P74/DA1

X0, X1

X0A, X1A

RST

8-bit

Clock control

block

(including timebase

timer)

D/A

converter

× 2 ch.

DV^CC

DV^SS

HST

8

P00/AD00 to P07/AD07

P10/AD08 to P17/AD15

P20/A16 to P27/A23

Port 0, 1, 2

16

Port 9

8

Chip select

output

P90/CS0 to P97/CS7

8

P30/ALE

P31/RD

Port A

2

6

External bus

interface

PA1/BIN0

P32/WRL

P33/WRH

P34/HRQ

PA2/ZIN0

PA3/AIN1/IRQ7

PA4/BIN1

6

8/16-bit up/down

counter/timer

P35/HAK

P36/RDY

P37/CLK

PA5/ZIN1

Port 3

2

PA6/SDA

PA7/SCL

I²C bus

P40/SIN0

P41/SOT0

P42/SCK0

P43/SIN1

P44/SOT1

P45/SCK1

P46/PPG0

P47/PPG1

Port 4

PA0/AIN0/IRQ6

DTP/

external

interrupt

circuit

2

UART0

6

PB0/IRQ0 to

PB5/IRQ5

(SCI),

UART1

(SCI)

× 8 ch.

2

PB7

Port B

8/16-bit

PPG timer

ch.0

PB6/ADTG

AVRL

AVRH

AV^CC

AV^SS

P80/AN0 to

P87/AN7

P50/SIN2

P51/SOT2

P52/SCK2

Port 5

8/10-bit

A/D converter

× 8 ch.

2

8

P53/SIN3

P54/SOT3

P55/SCK3

SIO × 2 ch

2

Port 8

Port C

P56/IN0

P57/IN1

4

2

PC0 to PC3

Input capture

(ICU)

16-bit free run timer

4

RAM

ROM

Output

P64/OUT0 to P67/OUT3

compare

(OCU)

P60/SIN4

P61/SOT4

P62/SCK4

SIO × 1 ch.

Port 6

P63/CKOT

Other pins

Clock output

P00 to P07 (8 ports): Provided with a register optional input pull-up resistor

P10 to P17 (8 ports): Provided with a register optional input pull-up resistor

P40 to P47 (8 ports): Heavy-current (I^OL= 10 mA) port

MD0 to MD2,

C, V^CC, V^SS

P60 to P67 (8 ports): Provided with a register optional input pull-up resistor

19

MB90570 Series

■ MEMORY MAP

Internal ROM

external bus mode

A mirror function

is supported.

Single chip mode

A mirror function is

supported.

External ROM

external bus mode

FFFFFF^H

ROM area

Address #1

FC0000^H

010000^H

ROM area

(image of

bank FF)

ROM area

(image of

bank FF)

Address #2

004000^H

Address #3

Register

RAM

Register

RAM

Register

RAM

000100^H

0000C0^H

000000^H

Peripheral

Part number

MB90573

Address #1*

FE0000^H

Address #2*

004000H

Address #3*

001800H

MB90574/C

MB90F574/A

FC0000H

004000H

002900H

FC0000H

004000H

002900H

: Internal access memory

: External access memory

: Inhibited area

*: Addresses #1, #2 and #3 are unique to the product type.

Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler

small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address,

enabling reference of the table on the ROM without stating “far”.

For example, if an attempt has been made to access 00C000^H, the contents of the ROM at FFC000H are

accessed actually. Since the ROM area of the FF bank exceeds 48 kbytes, the whole area cannot be reflected

in the image for the 00 bank. The ROM data at FF4000^Hto FFFFFFH looks, therefore, as if it were the image

for 00400^Hto 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H

to FFFFFF^H.

20

MB90570 Series

■ F²MC-16LX CPU PROGRAMMING MODEL

• Dedicated registers

: Accumulator (A)

AH

AL

Dual 16-bit register used for storing results of calculation etc. The two 16-bit

registers can be combined to be used as a 32-bit register.

: User stack pointer (USP)

The 16-bit pointer indicating a user stack address.

USP

SSP

PS

: System stack pointer (SSP)

The 16-bit pointer indicating the status of the system stack address.

: Processor status (PS)

The 16-bit register indicating the system status.

: Program counter (PC)

The 16-bit register indicating storing location of the current instruction code.

PC

: Direct page register (DPR)

DPR

The 8-bit register indicating bit 8 through 15 of the operand address in the short

direct addressing mode.

: Program bank register (PCB)

The 8-bit register indicating the program space.

PCB

DTB

USB

SSB

: Data bank register (DTB)

The 8-bit register indicating the data space.

: User stack bank register (USB)

The 8-bit register indicating the user stack space.

: System stack bank register (SSB)

The 8-bit register indicating the system stack space.

: Additional data bank register (ADB)

The 8-bit register indicating the additional data space.

ADB

8-bit

16-bit

32-bit

21

MB90570 Series

• General-purpose registers

Maximum of 32 banks

RW7

R7

R6

RL3

RL2

RL1

RL0

RW6

RW5

RW4

R5

R3

R4

R2

R1

R0

RW3

RW2

RW1

RW0

000180^H+ (RP × 10^H)

16-bit

• Processor status (PS)

ILM

RP

CCR

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

PS

ILM2 ILM1 ILM0 B4

B3

0

B2

0

B1

0

B0

0

—

I

S

1

T

X

N

X

Z

X

V

X

C

Initial value

0

X

—: Reserved

X : Undefined

22

MB90570 Series

■ I/O MAP

Abbreviated

Read/

write

Address

register

name

Register name

Port 0 data register

Resource name

Initial value

000000^H

000001H

000002H

000003H

000004H

000005H

000006H

000007H

000008H

000009H

00000AH

00000BH

00000CH

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

PDRA

PDRB

PDRC

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port B

Port C

X X X X X X X X B

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

Port 7 data register

Port 8 data register

Port 9 data register

Port A data register

Port B data register

Port C data register

00000DH

to

(Disabled)

00000FH

000010^H

000011H

000012H

000013H

000014H

000015H

000016H

000017H

000018H

000019H

00001AH

00001BH

00001CH

00001DH

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

DDR7

DDR8

DDR9

DDRA

DDRB

DDRC

ODR4

Port 0 direction register

Port 1 direction register

Port 2 direction register

Port 3 direction register

Port 4 direction register

Port 5 direction register

Port 6 direction register

Port 7 direction register

Port 8 direction register

Port 9 direction register

Port A direction register

Port B direction register

Port C direction register

Port 4 output pin register

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port B

Port C

Port 4

0 0 0 0 0 0 0 0 B

– – – 0 0 0 0 0 B

0 0 0 0 0 0 0 0 B

Port 8,

8/10-bit

00001EH

ADER

Analog input enable register

R/W

1 1 1 1 1 1 1 1 B

A/D converter

00001FH

000020^H

000021H

(Disabled)

SMR0

SCR0

Serial mode register 0

Serial control register 0

R/W

0 0 0 0 0 0 0 0 B

0 0 0 0 0 1 0 0 B

UART0

(SCI)

(Continued)

23

MB90570 Series

Abbreviated

Read/

write

Resource

name

Address

register

name

Register name

Initial value

SIDR0/

SODR0

Serial input data register 0/

serial output data register 0

000022^H

R/W

X X X X X X X X ^B

UART0

(SCI)

000023H

000024H

000025H

SSR0

SMR1

SCR1

Serial status register 0

Serial mode register 1

Serial control register 1

R/W

0 0 0 0 1 – 0 0 B

0 0 0 0 0 0 0 0 B

0 0 0 0 0 1 0 0 B

UART1

(SCI)

SIDR1/

SODR1

Serial input data register 1/

serial output data register 1

000026H

000027H

R/W

X X X X X X X X ^B

0 0 0 0 1 – 0 0 B

SSR1

Serial status register 1

Communica-

tions

prescaler

register 0

Communications prescaler control

register 0

000028H

000029H

00002A^H

CDCR0

R/W

0 – – – 1 1 1 1 ^B

(Disabled)

Communica-

tions

prescaler

register 0

Communications prescaler control

register 1

CDCR1

R/W

0 – – – 1 1 1 1 B

00002BH

to

(Disabled)

00002FH

000030^H

000031H

000032H

000033H

000034H

000035^H

ENIR

EIRR

DTP/interrupt enable register

DTP/interrupt factor register

R/W

0 0 0 0 0 0 0 0 B

X X X X X X X X B

0 0 0 0 0 0 0 0 B

DTP/external

interrupt cir-

cuit

ELVR

Request level setting register

R/W

(Disabled)

A/D control status register lower

digits

000036H

000037H

ADCS1

ADCS2

R/W

0 0 0 0 0 0 0 0 B

0 0 0 0 0 0 0 0 ^B

A/D control status register upper

digits

8/10-bit A/D

converter

R/W or W

000038H

000039H

00003AH

00003BH

00003CH

00003DH

ADCR1

ADCR2

DADR0

DADR1

DACR0

DACR1

A/D data register lower digits

A/D data register upper digits

D/A converter data register ch.0

D/A converter data register ch.1

D/A control register 0

R

X X X X X X X X B

0 0 0 0 1 – X X B

X X X X X X X X ^B

X X X X X X X X B

– – – – – – – 0 B

W

R/W

8-bit D/A

converter

D/A control register 1

Clock monitor

function

00003EH

CLKR

Clock output enable register

R/W

– – – – 0 0 0 0 ^B

00003FH

000040^H

000041H

(Disabled)

PRLL0

PRLH0

PPG0 reload register L ch.0

PPG0 reload register H ch.0

R/W

X X X X X X X X B

(Continued)

8/16-bit PPG

timer 0

24

MB90570 Series

Abbreviated

register

name

Read/

write

Address

Register name

Resource name

Initial value

000042^H

000043H

PRLL1

PRLH1

PPG1 reload register L ch.1

PPG1 reload register H ch.1

R/W

X X X X X X X X ^B

X X X X X X X X B

8/16-bit PPG

timer 1

PPG0 operating mode control

register ch.0

8/16-bit PPG

timer 0

000044H

000045H

PPGC0

PPGC1

PPGOE

R/W

0 X 0 0 0 X X 1 ^B

0 X 0 0 0 0 0 1 ^B

0 0 0 0 0 0 X X ^B

PPG1 operating mode control

register ch.1

8/16-bit PPG

timer 1

PPG0 and 1 output control registers

ch.0 and ch.1

8/16-bit PPG

timer 0, 1

000046H

000047H

000048^H

(Disabled)

Serial mode control lower status

register 0

SMCSL0

R/W

– – – – 0 0 0 0 B

Extended I/O

serial interface 0 0 0 0 0 0 0 1 0 ^B

Serial mode control upper status

register 0

000049H

SMCSH0

SDR0

R/W

00004AH

00004BH

Serial data register 0

X X X X X X X X B

(Disabled)

Serial mode control lower status

register 1

00004C^H

00004DH

SMCSL1

R/W

– – – – 0 0 0 0 B

Extended I/O

Serial mode control upper status

register 1

SMCSH1

SDR1

R/W

serial interface 1 0 0 0 0 0 0 1 0 B

00004EH

00004FH

000050^H

000051H

000052H

000053H

000054H

000055H

000056^H

000057H

000058H

000059H

00005A^H

00005BH

00005CH

00005DH

00005EH

00005FH

Serial data register 1

X X X X X X X X B

(Disabled)

X X X X X X X X ^B

IPCP0

ICU data register ch.0

R

X X X X X X X X B

16-bit I/O timer

(input capture

(ICU) section)

X X X X X X X X ^B

X X X X X X X X B

0 0 0 0 0 0 0 0 B

IPCP1

ICS01

ICU data register ch.1

R

ICU control status register

R/W

(Disabled)

0 0 0 0 0 0 0 0 ^B

0 0 0 0 0 0 0 0 B

16-bit I/O timer

(16-bit free run

timer section)

TCDT

TCCS

Free run timer data register

R/W

Free run timer control status register

(Disabled)

X X X X X X X X ^B

X X X X X X X X B

X X X X X X X X ^B

X X X X X X X X B

X X X X X X X X ^B

X X X X X X X X B

(Continued)

OCCP0

OCCP1

OCCP2

OCU compare register ch.0

OCU compare register ch.1

OCU compare register ch.2

R/W

16-bit I/O timer

(output compare

(OCU) section)

25

MB90570 Series

Abbreviated

Read/

write

Address

register

name

Register name

Resource name

Initial value

000060^H

000061H

000062H

000063H

000064H

000065H

000066H

000067^H

000068H

000069H

00006AH

00006BH

00006CH

00006DH

00006E^H

X X X X X X X X ^B

X X X X X X X X B

0 0 0 0 – – 0 0 B

– – – 0 0 0 0 0 B

0 0 0 0 – – 0 0 B

– – – 0 0 0 0 0 B

OCCP3

OCU compare register ch.3

R/W

16-bit I/O timer

(output compare

(OCU) section)

OCS0

OCS1

OCS2

OCS3

OCU control status register ch.0

OCU control status register ch.1

OCU control status register ch.2

OCU control status register ch.3

R/W

(Disabled)

I²C bus status register

I²C bus control register

I²C bus clock control register

I²C bus address register

I²C bus data register

IBSR

IBCR

ICCR

IADR

IDAR

R

0 0 0 0 0 0 0 0 ^B

– – 0 X X X X X ^B

– X X X X X X X ^B

X X X X X X X X ^B

R/W

I²C interface

(Disabled)

ROM mirroring

function

selection module

ROM mirroring function selection

register

00006FH

ROMM

W

– – – – – – – 1 ^B

000070H

000071H

000072H

000073H

000074H

000075H

000076H

000077H

000078H

000079H

00007AH

00007BH

UDCR0

UDCR1

RCR0

Up/down count register 0

Up/down count register 1

Reload compare register 0

Reload compare register 1

Counter status register 0

R

0 0 0 0 0 0 0 0 B

8/16-bit up/down

counter/timer

W

RCR1

W

CSR0

R/W

(Reserved area)*³

CCRL0

CCRH0

CSR1

– 0 0 0 0 0 0 0 B

0 0 0 0 0 0 0 0 B

Counter control register 0

Counter status register 1

R/W

8/16-bit up/down

counter/timer

R/W

(Reserved area)*³

CCRL1

CCRH1

– 0 0 0 0 0 0 0 B

8/16-bit up/down

counter/timer

Counter control register 1

R/W

Serial mode control lower status

register 2

00007CH

00007DH

SMCSL2

R/W

– – – – 0 0 0 0 ^B

Extended I/O

Serial mode control higher status

register 2

SMCSH2

SDR2

R/W

serial interface 2 0 0 0 0 0 0 1 0 ^B

00007EH

00007FH

Serial data register 2

X X X X X X X X B

(Disabled)

(Continued)

26

MB90570 Series

Abbreviated

register

name

Read/

write

Address

Register name

Resource name

Initial value

000080^H

000081H

000082H

000083H

000084H

000085H

000086H

CSCR0

CSCR1

CSCR2

CSCR3

CSCR4

CSCR5

CSCR6

Chip selection control register 0

Chip selection control register 1

Chip selection control register 2

Chip selection control register 3

Chip selection control register 4

Chip selection control register 5

Chip selection control register 6

R/W

– – – – 0 0 0 0 ^B

– – – – 0 0 0 0 B

Chip select

output

000087H

to

(Disabled)

00008B^H

Port 0 input pull-up resistor setup

register

00008C^H

00008DH

00008EH

RDR0

RDR1

RDR6

R/W

Port 0

Port 1

Port 6

0 0 0 0 0 0 0 0 ^B

0 0 0 0 0 0 0 0 B

Port 1 input pull-up resistor setup

register

Port 6 input pull-up resistor setup

register

00008FH

to

(Disabled)

00009D^H

Address match

detection

Program address detection control

status register

00009E^H

00009FH

PACSR

DIRR

R/W

0 0 0 0 0 0 0 0 ^B

– – – – – – – 0 B

function

Delayed

interrupt

generation

module

Delayed interrupt factor generation/

cancellation register

Low-power consumption mode

control register

Low-power

consumption

(standby) mode

0000A0H

0000A1H

LPMCR

CKSCR

R/W

0 0 0 1 1 0 0 0 ^B

1 1 1 1 1 1 0 0 B

Clock select register

0000A2H

to

(Disabled)

0000A4H

Automatic ready function select

register

0000A5H

ARSR

W

0 0 1 1 – – 0 0 B

External bus pin

0000A6H

0000A7H

0000A8H

0000A9H

0000AAH

HACR

ECSR

WDTC

TBTC

WTC

Upper address control register

Bus control signal select register

Watchdog timer control register

Timebase timer control register

Clock timer control register

W

0 0 0 0 0 0 0 0 B

W

R/W

Watchdog timer X X X X X X X X B

Timebase timer

Clock timer

1 – – 0 0 1 0 0 B

1 X 0 0 0 0 0 0 B

(Continued)

27

MB90570 Series

(Continued)

Abbreviated

Read/

write

Address

register

name

Register name

Resource name

Initial value

0000AB^H

to

(Disabled)

0000ADH

0000AE^H

0000AFH

0000B0^H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

0000BEH

0000BFH

FMCS

Flash control register

R/W

(Disabled)

Flash interface

0 0 0 X 0 X X 0 B

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

Interrupt control register 07

Interrupt control register 08

Interrupt control register 09

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

Interrupt control register 14

Interrupt control register 15

R/W

0 0 0 0 0 1 1 1 B

Interrupt

controller

0000C0H

to

0000FFH

(External area)*¹

(RAM area)*²

000100H

to

000###H

to

(Reserved area)*³

001FEF^H

001FF0H

001FF1H

001FF2H

001FF3H

001FF4H

001FF5H

Program address detection register 0

Program address detection register 1

Program address detection register 2

Program address detection register 3

Program address detection register 4

Program address detection register 5

R/W

X X X X X X X X ^B

X X X X X X X X B

X X X X X X X X ^B

X X X X X X X X B

PADR0

PADR1

Address match

detection

function

001FF6H

to

(Reserved area)

001FFFH

28

MB90570 Series

Descriptions for read/write

R/W: Readable and writable

R: Read only

W: Write only

Descriptions for initial value

0 : The initial value of this bit is “0”.

1 : The initial value of this bit is “1”.

X : The initial value of this bit is undefined.

– : This bit is unused. The initial value is undefined.

*1: This area is the only external access area having an address of 0000FF^Hor lower. An access operation to this

area is handled as that to external I/O area.

*2: For details of the RAM area, see “■ MEMORY MAP”.

*3: The reserved area is disabled because it is used in the system.

Notes: • For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an

initial value. Note that the values are different from reading results.

For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending

on the types of the reset. However initial value for resets that initializes the value are listed.

• The addresses following 0000FF^Hare reserved. No external bus access signal is generated.

• Boundary ####H between the RAM area and the reserved area varies with the product model.

29

MB90570 Series

■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

Interrupt vector

Number Address

Interrupt control register

EI²OS

Interrupt source

Priority

support

ICR

—

Address

Reset

×

# 08

# 09

# 10

# 11

FFFFDC^H

FFFFD8^H

FFFFD4H

FFFFD0H

—

High

INT9 instruction

Exception

—

8/10-bit A/D converter

ICR00

ICR01

ICR02

0000B0H

0000B1H

0000B2H

Input capture 0 (ICU) include

DTP0 (external interrupt 0)

Input capture 1 (ICU) include

Output compare 0 (OCU) match

Output compare 1 (OCU) match

Output compare 2 (OCU) match

Output compare 3 (OCU) match

Extended I/O serial interface 0

16-bit free run timer

# 12

# 13

# 14

# 15

# 16

# 17

# 18

# 19

# 20

# 21

# 22

# 23

# 24

FFFFCCH

FFFFC8H

FFFFC4H

FFFFC0H

FFFFBCH

FFFFB8H

FFFFB4H

FFFFB0H

FFFFACH

FFFFA8H

FFFFA4H

FFFFA0H

FFFF9CH

ICR03

ICR04

ICR05

ICR06

0000B3H

0000B4H

0000B5H

0000B6H

×

Extended I/O serial interface 1

Clock timer

Extended I/O serial interface 2

DTP1 (external interrupt 1)

DTP2/DTP3 (external interrupt 2/

external interrupt 3)

# 25

# 26

# 27

# 28

# 29

# 30

# 31

# 32

FFFF98^H

FFFF94^H

FFFF90^H

FFFF8C^H

FFFF88^H

FFFF84^H

FFFF80^H

FFFF7C^H

ICR07

ICR08

ICR09

0000B7H

0000B8H

0000B9H

8/16-bit PPG timer 0 counter

borrow

×

DTP4/DTP5 (external interrupt 4/

external interrupt 5)

8/16-bit PPG timer 1 counter

borrow

8/16-bit up/down counter/timer 0

borrow/overflow/inversion

8/16-bit up/down counter/timer 0

compare match

8/16-bit up/down counter/timer 1

borrow/overflow/inversion

0000BA^H

0000BAH

ICR10

ICR11

8/16-bit up/down counter/timer 1

compare match

DTP6 (external interrupt 6)

Timebase timer

# 33

# 34

FFFF78H

FFFF74H

0000BBH

×

Low

(Continued)

30

MB90570 Series

(Continued)

Interrupt source

Interrupt vector

Number Address

Interrupt control register

Priority

EI²OS

support

ICR

Address

DTP7 (external interrupt 7)

I²C interface

# 35

# 36

FFFF70^H

FFFF6C^H

ICR12

0000BCH

High

×

UART1 (SCI) reception complete

# 37

# 38

# 39

FFFF68H

FFFF64^H

FFFF60H

ICR13

0000BDH

UART1 (SCI) transmission

complete

UART0 (SCI) reception complete

ICR14

ICR15

0000BEH

0000BFH

UART0 (SCI) transmission

complete

# 40

# 41

# 42

FFFF5C^H

FFFF58H

FFFF54^H

Flash memory

×

Low

Delayed interrupt generation

module

: Can be used

×

: Can not be used

: Can be used. With EI²OS stop function.

31

MB90570 Series

■ PERIPHERALS

1. I/O Port

(1) Input/output Port

Port 0 through 4, 6, 8, A and B are general-purpose I/O ports having a combined function as an external bus

pin and a resource input. Port 0 to Port 3 have a general-purpose I/O ports function only in the single-chip mode.

• Operation as output port

The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.

Writing data to PDR register when the port is configured as output, the data is retained in the output latch in

the PDR and directly output to the pin.

The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR

register.

Note: When a read-modify-write instruction (e.g. bit set instruction) is performed to the port data register, the

destination bit of the operation is set to the specified value, not affecting the bits configured by the DDR

register for output, however, values of bits configured by the DDR register as inputs are changed because

input values to the pins are written into the output latch. To avoid this situation, configure the pins by the

DDR register as output after writing output data to the PDR register when configuring the bit used as

input as outputs.

• Operation as input port

The pin is configured as an input by setting the corresponding bit of the DDR register to “0”.

When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance

status.

When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs

are unaffected.

Reading the PDR register reads out the pin level (“0” or “1”).

32

MB90570 Series

(2) Register Configuration

• Port 0 data register (PDR0)

. . . . . . . . . . . .

Address bit 15

000000^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

XXXXXXXX

(PDR1)

B

P07

R/W

P06

R/W

P05

R/W

P04

R/W

P03

R/W

P02

R/W

P01

R/W

P00

R/W

• Port 1 data register (PDR1)

. . . . . . . . . . . .

(PDR0)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

P10

bit 0

Initial value

Address

B

XXXXXXXX

P17

R/W

P16

R/W

P15

R/W

P14

R/W

P13

R/W

P12

R/W

P11

R/W

000001^H

R/W

• Port 2 data register (PDR2)

. . . . . . . . . . . .

Address bit 15

000002^H

bit 8 bit 7

P27

bit 6

bit 5

bit 4

bit 3

bit 2

P22

R/W

bit 1

P21

R/W

bit 0

P20

R/W

Initial value

XXXXXXXX

(PDR3)

P26

R/W

P25

R/W

P24

R/W

P23

R/W

B

R/W

• Port 3 data register (PDR3)

. . . . . . . . . . . .

(PDR2)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

Address

B

XXXXXXXX

P37

R/W

P36

R/W

P35

R/W

P34

R/W

P33

R/W

P32

R/W

P31

R/W

P30

R/W

000003^H

• Port 4 data register (PDR4)

. . . . . . . . . . . .

Address bit 15

000004^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

P40

R/W

Initial value

XXXXXXXX

B

(PDR5)

P47

R/W

P46

R/W

P45

R/W

P44

R/W

P43

R/W

P42

R/W

P41

R/W

• Port 5 data register (PDR5)

. . . . . . . . . . . .

(PDR4)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

Address

B

XXXXXXXX

000005^H

P57

R/W

P56

R/W

P55

R/W

P54

R/W

P53

R/W

P52

R/W

P51

R/W

P50

R/W

• Port 6 data register (PDR6)

. . . . . . . . . . . .

Address bit 15

000006^H

bit 8 bit 7

P67

bit 6

bit 5

bit 4

bit 3

bit 2

P62

R/W

bit 1

P61

R/W

bit 0

P60

R/W

Initial value

XXXXXXXX

(PDR7)

P66

R/W

P65

R/W

P64

R/W

P63

R/W

B

R/W

• Port 7 data register (PDR7)

. . . . . . . . . . . .

(PDR6)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

P70

bit 0

Initial value

Address

B

—

P74

R/W

P73

R/W

P72

R/W

P71

R/W

- - -XXXXX

000007^H

—

R/W

• Port 8 data register (PDR8)

. . . . . . . . . . . .

Address bit 15

000008^H

bit 8 bit 7

P87

bit 6

bit 5

bit 4

bit 3

bit 2

P82

R/W

bit 1

P81

R/W

bit 0

P80

R/W

Initial value

XXXXXXXX

(PDR9)

P86

R/W

P85

R/W

P84

R/W

P83

R/W

B

R/W

(Continued)

33

MB90570 Series

• Port 9 data register (PDR9)

. . . . . . . . . . . .

(PDR8)

Address

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

B

XXXXXXXX

000009^H

P97

R/W

P96

R/W

P95

R/W

P94

R/W

P93

R/W

P92

R/W

P91

R/W

P90

R/W

• Port A data register (PDRA)

. . . . . . . . . . . .

Address bit 15

00000A^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PA0

Initial value

XXXXXXXX

B

(PDRB)

PA7

R/W

PA6

R/W

PA5

R/W

PA4

R/W

PA3

R/W

PA2

R/W

PA1

R/W

• Port B data register (PDRB)

. . . . . . . . . . . .

Address bit 15

00000B^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

XXXXXXXX

(PDRA)

B

PB7

R/W

PB6

R/W

PB5

R/W

PB4

R/W

PB3

R/W

PB2

R/W

PB1

R/W

PB0

R/W

• Port C data register (PDRC)

. . . . . . . . . . . .

Address bit 15

00000C^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

XXXXXXXX

(Disabled)

B

—

PC3

R/W

PC2

R/W

PC1

R/W

PC0

R/W

• Port 0 direction register (DDR0)

. . . . . . . . . . . .

Address bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

(DDR1)

000010^H

B

D07

R/W

D06

R/W

D05

R/W

D04

R/W

D03

R/W

D02

R/W

D01

R/W

D00

R/W

00000000

• Port 1 direction register (DDR1)

. . . . . . . . . . . .

(DDR0)

Address

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

B

00000000

000011^H

D17

R/W

D16

R/W

D15

R/W

D14

R/W

D13

R/W

D12

R/W

D11

R/W

D10

R/W

• Port 2 direction register (DDR2)

. . . . . . . . . . . .

Address bit 15

000012^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

D20

R/W

Initial value

00000000

(DDR3)

B

D27

R/W

D26

R/W

D25

R/W

D24

R/W

D23

R/W

D22

R/W

D21

R/W

• Port 3 direction register (DDR3)

. . . . . . . . . . . .

(DDR2)

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

B

00000000

000013^H

D37

R/W

D36

R/W

D35

R/W

D34

R/W

D33

R/W

D32

R/W

D31

R/W

D30

R/W

• Port 4 direction register (DDR4)

. . . . . . . . . . . .

Address bit 15

000014^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

D40

R/W

Initial value

00000000

(DDR5)

B

D47

R/W

D46

R/W

D45

R/W

D44

R/W

D43

R/W

D42

R/W

D41

R/W

(Continued)

34

MB90570 Series

• Port 5 direction register (DDR5)

. . . . . . . . . . . .

Address

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

D51

R/W

bit 8 bit 7

D50

bit 0

Initial value

B

00000000

D57

R/W

D56

R/W

D55

R/W

D54

R/W

D53

R/W

D52

R/W

000015^H

(DDR4)

R/W

• Port 6 direction register (DDR6)

. . . . . . . . . . . .

Address bit 15

000016^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

00000000

B

(DDR7)

D67

R/W

D66

R/W

D65

R/W

D64

R/W

D63

R/W

D62

R/W

D61

R/W

D60

R/W

• Port 7 direction register (DDR7)

. . . . . . . . . . . .

(DDR6)

Address

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

D70

bit 0

Initial value

B

- - - 00000

—

D74

R/W

D73

R/W

D72

R/W

D71

R/W

000017^H

—

R/W

• Port 8 direction register (DDR8)

. . . . . . . . . . . .

Address bit 15

000018^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

D80

R/W

Initial value

00000000

(DDR9)

B

D87

R/W

D86

R/W

D85

R/W

D84

R/W

D83

R/W

D82

R/W

D81

R/W

• Port 9 direction register (DDR9)

. . . . . . . . . . . .

(DDR8)

Address

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

D90

bit 0

Initial value

B

000019^H

00000000

D97

R/W

D96

R/W

D95

R/W

D94

R/W

D93

R/W

D92

R/W

D91

R/W

• Port A direction register (DDRA)

. . . . . . . . . . . .

Address bit 15

00001A^H

bit 8 bit 7

DA7

bit 6

bit 5

bit 4

bit 3

bit 2

DA2

R/W

bit 1

DA1

R/W

bit 0

DA0

Initial value

00000000

(DDRB)

DA6

R/W

DA5

R/W

DA4

R/W

DA3

R/W

B

R/W

• Port B direction register (DDRB)

. . . . . . . . . . . .

bit 15

bit 8 bit 7

DB7

bit 6

DB6

R/W

bit 5

DB5

R/W

bit 4

DB4

R/W

bit 3

DB3

R/W

bit 2

DB2

R/W

bit 1

DB1

R/W

bit 0

DB0

R/W

Address

00001B^H

Initial value

00000000

(DDRA)

B

R/W

• Port C direction register (DDRC)

. . . . . . . . . . . .

Address bit 15

00001C^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

(ODR4)

B

—

DC3

R/W

DC2

R/W

DC1

R/W

DC0

R/W

00000000

• Port 4 output pin register (ODR4)

. . . . . . . . . . . .

Address bit 15

00001D^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

00000000

(DDRC)

B

OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40

R/W

• Port 0 input pull-up resistor setup register (RDR0)

. . . . . . . . . . . .

Address bit 15

00008C^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

00000000

(RDR1)

B

RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00

R/W R/W R/W R/W R/W R/W R/W R/W

(Continued)

35

MB90570 Series

(Continued)

• Port 1 input pull-up resistor setup register (RDR1)

. . . . . . . . . . . .

(RDR0)

Address

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10

R/W R/W R/W R/W R/W R/W R/W R/W

bit 9

bit 8 bit 7

bit 0

Initial value

B

00000000

00008D^H

• Port 6 input pull-up resistor setup register (RDR6)

. . . . . . . . . . . .

Address bit 15

00008E^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

00000000

(Disabled)

B

RD67 RD66 RD65 RD64 RD63 RD62 RD61 RD60

R/W

• Analog input enable register (ADER)

. . . . . . . . . . . .

bit 15

bit 8 bit 7

bit 6

ADE6

R/W

bit 5

ADE5

R/W

bit 4

bit 3

bit 2

ADE2

R/W

bit 1

ADE1

R/W

bit 0

Address

Initial value

ADE0

B

(Disabled)

11111111

ADE4 ADE3

R/W R/W

00001E^H

ADE7

R/W

R/W : Readable and writable

— : Reserved

X : Undefined

36

MB90570 Series

(3) Block Diagram

• Input/output port

PDR (port data register)

PDR read

Output latch

P-ch

PDR write

DDR (port direction register)

N-ch

Direction latch

DDR write

Standby control (SPL=1)

DDR read

Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode

• Output pin register (ODR)

To resource input

From resource output

Resource output enable

PDR (port data register)

PDR read

Output latch

P-ch

N-ch

PDR write

DDR (port direction register)

Direction latch

DDR write

Standby control

(SPL=1)

DDR read

ODR (output pin register)

ODR latch

ODR write

ODR read

Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode

37

MB90570 Series

• Input pull-up resistor setup register (RDR)

To resource input

PDR (port data register)

Pull-up resistor

About 5.0 kΩ

(5.0 V)

PDR read

Output latch

PDR write

P-ch

N-ch

P-ch

DDR (port direction register)

Direction latch

DDR write

Standby control

(SPL=1)

DDR read

RDR latch

RDR write

RDR

(input pull-up resistor setup register)

RDR read

Standby control: Stop, timebase timer mode and SPL=1

• Analog input enable register (ADER)

ADER (analog input enable register)

ADER read

ADER latch

To analog input

ADER write

PDR (port data register)

RMW

(read-modify-write

type instruction)

PDR read

Output latch

PDR write

P-ch

N-ch

DDR (port direction register)

Direction latch

DDR write

Standby control

(SPL=1)

DDR read

Standby control: Stop, timebase timer mode and SPL=1

38

MB90570 Series

2. Timebase Timer

The timebase timer is a 18-bit free run counter (timebase counter) for counting up in synchronization to the

internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from

four types of 2¹²/HCLK, 2¹⁴/HCLK, 2¹⁶/HCLK, and 2¹⁹/HCLK.

The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation

stabilization time or the watchdog timer etc.

(1) Register Configuration

• Timebase timer control register (TBTC)

. . . . . . . . . . . .

Address

0000A9^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

TBIE TBOF TBR TBC1 TBC0

R/W R/W R/W R/W

bit 0

Initial value

1--00100^B

(WDTC)

—

RESV

—

W

R/W : Readable and writable

W : Write only

— : Unused

RESV: Reserved bit

(2) Block Diagram

To watchdog timer

To 8/16-bit PPG timer

Timebase timer counter

× 2¹× 2²× 2³

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

. . . . . .

Divided-by-2

of HCLK

OF

To oscillation stabilization

time selector of clock control block

Power-on reset

Counter

clear circuit

Interval

timer selector

Start stop mode

CKSCR: MCS = 1→0*¹

Set TBOF

Clear TBOF

Timebase timer control register

(TBTC)

RESV

TBIE TBOF TBR TBC1 TBC0

—

Timebase timer

interrupt signal

#34*²

OF: Overflow

HCLK: Oscillation clock

*1: Switch machine clock from oscillation clock to PLL clock

*2: Interrupt signal

39

MB90570 Series

3. Watchdog Timer

The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when

the counter is not cleared for a preset period of time.

(1) Register Configuration

• Watchdog timer control register (WDTC)

. . . . . . . . . . . .

(TBTC)

Address bit 15

0000A8^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

WT1

W

bit 0

WT0

W

Initial value

B

PONR STBR WRST ERST SRST WTE

XXXXXXXX

R

W

R : Read only

W: Write only

X : Indeterminate

(2) Block Diagram

Watchdog timer control register (WDTC)

PONR STBR WRST ERST SRST WTE WT1 WT0

2

Watchdog timer

CLR and start

Overflow

CLR

Start sleep mode

Start hold status

Start stop mode

Watchdog timer

reset generation

circuit

Counter clear

control circuit

Count clock

selector

2-bit

counter

To internal reset

generation circuit

CLR

4

Clear

(Timebase timer counter)

Divided-by-2

of HCLK

× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

× 2⁸

× 2¹× 2²

. . .

HCLK: Oscillation clock

40

MB90570 Series

4. 8/16-bit PPG Timer

The 8/16-bit PPG timer is a 2-CH reload timer module for outputting pulse having given frequencies/duty ratios.

The two modules performs the following operation by combining functions.

• 8-bit PPG output 2-CH independent operation mode

This is a mode for operating independent 2-CH 8-bit PPG timer, in which PPG0 and PPG1 pins correspond

to outputs from PPG0 and PPG1 respectively.

• 16-bit PPG timer output operation mode

In this mode, PPG0 and PPG1 are combined to be operated as a 1-CH 8/16-bit PPG timer operating as a 16-

bit timer. Because PPG0 and PPG1 outputs are reversed by an underflow from PPG1 outputting the same

output pulses from PPG0 and PPG1 pins.

• 8 + 8-bit PPG timer output operation mode

In this mode, PPG0 is operated as an 8-bit communications prescaler, in which an underflow output of PPG0

is used as a clock source for PPG1. A toggle output of PPG0 and PPG output of PPG1 are output from PPG0

and PPG1 respectively.

• PPG output operation

A pulse wave with any period/duty ratio is output. The module can also be used as a D/A converter with an

external add-on circuit.

41

MB90570 Series

(1) Register Configuration

• PPG0 operating mode control register ch.0 (PPGC0)

. . . . . . . . . . . .

Address bit 15

000044^H

bit 8 bit 7

PEN0

bit 6

—

bit 5

PE00 PIE0 PUF0

R/W R/W R/W

bit 4

bit 3

bit 2

—

bit 1

—

bit 0

RESV

—

Initial value

0X000XX1

(PPGC1)

B

R/W

—

• PPG1 operating mode control register ch.1 (PPGC1)

. . . . . . . . . . . .

(PPGC0)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

MD0 RESV

R/W R/W

bit 8 bit 7

bit 0

Address

000045^H

Initial value

B

0X000001

PEN1

R/W

—

PEI0

R/W

PIE1 PUF1 MD1

R/W R/W R/W

R/W

• PPG0, 1 output control register ch.0, ch.1(PPGOE)

. . . . . . . . . . . .

Address bit 15

000046^H

bit 8 bit 7

PCS2 PCS1 PCS0 PCM2 PCM1 PCM0

R/W R/W R/W R/W R/W R/W

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

—

bit 0

Initial value

000000XX

(Disabled)

—

B

—

• PPG0 reload register H ch.0 (PRLH0)

. . . . . . . . . . . .

(PRLL0)

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

R/W

bit 0

Initial value

B

XXXXXXXX

000041^H

R/W

• PPG1 reload register H ch.1 (PRLH1)

. . . . . . . . . . . .

(PRLL1)

Address

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

R/W

bit 8 bit 7

R/W

Initial value

B

000043^H

XXXXXXXX

R/W

• PPG0 reload register L ch.0 (PRLL0)

Address

. . . . . . . . . . . .

(PRLH0)

bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

000040^H

B

XXXXXXXX

Initial value

R/W

bit 6

R/W

bit 5

R/W

bit 4

R/W

bit 3

R/W

bit 2

R/W

bit 1

R/W

• PPG1 reload register L ch.1 (PRLL1)

Address

. . . . . . . . . . . .

bit 15

bit 8 bit 7

bit 0

R/W

000042^H

B

XXXXXXXX

(PRLH1)

R/W

R/W : Readable and writable

— : Reserved

X

: Undefined

RESV: Reserved bit

42

MB90570 Series

(2) Block Diagram

• Block diagram of 8/16-bit PPG timer (ch.0)

Data bus for “H” digits

Data bus for “L” digits

PPG0 output

control register

ch.0 (PPGOE0)

PPG0 reload

register

PPG0 operating mode

control register ch.0 (PPGC0)

PEN0

—

PE00 PIE0 PUF0

—

RESV PCM2 PCM1 PCM0

PRLH0

PRLL0

R

Temporary buffer

(PRLBH0)

Interrupt request

#26*

S

Q

2

Mode control signal

Select signal

Reload register

(L/H selector)

PPG1 underflow

PPG0 underflow

(to PPG1)

Count value

Re-load

Clear

Pulse selector

Underflow

Down counter

(PCNT0)

CLK

PPG0

output latch

Reverse

P46/PPG0

PPG output

control circuit

Timebase timer output (512/HCLK)

Peripheral clock (16/φ)

Peripheral clock (8/φ)

Count

clock

selector

Peripheral clock (4/φ)

3

Peripheral clock (2/φ)

Peripheral clock (1/φ)

Select signal

*

: Interrupt number

HCLK: Oscillation clock

: Machine clock frequency

φ

43

MB90570 Series

• Block diagram of 8/16-bit PPG timer (ch.1)

Data bus for “H” digits

Data bus for “L” digits

PPG1 output control

register ch.1 (PPGOE1)

PPG1 reload

register

PPG1 operating mode

control register ch.1 (PPGC1)

PCS1 PCS0

PCS2

RESV

PEI0 PIE1 PUF1 MD1 MD0

PEN1

—

PRLL1

PRLH1

Operating mode

control signal

2

Temporary buffer

(PRLBH1)

R

Interrupt request

#28*

Q

S

Reload selector

(L/H selector)

Select signal

Count value

Re-load

Clear

Underflow

PPG1

output latch

Down counter

(PCNT1)

Reverse

P47/PPG1

CLK

PPG1 underflow

(to PPG0)

PPG output control circuit

MD0

PPG0 underflow

Timebase timer output (512/HCLK)

Peripheral clock (16/φ)

Peripheral clock (8/φ)

Peripheral clock (4/φ)

Peripheral clock (2/φ)

Peripheral clock (1/φ)

Count clock selector

Select signal

*

: Interrupt number

HCLK: Oscillation clock

: Machine clock frequency

φ

44

MB90570 Series

5. 16-bit I/O timer

The 16-bit I/O timer module consists of one 16-bit free run timer, two input capture circuits, and four output

comparators. This module allows two independent waveforms to be output on the basis of the 16-bit free run

timer. Input pulse width and external clock periods can, therefore, be measured.

• Block Diagram

Internal data bus

16-bit

free run timer

Dedicated

bus

Dedicated

bus

Input capture

Output compare

45

MB90570 Series

(1) 16-bit free run Timer

The 16-bit free run timer consists of a 16-bit up counter, a control register, and a communications prescaler

register. The value output from the timer counter is used as basic timer (base timer) for input capture (ICU) and

output compare (OCU).

• A counter operation clock can be selected from four internal clocks (φ/4, φ/16, φ/32 and φ/64).

• An interrupt can be generated by overflow of counter value or compare match with OCU compare register 0.

(Compare match requires mode setup.)

• The counter value can be initialized to “0000^H” by a reset, software clear or compare match with OCU compare

register 0.

• Register Configuration

• free run timer data register (TCDT)

Address

bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Initial value

00000000^B

000056^H

000057^H

T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

• free run timer control status register (TCCS)

. . . . . . . . . . . . .

bit 15

bit 8 bit 7

RESV

bit 6

IVF

bit 5

IVFE STOP MODE CLR CLK1 CLK0

R/W R/W R/W R/W R/W R/W

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

00000000^B

Address

000058^H

(Disabled)

R/W

R/W : Readable and writable

RESV: Reserved bit

• Block Diagram

Count value output

to ICO and OCU

free run timer data register (TCDT)

16-bit counter

OF

CLK

STOP

CLR

Communications

prescaler register

φ

OCU compare register ch.0

match signal

2

free run timer

control status register

(TCCS)

RESV IVF IVFE STOP MODE CLR CLK1 CLK0

16-bit free run timer

interrupt request

#20*

* : Interrupt number

φ : Machine clock frequency

OF: Overflow

46

MB90570 Series

(2) Input Capture (ICU)

The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of

current counter value of the 16-bit free run timer to the ICU data register (IPCP) upon an input of a trigger edge

to the external pin.

There are four sets (four channels) of the input capture external pins and ICU data registers, enabling

measurements of maximum of four events.

• The input capture has two sets of external input pins (IN0, IN1) and ICU registers (IPCP), enabling

measurements of maximum of four events.

• A trigger edge direction can be selected from rising/falling/both edges.

• The input capture can be set to generate an interrupt request at the storage timing of the counter value of the

16-bit free run timer to the ICU data register (IPCP).

• The input compare conforms to the extended intelligent I/O service (EI²OS).

• The input capture (ICU) function is suited for measurements of intervals (frequencies) and pulse widths.

• Register Configuration

• ICU data register ch.0, ch.1 (IPCP0, IPCP1)

. . . . . . . . . . . . .

Address

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

IPCP0(high): 000051^H

IPCP1(high): 000053^H

(IPCP0 low, IPCP1 low)

CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08

XXXXXXXX^B

R

. . . . . . . . . . . .

Address

IPCP0(low): 000050^H

IPCP1(low): 000052^H

bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

(IPCP0 high, IPCP1 high)

CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00

XXXXXXXX^B

R

Note: This register holds a 16-bit free run timer value when the valid edge of the corresponding external pin input waveform is

detected. (You can word-access this register, but you cannot program it.)

• ICU control status register (ICS01)

. . . . . . . . . . . .

Address

bit 15

bit 8 bit 7

ICP1 ICP0

R/W R/W

bit 6

bit 5

ICE1 ICE0 EG11 EG10 EG01 EG00

R/W R/W R/W R/W R/W R/W

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

00000000^B

(Disabled)

000054^H

R/W : Readable and writable

R

X

: Read only

: Undefined

47

MB90570 Series

• Block Diagram

Internal data bus

Latch

signal

Output latch

ICU data register (IPCP)

16

Edge detection circuit

P56/IN0

Data latch signal

2

IPCP0H

IPCP1H

IPCP0L

16-bit free run

timer

P57/IN1

16

IPCP1L

2

ICU control status register (ICS01)

ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00

Interrupt request

#12*

Interrupt request

#14*

* : Interrupt number

48

MB90570 Series

(3) Output Compare (OCU)

The output compare (OCU) is two sets of compare units consisting of four-channel OCU compare registers, a

comparator and a control register.

An interrupt request can be generated for each channel upon a match detection by performing time-division

comparison between the OCU compare data register setting value and the counter value of the 16-bit free run

timer.

The OUT pin can be used as a waveform output pin for reversing output upon a match detection or a general-

purpose output port for directly outputting the setting value of the CMOD bit.

• Register Configuration

• OCU control status register ch.1, ch.3 (OCS1, OCS3)

. . . . . . . . . . . . .

Address

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

bit 0

Initial value

000063^H

000065^H

B

—

CMOD OTE1 OTE0 OTD1 OTD0

R/W R/W R/W R/W R/W

(OCS0, OCS2)

- - -00000

• OCU control status register ch.0, ch.2 (OCS0, OCS2)

. . . . . . . . . . . .

bit 15

Initial value

bit 8 bit 7

ICP1

bit 6

ICP0 ICE1

R/W R/W

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Address

000062^H

000064^H

B

(OCS1, OCS3)

ICE0

R/W

—

CST1 CST0

0000- -00

R/W

• OCU compare register ch.0 to ch.3 (OCCP0 to OCCP3)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

Initial value

Address

OCCP0 (high order address): 00005B^H

OCCP1 (high order address): 00005D^H

OCCP2 (high order address): 00005F^H

OCCP3 (high order address): 000061^H

C15

R/W

C14

R/W

C13

R/W

C12

R/W

C11

R/W

C10

R/W

C09

R/W

C08

R/W

B

XXXXXXXX

Address

OCCP0 (low order address): 00005A^H

OCCP1 (low order address): 00005C^H

OCCP2 (low order address): 00005E^H

OCCP3 (low order address): 000060^H

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

C00

R/W

Initial value

B

XXXXXXXX

C07

R/W

C06

R/W

C05

R/W

C04

R/W

C03

R/W

C02

R/W

C01

R/W

R/W : Readable and writable

— : Reserved

X : Undefined

49

MB90570 Series

• Block diagram

#16*

#15*

Output compare

interrupt request

OCU control

status register ch.0, ch.1 (OCS0, OCS1)

—

CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0

—

CST1 CST0

2

16-bit free run timer

Compare control circuit 3

OCU compare register ch.3

Compare control circuit 2

OCU compare register ch.2

Compare control circuit 1

OCCP3

OCCP2

P67/OUT3

Output

control circuit 3

P66/OUT2

Output

control circuit 2

P65/OUT1

Output

OCCP1

OCCP0

control circuit 1

OCU compare register ch.1

Compare control circuit 0

P64/OUT0

Output

control circuit 0

OCU compare register ch.0

2

OCU control status register

ch.2, ch.3 (OCS2, OCS3)

—

CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0

—

CST1 CST0

#18*

#17*

Output compare

interrupt request

* : Interrupt number

50

MB90570 Series

6. 8/16-bit up/down counter/timer

The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit

reload compare registers, and their controllers.

(1) Register configuration

• Up/down count register 0 (UDCR0)

. . . . . . . . . . . .

bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Address

Initial value

00000000

B

000070^H

(UDCR1)

D07

R

D06

R

D05

R

D04

R

D03

R

D02

R

D01

R

D00

R

• Up/down count register 1 (UDCR1)

. . . . . . . . . . . . .

(UDCR0)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

bit 0

Initial value

00000000

Address

D17

D16

D15

D14

R

D13

R

D12

R

D11

R

D10

R

000071^H

B

R

• Reload compare register 0 (RCR0)

. . . . . . . . . . . .

bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

D02

W

bit 1

D01

W

bit 0

D00

Address

Initial value

00000000

D07

W

D06

W

D05

W

D04

W

D03

W

(RCR1)

B

000072^H

W

• Reload compare register 1 (RCR1)

. . . . . . . . . . . . .

(RCR0)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

D10

bit 0

Initial value

00000000

Address

D17

D16

D15

D14

D13

W

D12

W

D11

W

000073^H

B

W

• Counter status register 0, 1 (CSR0, CSR1)

. . . . . . . . . . . .

bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Address

Initial value

00000000

000074^H

000078^H

(Reserved area)

CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0

R/W

bit 5

R/W

bit 4

R/W

bit 3

R/W

bit 2

R

• Counter control register 0, 1 (CCRL0, CCRL1)

. . . . . . . . . . . .

bit 15

bit 8 bit 7

bit 6

bit 1

bit 0

Address

Initial value

- 0000000

000076^H

00007A^H

(CCRH0, CCRH1)

CTUT UCRE RLDE UDCC CGSC CGE1 CGE0

R/W R/W R/W R/W R/W R/W R/W

—

• Counter control register 0 (CCRH0)

. . . . . . . . . . . . .

(CCRL0)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

bit 0

Initial value

00000000

Address

000077^H

B

M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0

R/W

• Counter control register 1 (CCRH1)

. . . . . . . . . . . . .

(CCRL1)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

Initial value

- 0000000

Address

CDCF CFIE CLKS CMS1 CMS0 CES1 CES0

R/W R/W R/W R/W R/W R/W R/W

—

00007B^H

B

R/W : Readable and writable

R

: Read only

W : Write only

— : Undefined

51

MB90570 Series

(2) Block Diagram

• Block diagram of 8/16-bit up/down counter/timer 0

Internal data bus

RCR0

Reload compare register 0

Re-load

control

circuit

UDCR0

CARRY/

BORRW

(to channel 1)

Up/down count register 0

Counter control

register 0 (CCRL0)

UCRE RLDE UDCC CGSC CGE1 CGE0

— ^CTUT

Compare

control circuit

Counter clear

circuit

PA2/ZIN0

Edge/level

detection circuit

Count clock

Counter status

register 0 (CSR0)

φ

Prescaler

UP/down count

clock selector

PA0/AIN0/IRQ6

CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0

PA1/BIN0

Interrupt request

#29*

Interrupt request

#30*

CDCF CFIE CLKS CMS1 CMS0 CES1 CES0

M16E

Counter control register 0 (CCRH0)

M16E

(to channel 1)

* : Interrupt number

φ: Machine clock frequency

52

MB90570 Series

• Block diagram of 8/16-bit up/down counter/timer 1

Internal data bus

RCR1

Reload compare register 1

Re-load

control

circuit

UDCR1

Up/down count register 1

Counter control

register 1 (CCRL1)

CTUT UCRE RLDE UDCC CGSC CGE1 CGE0

—

Compare

control circuit

PA5/ZIN1

Counter clear

circuit

Edge/level

detection circuit

CARRY/BORRW

(from channel 0)

Count clock

Counter status

register 1 (CSR1)

φ

Prescaler

PA3/AIN1/IRQ7

UP/down count

clock selector

CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0

PA4/BIN1

Interrupt request

#31*

M16E

(from channel 1)

Interrupt request

#32*

CDCF CFIE CLKS CMS1 CMS0 CES1 CES0

—

Counter control register 1 (CCRH1)

* : Interrupt number

φ: Machine clock frequency

53

MB90570 Series

7. Extended I/O serial interface

The extended I/O serial interface transfers data using a clock synchronization system having an 8-bit x 1 channel

configuration.

For data transfer, you can select LSB first/MSB first.

(1) Register Configuration

• Serial mode control upper status register 0 to 2 (SMCSH0 to SMCSH2)

. . . . . . . . . . . . .

(SMCSL)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

BUSY STOP STRT

R/W R/W

bit 0

Initial value

00000010

Address

SMCSH0: 000049^H

SMCSH1: 00004D^H

SMCSH2: 00007D^H

B

SMD2 SMD1 SMD0 SIE

R/W R/W R/W R/W

SIR

R/W

R

• Serial mode control lower status register 0 to 2 (SMCSL0 to SMCSL2)

. . . . . . . . . . . .

bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Address

SMCSL0: 000048^H

SMCSL1: 00004C^H

SMCSL2: 00007C^H

Initial value

- - - - 0000

(SMCSH)

MODE BDS

SOE SCOE

B

—

R/W

• Serial data register 0 _.to_{. .}2_{. . .}(_.S_.D_{. .}R_{. .}0 to SDR2)

bit 15

bit 8 bit 7

D7

bit 6

D6

bit 5

D5

bit 4

D4

bit 3

D3

bit 2

D2

bit 1

D1

bit 0

D0

Address

SDR0: 00004A^H

SDR1: 00004E^H

SDR2: 00007E^H

Initial value

XXXXXXXX

(Disabled)

B

R/W

R/W : Readable and writable

: Read only

— : Reserved

: Undefined

R

X

54

MB90570 Series

(2) Block Diagram

Internal data bus

D7 to D0 (LSB first)

(MSB first) D0 to D7

P40/SIN0

Transfer direction selection

Read

Write

Serial data register

(SDR)

P43/SIN1

P41/SOT0

P50/SIN2

P44/SOT1

P51/SOT2

P45/SCK1

Control circuit

Shift clock counter

P52/SCK2

Internal clock

P42/SCK0

2

1

0

MODE

SCOE

SMD2 SMD1 SMD0

BUSY STOP STRT

SIE SIR

—

BDS SOE

Serial mode control

status register (SMCS)

Interrupt request

#19 (SMCS0)*

#21 (SMCS1)*

#23 (SMCS2)*

*: Interrupt number

55

MB90570 Series

8. I²C Interface

The I²C interface is a serial I/O port supporting Inter IC BUS operating as master/slave devices on I²C bus.

The MB90570/A series contains one channel of an I²C interface, having the following features.

• Master/slave transmission/reception

• Arbitration function

• Clock synchronization function

• Slave address/general call address detection function

• Transmission direction detection function

• Repeated generation function start condition and detection function

• Bus error detection function

(1) Register Configuration

• I²C bus status register (IBSR)

. . . . . . . . . . . .

Address bit 15

000068^H

Initial value

00000000^B

bit 8 bit 7

BB

bit 6

bit 5

AL

bit 4

LRB

bit 3

TRX

bit 2

AAS

bit 1

bit 0

(IBCR)

RSC

GCA FBT

R

• I²C bus control register (IBCR)

. . . . . . . . . . . .

Address

000069^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

INT

bit 0

Initial value

00000000^B

(IBSR)

BER BEIE SCC

R/W R/W R/W

MSS

R/W

ACK GCAA INTE

R/W R/W R/W

R/W

• I²C bus clock control register (ICCR)

. . . . . . . . . . . .

Address bit 15

00006A^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

CS2

R/W

bit 1

CS1

R/W

bit 0

CS0

R/W

Initial value

--0XXXXX^B

(IADR)

—

EN

CS4

R/W

CS3

R/W

• I²C bus address register (IADR)

. . . . . . . . . . . .

Address

00006B^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

A0

bit 0

Initial value

-XXXXXXX^B

(ICCR)

—

A6

A5

A4

A3

A2

A1

R/W

• I²C bus data register (IDAR)

. . . . . . . . . . . .

Address bit 15

00006C^H

bit 8 bit 7

D7

bit 6

bit 5

bit 4

bit 3

bit 2

D2

bit 1

D1

bit 0

D0

R/W

Initial value

(Disabled)

D6

D5

D4

D3

XXXXXXXX^B

R/W

R/W : Readable and writable

R

—

X

: Read only

: Reserved

: Indeterminate

56

MB90570 Series

(2) Block Diagram

Internal data bus

I²C bus status register

I²C bus control register

(IBCR)

(IBSR)

BER BEIE SCC MSS ACK GCAA INTE INT

BB RSC AL LRB TRX AAS GCA FBT

Number of

interrupt

Start stop condition

generation circuit

Start stop condition

detection circuit

request

generated

Interrupt request signal

#36*

SDA line

SCL line

PA6/SDA

I²C enable

PA7/SCL

IDAR register

Arbitration lost

detection circuit

Slave address

comparison circuit

IADR register

Clock control block

Sync

Clock

4

Count

clock

selector 1

8

Count

clock

selector 2

Shift clock

generation

circuit

divider1

(1/5 to

1/8)

Clock

divider 2

φ

I²C enable

—

EN CS4 CS3 CS2 CS1 CS0

I²C bus clock control register

(ICCR)

φ: Machine clock frequency

* : Interrupt number

57

MB90570 Series

9. UART0 (SCI), UART1 (SCI)

UART0 (SCI) and UART1 (SCI) are general-purpose serial data communication interfaces for performing

synchronous or asynchronous communication (start-stop synchronization system).

• Data buffer: Full-duplex double buffer

• Transfer mode: Clock synchronized (with start and stop bit)

Clock asynchronized (start-stop synchronization system)

• Baud rate: Embedded dedicated baud rate generator

External clock input possible

Internal clock (a clock supplied from 16-bit reload timer 0 can be used.)

Internal machine clock

For 6 MHz, 8 MHz, 10 MHz

12 MHz and 16 MHz

• Data length: 7 bit to 9 bit selective (without a parity bit)

6 bit to 8 bit selective (with a parity bit)

Asynchronization 9615 bps/31250 bps/4808 bps/2404 bps/1202 bps

CLK synchronization 1 Mbps/500 kbps/250 kbps/125 kbps/62.5 kbps

}

• Signal format: NRZ (Non Return to Zero) system

• Reception error detection: Framing error

Overrun error

Parity error (multi-processor mode is supported, enabling setup of any baud rate

by an external clock.)

• Interrupt request: Receive interrupt (receive complete, receive error detection)

Transmit interrupt (transmission complete)

Transmit/receive conforms to extended intelligent I/O service (EI²OS)

58

MB90570 Series

(1) Register Configuration

• Serial control register 0,1 (SCR0, SCR1)

. . . . . . . . . . . . .

bit 0

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

TXE

Address

000021^H

000025^H

Initial value

B

PEN

R/W

P

SBL

R/W

CL

A/D

REC

W

RXE

R/W

00000100

(SMR0, SMR1)

R/W

• Serial mode register 0, 1 (SMR0, SMR1)

. . . . . . . . . . . .

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

bit 15

bit 8

Address

000020^H

000024^H

Initial value

B

(SCR0, SCR1)

MD1

R/W

MD0

R/W

CS2

R/W

CS1

R/W

CS0 RESV SCKE SOE

R/W R/W R/W R/W

00000000

• Serial status register 0,1 (SSR0, SSR1)

. . . . . . . . . . . . .

bit 0

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

Address

000023^H

000027^H

Initial value

B

00001 - 00

PE

R

ORE

R

FRE RDRF TRDE

—

RIE

TIE

(SIDR0, SIDR1/SODR0,SODR1)

R

R/W

• Serial input data register 0,1 (SIDR0, SIDR1)

. . . . . . . . . . . .

bit 15

bit 7

D7

R

bit 6

bit 5

bit 4

bit 3

bit 2

D2

R

bit 1

D1

R

bit 0

D0

R

bit 8

Address

000022^H

000026^H

Initial value

B

XXXXXXXX

(SSR0, SSR1)

D6

R

D5

R

D4

R

D3

R

• Serial output data register 0,1 (SODR0, SODR1)

. . . . . . . . . . . .

bit 7

D7

W

bit 6

D6

W

bit 5

D5

W

bit 4

D4

W

bit 3

D3

W

bit 2

D2

W

bit 1

D1

W

bit 0

D0

W

Address

000022^H

000026^H

bit 15

bit 8

Initial value

B

XXXXXXXX

(SSR0, SSR1)

• Communications prescaler control register 0,1 (CDCR0, CDCR1)

. . . . . . . . . . . .

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

bit 15

bit 8

Address

000028^H

00002A^H

Initial value

B

0 - - - 1111

(Disabled)

MD

—

DIV3 DIV2

R/W R/W

DIV1 DIV0

R/W R/W

R/W

—

R/W: Readable and writable

R : Read only

W : Write only

— : Reserved

X : Undefined

RESV: Reserved bit

59

MB90570 Series

(2) Block Diagram

• UART0 (SCI)

Control bus

Receive

interrupt signal

#39*

Dedicated baud

rate generator

Transmit

clock

Transmit

interrupt signal

#40*

Clock

8/16-bit PPG

timer 1 (upper)

External clock

selector

Receive

clock

Receive

control circuit

Transmit

control circuit

P42/SCK0

Start bit

detection circuit

Transmit start

circuit

Receive bit

counter

Transmit bit

counter

Receive parity

counter

Transmit parity

counter

P41/SOT0

Shift register for

transmission

Shift register for

reception

P40/SIN0

Reception

complete

Start transmission

SIDR0

SODR0

Receive condition

decision circuit

To I²C reception

error generation

signal (to CPU)

Internal data bus

PE

ORE

FRE

RDRF

TDRE

PEN

P

SBL

CL

A/D

REC

RXE

TXE

MD1

MD0

CS2

CS1

CS0

SMR0

register

SCR0

register

SSR0

register

RIE

TIE

SCKE

SOE

* : Interrupt number

60

MB90570 Series

• UART1 (SCI)

Control bus

Receive

interrupt signal

#37*

Dedicated baud

Transmit

clock

rate generator

Transmit

interrupt signal

#38*

Clock

selector

8/16-bit PPG

timer 1 (upper)

Receive

clock

Receive

control circuit

Transmit

control circuit

P45/SCK1

Start bit

detection circuit

Transmit start

circuit

Receive bit

counter

Transmit bit

counter

Receive parity

counter

Transmit parity

counter

P44/SOT1

Shift register for

transmission

Shift register for

reception

P43/SIN1

Reception

complete

Start transmission

SIDR1

SODR1

Receive condition

decision circuit

To EI²OS reception

error generation

signal (to CPU)

Internal data bus

PE

ORE

FRE

RDRF

TDRE

PEN

P

SBL

CL

A/D

REC

RXE

TXE

MD1

MD0

CS2

CS1

CS0

SMR1

register

SCR1

register

SSR1

register

RIE

TIE

SCKE

SOE

* : Interrupt number

61

MB90570 Series

10. DTP/External Interrupt Circuit

DTP (Data Transfer Peripheral), which is located between the peripheral circuit outside the device and the

F²MC-16LX CPU, receives an interrupt request or DMA request generated by the external peripheral circuit*

fortransmissiontotheF²MC-16LXCPU. DTPisusedtoactivatetheintelligentI/Oserviceorinterruptprocessing.

As request levels for IRQ2 to IRQ7, two types of “H” and “L” can be selected for the intelligent I/O service. Rising

and falling edges as well as “H” and “L” can be selected for an external interrupt request. For IRQ0 and IRQ1,

a request by a level cannot be entered, but both edges can be entered.

* : The external peripheral circuit is connected outside the MB90570/A series device.

Note: IRQ0 and IRQ1 cannot be used for the intelligent I/O service and return from an interrupt.

(1) Register Configuration

• DTP/interrupt factor register (EIRR)

. . . . . . . . . . . .

(ENIR)

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

ER1

R/W

bit 8 bit 7

ER0

bit 0

Initial value

ER7

R/W

ER6

R/W

ER5

R/W

ER4

R/W

ER3

R/W

ER2

R/W

000031^H

B

XXXXXXXX

R/W

• DTP/interrupt enable register (ENIR)

. . . . . . . . . . . .

Address bit 15

000030^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

EN2

R/W

bit 1

EN1

R/W

bit 0

EN0

Initial value

B

(EIRR)

EN7

R/W

EN6

R/W

EN5

R/W

EN4

R/W

EN3

R/W

00000000

R/W

• Request level setting register (ELVR)

. . . . . . . . . . . .

Address bit 15

Low order address 000032^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

B

(ELVR upper)

LB3

R/W

LA3

R/W

LB2

R/W

LA2

R/W

LB1

R/W

LA1

R/W

LB0

R/W

LA0

R/W

00000000

. . . . . . . . . . . .

(ELVR lower)

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

LA4

bit 0

Initial value

LB7

R/W

LA7

R/W

LB6

R/W

LA6

R/W

LB5

R/W

LA5

R/W

LB4

R/W

High order address 000033^H

B

00000000

R/W

R/W: Readable and writable

X : Undefined

62

MB90570 Series

(2) Block Diagram

Internal data bus

63

MB90570 Series

11. Delayed Interrupt Generation Module

The delayed interrupt generation module generates interrupts for switching tasks for development on a real-

timeoperatingsystem(REALOSseries). Themodulecanbeusedtogeneratesoftwarewisegenerateshardware

interrupt requests to the CPU and cancel the interrupts.

This module does not conform to the extended intelligent I/O service (EI²OS).

(1) Register Configuration

• Delayed interrupt factor generation/cancellation register (DIRR)

. . . . . . . . . . . .

(PACSR)

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

R0

bit 0

Initial value

00009F^H

—

B

- - - - - - - 0

—

R/W

Note: Upon a reset, an interrupt is canceled.

R/W: Readable and writable

— : Reserved

The DIRR is the register used to control delay interrupt request generation/cancellation. Programming this

register with “1” generates a delay interrupt request. Programming this register with “0” cancels a delay interrupt

request. Upon a reset, an interrupt is canceled. The reserved bit area can be programmed with either “0” or “1”.

For future extension, however, it is recommended that bit set and clear instructions be used to access this

register.

(2) Block Diagram

Internal data bus

—

R0

S factor

R latch

Interrupt request signal

#42*

Delayed interrupt factor generation/

cancellation register (DIRR)

*: Interrupt number

64

MB90570 Series

12. 8/10-bit A/D Converter

The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input

voltage) to digital values (A/D conversion) and has the following features.

• Minimum conversion time: 26.3 µs (at machine clock of 16 MHz, including sampling time)

• Minimum sampling time: 4 µs/256 µs (at machine clock of 16 MHz)

• Compare time: 176/352 machine cycles per channel (176 machine cycles are used for a machine clock below

8 MHz.)

• Conversion method: RC successive approximation method with a sample and hold circuit.

• 8-bit or 10-bit resolution

• Analog input pins: Selectable from eight channels by software

Single conversion mode: Selects and converts one channel.

Scan conversion mode:Converts two or more successive channels. Up to eight channels can be programmed.

Continuous conversion mode: Repeatedly converts specified channels.

Stop conversion mode:Stops conversion after completing a conversion for one channel and wait for the next

activation (conversion can be started synchronously.)

• Interrupt requests can be generated and the extended intelligent I/O service (EI²OS) can be started after the

end of A/D conversion. Furthermore, A/D conversion result data can be transferred to the memory, enabling

efficient continuous processing.

• When interrupts are enabled, there is no loss of data even in continuous operations because the conversion

data protection function is in effect.

• Starting factors for conversion: Selected from software activation, and external trigger (falling edge).

65

MB90570 Series

(1) Register Configuration

• A/D control status register upper digits (ADCS2)

. . . . . . . . . . . .

(ADCS1)

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

000037^H

B

BUSY INT

R/W R/W

INTE PAUS STS1 STS0 STRT RESV

R/W R/W R/W R/W R/W

00000000

W

• A/D control status register lower digits (ADCS1)

. . . . . . . . . . . .

Address bit 15

bit 8 bit 7

bit 6

MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0

R/W R/W R/W R/W R/W R/W R/W

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

000036^H

(ADCS2)

MD1

B

00000000

R/W

• A/D data register upper digits (ADCR2)

. . . . . . . . . . . .

(ADCR1)

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

B

00001 -XX

000039^H

DSEL ST1

ST0

W

CT1 XCT0

—

D9

—

D8

—

W

• A/D data register lower digits (ADCR1)

. . . . . . . . . . . .

Address bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

D2

R

bit 1

D1

R

bit 0

D0

Initial value

B

XXXXXXXX

000038^H

(ADCR2)

D7

R

D6

R

D5

R

D4

R

D3

R

R/W: Readable and writable

R : Read only

W : Write only

— : Reserved

X : Undefined

RESV: Reserved bit

66

MB90570 Series

(2) Block Diagram

A/D control status

register (ADCS)

Interrupt request #11*

BUSY

ANS2 ANS1 ANS0 ANE2 ANE1 ANE0

INT INTE PAUS STS1 STS0 STRT

DA MD1 MD0

6

2

PB6/ADTG

TO

Clock selector

Decoder

φ

Comparator

P87/AN7

Sample hold

circuit

P86/AN6

P85/AN5

P84/AN4

P83/AN3

P82/AN2

P81/AN1

P80/AN0

Control circuit

Analog

channel

selector

AVRH, AVRL

AV^CC

8-bit D/A converter

AV^SS

A/D data register

(ADCR)

RESV

ST1 ST0 CT1 CT0

—

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

φ

: Machine clock frequency

TO : 8/16-bit PPG timer channel 1 output

: Interrupt number

*

67

MB90570 Series

13. 8-bit D/A Converter

The 8-bit D/A converter, which is based on the R-2R system, supports 8-bit resolution mode. It contains two

channels each of which can be controlled in terms of output by the D/A control register.

(1) Register Configuration

• D/A converter data register ch.0 (DADR0)

. . . . . . . . . . . .

Address

bit 15

bit 8 bit 7

DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00

R/W R/W R/W R/W R/W R/W R/W R/W

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

00003A^H

(DADR1)

B

XXXXXXXX

• D/A converter data register ch.1 (DADR1)

. . . . . . . . . . . .

(DADR0)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10

R/W R/W R/W R/W R/W R/W R/W R/W

bit 9

bit 8 bit 7

bit 0

Address

Initial value

00003B^H

B

XXXXXXXX

• D/A control register 0 (DACR0)

. . . . . . . . . . . .

Address

00003C^H

bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

—

bit 1

—

bit 0

DAE0

R/W

Initial value

B

- - - - - - - 0

(DACR1)

—

• D/A control register 1 (DACR1)

. . . . . . . . . . . .

(DACR0)

Address

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

DAE1

bit 0

Initial value

B

- - - - - - - 0

00003D^H

—

R/W

R/W: Readable and writable

— : Reserved

X : Undefined

68

MB90570 Series

(2) Block Diagram

Internal data bus

D/A converter data register ch.1 (DADR1)

DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10

D/A converter data register ch.0 (DADR0)

DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00

D/A converter 1

D/A converter 0

DVRH

DVRL

DA17

DA07

P74/DA1

2R

P73/DA0

R

DA16

DA06

DA05

DA04

DA03

DA02

DA01

DA00

2R

R

DA15

2R

R

DA14

2R

R

DA13

2R

R

DA12

2R

R

DA11

2R

R

DA10

2R

DV^SS

Standby control

D/A control register 1 (DACR1)

D/A control register 0 (DACR0)

—

DAE1

—

— DAE0

Internal data bus

69

MB90570 Series

14. Clock Timer

The clock timer control register (WTC) controls operation of the clock timer, and time for an interval interrupt.

(1) Register Configuration

• Clock timer control register (WTC)

. . . . . . . . . . . .

bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Address

0000AA^H

Initial value

B

(Disabled)

WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0

R/W R/W R/W R/W R/W R/W

1X000000

R

R/W: Readable and writable

R : Read only

X : Undefined

(2) Block Diagram

To watchdog timer

Clock counter

× 2¹× 2²× 2³× 2⁴× 2⁵× 2⁶× 2⁷× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵

LCLK

OF

Power-on reset

Counter

Shift to a hardware standby

Shift to stop mode

To sub-clock oscillation stabilization

time controller

clear circuit

Interval

timer selector

Clock timer interrupt request

#22*

WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0

Clock timer control register (WTC)

*

: Interrupt number

OF : Overflow

LCLK : Oscillation sub-clock frequency

70

MB90570 Series

15. Chip Select Output

This module generates a chip select signal for facilitating a memory and I/O unit, and is provided with eight chip

select output pins. When access to an address is detected with a hardware-set area set for each pin register,

a select signal is output from the pin.

(1) Register Configuration

• Chip selection control register 1, 3, 5, 7 (CSCR1, CSCR3, CSCR5, CSCR7)

. . . . . . . . . . . .

Address

CSCR1: 000081^H

CSCR3: 000083^H

CSCR5: 000085^H

CSCR7: 000087^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

ACTL OPEL CSA1 CSA0

R/W R/W R/W R/W

bit 8 bit 7

bit 0

Initial value

(CSCR0, CSCR2, CSCR4, CSCR6)

—

B

- - - - 0000

• Chip selection control register 0, 2, 4, 6 (CSCR0, CSCR2, CSCR4, CSCR6)

. . . . . . . . . . . .

Address bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

ACTL OPEL CSA1 CSA0

R/W R/W R/W R/W

bit 2

bit 1

bit 0

Initial value

CSCR0: 000080^H

CSCR2: 000082^H

CSCR4: 000084^H

CSCR6: 000086^H

(CSCR1, CSCR3, CSCR5, CSCR7)

B

—

- - - - 0000

R/W: Readable and writable

— : Reserved

71

MB90570 Series

(2) Block Diagram

From address (CPU)

A23

A22

A17

A16

A15

A14

A01

A00

Address decoder

Decode signal

Program area

Decode

P90/CS0

(Program ROM area application)

2

Select and set

Chip selection control register 0 (CSCR0)

Chip selection control register 1 (CSCR1)

Chip selection control register 2 (CSCR2)

Selector

P91/CS1

P92/CS2

P93/CS3

P94/CS4

P95/CS5

P96/CS6

P97/CS7

Select and set

Chip selection control register 3 (CSCR3)

Chip selection control register 4 (CSCR4)

Selector

Chip selection control register 5 (CSCR5)

Chip selection control register 6 (CSCR6)

Chip selection control register 7 (CSCR7)

72

MB90570 Series

(3) Decode Address Spaces

CSA

Number of

area bytes

Decode space

Remarks

name

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

—

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

—

F00000^Hto FFFFFFH

1 Mbyte

512 kbyte

128 kbyte

Disabled

1 Mbyte

Becomes active when the program ROM

area or the program vector is fetched.

F80000H to FFFFFFH

CS0

FE0000^Hto FFFFFFH

—

E00000^Hto EFFFFFH

Adapted to the data ROM and RAM areas,

and external circuit connection

applications.

F00000^Hto F7FFFFH

512 kbyte

128 kbyte

128 byte

4 kbyte

CS1

CS2

CS3

CS4

CS5

FC0000^Hto FDFFFFH

68FF80H to 68FFFFH

003000^Hto 003FFFH

Adapted to the data ROM and RAM areas,

and external circuit connection

applications.

FA0000^Hto FBFFFFH

128 kbyte

128 byte

128 kbyte

128 byte

Disabled

2 kbyte

68FF80^Hto 68FFFFH

68FF00^Hto 68FF7FH

F80000^Hto F9FFFFH

Adapted to the data ROM and RAM areas,

and external circuit connection

applications.

68FF00^Hto 68FF7FH

68FE80^Hto 68FEFFH

—

002800^Hto 002FFFH

Adapted to the data ROM and RAM areas,

and external circuit connection

applications.

68FE80^Hto 68FEFFH

128 byte

Disabled

128 byte

Disabled

128 byte

Disabled

—

68FF80^Hto 68FFFFH

Adapted to the data ROM and RAM areas,

and external circuit connection

applications.

—

68FF00^Hto 68FF7FH

Adapted to the data ROM and RAM areas,

and external circuit connection

applications.

—

CS6

CS7

Disabled

73

MB90570 Series

16. Communications Prescaler Register

This register controls machine clock division.

Output from the communications prescaler register is used for UART0 (SCI), UART1 (SCI), and extended I/O

serial interface.

The communications prescaler register is so designed that a constant baud rate may be acquired for various

machine clocks.

(1) Register Configuration

• Communications prescaler control register 0,1 (CDCR0, CDCR1)

. . . . . . . . . . . .

(Disabled)

Address

bit 15

bit 8 bit 7

MD

bit 6

—

bit 5

—

bit 4

—

bit 3

DIV3 DIV2 DIV1 DIV0

R/W R/W R/W R/W

bit 2

bit 1

bit 0

Initial value

000028^H

00002A^H

B

0 - - - 1111

R/W

—

R/W: Readable and writable

— : Reserved

74

MB90570 Series

17. Address Match Detection Function

When the address is equal to a value set in the address detection register, the instruction code loaded into the

CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set

instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program

patching function to be implemented.

Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value

set in the address detection register matches an address and if the interrupt enable bit is set at “1”, the instruction

code loaded into the CPU is replaced forcibly with the INT9 instruction code.

(1) Register Configuration

• Program address detection register 0 to 2 (PADR0)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

B

XXXXXXXX

PADR0 (Low order address): 001FF0^H

R/W

bit 7

R/W

bit 6

R/W

bit 5

R/W

bit 4

R/W

bit 3

R/W

bit 2

R/W

bit 1

R/W

bit 0

Address

Initial value

B

XXXXXXXX

PADR0 (Middle order address): 001FF1^H

R/W

bit 7

R/W

bit 6

R/W

bit 5

R/W

bit 4

R/W

bit 3

R/W

bit 2

R/W

bit 1

R/W

bit 0

Address

Initial value

B

XXXXXXXX

PADR0 (High order address): 001FF2^H

R/W

bit 4

R/W

bit 3

R/W

bit 2

R/W

bit 1

R/W

bit 0

• Program address detection register 3 to 5 (PADR1)

Address

bit 7

bit 6

bit 5

Initial value

B

XXXXXXXX

PADR1 (Low order address): 001FF3^H

R/W

bit 7

R/W

bit 6

R/W

bit 5

R/W

bit 4

R/W

bit 3

R/W

bit 2

R/W

bit 1

R/W

bit 0

Address

Initial value

B

XXXXXXXX

PADR1 (Middle order address): 001FF4^H

R/W

bit 7

R/W

bit 6

R/W

bit 5

R/W

bit 4

R/W

bit 3

R/W

bit 2

R/W

bit 1

R/W

bit 0

Address

Initial value

B

XXXXXXXX

PADR1 (High order address): 001FF5^H

R/W

bit 3

R/W

bit 2

R/W

bit 1

R/W

bit 0

• Program address detection control status register (PACSR)

Address

bit 7

bit 6

bit 5

bit 4

Initial value

B

00000000

RESV RESV RESV RESV AD1E RESV AD0E RESV

R/W R/W R/W R/W R/W R/W R/W R/W

00009E^H

R/W: Readable and writable

X : Undefined

RESV: Reserved bit

75

MB90570 Series

(2) Block Diagram

Address latch

Address detection

register

INT9

instruction

F²MC-16LX

CPU core

Enable bit

76

MB90570 Series

18. ROM Mirroring Function Selection Module

The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the

00 bank according to register settings.

(1) Register Configuration

• ROM mirroring function selection register (ROMM)

. . . . . . . . . . . .

(Disabled)

Address

00006F^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

—

bit 8 bit 7

bit 0

Initial value

—

MI

W

B

- - - - - - - 1

—

W : Write only

— : Reserved

Note: Do not access this register during operation at addresses 004000^Hto 00FFFFH.

(2) Block Diagram

ROM mirroring function selection

register (ROMM)

Address area

Address

FF bank

00 bank

Data

ROM

77

MB90570 Series

19. Low-power Consumption (Standby) Mode

The F²MC-16LX has the following CPU operating mode configured by selection of an operating clock and clock

operation control.

• Clock mode

PLL clock mode: A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation

clock (HCLK).

Main clock mode: A mode in which the CPU and peripheral equipment are driven by divided-by-2 of the

oscillation clock (HCLK).

The PLL multiplication circuits stops in the main clock mode.

• CPU intermittent operation mode

The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU

intermittently while external bus and peripheral functions are operated at a high-speed.

• Hardware standby mode

The hardware standby mode is a mode for reducing power consumption by stopping clock supply to the CPU

by the low-power consumption control circuit, stopping clock supplies to the CPU and peripheral functions

(timebase timer mode), and stopping oscillation clock (stop mode, hardware standby mode). Of these modes,

modes other than the PLL clock mode are power consumption modes.

(1) Register Configuration

• Clock select register (CKSCR)

. . . . . . . . . . . .

(LPMCR)

Address

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

CS1

R/W

bit 8 bit 7

CS0

bit 0

Initial value

0000A1^H

SCM MCM WS1 WS0

R/W R/W

SCS

R/W

MCS

R/W

B

11111100

R

R/W

• Low-power consumption mode control register (LPMCR)

. . . . . . . . . . . .

Address bit 15

bit 8 bit 7

bit 6

SLP

W

bit 5

SPL

R/W

bit 4

bit 3

bit 2

CG1

W

bit 1

CG0

R/W

bit 0

SSR

R/W

Initial value

0000A0^H

B

(CKSCR)

STP

RST

W

TMD

R/W

00011000

W

R/W: Readable and writable

R : Read only

W : Write only

78

MB90570 Series

(2) Block Diagram

Standby control circuit

Low-power consumption mode control register

(LPMCR)

CPU intermittent

operation cycle

selector

CPU clock

control circuit

CPU operation

clock

STP SLP SPL RST TMD CG1 CG0 SSR

2

Clock mode

Sleep signal

Stop signal

Peripheral function

operation clock

Peripheral clock

control circuit

Hardware

standby

S

R

Q

S

R

Q

Machine clock

S

R

S

R

Reset

Interrupt

Clock selector

Oscillation

stabilization

time selector

2

PLL multiplication

circuit

SCM MCM WS1 WS0 SCS MCS CS1 CS0

Clock select register (CKSCR)

X0 Pin

1/2

1/2048

1/4

1/8

1/4

Oscillation

clock

Main

clock

X1

Clock oscillator

Timebase timer

To watchdog timer

X0A Pin

1/2

1/8

1/2

1/1024

Clock timer

Oscillation

sub-clock

X1A

Sub-clock oscillator

S: Set

R: Reset

Q: Output

79

MB90570 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

V^CC

VSS – 0.3

VSS + 6.0

V

AVCC

*1

Power supply voltage

AVRH,

AVRL

V^SS– 0.3

VSS + 6.0

V

DVRH

V^I

V^SS– 0.3

VSS – 0.3

VSS + 6.0

15

V

*1

*2

*3

*4

Input voltage

V

Output voltage

VO

V

“L” level maximum output current

“L” level average output current

I^OL

mA

IOLAV

4

“L” level total maximum output current ΣIOL

100

“L” level total average output current

“H” level maximum output current

“H” level average output current

ΣI^OLAV

50

*5

*3

*4

IOH

–15

IOHAV

–4

“H” level total maximum output current ΣI^OH

–100

–50

“H” level total average output current

Power consumption

ΣIOHAV

*5

MB90573/4

MB90V570/A

300

mW

P^D

500

800

mW

°C

MB90574C

MB90F574/A

Operating temperature

Storage temperature

T^A

–40

–55

+85

Tstg

+150

°C

*1: AV^CC, AVRH, AVRL, and DVRH shall never exceed VCC. AVRL shall never exceed AVRH.

*2: VI and VO shall never exceed VCC + 0.3 V.

*3: The maximum output current is a peak value for a corresponding pin.

*4: Average output current is an average current value observed for a 100 ms period for a corresponding pin.

*5: Total average current is an average current value observed for a 100 ms period for all corresponding pins.

Note: Average output current = operating × operating efficiency

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

80

MB90570 Series

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

3.0

Max.

5.5

V^CC

V

Normal operation (MB90574/C)

Normal operation (MB90F574/A)

4.5

5.5

Power supply voltage

Smoothing capacitor

Retains status at the time of

operation stop

V^CC

C^S

3.0

5.5

V

0.1

1.0

µF

°C

*

Operating temperature TA

–40

+85

* : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be

connected to the V^CCpin must have a capacitance value higher than CS.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

• C pin connection circuit

C

C^S

81

MB90570 Series

3. DC Characteristics

(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter Symbol

Pin name

CMOS

hysteresis input

Condition

Unit Remarks

Min.

Typ.

Max.

VCC + 0.3

0.2 VCC

VSS + 0.3

—

“H” level

V^IHS

0.8 VCC

—

V

input

V^CC= 3.0 V to 5.5 V

(MB90573)

(MB90574)

V^CC= 4.5 V to 5.5 V

(MB90F574)

voltage

VIHM

MD pin input

VCC – 0.3

V^SS– 0.3

VSS – 0.3

V^CC– 0.5

—

CMOS

hysteresis input

“L” level

V^ILS

—

input

voltage

VILM

MD pin input

—

“H” level

output

Other than PA6 VCC = 4.5 V

and PA7

V^OH

—

I^OH= –2.0 mA

voltage

“L” level

output

voltage

V^CC= 4.5 V

IOL = 2.0 mA

V^OL

All output pins

—

–5

—

0.1

—

0.4

5

V

Open-drain

output

leakage

current

I^leak

PA6, PA7

—

µA

Input

leakage

current

Other than PA6 VCC = 5.5 V

I^IL

5

and PA7

VSS < VI < VCC

P00 to P07,

P10 to P17,

P60 to P67,

RST, MD0,

MD1

Pull-up

resistance

R^UP

—

15

30

100

kΩ

Pull-down

resistance

R^DOWN

MD0 to MD2

MB90574

I^CC

ICC

VCC

Internal operation

at 16 MHz

VCC at 5.0 V

—

30

85

50

35

90

40

130

80

mA

MB90F574/A

MB90574C

MB90574

Normal operation

Internal operation

at 16 MHz

VCC at 5.0 V

A/D converter

operation

45

140

mA MB90F574/A

Power

supply

current*

MB90574C

ICC

VCC

—

55

85

mA

ICC

VCC

Internal operation

at 16 MHz

VCC at 5.0 V

D/A converter

operation

—

40

95

50

mA MB90574

145

mA MB90F574/A

MB90574C

mA

ICC

VCC

—

65

85

(Continued)

82

MB90570 Series

(Continued)

(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter Symbol

Pin name

Condition

Unit Remarks

Min.

Typ.

Max.

When data written

in flash mode

programming of

erasing

I^CC

VCC

—

95

140

mA MB90F574/A

I^CCS

I^CCL

ICCL

VCC

Internal operation

at 16 MHz

V^CC= 5.0 V

—

7

5

12

10

20

1.0

7

mA MB90574

mA MB90F574/A

mA MB90574C

mA MB90574

15

0.1

4

In sleep mode

Internal operation

at 8 kHz

V^CC= 5.0 V

TA = +25°C

Subsystem

operation

mA MB90F574/A

I^CCL

VCC

—

0.03

1

mA MB90574C

Power

supply

current*

I^CCLS

VCC

Internal operation

at 8 kHz

VCC = 5.0 V

—

30

50

1

mA MB90574

0.1

mA MB90F574/A

T^A= +25°C

In subsleep mode

I^CCLS

VCC

—

10

50

µA MB90574C

I^CCT

VCC

Internal operation

at 8 kHz

VCC = 5.0 V

T^A= +25°C

—

15

30

50

µA MB90574

µA MB90F574/A

I^CCT

I^CCH

VCC

—

1.0

5

30

20

10

µA MB90574C

µA MB90574

In clock mode

TA = +25°C

In stop mode

MB90F574/A

µA

0.1

MB90574C

Input

capacitance

Other than AVCC,

AVSS, VCC, VSS

C^IN

—

10

80

pF

* : Thecurrentvalueispreliminaryvalueandmaybesubjecttochangeforenhancedcharacteristicswithoutprevious

notice.

83

MB90570 Series

4. AC Characteristics

(1) Reset, Hardware Standby Input Timing

(AV^CC= VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Max.

Symbol Pin name Condition

Unit

Remarks

Parameter

Min.

4 t^CP*

4 tCP*

Reset input time

t^RSTL

RST

HST

—

ns

—

Hardware standby input time t^HSTL

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timings.”

t^RSTL, t^HSTL

RST

HST

0.2 V^CC

• Measurement conditions for AC characteristics

C^L

C^Lis a load capacitance connected to a pin under test.

Capacitors of C^L= 30 pF must be connected to CLK and ALE pins, while C^Lof 80 pF must

be connected to address data bus (AD15 to AD00), RD, WRL, and WRH pins.

84

MB90570 Series

(2) Specification for Power-on Reset

(AV^SS= VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol Pin name Condition

Unit

ms

Remarks

Parameter

Min.

Max.

Power supply rising time

Power supply cut-off time

t^R

VCC

0.05

30

*

—

Due to repeated

operations

t^OFF

4

—

ms

* : V^CCmust be kept lower than 0.2 V before power-on.

Notes: • The above ratings are values for causing a power-on reset.

• There are internal registers which can be initialized only by a power-on reset.

Apply power according to this rating to ensure initialization of the registers.

t^R

2.7 V

0.2 V

V^CC

0.2 V

t^OFF

0.2 V

Sudden changes in the power supply voltage may cause a power-on reset.

To change the power supply voltage while the device is in operation, it is recommended to raise the voltage

smoothly to suppress fluctuations as shown below.

In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 mV or fewer per

second, however, you can use the PLL clock.

V^CC

It is recommended to keep the rising

speed of the supply voltage at 50 mV/ms

or slower.

3.0 V

V^SS

85

MB90570 Series

(3) Clock Timings

(AV^CC= VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Clock frequency

Min.

3

Typ. Max.

F^C

X0, X1

—

32.768

—

16

—

MHz

kHz

ns

F^CL

X0A, X1A

X0, X1

—

t^HCYL

t^LCYL

62.5

—

333

—

Clock cycle time

X0A, X1A

30.5

µs

Recommend

ns duty ratio of

30% to 70%

P^WH,

P^WL

X0

10

—

Input clock pulse width

PWLH,

P^WLL

X0A

X0, X0A

—

15.2

—

5

µs

t^CR,

tCF

External clock

operation

Input clock rising/falling time

ns

—

Main clock

MHz

f^CP

f^LCP

t^CP

t^LCP

∆f

1.5

—

16

—

333

—

5

operation

Internal operating clock

frequency

Subclock

kHz

—

8.192

—

operation

External clock

operation

—

62.5

—

ns

Internal operating clock cycle

time

Subclock

µs

—

122.1

—

operation

Frequency fluctuation rate

locked

—

%

*

* : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied

PLL signal is locked.

+

+ α

| α |

f^O

∆f =

× 100 (%)

Center frequency f^O

– α

–

The PLL frequency deviation changes periodically from the preset frequency “(about CLK × (1CYC to 50 CYC)”,

thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with

long intervals).

86

MB90570 Series

• X0, X1 clock timing

t^HCYL

0.8 V^CC

0.2 V^CC

X0

P^WH

P^WL

t^CF

t^CR

• X0A, X1A clock timing

t^LCYL

0.8 V^CC

0.2 V^CC

0.8 V^CC

0.2 V^CC

X0A

P^WLH

P^WLL

t^CF

t^CR

• PLL operation guarantee range

Relationship between internal operating clock

frequency and power supply voltage

Operation guarantee range (MB90F574/A)

Operation guarantee range MB90574C

(V)

5.5

4.5

PLL operation

guarantee range

Operation guarantee range

MB90V570/A

3.3

3.0

Operation guarantee range

MB90573/4

(MHz)

1.5

3

8

12

16

Internal clock f^CP

Relationship between oscillating frequency, internal

operating clock frequency, and power supply voltage

(MHz)

Multiplied-

by-4

Multiplied-

by-3

Multiplied-by-2

16

Multiplied-by-1

12

9

8

Not multiplied

6

4

3

2

1.5

(MHz)

3

4

6

8

12

16

Oscillation clock F^C

87

MB90570 Series

The AC ratings are measured for the following measurement reference voltages.

• Input signal waveform

• Output signal waveform

Hystheresis input pin

0.8 V^CC

Hystheresis input pin

2.4 V^CC

0.2 V^CC

0.8 V^CC

Pins other than hystheresis input/MD input

0.7 V^CC

0.3 V^CC

(4) Recommended Resonator Manufacturers

• Sample application of ceramic resonator

X0

X1

R

*

C¹

C2

• Mask ROM product (MB90574)

Resonator

Frequency (MHz)

C¹(pF)

R

manufacturer*

CSA2.00MG040

CSA4.00MG040

2.00

4.00

100

30

15

5

100

30

No required

Murata Mfg. Co., Ltd. CSA8.00MTZ

CSA16.00MXZ040

8.00

16.00

32.00

15

5

CSA32.00MXZ040

CCR3.52MC3 to

CCR6.96MC3

3.52 to 6.96

7.00 to 12.00

20.00 to 32.00

Built-in

No required

CCR7.0MC5 to

CCR12.0MC5

TDK Corporation

CCR20.0MSC6 to

CCR32.0MSC6

No required

(Continued)

88

MB90570 Series

(Continued)

• Flash product (MB90F574)

Resonator

manufacturer*

Resonator

Frequency (MHz)

C¹(pF)

C²(pF)

R

CSA2.00MG040

CSA4.00MG040

2.00

4.00

100

30

15

5

100

30

No required

Murata Mfg. Co., Ltd. CSA8.00MTZ

CSA16.00MXZ040

8.00

16.00

32.00

15

5

CSA32.00MXZ040

CCR3.52MC3 to

CCR6.96MC3

3.52 to 6.96

7.00 to 12.00

20.00 to 32.00

Built-in

No required

CCR7.0MC5 to

CCR12.0MC5

TDK Corporation

CCR20.0MSC6 to

CCR32.0MSC6

Inquiry: Murata Mfg. Co., Ltd.

• Murata Electronics North America, Inc.: TEL 1-404-436-1300

• Murata Europe Management GmbH: TEL 49-911-66870

• Murata Electronics Singapore (Pte.): TEL 65-758-4233

TDK Corporation

• TDK Corporation of America

Chicago Regional Office: TEL 1-708-803-6100

• TDK Electronics Europe GmbH

Components Division: TEL 49-2102-9450

• TDK Singapore (PTE) Ltd.: TEL 65-273-5022

• TDK Hongkong Co., Ltd.: TEL: 852-736-2238

• Korea Branch, TDK Corporation: TEL 82-2-554-6636

(5) Clock Output Timing

(AV^CC= VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Cycle time

CLK ↑ → CLK ↓

Min.

62.5

20

Max.

—

t^CYC

CLK

ns

—

tCHCL

CLK

—

t^CYC

t^CHCL

2.4 V

0.8 V

CLK

89

MB90570 Series

(6) Bus Read Timing

(AV^CC= VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Unit

Remarks

Symbol

Pin name

Condition

Parameter

Min.

Max.

ALE pulse width

t^LHLL

ALE

1 tCP*/2 – 20

—

ns

ALE,

A23 to A16,

AD15 to AD00

Effective address →

ALE ↓ time

t^AVLL

t^LLAX

t^AVRL

1 t^CP*/2 – 20

1 t^CP*/2 – 15

1 tCP* – 15

—

ns

ALE ↓ → address

effective time

ALE,

AD15 to AD00

RD,

A23 to A16,

AD15 to AD00

Effective address →

RD ↓ time

Effective address →

valid data input

A23 to A16,

AD15 to AD00

t^AVDV

—

3 tCP*/2 – 20

—

5 t^CP*/2 – 60 ns

ns

RD pulse width

tRLRH

RD

—

RD,

AD15 to AD00

RD ↓ → valid data input tRLDV

RD ↑ → data hold time tRHDX

3 t^CP*/2 – 60 ns

RD,

AD15 to AD00

0

—

ns

RD ↑ → ALE ↑ time

tRHLH

ALE, RD

1 tCP*/2 – 15

1 t^CP*/2 – 10

RD ↑ → address

effective time

ALE,

A23 to A16

t^RHAX

CLK,

A23 to A16,

AD15 to AD00

Effective address →

CLK ↑ time

t^AVCH

1 t^CP*/2 – 20

—

ns

RD ↓ → CLK ↑ time

ALE ↓ → RD ↓ time

tRLCH

tALRL

CLK, RD

ALE, RD

1 tCP*/2 – 20

1 tCP*/2 – 15

—

ns

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timings.”

90

MB90570 Series

t^AVCH

t^RLCH

2.4 V

CLK

t^RHLH

2.4 V

0.8 V

2.4 V

t^LHLL

t^AVLL

ALE

RD

t^LLAX

t^RLRH

2.4 V

0.8 V

t^RHAX

t^AVRL

t^RLDV

2.4 V

0.8 V

2.4 V

0.8 V

AD23 to AD16

AD15 to AD00

t^AVDV

t^RHDX

2.4 V

0.8 V

2.4 V

0.8 V

0.8 V^CC

0.2 V^CC

0.8 V^CC

Address

Read data

0.2 V^CC

91

MB90570 Series

(7) Bus Write Timing

(AV^CC= VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Unit

Symbol

Pin name

Condition

Remarks

Parameter

Min.

Max.

WRL, WRH,

A23 to A16,

AD15 to AD00

Effective address →

WR ↓ time

t^AVWL

1 t^CP– 15

—

ns

WR pulse width

tWLWH

WRL, WRH

3 tCP*/2 – 20

3 t^CP*/2 – 20

—

ns

WRL, WRH,

AD15 to AD00

Write data → WR ↑ time tDVWH

WR ↑ → data hold time tWHDX

—

WRL, WRH,

AD15 to AD00

20

—

ns

WR ↑ → address

t^WHAX

WRL, WRH,

A23 to A16

1 t^CP*/2 – 10

effective time

WR ↑ → ALE ↑ time

WR ↓ → CLK ↑ time

tWHLH

tWLCH

ALE, WRL

CLK, WRH

1 tCP*/2 – 15

1 tCP*/2 – 20

—

ns

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timings.”

t^WLCH

2.4 V

CLK

t^WHLH

2.4 V

ALE

t^AVWL

t^WLWH

WRL, WRH

2.4 V

0.8 V

t^WHAX

2.4 V

0.8 V

2.4 V

0.8 V

A23 to A16

t^DVWH

t^WHDX

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

AD15 to AD00

Address

Write data

92

MB90570 Series

(8) Ready Input Timing

(AV^CC= VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

t^RYHS

t^RYHH

Pin name

RDY

Condition

Unit Remarks

Parameter

Min.

45

0

Max.

—

RDY setup time

RDY hold time

ns

—

Note: Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient.

2.4 V

CLK

ALE

RD/WRL, RD/WRH

t^RYHS

0.2 V^CC

t^RYHS

RDY

(wait inserted)

0.2 V^CC

RDY

(wait not inserted)

0.8 V^CC

t^RYHH

(9) Hold Timing

Parameter

(AV^CC= VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Min.

30

Max.

1 t^CP*

2 tCP*

Pins in floating status →

HAK ↓ time

t^XHAL

HAK

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timings.”

ns

—

HAK ↑ → pin valid time tHAHV

1 tCP*

Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.

HAK

2.4 V

0.8 V

t^XHAL

2.4 V

0.8 V

tHAHV

2.4 V

0.8 V

Pins

High impedance

93

MB90570 Series

(10) UART0 (SCI), UART1 (SCI) Timing

(AV^CC= VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

t^SCYC

Pin name

Condition

Unit Remarks

Parameter

Min.

Max.

Serial clock cycle time

SCK0 to SCK4

8 t^CP*

—

ns

SCK ↓ → SOT delay

SCK0 to SCK4,

SOT0 to SOT4

Internal shift clock

mode

C^L= 80 pF

+ 1 TTL for an

output pin

t^SLOV

– 80

100

60

80

—

time

SCK0 to SCK4,

SIN0 to SIN4

Valid SIN → SCK ↑

t^IVSH

t^SHIX

t^SHSL

t^SLSH

t^SLOV

t^IVSH

t^SHIX

ns

SCK ↑ → valid SIN

hold time

SCK0 to SCK4,

SIN0 to SIN4

—

Serial clock “H” pulse

width

SCK0 to SCK4

4 t^CP*

4 tCP*

—

Serial clock “L” pulse

width

—

External shift

clock mode

C^L= 80 pF

+ 1 TTL for an

output pin

SCK ↓ → SOT delay

SCK0 to SCK4,

SOT0 to SOT4

150

—

time

SCK0 to SCK4,

SIN0 to SIN4

Valid SIN → SCK ↑

60

SCK ↑ → valid SIN

hold time

SCK0 to SCK4,

SIN0 to SIN4

60

—

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timings.”

Notes: • These are AC ratings in the CLK synchronous mode.

• C^Lis the load capacitance value connected to pins while testing.

94

MB90570 Series

• Internal shift clock mode

t^SCYC

SCK0 to SCK4

2.4 V

0.8 V

t^SLOV

0.8 V

2.4 V

0.2 V

SOT0 to SOT4

t^IVSH

t^SHIX

0.8 V^CC

0.2 V^CC

0.8 V^CC

0.2 V^CC

SIN0 to SIN4

• External shift clock mode

SCK0 to SCK4

t^SLSH

t^SHSL

0.8 V^CC

0.2 V^CC

tSLOV

2.4 V

0.8 V

SOT0 to SOT4

SIN0 to SIN4

t^IVSH

t^SHIX

0.8 V^CC

0.2 V^CC

0.8 V^CC

0.2 V^CC

95

MB90570 Series

(11) Timer Input Timing

(AV^CC= VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

IN0, IN1

Condition

Unit Remarks

Parameter

Min.

Max.

t^TIWH,

t^TIWL

Input pulse width

—

4 tCP*

—

ns

* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”

0.8 V^CC

0.2 V^CC

IN0, IN1

t^TIWH

t^TIWL

(12) Timer Output Timing

(AV^CC= VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

CLK ↑ → T^OUT

Min.

Max.

OUT0 to OUT3,

PPG0, PPG1

t^TO

—

30

—

ns

transition time

2.4 V

CLK

T^OUT

t^TO

2.4 V

0.8 V

96

MB90570 Series

(13) Trigger Input Timing

(AV^CC= VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min.

Max.

IRQ0 to IRQ5,

ADTG, IN0, IN1

Input pulse width

t^TRGL

—

5 t^CP*

—

ns

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timings.”

0.8 V^CC

0.2 V^CC

IRQ0 to IRQ5

ADTG, IN0, IN1

t^TRGH

t^TRGL

97

MB90570 Series

(14) Chip Select Output Timing

(AV^CC= VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Unit

Symbol

Pin name

Condition

Remarks

Parameter

Min.

Max.

Valid chip select output

→ Valid data input time

CS0 to CS7,

AD15 to AD00

t^SVDV

t^RHSV

t^WHSV

t^SVCH

—

5 t^CP*/2 – 60 ns

RD ↑ → chip select

output effective time

RD,

CS0 to CS7

1 t^CP*/2 – 10

1 tCP*/2 – 10

1 t^CP*/2 – 20

—

ns

—

WR ↑ → chip select

output effective time

CS0 to CS7,

WRL, WRH

Valid chip select output

→ CLK ↑ time

CLK,

CS0 to CS7

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timings.”

t^SVCH

CLK

2.4 V

RD

2.4 V

t^RHSV

A23 to A16

CS0 to CS7

2.4 V

0.8 V

t^SVDV

2.4 V

0.8 V

AD15 to AD00

Read data

t^WHSV

2.4 V

WRL, WRH

AD15 to AD00

Write data

98

MB90570 Series

(15) I²C Timing

Parameter

(AV^CC= VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol Pin name Condition

Unit

Remarks

Min.

Max.

Internal clock cycle time tCP

—

62.5

666

ns All products

Start condition output

Stop condition output

t^STAO

t^CP×m×n/2-20 tCP×m×n/2+20 ns

Only as master

Only as slave

tCP(m×n/

2+4)+20

t^STOO

ns

2+4)-20

SDA,SCL

Start condition detection t^STAI

Stop condition detection t^STOI

3tCP+40

—

SCL output “L” width

SCL output “H” width

SDA output delay time

t^LOWO

t^HIGHO

t^DOO

t^CP×m×n/2-20 tCP×m×n/2+20 ns

SCL

Only as master

tCP(m×n/

2+4)+20

—

ns

2+4)-20

2t^CP-20

4tCP-20

3t^CP+40

tCP+40

40

2tCP+20

—

SDA,SCL

SCL

Setup after SDA output

interrupt period

t^DOSUO

t^LOWI

t^HIGHI

t^SUI

SCL input “L” width

SCL input “H” width

SDA input setup time

SDA input hold time

—

SDA,SCL

t^HOI

0

—

Notes: • “m” and “n” in the above table represent the values of shift clock frequency setting bits (CS4-CS0) in the

clock control register “ICCR”. For details, refer to the register description in the hardware manual.

• t^DOSUOrepresents the minimum value when the interrupt period is equal to or greater than the SCL “L” width.

• The SDA and SCL output values indicate that rise time is 0 ns.

99

MB90570 Series

• I²C interface [data transmitter (master/slave)]

tLOWO

tHIGHO

0.8 VCC

0.8 VCC 0.8 VCC

SCL

SDA

0.2 VCC

tDOO

0.2 VCC

1

8

9

t^STAO

tDOO

tSUI

tHOI

tDOSUO

ACK

• I²C interface [data receiver (master/slave)]

tHIGHI

tLOWI

0.8 VCC

tSUI

0.8 VCC

SCL

SDA

0.2 VCC

tHOI

0.2 VCC

8

0.2 VCC

6

7

9

tSTOI

tDOO

tDOSUO

ACK

100

MB90570 Series

(16) Pulse Width on External Interrupt Pin at Return from STOP Mode

(AV^CC= VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Pin name

Condition

Unit

Remarks

Min.

Max.

t^IRQWH

tIRQWL

Input pulse width

IRQ2 to IRQ7

6tCP

ns

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timings.”

0.80V.8CCVCC

0.20V.2CCVCC

0.80V.8CCVCC

0.20V.2CCVCC

IRQIR2Q2IRQIR7Q7

tIRQtWIRHQWH

tIRQtWIRLQWL

101

MB90570 Series

5. A/D Converter Electrical Characteristics

≤

(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, 2.7 V AVRH – AVRL, TA = –40°C to +85°C)

Value

Symbol Pin name

Condition

Unit

Parameter

Resolution

Min.

—

Typ.

8/10

—

Max.

—

bit

Total error

—

±5.0

±2.5

LSB

Non-linear error

—

Differential

linearity error

—

±1.9

LSB

—

Zero transition

voltage

AN0 to

AN7

V^OT

V^FST

–3.5 LSB +0.5 LSB +4.5 LSB mV

Full-scale

transition

voltage

AN0 to

AN7

AVRH

mV

–6.5 LSB –1.5 LSB +1.5 LSB

V^CC= 5.0 V ±10%

at machine clock of 16 MHz

Conversion time

Sampling period

—

352t^CP

64t^CP

—

µs

µA

V

V^CC= 5.0 V ±10% at

machine clock of 6 MHz

—

Analog port

input current

AN0 to

AN7

I^AIN

10

Analog input

voltage

AN0 to

AN7

V^AIN

AVRL

AVRH

AV^CC

—

AVRL

+2.7

—

AVRH

V

Reference

voltage

AVRH

–2.7

AVRL

0

—

5

V

I^A

AVCC

—

mA

CPU stopped and 8/10-bit

A/D converter not in

operation

Power supply

current

I^AH

I^R

AVCC

—

400

—

5

µA

(V^CC= AVCC = AVRH = 5.0 V)

AVRH

—

5

Reference

voltage supply

current

CPU stopped and 8/10-bit

A/D converter not in

operation

I^RH

(V^CC= AVCC = AVRH = 5.0 V)

Offset between

channels

AN0 to

AN7

—

4

LSB

102

MB90570 Series

6. A/D Converter Glossary

Resolution: Analog changes that are identifiable with the A/D converter

Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000

0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual

conversion characteristics

Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the

theoretical value

Total error: The total error is defined as a difference between the actual value and the theoretical value, which

includes zero-transition error/full-scale transition error and linearity error.

Total error

3FF

0.5 LSB

3FE

3FD

Actual conversion

value

{1 LSB × (N – 1) + 0.5 LSB}

004

003

002

001

V^NT

(measured value)

Actual conversion

characteristics

Theoretical

characteristics

0.5 LSB

Analog input

AVRL

AVRH

AVRH – AVRL

1024

V^NT– {1 LSB × (N – 1) + 0.5 LSB}

1 LSB = (Theoretical value)

[V]

Total error for digital output N

[LSB]

=

1 LSB

V^NT: Voltage at a transition of digital output from (N – 1) to N

V^OT(Theoretical value) = AVRL + 0.5 LSB[V]

V^FST(Theoretical value) = AVRH – 1.5 LSB[V]

(Continued)

103

MB90570 Series

(Continued)

Linearity error

Differential linearity error

Theoretical characteristics

3FF

Actual conversion

3FE

3FD

value

N + 1

N

Actual conversion value

{1 LSB × (N – 1)+ V^OT}

V^FST

(measured value)

V^NT

N – 1

N – 2

004

003

002

001

V^{(N + 1)T}

(measured value)

Actual conversion

characteristics

V^NT(measured

Theoretical

Actual conversion

value

characteristics

V^OT(measured value)

Analog input

AVRL

AVRH

AVRL

Analog input

AVRH

Linearity error of

digital output N

V^NT– {1 LSB × (N – 1) + V^OT}

[LSB]

=

1 LSB

V^{(N + 1)T}– V^NT

1 LSB

Differential linearity error

of digital N

– 1 LSB [LSB]

=

V^FST– V^OT

1 LSB

[V]

=

1022

V^OT:Voltage at transition of digital output from “000^H” to “001^H”

V^FST: Voltage at transition of digital output from “3FE^H” to “3FF^H”

7. Notes on Using A/D Converter

Select the output impedance value for the external circuit of analog input according to the following conditions.

Output impedance values of the external circuit of 7 kΩ or lower are recommended.

Whencapacitorsareconnectedtoexternalpins, thecapacitanceofseveralthousandtimestheinternalcapacitor

value is recommended to minimized the effect of voltage distribution between the external capacitor and internal

capacitor.

When the output impedance of the external circuit is too high, the sampling period for analog voltages may not

be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz).

• Equipment of analog input circuit model

C⁰

Analog input

Comparator

C¹

MB90573/4, MB90V570/A

MB90F574/A

MB90574C

R

1.5 kΩ, C 30 pF

3.0 kΩ, C 65 pF

Note: Listed values must be considered as standards.

• Error

The smaller the | AVRH – AVRL |, the greater the error would become relatively.

104

MB90570 Series

8. D/A Converter Electrical Characteristics

(AVCC = VCC = DVCC = 5.0 V ±10%, AVSS = VSS = DVSS = 0.0 V, TA = –40°C to +85°C)

Value

Unit

Symbol

Pin name

Remarks

Parameter

Resolution

Min.

Typ.

Max.

—

8

—

bit

Differential linearity

error

—

±0.9

LSB

Absolute accuracy

Linearity error

—

10

±1.2

±1.5

20

%

LSB

Conversion time

µs Load capacitance: 20 pF

Analog reference

voltage

—

DV^CC

VSS + 3.0

—

AVCC

V

Conversion under

no load

I^DVR

I^DVRS

—

DVCC

—

120

—

300

10

µA

Reference voltage

supply current

µA In sleep mode

Analog output

impedance

—

20

—

kΩ

105

MB90570 Series

■ EXAMPLE CHARACTERISTICS

(1) Power Supply Current (MB90574)

I^CC- V^CC

I^CCS- V^CC

I^CC(mA)

35

I^CCS(mA)

10

T^A= +25°C

9

8

7

6

5

4

3

2

1

30

25

20

15

10

5

Fc = 16 MHz

Fc = 12.5 MHz

Fc = 10 MHz

Fc = 8 MHz

Fc = 10 MHz

Fc = 8 MHz

Fc = 5 MHz

Fc = 4 MHz

Fc = 5 MHz

Fc = 4 MHz

Fc = 2 MHz

3.0

4.0

5.0

6.0

V^CC(V)

3.0

4.0

5.0

6.0

V^CC(V)

I^CC- T^A

I^CCS- T^A

I^CC(mA)

35

I^CCS(mA)

10

V^CC= 5.0 V

9

8

7

6

5

4

3

2

1

30

25

20

15

10

5

Fc = 16 MHz

Fc = 12.5 MHz

Fc = 10 MHz

Fc = 8 MHz

Fc = 10 MHz

Fc = 8 MHz

Fc = 5 MHz

Fc = 4 MHz

Fc = 2 MHz

Fc = 5 MHz

Fc = 4 MHz

Fc = 2 MHz

–20

+10 +40

+70 +100

T^A(°C)

–20

+10

+40

+70

+100

T^A(°C)

I^CCLS- V^CC

I^CCLS(mA)

70

I^CCL- V^CC

I^CCL(µA)

T^A= +25°C

160

T^A= +25°C

60

50

40

30

20

10

140

120

100

80

Fc = 8 kHz

60

40

20

3.0

4.0

5.0

6.0

V^CC(V)

3.0

4.0

5.0

6.0

V^CC(V)

106

MB90570 Series

I^CC- Fc

I^CCS- Fc

I^CC(mA)

35

I^CCS(mA)

10

V^CC= 6.0 V

V^CC= 5.5 V

V^CC= 5.0 V

V^CC= 4.5 V

V^CC= 4.0 V

V^CC= 3.5 V

T^A= +25°C

9

8

7

6

5

4

3

2

1

T^A= +25°C

V^CC= 5.5 V

V^CC= 5.0 V

V^CC= 4.5 V

V^CC= 4.0 V

V^CC= 3.5 V

30

25

20

15

10

5

V^CC= 3.0 V

V^CC= 2.5 V

4.0

6.0

8.0

12.0 16.0

Fc (MHz)

4.0

6.0

8.0

12.0 16.0

Fc (MHz)

I^CCH- V^CC

I^CCT- V^CC

I^CCH(µA)

I^CCT(µA)

10

20

T^A= +25°C

9

8

7

6

5

4

3

2

1

18

16

14

12

10

8

Fc = 8 kHz

6

4

2

3.0

4.0

5.0

6.0

V^CC(V)

3.0

4.0

5.0

6.0

V^CC(V)

I^CCT- T^A

I^CCLH- T^A

I^CCT(µA)

I^CCLH(µA)

10

V^CC= 6.0 V

V^CC= 5.5 V

V^CC= 5.0 V

V^CC= 4.5 V

9

8

7

6

5

4

3

2

1

9

8

7

6

5

4

3

2

1

V^CC= 6.0 V

V^CC= 5.5 V

V^CC= 5.0 V

V^CC= 4.0 V

V^CC= 3.5 V

V^CC= 3.0 V

V^CC= 2.5 V

V^CC= 4.5 V

V^CC= 4.0 V

V^CC= 3.5 V

V^CC= 3.0 V

V^CC= 2.5 V

–20

+10 +40

+70

+100

T^A(°C)

–20

+10 +40

+70

+100

T^A(°C)

107

MB90570 Series

I^CCL- T^A

I^CCLS- T^A

I^CCL(µA)

I^CCLS(µA)

20

18

16

14

12

10

8

14

V^CC= 6.0 V

V^CC= 5.5 V

V^CC= 5.0 V

V^CC= 6.0 V

V^CC= 5.5 V

V^CC= 5.0 V

V^CC= 4.5 V

V^CC= 4.0 V

V^CC= 3.5 V

V^CC= 3.0 V

V^CC= 2.5 V

12

10

8

V^CC= 4.5 V

V^CC= 4.0 V

V^CC= 3.5 V

V^CC= 3.0 V

V^CC= 2.5 V

6

4

2

–20

+10 +40

+70

+100

T^A(°C)

–20

+10 +40

+70

+100

T^A(°C)

(2) Power Supply Current (MB90F574)

I^CCS- V^CC

I^CC- V^CC

I^CCS(mA)

40

I^CC(mA)

140

T^A= +25°C

Fc = 16 MHz

120

100

80

35

30

25

20

15

10

5

Fc = 12.5 MHz

Fc = 16 MHz

Fc = 10 MHz

Fc = 8 MHz

Fc = 12.5 MHz

Fc = 10 MHz

Fc = 8 MHz

Fc = 5 MHz

Fc = 4 MHz

60

Fc = 5 MHz

Fc = 4 MHz

Fc = 2 MHz

40

20

3.0

4.0

5.0

6.0

V^CC(V)

3.0

4.0

5.0

6.0

V^CC(V)

I^CC- T^A

I^CCS- T^A

I^CC(mA)

120

I^CCS(mA)

40

V^CC= 5.0 V

35

30

25

20

15

10

5

100

80

Fc = 16 MHz

Fc = 12.5 MHz

Fc = 16 MHz

Fc = 10 MHz

Fc = 8 MHz

60

Fc = 12.5 MHz

Fc = 10 MHz

Fc = 5 MHz

Fc = 4 MHz

40

20

Fc = 8 MHz

Fc = 5 MHz

Fc = 4 MHz

Fc = 2 MHz

–20

+10 +40

+70

+100

T^A(°C)

–20

+10 +40

+70

+100

T^A(°C)

108

MB90570 Series

I^CCLS- VCC

I^CCLS(µA)

200

TA = +25°C

180

160

FC = 8 kHz

140

120

100

80

60

40

20

3.0

4.0

5.0

6.0

V^CC(V)

I^CCS- FC

I^CC- FC

I^CCS(mA)

40

I^CC(mA)

120

V^CC= 6.0 V

TA = +25°C

35

30

100

80

V^CC= 5.5 V

V^CC= 5.0 V

V^CC= 6.0 V

V^CC= 5.5 V

V^CC= 5.0 V

25

20

15

10

V^CC= 4.5 V

VCC = 4.0 V

60

40

20

V^CC= 4.5 V

VCC = 4.0 V

V^CC= 3.5 V

V^CC= 3.0 V

V^CC= 2.5 V

5

V^CC= 2.5 V

4.0

8.0

12.0

16.0

FC (MHZ)

4.0

8.0

12.0

16.0

FC (MHZ)

I^CCT- VCC

I^CCH-VCC

I^CCH(µA)

I^CCT(µA)

50

10

9

T^A= +25°C

TA = +25°C

40

30

20

8

7

6

5

4

3

F^C= 8 kHZ

10

2

1

6.0

V^CC(V)

3.0

4.0

5.0

3

5

4

6

V^CC(V)

109

MB90570 Series

I^CCT- TA

I^CCH- TA

I^CCT(µA)

ICCH (µA)

10

9

8

9

8

7

6

7

6

5

4

3

2

1

5

4

3

2

1

VCC = 6.0 V

V^CC= 5.5 V

V^CC= 5.0 V

V^CC= 4.5 V

V^CC= 4.0 V

V^CC= 3.5 V

V^CC= 3.0 V

V^CC= 2.5 V

VCC = 6.0 V

V^CC= 5.5 V

V^CC= 5.0 V

V^CC= 4.5 V

VCC = 4.0 V

V^CC= 3.5 V

V^CC= 3.0 V

V^CC= 2.5 V

+10

+40 +70

+100

T^A(°C)

+40 +70

+100

T^A(°C)

-20

+10

-20

I^CCLS- TA

I^CCLS(µA)

20

18

16

V^CC= 6.0 V

V^CC= 5.5 V

V^CC= 5.0 V

14

12

V^CC= 4.5 V

V^CC= 4.0 V

10

8

V^CC= 3.5 V

V^CC= 3.0 V

6

V^CC= 2.5 V

4

2

+40 +70

+100

T^A(°C)

+10

-20

110

MB90570 Series

(3)Power Supply Current (MB90574C)

I^CC(mA)

50

I^CC(mA)

ICC − TA

V^CC= 5.0 V

ICC − VCC

T^A= +25 °C

70

60

50

40

30

20

10

0

F^C= 16 MHz

45

40

35

30

25

20

15

10

F^C= 16 MHz

F^C= 12 MHz

F^C= 10 MHz

F^C= 8 MHz

F^C= 12 MHz

F^C= 10 MHz

F^C= 8 MHz

F^C= 5 MHz

F^C= 4 MHz

F^C= 2 MHz

FC = 5 MHz

F^C= 4 MHz

FC = 2 MHz

5

0

−50

−20

10

40

70

100

3.0

3.5

4.0

4.5

5.0

5.5

6.0

TA (°C)

VCC (V)

I^CCS(mA)

18

I^CC(mA)

70

ICCS − VCC

T^A= +25 °C

ICC − FC

T^A= +25 °C

F^C= 16 MHz

16

14

60

50

40

30

20

10

V^CC= 6.0 V

V^CC= 5.5 V

V^CC= 5.0 V

F^C= 12 MHz

F^C= 10 MHz

F^C= 8 MHz

12

10

8

V^CC= 4.5 V

V^CC= 4.0 V

V^CC= 3.5 V

V^CC= 3.0 V

F^C= 5 MHz

F^C= 4 MHz

6

4

2

0

F^C= 2 MHz

0

2

3.000 3.500 4.000

5.000

6.000

5.500

4

6

10 12

16

14

4.500

8

VCC (V)

FC (MHz)

I^CCS(mA)

18

I^CCS(mA)

ICCS − TA

VCC = 5 V

ICCS − FC

T^A= +25 °C

18

16

14

12

10

8

V^CC= 6.0 V

16

14

12

10

8

V^CC= 5.5 V

F^C= 16 MHz

VCC = 5.0 V

V^CC= 4.5 V

F^C= 12 MHz

F^C= 10 MHz

FC = 8 MHz

F^C= 4 MHz

F^C= 2 MHz

VCC = 4.0 V

V^CC= 3.5 V

VCC = 3.0 V

6

4

2

4

2

0

−50

0

2

−20

10

40

70

100

4

6

8

10 12 14

16

TA (°C)

FC (MHz)

111

MB90570 Series

I^CCH(µA)

I^CCH− VCC

TA = +25 °C

ICCH − TA

10

9

8

7

6

5

4

3

2

1

0

10

9

8

7

6

5

4

3

2

1

VCC = 6.0 V

V^CC= 5.5 V

VCC = 5.0 V

VCC = 4.5 V

V^CC= 4.0 V

VCC = 3.5 V

VCC = 3.0 V

0

−50

3.000 3.500 4.000 4.500 5.000 5.500 6.000

V^CC(V)

−20

10

40

70

100

T^A(°C)

I^CCT(µA)

ICCT − TA

ICCT − VCC

TA = +25 °C

10

9

8

7

6

5

4

3

2

1

0

10

9

8

7

6

5

4

3

2

1

0

VCC = 6.0 V

VCC = 5.5 V

V^CC= 5.0 V

VCC = 4.5 V

VCC = 4.0 V

V^CC= 3.5 V

VCC = 3.0 V

F^C= 8 kHz

−50

−20

10

40

70

100

T^A(°C)

3.000 3.500 4.000 4.500 5.000 5.500 6.000

V^CC(V)

I^CCL(µA)

70

I^CCL(µA)

70

ICCL − VCC

TA = +25 °C

ICCL − TA

60

50

40

30

20

10

0

60

50

40

30

20

10

0

VCC = 6.0 V

V^CC= 5.5 V

VCC = 5.0 V

VCC = 4.5 V

VCC = 4.0 V

V^CC= 3.5 V

VCC = 3.0 V

F^C= 8 kHz

−50 −20

10

40

70

100

T^A(°C)

3.000 3.500 4.000 4.500 5.000 5.500 6.000

V^CC(V)

112

MB90570 Series

I^CCLS(µA)

25

I^CCLS(µA)

25

ICCLS − VCC

TA = +25 °C

ICCLS − TA

20

15

10

5

20

15

10

5

VCC = 6.0 V

VCC = 5.5 V

VCC = 5.0 V

VCC = 4.5 V

V^CC= 4.0 V

VCC = 3.5 V

VCC = 3.0 V

F^C= 8 kHz

0

−50 −20

10

40

70

100

T^A(°C)

3.000 3.500 4.000 4.500 5.000 5.500 6.000

V^CC(V)

113

MB90570 Series

■ INSTRUCTIONS (351 INSTRUCTIONS)

Table 1 Explanation of Items in Tables of Instructions

Meaning

Mnemonic Upper-case letters and symbols: Represented as they appear in assembler.

Item

Lower-case letters: Replaced when described in assembler.

Numbers after lower-case letters:Indicate the bit width within the instruction code.

#

~

Indicates the number of bytes.

Indicates the number of cycles.

m: When branching

n : When not branching

See Table 4 for details about meanings of other letters in items.

RG

B

Indicates the number of accesses to the register during execution of the instruction.

It is used calculate a correction value for intermittent operation of CPU.

Indicates the correction value for calculating the number of actual cycles during execution of the

instruction. (Table 5)

The number of actual cycles during execution of the instruction is the correction value summed

with the value in the “~” column.

Operation

LH

Indicates the operation of instruction.

Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.

Z : Transfers “0”.

X : Extends with a sign before transferring.

– : Transfers nothing.

AH

Indicates special operations involving the upper 16 bits in the accumulator.

* : Transfers from AL to AH.

– : No transfer.

Z : Transfers 00^Hto AH.

X : Transfers 00H or FFH to AH by signing and extending AL.

I

Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),

N (negative), Z (zero), V (overflow), and C (carry).

* : Changes due to execution of instruction.

– : No change.

S

T

N

Z

S : Set by execution of instruction.

R : Reset by execution of instruction.

V

C

RMW

Indicates whether the instruction is a read-modify-write instruction. (a single instruction that

reads data from memory, etc., processes the data, and then writes the result to memory.)

* : Instruction is a read-modify-write instruction.

– : Instruction is not a read-modify-write instruction.

Note: A read-modify-write instruction cannot be used on addresses that have different

meanings depending on whether they are read or written.

• Number of execution cycles

The number of cycles required for instruction execution is acquired by adding the number of cycles for each

instruction, a corrective value depending on the condition, and the number of cycles required for program fetch.

Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal

ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution

cycles is increased.

For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data

bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased.

When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external

bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles

specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number

of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the

number of times access is done × the number of cycles suspended as the corrective value to the number of

ordinary execution cycles.

114

MB90570 Series

Table 2 Explanation of Symbols in Tables of Instructions

Meaning

Symbol

A

32-bit accumulator

The bit length varies according to the instruction.

Byte : Lower 8 bits of AL

Word : 16 bits of AL

Long : 32 bits of AL and AH

AH

AL

Upper 16 bits of A

Lower 16 bits of A

SP

PC

Stack pointer (USP or SSP)

Program counter

PCB

DTB

ADB

SSB

USB

SPB

DPR

brg1

brg2

Ri

Program bank register

Data bank register

Additional data bank register

System stack bank register

User stack bank register

Current stack bank register (SSB or USB)

Direct page register

DTB, ADB, SSB, USB, DPR, PCB, SPB

DTB, ADB, SSB, USB, DPR, SPB

R0, R1, R2, R3, R4, R5, R6, R7

RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

RW0, RW1, RW2, RW3

RWi

RWj

RLi

RL0, RL1, RL2, RL3

dir

Compact direct addressing

addr16

addr24

ad24 0 to 15

ad24 16 to 23

Direct addressing

Physical direct addressing

Bit 0 to bit 15 of addr24

Bit 16 to bit 23 of addr24

io

I/O area (000000^Hto 0000FFH)

imm4

imm8

4-bit immediate data

8-bit immediate data

imm16

imm32

ext (imm8)

16-bit immediate data

32-bit immediate data

16-bit data signed and extended from 8-bit immediate data

disp8

disp16

8-bit displacement

16-bit displacement

bp

Bit offset

vct4

vct8

Vector number (0 to 15)

Vector number (0 to 255)

( )b

rel

Bit address

PC relative addressing

ear

eam

Effective addressing (codes 00 to 07)

Effective addressing (codes 08 to 1F)

rlst

Register list

115

MB90570 Series

Table 3 Effective Address Fields

Address format

Number of bytes in address

extension *

Code

Notation

00

01

02

03

04

05

06

07

R0

R1

R2

R3

R4

R5

R6

R7

RW0

RW1

RW2

RW3

RW4

RW5

RW6

RW7

RL0 Register direct

(RL0)

RL1 “ea” corresponds to byte, word, and

(RL1) long-word types, starting from the left

RL2

(RL2)

RL3

—

(RL3)

08

09

0A

0B

@RW0

Register indirect

@RW1

@RW2

@RW3

0

0C

0D

0E

0F

@RW0 +

@RW1 +

@RW2 +

@RW3 +

Register indirect with post-increment

10

11

12

13

14

15

16

17

@RW0 + disp8

@RW1 + disp8

@RW2 + disp8

@RW3 + disp8

@RW4 + disp8

@RW5 + disp8

@RW6 + disp8

@RW7 + disp8

Register indirect with 8-bit

displacement

1

2

18

19

1A

1B

@RW0 + disp16

@RW1 + disp16

@RW2 + disp16

@RW3 + disp16

Register indirect with 16-bit

displacement

1C

1D

1E

1F

@RW0 + RW7

@RW1 + RW7

@PC + disp16

addr16

Register indirect with index

PC indirect with 16-bit displacement

Direct address

0

2

Note : The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)

column in the tables of instructions.

116

MB90570 Series

Table 4 Number of Execution Cycles for Each Type of Addressing

(a)

Number of register accesses

for each type of addressing

Code

Operand

Number of execution cycles

for each type of addressing

Ri

RWi

RLi

00 to 07

Listed in tables of instructions Listed in tables of instructions

08 to 0B

0C to 0F

10 to 17

18 to 1B

@RWj

2

4

2

1

2

1

@RWj +

@RWi + disp8

@RWj + disp16

1C

1D

1E

1F

@RW0 + RW7

@RW1 + RW7

@PC + disp16

addr16

4

2

1

2

0

Note : “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.

Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles

(b) byte

(c) word

(d) long

Operand

Cycles

Access

Cycles

Access

Cycles

Access

Internal register

+0

1

+0

1

+0

2

Internal memory even address

Internal memory odd address

+0

1

+0

+2

1

2

+0

+4

2

4

Even address on external data bus (16 bits)

Odd address on external data bus (16 bits)

+1

1

+1

+4

1

2

+2

+8

2

4

External data bus (8 bits)

+1

1

+4

2

+8

4

Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)

in the tables of instructions.

• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready

input and automatic ready.

Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles

Instruction

Internal memory

Byte boundary

Word boundary

—

+3

+2

+3

—

External data bus (16 bits)

External data bus (8 bits)

Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready

input and automatic ready.

• Because instruction execution is not slowed down by all program fetches in actuality, these correction

values should be used for “worst case” calculations.

117

MB90570 Series

Table 7 Transfer Instructions (Byte) [41 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

MOV

A, dir

A, addr16

A, Ri

A, ear

A, eam

A, io

A, #imm8

A, @A

A, @RLi+disp8

2

3

1

2

3

4

2

0

1

0

2

0

(b) byte (A) ← (dir)

(b) byte (A) ← (addr16)

Z

*

–

*

–

*

–

0

byte (A) ← (Ri)

byte (A) ← (ear)

2+ 3+ (a)

(b) byte (A) ← (eam)

(b) byte (A) ← (io)

2

3

1

3

2

3

10

1

0

byte (A) ← imm8

(b) byte (A) ← ((A))

(b) byte (A) ← ((RLi)+disp8) Z

MOVN A, #imm4

0

byte (A) ← imm4

Z

– R

MOVX A, dir

MOVX A, addr16

MOVX A, Ri

MOVX A, ear

MOVX A, eam

MOVX A, io

MOVX A, #imm8

MOVX A, @A

MOVX A,@RWi+disp8

MOVX A, @RLi+disp8

2

3

2

3

4

2

0

1

0

1

2

(b) byte (A) ← (dir)

(b) byte (A) ← (addr16)

X

*

–

*

–

*

–

0

byte (A) ← (Ri)

byte (A) ← (ear)

2+ 3+ (a)

(b) byte (A) ← (eam)

(b) byte (A) ← (io)

2

3

2

3

5

10

0

byte (A) ← imm8

(b) byte (A) ← ((A))

(b) byte (A) ← ((RWi)+disp8) X

(b) byte (A) ← ((RLi)+disp8) X

MOV

dir, A

addr16, A

Ri, A

ear, A

eam, A

io, A

@RLi+disp8, A

Ri, ear

Ri, eam

ear, Ri

eam, Ri

Ri, #imm8

io, #imm8

dir, #imm8

ear, #imm8

eam, #imm8

@AL, AH

2

3

1

2

3

4

2

0

1

0

2

1

2

1

0

1

0

(b) byte (dir) ← (A)

(b) byte (addr16) ← (A)

–

*

–

*

–

*

–

*

–

0

byte (Ri) ← (A)

byte (ear) ← (A)

2+ 3+ (a)

(b) byte (eam) ← (A)

(b) byte (io) ← (A)

(b) byte ((RLi) +disp8) ← (A) –

2

3

2

3

10

3

0

byte (Ri) ← (ear)

(b) byte (Ri) ← (eam)

byte (ear) ← (Ri)

(b) byte (eam) ← (Ri)

byte (Ri) ← imm8

–

2+ 4+ (a)

2

2+ 5+ (a)

2

3

4

0

2

5

2

0

(b) byte (io) ← imm8

(b) byte (dir) ← imm8

0

byte (ear) ← imm8

3+ 4+ (a)

(b) byte (eam) ← imm8

/MOV @A, T

2

3

0

(b) byte ((A)) ← (AH)

–

*

–

XCH

A, ear

4

2

0

4

2

0

byte (A) ↔ (ear)

2× (b) byte (A) ↔ (eam)

byte (Ri) ↔ (ear)

2× (b) byte (Ri) ↔ (eam)

Z

–

A, eam

Ri, ear

Ri, eam

2+ 5+ (a)

2

2+ 9+ (a)

7

0

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

118

MB90570 Series

Table 8 Transfer Instructions (Word/Long Word) [38 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

MOVW A, dir

MOVW A, addr16

MOVW A, SP

MOVW A, RWi

MOVW A, ear

MOVW A, eam

MOVW A, io

MOVW A, @A

#

~

B

Operation

2

3

1

2

3

4

1

2

0

1

0

1

2

(c) word (A) ← (dir)

(c) word (A) ← (addr16)

0

(c) word (A) ← (eam)

(c) word (A) ← (io)

(c) word (A) ← ((A))

0

(c)

–

*

–

*

–

*

–

word (A) ← (SP)

word (A) ← (RWi)

word (A) ← (ear)

2+ 3+ (a)

2

3

2

3

2

5

10

MOVW A, #imm16

MOVW A,@RWi+disp8

MOVW A, @RLi+disp8

word (A) ← imm16

word (A) ← ((RWi) +disp8)

word (A) ← ((RLi) +disp8)

MOVW dir, A

MOVW addr16, A

MOVW SP, A

MOVW RWi, A

MOVW ear, A

MOVW eam, A

MOVW io, A

MOVW @RWi+disp8,A

MOVW @RLi+disp8, A

MOVW RWi, ear

MOVW RWi, eam

MOVW ear, RWi

MOVW eam, RWi

MOVW RWi, #imm16

MOVW io, #imm16

MOVW ear, #imm16

MOVW eam, #imm16

MOVW @AL, AH

/MOVW@A, T

2

3

1

2

3

4

1

2

0

1

0

1

2

1

2

1

0

1

0

(c) word (dir) ← (A)

(c) word (addr16) ← (A)

–

*

–

*

–

*

–

*

–

0

word (SP) ← (A)

word (RWi) ← (A)

word (ear) ← (A)

2+ 3+ (a)

(c) word (eam) ← (A)

(c) word (io) ← (A)

2

3

2

3

5

10

3

word ((RWi) +disp8) ← (A)

word ((RLi) +disp8) ← (A)

(c)

(0) word (RWi) ← (ear)

(c) word (RWi) ← (eam)

2+ 4+ (a)

2

2+ 5+ (a)

3

4

0

word (ear) ← (RWi)

(c) word (eam) ← (RWi)

word (RWi) ← imm16

(c) word (io) ← imm16

word (ear) ← imm16

2

5

2

0

4+ 4+ (a)

(c) word (eam) ← imm16

2

3

4

0

(c) word ((A)) ← (AH)

–

*

–

XCHW A, ear

2

0

4

2

0

word (A) ↔ (ear)

2× (c) word (A) ↔ (eam)

word (RWi) ↔ (ear)

2× (c) word (RWi) ↔ (eam)

–

XCHW A, eam

XCHW RWi, ear

XCHW RWi, eam

2+ 5+ (a)

2

2+ 9+ (a)

7

0

MOVL A, ear

MOVL A, eam

MOVL A, #imm32

2

4

2

0

long (A) ← (ear)

–

*

–

2+ 5+ (a)

5

(d) long (A) ← (eam)

0

3

long (A) ← imm32

long (ear) ← (A)

MOVL ear, A

MOVL eam, A

2

4

2

0

–

*

–

2+ 5+ (a)

(d) long (eam) ← (A)

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

119

MB90570 Series

Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

ADD A,#imm8

#

~

B

Operation

2

5

3

0

1

0

2

0

1

0

1

0

2

0

1

0

byte (A) ← (A) +imm8

Z

–

Z

–

*

–

*

–

*

ADD

ADDC

A, dir

A, ear

A, eam

ear, A

eam, A

A

(b) byte (A) ← (A) +(dir)

byte (A) ← (A) +(ear)

(b) byte (A) ← (A) +(eam)

byte (ear) ← (ear) + (A)

2× (b) byte (eam) ← (eam) + (A)

0

2+ 4+ (a)

2

2+ 5+ (a)

1

2

3

0

2

3

0

byte (A) ← (AH) + (AL) + (C) Z

byte (A) ← (A) + (ear) + (C)

ADDC A, ear

ADDC A, eam

ADDDC A

Z

2+ 4+ (a)

(b) byte (A) ← (A) + (eam) + (C) Z

byte (A) ← (AH) + (AL) + (C) (decimal)

1

2

3

2

5

3

0

Z

–

SUB

SUBC

A, #imm8

A, dir

A, ear

A, eam

ear, A

eam, A

A

byte (A) ← (A) –imm8

(b) byte (A) ← (A) – (dir)

byte (A) ← (A) – (ear)

(b) byte (A) ← (A) – (eam)

byte (ear) ← (ear) – (A)

2× (b) byte (eam) ← (eam) – (A)

0

2+ 4+ (a)

2

2+ 5+ (a)

1

2

2+ 4+ (a)

1

3

0

2

3

0

byte (A) ← (AH) – (AL) – (C) Z

byte (A) ← (A) – (ear) – (C)

–

SUBC A, ear

SUBC A, eam

SUBDC A

Z

(b) byte (A) ← (A) – (eam) – (C) Z

byte (A) ← (AH) – (AL) – (C) (decimal)

3

0

Z

ADDW A

1

2

3

0

1

0

2

0

1

0

1

0

2

0

1

0

word (A) ← (AH) + (AL)

word (A) ← (A) +(ear)

–

*

–

*

–

*

ADDW A, ear

ADDW A, eam

ADDW A, #imm16

ADDW ear, A

ADDW eam, A

ADDCWA, ear

ADDCWA, eam

SUBW A

SUBW A, ear

SUBW A, eam

SUBW A, #imm16

SUBW ear, A

SUBW eam, A

SUBCW A, ear

SUBCW A, eam

2+ 4+ (a)

3

2

2+ 5+ (a)

2

2+ 4+ (a)

1

2

2+ 4+ (a)

3

2

(c) word (A) ← (A) +(eam)

0

2

3

word (A) ← (A) +imm16

word (ear) ← (ear) + (A)

2× (c) word (eam) ← (eam) + (A)

word (A) ← (A) + (ear) + (C)

3

0

(c) word (A) ← (A) + (eam) + (C) –

0

(c) word (A) ← (A) – (eam)

0

2

3

word (A) ← (AH) – (AL)

word (A) ← (A) – (ear)

–

2

3

word (A) ← (A) –imm16

word (ear) ← (ear) – (A)

2+ 5+ (a)

2

2+ 4+ (a)

2× (c) word (eam) ← (eam) – (A)

word (A) ← (A) – (ear) – (C)

3

0

–

(c) word (A) ← (A) – (eam) – (C) –

ADDL A, ear

2

6

2

0

2

0

long (A) ← (A) + (ear)

–

*

–

ADDL A, eam

ADDL A, #imm32

SUBL A, ear

SUBL A, eam

SUBL A, #imm32

2+ 7+ (a)

5

2

2+ 7+ (a)

5

(d) long (A) ← (A) + (eam)

0

4

6

long (A) ← (A) +imm32

long (A) ← (A) – (ear)

(d) long (A) ← (A) – (eam)

long (A) ← (A) –imm32

4

0

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

120

MB90570 Series

Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

INC

ear

eam

2

0

byte (ear) ← (ear) +1

–

*

–

*

2+ 5+ (a)

2× (b) byte (eam) ← (eam) +1

DEC

ear

eam

2

3

2

0

byte (ear) ← (ear) –1

–

*

–

*

2+ 5+ (a)

2× (b) byte (eam) ← (eam) –1

INCW ear

INCW eam

2

3

2

0

word (ear) ← (ear) +1

–

*

–

*

2+ 5+ (a)

2× (c) word (eam) ← (eam) +1

DECW ear

DECW eam

2

3

2

0

word (ear) ← (ear) –1

–

*

–

*

2+ 5+ (a)

2× (c) word (eam) ← (eam) –1

INCL ear

INCL eam

2

7

4

0

long (ear) ← (ear) +1

–

*

–

*

2+ 9+ (a)

2× (d) long (eam) ← (eam) +1

DECL ear

DECL eam

2

7

4

0

long (ear) ← (ear) –1

–

*

–

*

2+ 9+ (a)

2× (d) long (eam) ← (eam) –1

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 11 Compare Instructions (Byte/Word/Long Word) [11 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

CMP

A

1

2

1

2

0

1

0

byte (AH) – (AL)

byte (A) ← (ear)

–

*

–

CMP

A, ear

A, eam

A, #imm8

2+ 3+ (a)

2

(b) byte (A) ← (eam)

0

2

byte (A) ← imm8

CMPW A

1

2

1

2

0

1

0

word (AH) – (AL)

word (A) ← (ear)

–

*

–

CMPW A, ear

CMPW A, eam

CMPW A, #imm16

2+ 3+ (a)

3

(c) word (A) ← (eam)

0

2

word (A) ← imm16

CMPL A, ear

CMPL A, eam

CMPL A, #imm32

2

6

2

0

word (A) ← (ear)

–

*

–

2+ 7+ (a)

5

(d) word (A) ← (eam)

word (A) ← imm32

3

0

Note:Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

121

MB90570 Series

Table 12 Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]

LH AH

I

S

T

N

Z

V

C

RMW

RG

Mnemonic

#

~

B

Operation

1

DIVU

A

1

0

0 word (AH) /byte (AL)

–

*

–

*

Quotient → byte (AL) Remainder → byte (AH)

2

DIVU

A, ear

2

1

0

1

0

0 word (A)/byte (ear)

–

*

–

*

Quotient → byte (A) Remainder → byte (ear)

6

3

A, eam 2+

word (A)/byte (eam)

Quotient → byte (A) Remainder → byte (eam)

*

4

DIVUW A, ear

2

long (A)/word (ear)

Quotient → word (A) Remainder → word (ear)

0

*

7

5

DIVUW A, eam 2+

long (A)/word (eam)

Quotient → word (A) Remainder → word (eam)

*

8

MULU

MULU A, ear

MULU A, eam 2+

A

1

2

0

1

0

byte (AH) *byte (AL) → word (A)

byte (A) *byte (ear) → word (A)

byte (A) *byte (eam) → word (A)

–

0

(b)

*

9

*

10

*

MULUW A

MULUW A, ear

MULUW A, eam 2+

1

2

11

12

13

0

1

0

word (AH) *word (AL) → long (A)

word (A) *word (ear) → long (A)

word (A) *word (eam) → long (A)

–

0

(c)

*

*1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally.

*2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally.

*3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.

*4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally.

*5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.

*6: (b) when the result is zero or when an overflow occurs, and 2 × (b) normally.

*7: (c) when the result is zero or when an overflow occurs, and 2 × (c) normally.

*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not zero.

*9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero.

*10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.

*11: 3 when word (AH) is zero, and 11 when word (AH) is not zero.

*12: 4 when word (ear) is zero, and 12 when word (ear) is not zero.

*13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

122

MB90570 Series

Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

DIV

A

2

*1

0

word (AH) /byte (AL)

Quotient → byte (AL)

Remainder → byte (AH)

word (A)/byte (ear)

Z

–

*

–

DIV

A, ear

2

*2

1

0

1

0

–

*

–

Quotient → byte (A)

Remainder → byte (ear)

DIV

A, eam 2 + *3

*6 word (A)/byte (eam)

Quotient → byte (A)

Remainder → byte (eam)

long (A)/word (ear)

DIVW

A, ear

2

*4

0

Quotient → word (A)

Remainder → word (ear)

A, eam 2+ *5

*7 long (A)/word (eam)

Quotient → word (A)

Remainder → word (eam)

MULU

MULUW A

MULUW A, ear

A

A, ear

A, eam 2 + *10

2

*8

*9

0

1

0

1

0

byte (AH) *byte (AL) → word (A)

byte (A) *byte (ear) → word (A)

–

(b) byte (A) *byte (eam) → word (A)

0

2

*11

*12

word (AH) *word (AL) → long (A)

word (A) *word (ear) → long (A)

MULUW A, eam 2 + *13

(c) word (A) *word (eam) → long (A)

*1: Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation.

*2: Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation.

*3: Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation.

*4: Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation.

Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation.

*5: Positive dividend:Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for

normal operation.

Negative dividend:Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for

normal operation.

*6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation.

*7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation.

*8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.

*9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.

*10: Setto4+(a)whenbyte(eam)iszero, 13+(a)whentheresultispositive, and14+(a)whentheresultisnegative.

*11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.

*12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.

*13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is

negative.

Notes: • When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes

two values because of detection before and after an operation.

• When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.

• For (a) to (d), refer to “Table 4 Number of Execution Cycles for Effective Address in Addressing Modes”

and “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”

123

MB90570 Series

Table 14 Logical 1 Instructions (Byte/Word) [39 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

AND A, #imm8

#

~

B

Operation

2

3

0

1

0

2

0

byte (A) ← (A) and imm8

byte (A) ← (A) and (ear)

–

*

R

–

*

AND

A, ear

A, eam

ear, A

2+ 4+ (a)

2

2+ 5+ (a)

(b) byte (A) ← (A) and (eam)

byte (ear) ← (ear) and (A)

3

0

eam, A

2× (b) byte (eam) ← (eam) and (A) –

OR

A, #imm8

A, ear

A, eam

ear, A

2

3

0

1

0

2

0

byte (A) ← (A) or imm8

byte (A) ← (A) or (ear)

–

*

R

–

*

2+ 4+ (a)

2

2+ 5+ (a)

(b) byte (A) ← (A) or (eam)

byte (ear) ← (ear) or (A)

2× (b) byte (eam) ← (eam) or (A)

3

0

eam, A

XOR A, #imm8

XOR A, ear

XOR A, eam

XOR ear, A

XOR eam, A

2

3

0

1

0

2

0

byte (A) ← (A) xor imm8

byte (A) ← (A) xor (ear)

–

*

R

–

*

2+ 4+ (a)

2

2+ 5+ (a)

(b) byte (A) ← (A) xor (eam)

byte (ear) ← (ear) xor (A)

3

0

2× (b) byte (eam) ← (eam) xor (A) –

NOT

A

ear

eam

1

2

3

0

2

0

byte (A) ← not (A)

byte (ear) ← not (ear)

–

*

R

–

*

2+ 5+ (a)

2× (b) byte (eam) ← not (eam)

ANDW A

1

3

2

3

0

1

0

2

0

word (A) ← (AH) and (A)

word (A) ← (A) and imm16

word (A) ← (A) and (ear)

–

*

R

–

*

ANDW A, #imm16

ANDW A, ear

ANDW A, eam

ANDW ear, A

ANDW eam, A

2+ 4+ (a)

2

2+ 5+ (a)

(c) word (A) ← (A) and (eam)

word (ear) ← (ear) and (A)

2× (c) word (eam) ← (eam) and (A)

3

0

ORW

A

1

3

2

3

0

1

0

2

0

word (A) ← (AH) or (A)

word (A) ← (A) or imm16

word (A) ← (A) or (ear)

–

*

R

–

*

ORW A, #imm16

ORW A, ear

ORW A, eam

ORW ear, A

2+ 4+ (a)

2

2+ 5+ (a)

(c) word (A) ← (A) or (eam)

word (ear) ← (ear) or (A)

2× (c) word (eam) ← (eam) or (A)

3

0

ORW eam, A

XORW A

1

3

2

3

0

1

0

2

0

word (A) ← (AH) xor (A)

word (A) ← (A) xor imm16

word (A) ← (A) xor (ear)

–

*

R

–

*

XORW A, #imm16

XORW A, ear

XORW A, eam

XORW ear, A

XORW eam, A

2+ 4+ (a)

2

2+ 5+ (a)

(c) word (A) ← (A) xor (eam)

word (ear) ← (ear) xor (A)

2× (c) word (eam) ← (eam) xor (A)

3

0

NOTW A

NOTW ear

NOTW eam

1

2

3

0

2

0

word (A) ← not (A)

word (ear) ← not (ear)

–

*

R

–

*

2+ 5+ (a)

2× (c) word (eam) ← not (eam)

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

124

MB90570 Series

Table 15 Logical 2 Instructions (Long Word) [6 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

ANDL A, ear

ANDL A, eam

2

6

2

0

long (A) ← (A) and (ear)

–

*

R

–

2+ 7+ (a)

(d) long (A) ← (A) and (eam)

ORL

A, ear

A, eam

2

6

2

0

long (A) ← (A) or (ear)

–

*

R

–

2+ 7+ (a)

(d) long (A) ← (A) or (eam)

XORL A, ea

XORL A, eam

2

6

2

0

long (A) ← (A) xor (ear)

–

*

R

–

2+ 7+ (a)

(d) long (A) ← (A) xor (eam)

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 16 Sign Inversion Instructions (Byte/Word) [6 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

NEG

A

1

2

0

byte (A) ← 0 – (A)

X

–

*

–

NEG ear

NEG eam

2

3

2

0

byte (ear) ← 0 – (ear)

–

*

–

*

2+ 5+ (a)

2× (b) byte (eam) ← 0 – (eam)

NEGW A

1

2

0

word (A) ← 0 – (A)

–

*

–

NEGW ear

NEGW eam

2

3

2

0

word (ear) ← 0 – (ear)

–

*

–

*

2+ 5+ (a)

2× (c) word (eam) ← 0 – (eam)

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 17 Normalize Instruction (Long Word) [1 Instruction]

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

RG

B

Operation

1

NRML A, R0

2

1

0

long (A) ← Shift until first digit is “1” –

byte (R0) ← Current shift count

–

*

–

*

*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

125

MB90570 Series

Table 18 Shift Instructions (Byte/Word/Long Word) [18 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

RORC A

#

~

B

Operation

byte (A) ← Right rotation with carry

byte (A) ← Left rotation with carry

2

0

–

*

–

*

–

ROLC A

RORC ear

RORC eam

ROLC ear

ROLC eam

byte (ear) ← Right rotation with carry

byte (eam) ← Right rotation with carry

byte (ear) ← Left rotation with carry

byte (eam) ← Left rotation with carry

2

2+

2

3

2

0

–

*

–

*

–

*

–

*

5+ (a)

0 2× (b)

2

0 2× (b)

0

3

2+

5+ (a)

byte (A) ← Arithmetic right barrel shift (A, R0)

byte (A) ← Logical right barrel shift (A, R0)

byte (A) ← Logical left barrel shift (A, R0)

ASR A, R0

LSR A, R0

LSL A, R0

1

2

1

0

–

*

–

*

–

*

–

*

1

*

1

*

word (A) ← Arithmetic right shift (A, 1 bit)

word (A) ← Logical right shift (A, 1 bit)

word (A) ← Logical left shift (A, 1 bit)

ASRW A

LSRW A/SHRW A

LSLW A/SHLW A

1

2

0

–

*

–

*

R

*

–

*

–

1

word (A) ← Arithmetic right barrel shift (A,

R0)

ASRW A, R0

LSRW A, R0

LSLW A, R0

2

1

0

–

*

–

*

–

*

–

*

1

*

1

word (A) ← Logical right barrel shift (A, R0)

word (A) ← Logical left barrel shift (A, R0)

*

2

ASRL A, R0

LSRL A, R0

LSLL A, R0

long (A) ← Arithmetic right shift (A, R0)

long (A) ← Logical right barrel shift (A, R0)

long (A) ← Logical left barrel shift (A, R0)

2

1

0

–

*

–

*

–

*

–

*

2

*

2

*

*1: 6 when R0 is 0, 5 + (R0) in all other cases.

*2: 6 when R0 is 0, 6 + (R0) in all other cases.

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

126

MB90570 Series

Table 19 Branch 1 Instructions [31 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

1

BZ/BEQ

BNZ/BNE rel

BC/BLO

BNC/BHS rel

rel

2

*

0

Branch when (Z) = 1

Branch when (Z) = 0

Branch when (C) = 1

Branch when (C) = 0

Branch when (N) = 1

Branch when (N) = 0

Branch when (V) = 1

Branch when (V) = 0

Branch when (T) = 1

Branch when (T) = 0

Branch when (V) xor (N) = 1

Branch when (V) xor (N) = 0

Branch when ((V) xor (N)) or (Z) = 1

Branch when ((V) xor (N)) or (Z) = 0

Branch when (C) or (Z) = 1

Branch when (C) or (Z) = 0

Branch unconditionally

–

1

rel

1

BN

BP

BV

BNV

BT

BNT

BLT

BGE

BLE

BGT

BLS

BHI

BRA

rel

1

*

JMP

@A

1

3

2

3

0

1

0

2

0

word (PC) ← (A)

word (PC) ← addr16

word (PC) ← (ear)

–

addr16

@ear

@eam

2+ 4+ (a)

2

2+ 6+ (a)

4

(c) word (PC) ← (eam)

0

(d)

0

JMPP @ear *³

JMPP @eam *³

JMPP addr24

word (PC) ← (ear), (PCB) ← (ear +2)

5

word (PC) ← (eam), (PCB) ← (eam +2)

4

word (PC) ← ad24 0 to 15,

(PCB) ← ad24 16 to 23

CALL @ear *⁴

CALL @eam *⁴

CALL addr16 *⁵

CALLV #vct4 *⁵

CALLP @ear *⁶

2

6

1

0

2

(c) word (PC) ← (ear)

–

2+ 7+ (a)

2× (c) word (PC) ← (eam)

(c) word (PC) ← addr16

2× (c) Vector call instruction

2× (c) word (PC) ← (ear) 0 to 15,

3

1

2

6

7

10

(PCB) ← (ear) 16 to 23

2

CALLP @eam *⁶

CALLP addr24 *⁷

2+ 11+ (a)

10

0

word (PC) ← (eam) 0 to 15,

(PCB) ← (eam) 16 to 23

word (PC) ← addr0 to 15,

(PCB) ← addr16 to 23

–

*

4

2× (c)

*1: 4 when branching, 3 when not branching.

*2: (b) + 3 × (c)

*3: Read (word) branch address.

*4: W: Save (word) to stack; R: read (word) branch address.

*5: Save (word) to stack.

*6: W: Save (long word) to W stack; R: read (long word) R branch address.

*7: Save (long word) to stack.

Note:Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

127

MB90570 Series

Table 20 Branch 2 Instructions [19 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

1

Branch when byte (A) ≠ imm8

Branch when word (A) ≠ imm16

CBNE A, #imm8, rel

CWBNE A, #imm16, rel

3

4

0

–

– – – – *

*

–

*

1

2

Branch when byte (ear) ≠ imm8

Branch when byte (eam) ≠ imm8

Branch when word (ear) ≠ imm16

Branch when word (eam) ≠ imm16

CBNE ear, #imm8, rel

4

4+

5

*

1

0

1

0

(b)

0

–

– – – – *

*

–

CBNE

eam, #imm8, rel*¹⁰

3

4

CWBNE ear, #imm16, rel

CWBNE eam, #imm16, rel*¹⁰

3

5+

(c)

5

DBNZ ear, rel

DBNZ eam, rel

3

2

0

Branch when byte (ear) =

(ear) – 1, and (ear) ≠ 0

–

– – – – *

*

* –

–

*

6

*

3+

2× (b) Branch when byte (eam) =

(eam) – 1, and (eam) ≠ 0

5

DWBNZ ear, rel

DWBNZ eam, rel

3

*

2

0

Branch when word (ear) =

(ear) – 1, and (ear) ≠ 0

–

– – – – *

*

* –

–

*

6

3+

2× (c) Branch when word (eam) =

(eam) – 1, and (eam) ≠ 0

*

INT

INTP

INT9

RETI

#vct8

addr16

addr24

8× (c)

6× (c)

8× (c)

2

3

4

1

0

Software interrupt

Return from interrupt

–

– R S – – – – –

–

20

16

17

20

15

7

*

–

*

LINK

#imm8

(c)

2

0

At constant entry, save old

frame pointer to stack, set

new frame pointer, and

allocate local pointer area

At constant entry, retrieve old

frame pointer from stack.

–

– – – – – – – –

–

6

UNLINK

1

0

–

– – – – – – – –

–

5

RET *⁸

(c)

(d)

1

0

Return from subroutine

–

– – – – – – – –

–

4

6

RETP *⁹

*1: 5 when branching, 4 when not branching

*2: 13 when branching, 12 when not branching

*3: 7 + (a) when branching, 6 + (a) when not branching

*4: 8 when branching, 7 when not branching

*5: 7 when branching, 6 when not branching

*6: 8 + (a) when branching, 7 + (a) when not branching

*7: Set to 3 × (b) + 2 × (c) when an interrupt request occurs, and 6 × (c) for return.

*8: Retrieve (word) from stack

*9: Retrieve (long word) from stack

*10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

128

MB90570 Series

Table 21 Other Control Instructions (Byte/Word/Long Word) [28 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

PUSHW A

PUSHW AH

PUSHW PS

PUSHW rlst

#

~

B

Operation

word (SP) ← (SP) –2, ((SP)) ← (A)

word (SP) ← (SP) –2, ((SP)) ← (AH)

word (SP) ← (SP) –2, ((SP)) ← (PS)

(SP) ← (SP) –2n, ((SP)) ← (rlst)

1

2

4

0

(c)

–

– – – – – – –

–

3

5

4

*

word (A) ← ((SP)), (SP) ← (SP) +2

word (AH) ← ((SP)), (SP) ← (SP) +2

word (PS) ← ((SP)), (SP) ← (SP) +2

(rlst) ← ((SP)), (SP) ← (SP) +2n

POPW A

1

2

–

*

– – – – – – –

–

3

4

0

(c)

POPW AH

POPW PS

POPW rlst

–

*

2

5

4

– – – – – – –

*

JCTX @A

1

Context switch instruction

–

*

–

14

0

6× (c)

AND CCR, #imm8

OR CCR, #imm8

2

byte (CCR) ← (CCR) and imm8 –

–

*

–

3

0

byte (CCR) ← (CCR) or imm8

–

MOV RP, #imm8

MOV ILM, #imm8

2

byte (RP) ←imm8

byte (ILM) ←imm8

–

– – – – – – –

–

2

0

MOVEA RWi, ear

MOVEA RWi, eam 2+

MOVEA A, ear

MOVEA A, eam

2

word (RWi) ←ear

word (RWi) ←eam

word(A) ←ear

–

*

– – – – – – –

–

3

1

0

2+ (a)

1

1+ (a)

2

2+

word (A) ←eam

*

ADDSP #imm8

ADDSP #imm16

2

3

word (SP) ← (SP) +ext (imm8)

word (SP) ← (SP) +imm16

–

– – – – – – –

–

3

0

1

MOV

A, brgl

brg2, A

2

byte (A) ← (brgl)

byte (brg2) ← (A)

Z

–

*

–

– – –

*

– –

–

0

*

1

NOP

ADB

DTB

PCB

SPB

NCC

CMR

1

No operation

–

– – – – – – –

–

0

1

Prefix code for accessing AD space

Prefix code for accessing DT space

Prefix code for accessing PC space

Prefix code for accessing SP space

Prefix code for no flag change

Prefix code for common register bank

*1: PCB, ADB, SSB, USB, and SPB : 1 state

DTB, DPR : 2 states

*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)

*3: 29 +3 × (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)

*4: Pop count × (c), or push count × (c)

*5: Pop count or push count.

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

129

MB90570 Series

Table 22 Bit Manipulation Instructions [21 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

MOVB A, dir:bp

MOVB A, addr16:bp

MOVB A, io:bp

3

4

3

5

4

0

(b) byte (A) ← (dir:bp) b

(b) byte (A) ← (addr16:bp) b

(b) byte (A) ← (io:bp) b

Z

*

–

*

–

MOVB dir:bp, A

MOVB addr16:bp, A

MOVB io:bp, A

3

4

3

7

6

0

2× (b) bit (dir:bp) b ← (A)

2× (b) bit (addr16:bp) b ← (A)

2× (b) bit (io:bp) b ← (A)

–

*

–

*

SETB dir:bp

SETB addr16:bp

SETB io:bp

3

4

3

7

0

2× (b) bit (dir:bp) b ← 1

2× (b) bit (addr16:bp) b ← 1

2× (b) bit (io:bp) b ← 1

–

*

CLRB dir:bp

CLRB addr16:bp

CLRB io:bp

3

4

3

7

0

2× (b) bit (dir:bp) b ← 0

2× (b) bit (addr16:bp) b ← 0

2× (b) bit (io:bp) b ← 0

–

*

1

BBC dir:bp, rel

BBC addr16:bp, rel

BBC io:bp, rel

4

5

4

0

(b) Branch when (dir:bp) b = 0

(b) Branch when (addr16:bp) b = 0

(b) Branch when (io:bp) b = 0

–

*

–

*

1

2

1

BBS dir:bp, rel

BBS addr16:bp, rel

BBS io:bp, rel

4

5

4

0

(b) Branch when (dir:bp) b = 1

(b) Branch when (addr16:bp) b = 1

(b) Branch when (io:bp) b = 1

–

*

–

*

1

2

3

Branch when (addr16:bp) b = 1, bit = 1

SBBS addr16:bp, rel

WBTS io:bp

5

3

0

2× (b)

–

*

–

*

5

4

Wait until (io:bp) b = 1

Wait until (io:bp) b = 0

–

*

4

5

WBTC io:bp

*

*1: 8 when branching, 7 when not branching

*2: 7 when branching, 6 when not branching

*3: 10 when condition is satisfied, 9 when not satisfied

*4: Undefined count

*5: Until condition is satisfied

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 23 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

SWAP

SWAPW/XCHW A,T

EXT

EXTW

ZEXT

#

~

B

Operation

1

3

2

1

2

1

0

0 byte (A) 0 to 7 ↔ (A) 8 to 15

0 word (AH) ↔ (AL)

0 byte sign extension

0 word sign extension

0 byte zero extension

0 word zero extension

–

X

–

Z

–

*

–

X

–

Z

–

*

R

–

*

–

ZEXTW

*

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

130

MB90570 Series

Table 24 String Instructions [10 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

2

5

3

Byte transfer @AH+ ← @AL+, counter = RW0

Byte transfer @AH– ← @AL–, counter = RW0

MOVS/MOVSI

MOVSD

2

–

*

2

5

3

*

1

5

4

Byte retrieval (@AH+) – AL, counter = RW0

Byte retrieval (@AH–) – AL, counter = RW0

SCEQ/SCEQI

SCEQD

2

–

*

–

*

1

5

4

*

5

3

Byte filling @AH+ ← AL, counter = RW0

FISL/FILSI

2

–

*

–

6m +6

*

2

8

6

Word transfer @AH+ ← @AL+, counter = RW0

Word transfer @AH– ← @AL–, counter = RW0

MOVSW/MOVSWI 2

–

*

2

8

6

MOVSWD

2

*

1

8

7

Word retrieval (@AH+) – AL, counter = RW0

Word retrieval (@AH–) – AL, counter = RW0

SCWEQ/SCWEQI

SCWEQD

2

–

*

–

*

1

8

7

*

8

6

Word filling @AH+ ← AL, counter = RW0

FILSW/FILSWI

2

–

*

–

6m +6

*

m: RW0 value (counter value)

n: Loop count

*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs

*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case

*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) sepa-

rately for each.

*4: (b) × n

*5: 2 × (RW0)

*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c)

separately for each.

*7: (c) × n

*8: 2 × (RW0)

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

131

MB90570 Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB90573PFF

MB90574PFF

MB90F574PFF

MB90F574APFF

120-pin Plastic LQFP

(FPT-120P-M05)

MB90573PFV

MB90574PFV

MB90574CPFV

MB90F574PFV

MB90F574APFV

120-pin Plastic QFP

(FPT-120P-M13)

MB90574CPMT

MB90F574APMT

120-pin Plastic LQFP

(FPT-120P-M21)

132

MB90570 Series

■ PACKAGE DIMENSIONS

120-pin plastic LQFP

(FPT-120P-M05)

16.00±0.20(.630±.008)SQ

14.00±0.10(.551±.004)SQ

90

61

91

60

0.08(.003)

Details of "A" part

1.50 –⁺0⁰.^.1²0⁰

(Mounting height)

.059 –⁺.^.0⁰0⁰4⁸

INDEX

120

31

"A"

0~8°

1

30

LEAD No.

0.10±0.10

(.004±.004)

(Stand off)

0.16±0.03

(.006±.001)

0.145±0.055

(.006±.002)

0.50±0.20

(.020±.008)

M

0.07(.003)

0.40(.016)

0.45/0.75

(.018/.030)

0.25(.010)

C

Dimensions in mm (inches)

1998 FUJITSU LIMITED F120006S-3C-4

120-pin plastic QFP

(FPT-120P-M13)

22.60±0.20(.890±.008)SQ

20.00±0.10(.787±.004)SQ

3.85(.152)MAX

(Mounting height)

0.05(.002)MIN

(STAND OFF)

90

61

91

60

Details of "A" part

0.15(.006)

14.50

(.571)

REF

21.60

(.850)

NOM

0.15(.006)

INDEX

0.15(.006)MAX

0.40(.016)MAX

"A"

120

31

M

Details of "B" part

1

30

LEAD No.

0.50(.0197)

0.20±0.10

(.008±.004)

0.125±0.05

(.005±.002)

0.08(.003)

0

10°

0.50±0.20(.020±.008)

"B"

0.10(.004)

Dimensions in mm (inches)

C

2000 FUJITSU LIMITED F120013S-2C-4

133

MB90570 Series

120-pin plastic LQFP

(FPT-120P-M21)

18.00±0.20(.709±.008)SQ

16.00±0.10(.630±.004)SQ

90

61

91

60

0.08(.003)

Details of "A" part

1.50 –⁺0⁰.^.1²0⁰

(Mounting height)

.059 –⁺.^.0⁰0⁰4⁸

INDEX

0~8°

"A"

120

31

0.10±0.05

(.004±.002)

(Stand off)

1

30

LEAD No.

0.145 ⁺–0⁰.^.0⁰3⁵

.006 –⁺.^.0⁰0⁰1²

0.45/0.75

(.018/.030)

0.22±0.05

(.009±.002)

M

0.50(.020)

0.08(.003)

0.25(.010)

Dimensions in mm (inches)

C

1998 FUJITSU LIMITED F120033S-2C-2

134

MB90570 Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

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The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

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FUJITSU MICROELECTRONICS, INC.

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FUJITSU semiconductor devices are intended for use in standard

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CAUTION:

Europe

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or

where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters,

vehicle operating controls, medical devices for life support, etc.)

are requested to consult with FUJITSU sales representatives before

such use. The company will not be responsible for damages arising

from such use without prior approval.

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Germany

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Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

Singapore 556741

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If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

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Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0101

FUJITSU LIMITED Printed in Japan

136


型号：	MB90F574APFV
厂家：	FUJITSU
描述：	16-bit Proprietary Microcontroller 16位微控制器专有微控制器和处理器外围集成电路时钟
文件：	总135页 (文件大小：2311K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90F574APFV [FUJITSU]

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