MB91305PMC_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-16703-1E

32-bit Microcontroller

CMOS

FR60 MB91305

MB91305

■ DESCRIPTION

MB91305 is a single-chip microcontroller that has a 32-bit high-performance RISC CPU as well as built-in I/O

resources for embedded controllers requiring high-performance and high-speed CPU processing.

The FR family is the most suitable for embedded applications, for example, DVD player, printer, TV, and PDP

control, that require a high level of CPU processing power.

MB91305 is an FR60 model that is based on the FR30/40 of CPUs. It has enhanced bus access and is optimized

for high-speed use.

■ FEATURES

1. FR CPU

• 32-bit RISC, load/store architecture, 5 stages pipeline

• With USB function (MOD = 0000^B) : operating frequency of 64 MHz [original oscillation at 48 MHz] 48 MHz /

3-divided × 4 multiplication

(Continued)

■ PACKAGE

176-pin plastic LQFP

(FPT-176P-M07)

MB91305

(Continued)

• With no USB function (MOD = 0010^B) : operating frequency of 64 MHz [original oscillation at 16 MHz]

16 MHz × 4 multiplication

• 16-bit fixed-length instructions (basic instructions) , one instruction per cycle

• Memory-to-memory transfer, bit processing, instructions including barrel shift, etc. : instructions appropriate

for embedded applications

• Function entry and exit instructions, multi load/store instructions of register contents : instructions compatible

with high-level languages

• Register interlock function to facilitate assembly-language coding

• Built-in multiplier/instruction-level support

- Signed 32-bit multiplication : 5 cycles

- Signed 16-bit multiplication : 3 cycles

• Interrupts (saving of PC and PS) : 6 cycles, 16 priority levels

• Harvard architecture enabling simultaneous execution of both program access and data access

• 4-word queues in the CPU provided to add an instruction prefetch function

• Instructions compatible with the FR family

2. Bus Interface

This bus interface is used for external bus and internal macro USB function.

• Maximum operating frequency of 32 MHz

• 16-bit data input-output

• Totally independent 8-area chip select outputs that can be defined in the minimum units of 64K bytes. The

CS2 and CS3 areas are reserved as shown below. CS0, CS1, and CS4 to CS7 can be used only.

- CS2 area : USB function

- CS3 area : Unused

• Basic bus cycle (2 cycles)

• Automatic wait cycle generator that can be programmed for each area and can insert waits because CS2 and

CS3 are reserved, the setting is fixed.

• 24-bit address can be fully outputted

• 8- and 16-bit data I/O

• Prefetch buffer installed

• Unused data and address pins can be used as general-purpose I/O and resource function.

• Support of interfaces for various memory modules

Asynchronous SRAM, asynchronous ROM/Flash memory

Page-mode ROM/Flash memory (a page-size of 1, 2, 4, or 8 can be selected)

Burst-mode ROM/Flash memory (MBM29BL160D/161D/162D etc.)

SDRAM (or FCRAM type, CAS Latency1 to Latency8, 2/4 bank product)

Address/data multiplexed bus (8-bit/16-bit width only)

• Basic bus cycle : 2 cycles

• Automatic wait cycle generator (Max 15 cycles) that can be programmed for each area

• External wait cycles due to RDY input

• Endian setting of byte ordering (big/little)

Note : CS0 area is only big endian.

• Write disable setting (read only area)

• Enable/disable set of capturing to the built-in cache

• Enable/disable set of prefetch function

• External bus arbitration using BRQ and BGRNT is enabled

3. Built-in Memory

64K bytes RAM of built-in F-bus

2

MB91305

4. Instruction Cache Memory

•Instruction cache : 4K bytes

•2 way set associative

•128 block/way, 4 entry (4 words) /block

•Lock function allows specific program codes to stay resident in cache.

•Instruction RAM function : A part of the instruction cache not in use can be used as RAM for instruction execution

5. DMAC (DMA Controller)

•5 channels (channels 1 and 2 are connected to the USB function.)

•3 transfer sources (internal peripherals, software)

•Addressing mode with 32-bit full address specifications (increase, decrease, fixed)

•Transfer modes (demand transfer, burst transfer, step transfer, block transfer)

•Transfer data size that can be selected from 8, 16, and 32 bits

6. Bit Search Module (Used by REALOS)

Searches for the position of the first bit varying between 1 and 0 in the MSB of a word

7. 16-bit Reload Timer (Including One Channel for REALOS)

•16-bit timer; 3 channels

•Internal clock that can be selected from those resulting from frequency divided by 2, 8, and 32

8. UART

•Full-duplex double buffer

•5 channels

•Parity or no parity can be selected.

•Either asynchronous (start-stop synchronization) or CLK synchronous communication can be selected.

•Built-in timer for dedicated baud rates

•An external clock can be used as the transfer clock.

•Plentiful error detection functions (parity, frame, overrun)

9. I²C Interface*

•4 channels (bridge function and pin function for 5 channels)

•Master/slave transmission and reception

•Clock synchronization function

•Transfer direction detection function

•Bus error detection function

•Supports standard mode (Max 100 Kbps) and high-speed mode (Max 400 Kbps) .

•Built-in FIFO function : each 16-byte sending/receiving

•Arbitration function

•Slave address/general call address detection function

•Start condition repetitious occurrence and detection function

•10-bit/7-bit slave address

10.Interrupt Controller

•Totalof17externalinterrupts(oneunmaskableinterruptpin(NMI) and16regularinterruptpins(INT15toINT0) )

•Interrupts from internal peripherals

•Priority level can be defined as programmable (16 levels) except for the unmaskable interrupt pin.

•Can be used for wake-up during stop.

11.10-bit A/D Converter

•10-bit resolution, 10 channels

•Sequential comparison and conversion type (conversion time : about 8.18 µs)

•Conversion modes (single conversion mode and scan conversion mode)

•Causes of startup (software and external triggers)

3

MB91305

12. PPG

• 4 channels

• 16-bit data register with 16-bit down counter and cycle setting buffer

• Internal clock : Frequency-divide-by number selectable from 1, 4, 16, and 64

13. PWC

• 1 channel (1 input)

• 16-bit up counter

• Simple Low-pass digital filter

14. 16-bit Free-run Timer

• 16-bit 1channel

• Input capture 4 channels

15. USB Function (Enabling/Disabling Function Can Be Selected by Mode Pin)

• USB2.0 full-speed, double buffer

• Configuration of FIFO for End point

CONTROL IN/OUT, BULK IN/OUT, and INTERRUPT IN

16. Other Interval Timers

Watchdog timer

17. I/O Ports

Maximum of 98 ports

18. Other Features

• Has a built-in oscillation circuit as a clock source.

• INIT is provided as a reset pin.

• Additionally, a watchdog timer reset and software resets are provided.

• Stop mode and sleep mode supported as low-power consumption modes

• Gear function

• Built-in timebase timer

• Package : LQFP-176, 0.5 mm pitch, and 24 mm × 24 mm

• CMOS technology : 0.18 µm

• Power supply voltage : two sources (0.18 µm) of 3.3 V (−0.3 V to +0.3 V) and 1.8 V (−0.15 V to +0.15 V)

* : LICENSE

Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use, these com-

ponents in an I²C system provided that the system conforms to the I²C Standard Specification as defined by

Philips.

4

MB91305

■ PIN ASSIGNMENT

(TOP VIEW)

VDDE

VSS

VDDI

D24

D25

D26

D27

D28

D29

D30

D31

1

2

3

4

5

6

7

8

9

10

11

12

13

14

132 PA4/INT4

131 PA3/INT3

130 PA2/INT2

129 PA1/INT1

128 PA0/INT0

127

NMI

126 VDDI

125 VSS

124 VDDE

123

122 P96/SCL4

121

P97/SDA4

VDDE

VSS

VDDI

P95/SDA3

120 P94/SCL3

119

118

P93/SDA2

P92/SCL2

RD 15

16

17

18

19

117 P91/SDA1

P90/SCL1

WR0/DQMUU

WR1/DQMUL/P30

CS0/P31

116

115 P84/SDA0

P83/SCL0

114

113

CS1/P32

CS4/P33 20

P82/SCK4

21

22

23

24

112 P81/SOUT4

CS5/P34

CS6/P35

CS7/P36

RDY/P37

P80/SIN4

P75/SCK3

P74/SOUT3

P73/SIN3

111

110

109

108

107

P40/BGRNT 25

P41/BRQ 26

P72/SCK2

SYSCLK/P42 27

106 P71/SOUT2

MCLKE/P43

P70/SIN2

P65/SCK1

103 P64/SOUT1

28

105

104

29

30

31

32

MCLK/P44

P45/SRAS/LBA/AS

P46/SCAS/BAA

P47/SWE/WR

P63/SIN1

P62/SCK0

102

101

VDDE 33

VSS 34

VDDI 35

A0 36

100 P61/SOUT0

P60/SIN0

99

98

97

96

95

94

93

VDDI

VSS

VDDE

TRST

ICLK

A1 37

A2

A3

38

39

IBREAK

A4 40

A5 41

A6 42

92 ICD3

91 ICD2

90 ICD1

89 ICD0

43

44

A7

A8

(FPT-176P-M07)

5

MB91305

■ PIN DESCRIPTION

• Function pins

I/O

Type*

Pin no.

Pin name

Function

D16 to D23

P20 to P27

External data bus bit16 to bit23. It is available in the external bus mode.

Can be used as ports in 8-bit external bus mode.

169 to 176

C

External data bus bit24 to bit31.

It is available in the external bus mode.

4 to 11

15

D24 to D31

RD

C

H

External bus read strobe output. This pin is enabled at external bus mode.

External bus write strobe output. This pin is enabled at external bus mode.

When WR is used as the write strobe, this becomes the byte-enable pin

(DQMUU) .

WR0

/DQMUU

16

H

External bus write strobe output. The pin is enabled when WR1 output is

enabled in the external bus mode. When WR is used as the write strobe, this

becomes the byte-enable pin (DQMUL) .

WR1

/DQMUL

17

D

General-purpose input/output port. The pin is enabled when the external bus

write-enable output is disabled.

P30

CS0

P31

Chip select 0 output. This pin is enabled at external bus mode.

18

19

D

General-purpose input/output port. This pin is enabled in the single-chip

mode.

Chip select 1 output. This function is enabled when chip select 1 output is

enabled.

CS1

P32

CS4

P33

CS5

P34

CS6

P35

CS7

P36

General-purpose input/output port. This function is enabled when chip select

1 output is disabled.

Chip select 4 output. This function is enabled when chip select 4 output is

enabled.

20

21

22

23

D

General-purpose input/output port. This function is enabled when chip select

4 output is disabled.

Chip select 5 output. This function is enabled when chip select 5 output is

enabled.

General-purpose input/output port. This function is enabled when chip select

5 output is disabled.

Chip select 6 output. This function is enabled when chip select 6 output is

enabled.

General-purpose input/output port. This function is enabled when chip select

6 output is disabled.

Chip select 7 output. This function is enabled when chip select 7 output is

enabled.

General-purpose input/output port. This function is enabled when chip select

7 output is disabled.

(Continued)

6

MB91305

I/O

Type*

Pin no.

Pin name

RDY

Function

External ready input. This function is enabled when external ready input is

enabled.

24

D

General-purpose input/output port. This function is enabled when external

ready input is disabled.

P37

Acceptance output for external bus release.

Outputs “L” when the external bus is released. This function is enabled when

output is enabled.

BGRNT

25

26

General-purpose input/output port. This function is enabled when external bus

release acceptance is disabled.

P40

BRQ

P41

External bus release request input. Input "1" to request release of the external

bus. The function is enabled when input is enabled.

General-purpose input/output port. This function is enabled when the external

bus release request is disabled.

System clock output. This function is enabled when system clock output is

enabled. This outputs the same clock as the external bus operating frequency.

(Output halts in stop mode.)

SYSCLK

27

28

29

D

General-purpose input/output port. This function is enabled when system clock

output is disabled.

P42

MCLKE

P43

Clock enable signal for SDRAM.

General-purpose input/output port. This function is enabled when memory

clock output is disabled.

Memory clock output. This function is enabled when memory clock output is

enabled. This outputs the same clock as the external bus operating frequency.

(Output halts in sleep mode.)

MCLK

General-purpose input/output port. This function is enabled when memory

clock output is disabled.

P44

AS

Address strobe output. This function is enabled when address strobe output is

enabled.

Address load output for burst flash memory. This function is enabled when

address load output is enabled.

LBA

SRAS

P45

30

31

D

RAS strobe single for SDRAM.

General-purpose input/output port. This function is enabled when address load

output is disabled.

Address advance output for burst flash memory. This function is enabled when

address advance output is enabled.

BAA

SCAS

P46

CAS strobe signal for SDRAM.

General-purpose input/output port. This function is enabled when address

advance output is disabled.

(Continued)

7

MB91305

I/O

Type*

Pin no.

Pin name

Function

Memory write strobe output. This function is enabled when write strobe out-

put is enabled.

WR

SWE

P47

32

D

Write output for SDRAM.

General-purpose input/output port. This function is enabled when write

strobe output is disabled.

36 to 51

55 to 62

A0 to A15

A16 to A23

P50 to P57

X0

H

D

External address bus bit0 to bit15.

External address bus bit16 to bit23.

Can be used as ports when external address bus is not used.

Clock (oscillation) input.

64

66

68

A

X1

Clock (oscillation) output.

INIT

B

I

External reset input (Reset to initialize settings)

MD0 to

MD2

69 to 71

These pins set the basic operating mode. Connect V^CCor VSS.

72

MD3

J

These pins set the basic operating mode. Connect V^CCor VSS.

Analog input pin.

76, 77

AN0, AN1

M

AN2 to

AN9

Analog input pin.

78 to 85

F

PF0 to PF7

Can be used as ports when analog input pin is not used.

Status output pin for development tool.

ICS0 to

ICS2

86 to 88

89 to 92

C

L

ICD0 to

ICD3

Data input/output pin for development tool.

93

94

95

IBREAK

ICLK

J

D

B

Break pin for development tool.

Clock pin for development tool.

Reset pin for development tool.

TRST

UART0 data input pin. This input is used continuously when UART0 is

performing input. In this case, do not output to this port unless doing so

intentionally.

SIN0

99

D

P60

SOUT0

P61

General-purpose input/output port.

UART0 data output pin. This function is enabled when UART0 data output is

enabled.

100

101

D

General-purpose input/output port.

UART0 clock input/output pin. This function is enabled when UART0 clock

output is enabled.

SCK0

P62

General-purpose input/output port.

(Continued)

8

MB91305

I/O

Type*

Pin no.

Pin name

Function

UART1 data input pin. This input is used continuously when UART1 is

performing input. In this case, do not output to this port unless doing so

intentionally.

SIN1

102

D

P63

SOUT1

P64

General-purpose input/output port.

UART1 data output pin. This function is enabled when UART1 data output is

enabled.

103

104

D

General-purpose input/output port.

UART1 clock input/output pin. This function is enabled when UART1 clock

output is enabled.

SCK1

P65

General-purpose input/output port.

UART2 data input pin. This input is used continuously when UART2 is

performing input. In this case, do not output to this port unless doing so

intentionally.

SIN2

105

D

P70

SOUT2

P71

General-purpose input/output port.

UART2 data output pin. This function is enabled when UART2 data output is

enabled.

106

107

D

General-purpose input/output port.

UART2 clock input/output pin. This function is enabled when UART2 clock

output is enabled.

SCK2

P72

General-purpose input/output port.

UART3 data input pin. This input is used continuously when UART3 is

performing input. In this case, do not output to this port unless doing so

intentionally.

SIN3

108

D

P73

SOUT3

P74

General-purpose input/output port.

UART3 data output pin. This function is enabled when UART3 data output is

enabled.

109

110

D

General-purpose input/output port.

UART3 clock input/output pin. This function is enabled when UART3 clock

output is enabled.

SCK3

P75

General-purpose input/output port.

UART4 data input pin. This input is used continuously when UART4 is

performing input. In this case, do not output to this port unless doing so

intentionally.

SIN4

111

112

D

P80

SOUT4

P81

General-purpose input/output port.

UART4 data output pin. This function is enabled when UART4 data output is

enabled.

General-purpose input/output port.

(Continued)

9

MB91305

I/O

Type*

Pin no.

Pin name

Function

UART4 clock input/output pin. This function is enabled when UART4 clock

output is enabled.

SCK4

P82

113

D

General-purpose input/output port.

Clock I/O pin for I²C bus. This function is enabled when typical operation of

I²C is enabled. The port output must remain off unless intentionally turned on.

(pseudo open drain output)

SCL0

P83

114

115

116

117

118

119

120

121

122

General-purpose input/output port.

Data I/O pin for I²C bus. This function is enabled when typical operation of

I²C is enabled. The port output must remain off unless intentionally turned on.

(pseudo open drain output)

SDA0

P84

D

K

General-purpose input/output port.

Clock I/O pin for I²C bus. This function is enabled when typical operation of

I²C is enabled. The port output must remain off unless intentionally turned on.

(pseudo open drain output)

SCL1

P90

General-purpose input/output port.

Data I/O pin for I²C bus. This function is enabled when typical operation of

I²C is enabled. The port output must remain off unless intentionally turned on.

(pseudo open drain output)

SDA1

P91

General-purpose input/output port.

Clock I/O pin for I²C bus. This function is enabled when typical operation of

I²C is enabled. The port output must remain off unless intentionally turned on.

(pseudo open drain output)

SCL2

P92

General-purpose input/output port.

Data I/O pin for I²C bus. This function is enabled when typical operation of

I²C is enabled. The port output must remain off unless intentionally turned on.

(pseudo open drain output)

SDA2

P93

General-purpose input/output port.

Clock I/O pin for I²C bus. This function is enabled when typical operation of

I²C is enabled. The port output must remain off unless intentionally turned on.

(pseudo open drain output)

SCL3

P94

General-purpose input/output port.

Data I/O pin for I²C bus. This function is enabled when typical operation of

I²C is enabled. The port output must remain off unless intentionally turned on.

(pseudo open drain output)

SDA3

P95

General-purpose input/output port.

Clock I/O pin for I²C bus. This function is enabled when typical operation of

I²C is enabled. The port output must remain off unless intentionally turned on.

(pseudo open drain output)

SCL4

P96

General-purpose input/output port.

(Continued)

10

MB91305

I/O

Type*

Pin no.

Pin name

Function

Data I/O pin for I²C bus. This function is enabled when typical operation of I²C

is enabled. The port output must remain off unless intentionally turned on.

(pseudo open drain output)

SDA4

123

127

K

B

G

P97

NMI

General-purpose input/output port.

NMI (Non Maskable Interrupt) input

External interrupt inputs. These inputs are used continuously when the

corresponding external interrupt is enabled. In this case, do not output to

these ports unless doing so intentionally.

INT0 to

INT3

128 to 131

PA0 to PA3

General-purpose input/output port.

External interrupt input. These inputs are used continuously when the

corresponding external interrupt is enabled. In this case, do not output to

these ports unless doing so intentionally. When USB function is enabled

(MD3, MD2, MD1, MD0 = 0000^B) , INT4 function is used only for the USB

interrupt. Therefore, it is not possible to use it as an external interrupt pin.

INT4

132

G

PA4

General-purpose input/output port.

External interrupt input. These inputs are used continuously when the

corresponding external interrupt is enabled. In this case, do not output to

these ports unless doing so intentionally.

INT5 to

INT7

133 to 135

136

G

PA5 to PA7

INT8

General-purpose input/output port.

External interrupt input. These inputs are used continuously when the

corresponding external interrupt is enabled. In this case, do not output to

these ports unless doing so intentionally.

PB0

General-purpose input/output port.

External interrupt input. These inputs are used continuously when the

corresponding external interrupt is enabled. In this case, do not output to

these ports unless doing so intentionally.

INT9

137

PB1

General-purpose input/output port.

External interrupt input. These inputs are used continuously when the

corresponding external interrupt is enabled. In this case, do not output to

these ports unless doing so intentionally.

INT10

138

139

G

A/D converter external trigger input. These inputs are used continuously

when using as A/D start trigger. In this case, do not output to these ports

unless doing so intentionally.

ATRG

PB2

General-purpose input/output port.

External interrupt input. These inputs are used continuously when the

corresponding external interrupt is enabled. In this case, do not output to

these ports unless doing so intentionally.

INT11

External clock input pin of free-run timer. These inputs are used continuously

when using as external clock input pin of free-run timer. In this case, do not

output to these ports unless doing so intentionally.

FRCK

PB3

General-purpose input/output port.

(Continued)

11

MB91305

I/O

Type*

Pin no.

Pin name

Function

External interrupt input. These inputs are used continuously when the

corresponding external interrupt is enabled. In this case, do not output to

these ports unless doing so intentionally.

INT12 to

INT15

Input capture input pins. These inputs are used continuously when selected

as input capture inputs. In this case, do not output to these ports unless doing

so intentionally.

140 to 143

ICU0 to

ICU3

G

PB4 to

PB7

General-purpose input/output port.

145

146

UDP

UDM

+ pin of USB.

− pin of USB.

USB

D

PPG0 to

PPG3

PPG ch.0 to PPG ch.3 timer output.

General-purpose input/output port.

149 to 152

PC0 to

PC3

Data output of reload timer 0. This function is enabled when data output of

reload timer 0 is enabled using port function register.

TOUT0

External trigger input for PPG0 timer. This input is used continuously when

the corresponding timer input is enabled. In this case, do not output to this

port unless doing so intentionally.

153

D

TRG0

PC4

TOUT1

PC5

General-purpose input/output port.

Data output of reload timer 1. This function is enabled when data output of

reload timer 1 is enabled using port function register.

154

155

D

General-purpose input/output port.

Data output of reload timer 2. This function is enabled when data output of

reload timer 2 is enabled using port function register.

TOUT2

Write strobe output for DMA fly-by transfer. This function is enabled when

outputting a write strobe for DMA fly-by transfer is enabled.

IOWR

PC6

General-purpose input/output port.

PWC input. These inputs are used continuously when the corresponding

external interrupt is enabled. In this case, do not output to these ports unless

doing so intentionally.

RIN

156

157

D

Read strobe output for DMA fly-by transfer. This function is enabled when

outputting a read strobe for DMA fly-by transfer is enabled.

IORD

PC7

General-purpose input/output port.

External input for DMA transfer requests. This input is used continuously

when the corresponding external input for DMA transfer requests are

enabled. In this case, do not output to this port unless doing so intentionally.

DREQ0

PD0

General-purpose input/output port.

(Continued)

12

MB91305

I/O

Type*

Pin no.

Pin name

Function

DMA external transfer request acceptance output. This function is enabled

when DMA external transfer request acceptance output is enabled.

DACK0

PD1

158

D

General-purpose input/output port.

Completion output for DMA external transfer. This function is enabled when

completion output for DMA external transfer is enabled.

DEOP0

PD2

159

160

General-purpose input/output port.

External input for DMA transfer requests. This input is used continuously

when external input for DMA transfer request is enabled. In this case, do not

output to this port unless doing so intentionally. When using USB, this

function (DMAC ch.1) cannot be used because it is used as USB data

transfer. DREQ2 input is disabled.

DREQ1

D

Reload timer input. This input is used continuously when the corresponding

timer input is enabled. In this case, do not output to this port unless doing so

intentionally.

TIN0

PD3

General-purpose input/output port.

DMA external transfer request acceptance output. This function is enabled

when DMA transfer request acceptance output is enabled.

When using USB, this function (DMAC ch.1) cannot be used because it is

used as USB data transfer. External transfer ACK output of DMA should be

disabled.

DACK1

161

162

163

D

Reload timer input. This input is used continuously when the corresponding

timer input is enabled. In this case, do not output to this port unless doing so

intentionally.

TIN1

PD4

General-purpose input/output port.

Completion output for DMA external transfer. This function is enabled when

completion output for DMA external transfer is enabled. When using USB, this

function (DMAC ch.1) cannot be used because it is used as USB data

transfer. External transfer EOP output of DMA should be disabled.

DEOP1

Reload timer input. This input is used continuously when the corresponding

timer input is enabled. In this case, do not output to this port unless doing so

intentionally.

TIN2

PD5

General-purpose input/output port.

External input for DMA transfer requests. This input is used continuously

when external input for DMA transfer request is enabled. In this case, do not

output to this port unless doing so intentionally.

When using USB, this function (DMAC ch.2) cannot be used because it is

used as USB data transfer. DREQ2 input is disabled.

DREQ2

External trigger input for PPG1 timer. This input is used continuously when

the corresponding timer input is enabled. In this case, do not output to this

port unless doing so intentionally.

TRG1

PE0

General-purpose input/output port.

(Continued)

13

MB91305

(Continued)

I/O

Type*

Pin no.

Pin name

Function

DMA external transfer request acceptance output. This function is enabled

when DMA transfer request acceptance output is enabled.

When using USB, this function (DMAC ch.2) cannot be used because it is

used as USB data transfer. External transfer ACK output of DMA should be

disabled.

DACK2

164

D

External trigger input for PPG2 timer. This input is used continuously when the

corresponding timer input is enabled. In this case, do not output to this port

unless doing so intentionally.

TRG2

PE1

General-purpose input/output port.

Completion output for DMA external transfer. This function is enabled when

completion output for DMA external transfer is enabled.

When using USB, this function (DMAC ch.2) cannot be used because it is

used as USB data transfer. External transfer EOP output of DMA should be

disabled.

DEOP2

165

D

External trigger input for PPG3 timer. This input is used continuously when the

corresponding timer input is enabled. In this case, do not output to this port

unless doing so intentionally.

TRG3

PE2

General-purpose input/output port.

* : For I/O circuit type, refer to “■ I/O CIRCUIT TYPES”.

• Power supply and GND pins

Pin no.

Pin name

Function

2, 13, 34, 53, 65, 97,

125, 147, 167

GND pins.

Connect all pins at the same potential.

VSS

3, 14, 35, 54, 67, 98,

126, 148, 168

1.8 V power supply pins.

Connect all pins at the same potential.

VDDI

1, 12, 33, 52, 63, 96,

124, 144, 166

3.3 V power supply pins.

Connect all pins at the same potential.

VDDE

73

74

75

AVCC

AVRH

AVSS

Analog power supply pin for A/D converter

Reference power supply pin for A/D converter

Analog GND pin for the A/D converter

14

MB91305

■ I/O CIRCUIT TYPES

Type

Circuit

Remarks

Oscillation feedback resistance

approx. 1MΩ

X1

Clock input

A

X0

Standby control

P-ch

• With pull-up resistor

• CMOS level hysteresis input

P-ch

N-ch

B

Digital input

• CMOS level I/O

• With standby control

• I^OL= 4 mA

P-ch

N-ch

Digital output

C

Digital input

Standby control

(Continued)

15

MB91305

Type

Circuit

Remarks

• CMOS level output

• CMOS level hysteresis input

• With standby control

• I^OL= 4 mA

P-ch

Digital output

D

N-ch

Digital input

Standby control

• CMOS level input

• No standby control

P-ch

N-ch

E

Digital input

• CMOS level output

• CMOS level hysteresis input

• With standby control

• With analog input

• I^OL= 4 mA

P-ch

Digital output

N-ch

F

Analog input

Digital input

Standby control

(Continued)

16

MB91305

Type

Circuit

Remarks

• With pull-up control

• CMOS level output

• CMOS level hysteresis input

• No standby control

• I^OL= 4 mA

Pull-up control

Digital output

P-ch

G

Digital output

Digital input

N-ch

CMOS level output

P-ch

Digital output

H

N-ch

P-ch

• CMOS level hysteresis input

• No standby control

I

N-ch

Digital input

(Continued)

17

MB91305

Type

Circuit

Remarks

• CMOS level hysteresis input

• With pull-down resistor

P-ch

J

N-ch

Digital input

• 3 ports for I²C

• CMOS level hysteresis input

• CMOS level output

• With stop control

P-ch

N-ch

Open-drain control

Digital output

Digital input

Control

Digital input

Control

Open-drain control

K

P-ch

N-ch

Digital output

Digital input

P-ch

Open-drain control

Digital output

N-ch

(Continued)

18

MB91305

(Continued)

Type

Circuit

Remarks

• CMOS I/O

• With pull-down control

Pull-down control

Digital output

P-ch

L

Digital output

N-ch

P-ch

N-ch

Digital input

Analog pin

M

Analog input

19

MB91305

■ HANDLING DEVICES

• Preventing a Latch-up

A latch-up can occur on a CMOS IC under following conditions. A latch-up, if it occurs, significantly increases

the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very

careful not to exceed the maximum rating.

- When a voltage higher than VDDE or VDDI or a voltage lower than VSS is applied to an input or output pin.

- When a voltage higher than the rating is applied between VDDE or VDDI and VSS.

• Handling of Unused Input Pins

Do not leave an unused input pin open since it may cause a malfunction. Handle by, for example, using a pull-

up or pull-down resistor.

• Power Supply Pins

If more than one VDDE or VDDI or VSS pin exists, those that must be kept at the same potential are designed

to be connected to one other inside the device to prevent malfunctions such as latch-up. Be sure to connect the

pins to a power supply and ground external to the deviceto minimize undesired electromagnetic radiation, prevent

strobe signal malfunctions due to an increase in ground level, and conform to the total output current rating.

Given consideration to connecting the current supply source to VDDE or VDDI and VSS pin of the device at the

lowest impedance possible.

It is also recommended that a ceramic capacitor of around 0.1 µF be connected between VDDE or VDDI and

VSS pin at circuit points close to the device as a bypass capacitor.

• Quartz Oscillation Circuit

Noise near the X0 or X1 pin may cause the device to malfunction. Design printed circuit boards so that X0, X1,

the quartz oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as near to one another

as possible.

It is strongly recommended that printed circuit board artwork that surrounds the X0 and X1 pins with ground be

used to increase the expectation of stable operation.

Please ask the Oscillation maker to evaluate the oscillational characteristics of the crystal and this device.

• Mode Pins (MD0 to MD3)

In order to prevent mistakes due to noise, and sending them into test mode, connect these pins as close to

VDDE and VSS pins, and at as low an impedance as possible.

• Tool Reset Pins (TRST)

Be sure to input the same signal as the INIT when this pin is not used for the tool. The same processing is

executed for the mass product.

• Power-on

Immediately after power-on, be sure to apply setting initialization reset (INIT) with INIT pin.

Also immediately after power-on, keep the INIT pin at the “L” level until the oscillator has reached the required

oscillation stabilization wait time. (For initialization by INIT from the INIT pin, the oscillation stabilization wait time

is set to the minimum value.)

• Source Oscillation Input at Power-on

At power-on, be sure to input a source clock until the oscillation stabilization wait time is reached.

20

MB91305

• Precautions at Power-On/Power-Off

• Precautions when turning on and off VDDI pin and VDDE pin

To ensure the reliability of LSI devices, do not continuously apply only VDDE pin for about a minute when VDDI

is off.

When VDDE pin is changed from off to on, the power noise may make it impossible to retain the internal state

of the circuit.

Power-on : Supply voltage of VDDI pin → analog → Supply voltage of VDDE pin → signal

Power-off : Signal → Supply voltage of VDDE pin → analog → Supply voltage of VDDI pin

• Indeterminate Output when the Power is Turned On

When turning on the power, the output pin may remain indeterminate until internal power supply becomes stable.

• Clocks

• Notes on using external clock

When the external clock is used, in principle, supply a clock signal to the X0 pin and an opposite-phase clock

signal to the X1 pin at the same time. However, in this case the STOP mode (oscillation stop mode) must not

be used (This is because, in the STOP mode, the X1 pin stops at “H” output).

Example of using an external clock is illustrated in the following figure.

Example of using external clock (normal)

X0

X1

MB91305

The STOP mode (oscillation stop mode) cannot be used.

• Limitations

• Clock controller

Secure the stabilization wait time while “L” is input to INIT pin.

• Bit search module

Only word access is permitted for data register for detection 0 (BSD0), data register for detection 1 (BSD1), and

data register for change point detection (BSDC) .

• I/O port

Only byte access is permitted for ports.

21

MB91305

• Low-power Consumption Mode

To switch to standby mode, use synchronous standby mode (set by the SYNCS bit, that is bit8 of the TBCR,

timebase counter control register) and be sure to use the following sequence :

(LD1 #value_of_stanby, R0)

(LD1 #_STCR, R12)

STB

R0, @R12 : Writing into the standby control register (STCR)

LDUB @R12, R0 : STCR read for synchronous standby

LDUB @R12, R0 : Dummy re-read of STCR

NOP

: NOP × 5 for timing adjustment

• When using the monitor debugger, do not :

- Set a break point within the above sequence of instructions.

- Step of the instructions within the above sequence of instructions.

• Prefetch

When allowing prefetch in the little endian area, only word access (32-bit) should be used to access the area.

Byte access and halfword access are not working properly.

• Notes on using PS register

PS register is processed by some instructions in advance so that exception operations as stated below may

cause breaks during interruption handling routine when using debugger and may cause updates to the display

contents of PS flags.

In either case, this device is designed to carry out reprocessing properly after returning from such EIT events.

The operations before and after EIT events are performed as prescribed in the specification.

1. The following operations may be performed when the instruction immediately followed by a DIVOV/DIVOS

instruction is acceptance of a user interrupt/NMI, single-stepped, or breaks in response to an emulator menu.

(1) D0 and D1 flags are updated in advance.

(2) EIT handling routine (user interrupt/NMI, or emulator) is executed.

(3) After returning from the EIT, a DIVOU/DIVOS instruction is executed and the D0 and D1 flags are

updated to the same values as in (1) .

2. The following operations are performed if each instruction from ORCCR, STILM, MOV Ri, and PS is executed

to allow an interruption while user interrupt/NMI trigger exists.

(1) PS register is updated in advance.

(2) EIT handling routine (user interrupt/NMI) is executed.

(3) After returning from the EIT, the above instructions are executed and the PS register is updated to

the same value as in (1) .

22

MB91305

• Watchdog Timer Function

The watchdog timer equipped in this model operates to monitor programs to ensure that they execute reset

defer function within a certain period of time, and to reset the CPU if the reset defer function is not executed

due to the program runaway. For that reason, once the watchdog timer function is enabled, it keeps its operation

until it is reset.

By way of exception, the watchdog timer automatically defers a reset under the condition where the CPU

program executions are stopped. For more detail, refer to the description section of the watchdog timer function

in “Hardware Manual”.

If the system gets out of control and the situation becomes as mentioned above, watchdog reset may not be

generated. In that case, please reset (INIT) from the external INIT pin.

• Note on using A/D

The MB91305 has a built-in A/D converter. Do not supply a voltage higher than VDDE to the AVCC.

• Software reset in synchronous mode

When software reset in the synchronous mode is used, the following two conditions must be satisfied before

setting the SRST bit of the STCR (standby control register) to 0.

- Set the interrupt enable flag (I-Flag) to the interrupt disabled (I-Flag = 0).

- Do not use NMI.

• Simultaneous occurrences of software break and user interrupt/NMI

If software break and user interrupt/NMI occur together, emulator debugger may:

- Stop at a point other than the programmed break points.

- Not reexecute properly after halting.

If such failures occur, use hardware break instead of software break. When using monitor debugger, do not set

any break points within the corresponding instructions.

• Stepping of the RETI Instruction

In the environment where interruptions occur frequently during stepping, the RETI is executed repeatedly for

the corresponding interrupt process routines after the stepping. As the result of it, the main routine and low

interrupt- level programs are not executed. To avoid this situation, do not step the RETI instruction. Otherwise,

perform debugging by disabling the interruptions when the debug on the corresponding interrupt routines

becomes unnecessary.

• Operand Break

Do not set the access to the areas containing the address of stack pointer as a target of data event break.

• Sample Batch File for Configuration

When a program is downloaded to internal RAM to execute debug, be sure to execute the following batch file

after reset.

#-----------------------------------------------------------------------------------------------------------------------------------

# Set MODR (0x7fd) = Enable In memory + 16-bit External Bus

set mem/byte 0x7fd = 0x5

#-----------------------------------------------------------------------------------------------------------------------------------

23

MB91305

■ BLOCK DIAGRAM

FR CPU Core

32

Instruction

cache 4KB

32

Bit search

Module

RAM 64KB

Bus converter

DMAC

5 channels

32 ↔ 16

adapter

USB

function

External bus

interface

SDRAM

interface

Clock

control

Interrupt

controller

I²C

interface

4 channels

10-bit

16-bit

UART

5 channels

A/D converter

10channels

Free-run timer

1 channel

External

interrupt

16-bit

Reload timer

3 channels

16-bit

Input capture

4 channels

PWC

PPG

Port

1 channel 4 channels

24

MB91305

■ CPU AND CONTROL UNIT

Internal Architecture

The FR family is a high-performance core based on RISC architecture and advanced instructions for embedded

applications.

1. Features

• RISC architecture used

Basic instruction : One instruction per cycle

• 32-bit architecture

General-purpose register : 32 bits × 16

• 4G bytes linear memory space

• Multiplier installed

32-bit by 32-bit multiplication : 5 cycles

16-bit by 16-bit multiplication : 3 cycles

• Enhanced interrupt processing function

Quick response speed : 6 cycles

Support of multiple interrupts

Level mask function : 16 levels

• Enhanced instructions for I/O operations

Memory-to-memory transfer instruction

Bit-processing instructions

• Efficient code

Basic instruction word length : 16 bits

• Low-power consumption

Sleep and stop modes

• Gear function

25

MB91305

2. Internal Architecture

The FR family CPU uses the Harvard architecture, which has separate buses for instructions and data. A 32-

bit↔16-bit bus converter is connected to the 32-bit bus (F-bus) , providing an interface between the CPU and

peripheral resources. A Harvard↔Princeton bus converter is connected to both the I-bus and D-bus, providing

an interface between the CUP and bus controllers.

FRex CPU

D-bus

I-bus

32

External

I address

I data

address

Harvard

24

External date

Princeton

bus

16

32

D address

D data

converter

address

data

32

32-bit

16-bit

Bus converter

16

F-bus

R-bus

Peripheral resources

Internal I/O

Bus controller

F-bus RAM

26

MB91305

3. Programming Model

• Programming Model

32 bits

Initial value

R0

R1

XXXX XXXX^H

General-purpose

register

R12

R13

R14

R15

AC

XXXX XXXXH

0000 0000H

FP

SP

PC

Program counter

Program status

ILM

CCR

PS

SCR

TBR

RP

Table base register

Return pointer

SSP

USP

System stack pointer

User stack pointer

Multiply and

divide registers

MDH

MDL

27

MB91305

4. Registers

• General-purpose Registers

32 bits

Initial value

XXXX XXXXH

R0

R1

R12

R13

R14

R15

AC

FP

SP

XXXX XXXXH

0000 0000H

Registers R0 to R15 are general-purpose registers. These registers are used as an accumulator in an operation

or a pointer in a memory access.

Of these 16 registers, the following are intended for special applications and therefore enhanced instructions

are provided for them :

• R13 :

Virtual accumulator (AC)

• R14 :

Frame pointer (FP)

• R15 :

Stack pointer (SP)

The initial value upon reset is undefined for R0 through R14 and is “00000000^H” (SSP value) for R15.

• PS (Program Status)

The program status register (PS : Program Status) holds the program status. The PS register consists of three

parts : ILM, SCR, and CCR. All undefined bits are reserved. During reading, “0” is always read. Writing is

disabled.

bit31

bit20

bit16

bit10bit8 bit7

bit0

ILM

SCR

CCR

28

MB91305

• CCR (Condition Code Register)

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Initial value

--00XXXX^B

⎯

S

I

N

Z

V

C

S : Stack flag

• This bit is cleared to “0” by a reset.

• Set this bit to “0” when the RETI instruction is executed.

I : Interrupt enable flag

This bit is cleared to “0” by a reset.

N : Negative flag

The initial state of this bit upon reset is undefined.

Z : Zero flag

The initial state of this bit upon reset is undefined.

V : Overflow flag

The initial state of this bit upon reset is undefined.

C : Carry flag

The initial state of this bit upon reset is undefined.

• SCR (System Condition code Register)

bit10 bit9 bit8

Initial value

XX0^B

D1

D0

T

D1, D0 : Step division flag

These bits hold the intermediate data obtained when step division is executed.

T : Step trace trap flag

This bit specifies whether the step trace trap is to be enabled.

The step trace trap function is used by an emulator. When an emulator is used, this function cannot be used in

a user program.

• ILM (Interrupt Level Mask Register)

bit18

bit16

Initial value

01111^B

bit17

bit19

bit20

ILM4 ILM3 ILM2 ILM1 ILM0

The interrupt level mask (ILM) register holds an interrupt level mask value. The value held in ILM register is

used as a level mask.

This register is initialized to 15 (01111^B) by a reset.

29

MB91305

• PC (Program Counter)

Initial value

bit31

bit0

XXXXXXXX^H

The program counter indicates the address of the instruction being executed.

The initial value upon reset is undefined.

• TBR (Table Base Register)

Initial value

000FFC00^H

bit0

bit31

The table base register holds the first address of the vector table to be used during EIT processing.

The initial value upon reset is “000FFC00^H”.

• RP (Return Pointer)

Initial value

bit0

bit31

XXXXXXXX^H

The return pointer holds the return address from a subroutine.

When the CALL instruction is executed, the value of the PC is transferred to the RP.

When the RET instruction is executed, the contents of the RP are transferred to the PC.

The initial value upon reset is undefined.

• SSP (System Stack Pointer)

Initial value

00000000^H

bit0

bit31

The SSP is the system stack pointer.

This register is used as an R15 general-purpose register if the S flag of the condition code register (CCR) is “0”.

The SSP can also be specified explicitly.

This register is also used as a stack pointer that specifies a stack on which the contents of the PS and PC are

to be saved if an EIT occurs.

The initial value upon reset is “00000000^H”.

30

MB91305

• USP (User Stack Pointer)

Initial value

bit31

bit0

XXXXXXXX^H

The USP is the user stack pointer.

This register is used as an R15 general-purpose register if the S flag of the condition code register (CCR) is “1”.

The USP can also be specified explicitly.

The initial value upon reset is undefined.

This register cannot be used by the RETI instruction.

• MDH/MDL (Multiply & Divide register)

Initial value

bit31

bit0

MDH

MDL

XXXXXXXX^H

MDH and MDL are the multiply and divide registers. Each register is 32 bits long.

The initial value upon reset is undefined.

31

MB91305

■ MODE SETTINGS

For the FR family, set the operating mode using the mode pins (MD3, MD2, MD1 and MD0) and the mode

register (MODR) .

1. Mode pins

Use the four mode pins (MD3, MD2, MD1, and MD0) to specify mode vector fetch.

shows the specification related to the mode vector fetch.

Mode pin

Reset vector access

Mode name

Remarks

area

MD3 MD2 MD1 MD0

External ROM

mode vector

With USB.

Used at 48 MHz source oscillation.

0

1

0

External

External ROM

mode vector

Without USB.

Used at 16 MHz source oscillation.

External

Note : The setting other than that shown is prohibited. The single-chip mode is not supported.

2. Mode Register (MODR)

• Detailed explanation of the register

MODR

Initial value

XXXXXXXX^B

bit23

0

bit22

0

bit21

0

bit20

0

bit19

0

bit18

bit17

bit16

Address

07FD^H

ROMA WTH1 WTH0

Operation mode setting bit

Mode data is data written to the mode register by a mode vector fetch.

After setting to the mode register (MODR) is completed, perform with the operation mode according to this

register.

The mode register is set by all reset sources. Accordingly, user program cannot write data to the mode register.

• Detailed explanation of the mode data.

• In the save way of the reset vector, set the mode vector in the vector area.

• Details of the mode data which sets to the mode vector is shown below.

Initial value

bit31

0

bit30

0

bit29

0

bit28

0

bit27

0

bit26

bit25

bit24

Address

FFFF8^H

XXXXXXXX^B

ROMA WTH1 WTH0

Operation mode setting bit

[bit31 to bit27] Reserved bits

Be sure to set “00000^B” to these bits.

Operation when value other than “00000^B” is set cannot guarantee.

[bit26] ROMA (Internal ROM enable bit)

This bit sets whether to enable internal ROM areas.

32

MB91305

ROMA

Function

Remarks

0

External ROM mode * Internal F-bus region (40000^Hto 100000^H) becomes an external region.

Internal F-bus region (40000^Hto 100000^H) becomes access prohibited

1

Internal ROM mode

(setting disabled) .

* : MB91305 does not contain internal ROM. Use as external ROM mode (setting ROMA = 0) .

[bit25, bit24] WTH1, WTH0 (Bus width specification bit)

Set the bus width specification in external bus mode.

This value is set by DBW1 and DBW0 bits of ACR0 (CS0 area) in the external bus mode.

WTH1

WTH0

Function

8-bit bus width

Remarks

0

1

0

1

0

1

External bus mode

16-bit bus width

32-bit bus width

Single-chip mode *

External bus mode (setting disabled)

Single-chip mode (setting disabled)

* : not supported.

Note : Mode data set in mode vector must be allocated to “0x000FFFF8^H” as a byte data. In the FR family, since

big endian is used as byte endian, the data must be allocated to the most significant byte in bit31 to bit24

as shown below.

bit31

bit24 bit23

XXXXXXXX

Reset Vector

bit16 bit15

bit8 bit7

bit0

Address

0x000FFFF8^H

XXXXXXXX

Mode Data

XXXXXXXX

0x000FFFFC^H

33

MB91305

■ MEMORY SPACE

1. Memory Space

The FR family has a logical address space of 4G bytes (2³²addresses) , which the CPU accesses linearly.

• Direct addressing area

The areas in the address space listed below are used for input-output.

These areas are called the direct addressing area. The address of an operand can be directly specified in an

instruction.

The size of the direct addressing area varies according to the size of data to be accessed :

• Byte data access

: 000^Hto 0FF^H

• Halfword data access : 000^Hto 1FF^H

• Word data access

: 000^Hto 3FF^H

2. Memory Map

External ROM External bus mode

0000 0000H

Direct

addressing area

I/O

0000 0400H

See "3. I/O MAP"

0001 0000H

0003 0000H

Access

disallowed

Built-in RAM

0004 0000H

0005 0000H

Access

disallowed

External

area

USB

function

0006 0000H

0007 0000H

Fixed in the CS2 area

External

area

FFFF FFFFH

Note : Internal RAM area of the MB91305 is “0003 0000^H” to “0003 FFFF^H”.

34

MB91305

■ I/O MAP

Shows the correspondence between the memory space area and the peripheral resource registers.

Reading the table

Register

Address

Block

+0

PDR0 [R/W] PDR1 [R/W] PDR2 [R/W] PDR3 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

+1

+2

+3

T-unit

Port Data Register

000000^H

Read/write attribute

Initial value of register after reset

Register name (column 1 of the register is at address 4n,

column 2 is at address 4n + 2...)

Leftmost register address (For word-length access,

column 1 of the register becomes the MSB of the data.)

Note : The initial value of bits in a register are indicated as follows :

“1” : Initial value “1”

“0” : Initial value “0”

“X” : Initial value “X”

“-” : A physical register does not exist at the location.

35

MB91305

Register

Address

Block

+0

+1

⎯

+2

+3

000000^H

to

00000F^H

⎯

Reserved

PDR0[R/W]

XXXXXXXX

PDR1[R/W]

XXXXXXXX

PDR2[R/W]

XXXXXXXX

PDR3[R/W]

XXXXXXXX

000010^H

000014^H

000018^H

00001C^H

000020^H

000024^H

000028^H

00002C^H

000030^H

000034^H

PDR4[R/W]

XXXXXXXX

PDR5[R/W]

XXXXXXXX

PDR6[R/W]

--XXXXXX

PDR7[R/W]

--XXXXXX

R-bus

Port Data

Register

PDR8[R/W]

XXXXXXXX

PDR9[R/W]

XXXXXXXX

PDRA[R/W]

-----XXX

PDRB[R/W]

XXXXXXXX

PDRC[R/W]

XXXXXXXX

PDRD[R/W]

--XXXXXX

PDRE[R/W]

-----XXX

PDRF[R/W]

XXXXXXXX

ADCTH[R/W]

XXXXXX00

ADCTL[R/W]

00000X00

ADCH[R/W]

00000000 00000000

ADAT0[R]

XXXXXX00 00000000

ADAT1[R]

XXXXXX00 00000000

ADAT2[R]

XXXXXX00 00000000

ADAT3[R]

XXXXXX00 00000000

ADAT4[R]

XXXXXX00 00000000

ADAT5[R]

XXXXXX00 00000000

10-bit A/D

converter

ADAT6[R]

XXXXXX00 00000000

ADAT7[R]

XXXXXX00 00000000

ADAT8[R]

XXXXXX00 00000000

ADAT9[R]

XXXXXX00 00000000

TEST [R/W]

00000000

000038^H

00003C^H

000040^H

⎯

Reserved

HEIRR0 [R/W]

00000000

ENIR0 [R/W]

00000000

ELVR0 [R/W]

00000000

External interrupt

DICR [R/W]

-------0

HRCL [R/W]

0--11111

000044^H

000048^H

00004C^H

000050^H

000054^H

⎯

DLYI/I-unit

TMRLR0 [W]

XXXXXXXX XXXXXXXX

TMR0 [R]

XXXXXXXX XXXXXXXX

16-bit

Reload Timer 0

TMCSR0 [R/W]

----0000 00000000

⎯

TMRLR1 [W]

XXXXXXXX XXXXXXXX

TMR1 [R]

XXXXXXXX XXXXXXXX

16-bit

Reload Timer 1

TMCSR1 [R/W]

----0000 00000000

⎯

(Continued)

36

MB91305

Register

Address

Block

+0

+1

+2

+3

TMRLR2 [W]

XXXXXXXX XXXXXXXX

TMR2 [R]

XXXXXXXX XXXXXXXX

000058^H

00005C^H

16-bit

Reload Timer 2

TMCSR2 [R/W]

----0000 00000000

⎯

SIDR0 [R]/

SODR0 [W]

XXXXXXXX

SSR0 [R/W]

00001000

SCR0 [R/W]

00000100

SMR0 [R/W]

00--0-0-

000060^H

000064^H

000068^H

00006C^H

000070^H

000074^H

000078^H

00007C^H

000080^H

000084^H

UART0

U-TIMER 0

UART1

UTIM0 [R] (UTIMR0 [W])

00000000 00000000

DRCL0 [W]

--------

UTIMC0 [R/W]

0--00001

SIDR1 [R]/

SODR1 [W]

XXXXXXXX

SSR1 [R/W]

00001000

SCR1 [R/W]

00000100

SMR1 [R/W]

00--0-0-

UTIM1 [R] (UTIMR1 [W])

00000000 00000000

DRCL1 [W]

--------

UTIMC1 [R/W]

0--00001

U-TIMER 1

UART2

SIDR2 [R]/

SODR2 [W]

XXXXXXXX

SSR2 [R/W]

00001000

SCR2 [R/W]

00000100

SMR2 [R/W]

00--0-0-

UTIM2 [R] (UTIMR2 [W])

00000000 00000000

DRCL2 [W]

--------

UTIMC2 [R/W]

0--00001

U-TIMER 2

UART3

SIDR3 [R]/

SODR3 [W]

XXXXXXXX

SSR3 [R/W]

00001000

SCR3 [R/W]

00000100

SMR3 [R/W]

00--0-0-

UTIM3 [R] (UTIMR3 [W])

00000000 00000000

DRCL3 [W]

--------

UTIMC3 [R/W]

0--00001

U-TIMER 3

UART4

SIDR4 [R]/

SODR4 [W]

XXXXXXXX

SSR4 [R/W]

00001000

SCR4 [R/W]

00000100

SMR4 [R/W]

00--0-0-

UTIM4 [R] (UTIMR4 [W])

00000000 00000000

DRCL4 [W]

--------

UTIMC4 [R/W]

0--00001

U-TIMER 4

Reserved

000088^H

00008C^H

⎯

PWCCL[R/W]

0000--00

PWCCH[R/W]

00-00000

000090^H

000094^H

000098^H

00009C^H

⎯

PWCD[R]

XXXXXXXX XXXXXXXX

PWC

PWCC2[R/W]

000-----

Reserved

PWCUD[R]

XXXXXXXX XXXXXXXX

(Continued)

37

MB91305

Register

Address

Block

+0

+1

+2

+3

0000A0^H

0000A4^H

0000A8^H

0000AC^H

⎯

Reserved

IFN0 [R]

00000000

IFRN0 [R/W]

00000000

IFCR0 [R/W]

00-00000

IFDR0 [R/W]

00000000

0000B0^H

0000B4^H

0000B8^H

0000BC^H

0000C0^H

0000C4^H

0000C8^H

0000CC^H

0000D0^H

0000D4^H

0000D8^H

0000DC^H

0000E0^H

0000E4^H

0000E8^H

IBCR0 [R/W]

00000000

IBSR0 [R]

00000000

ITBA0 [R, R/W]

00000000 00000000

I²C interface ch.0

I²C interface ch.1

I²C interface ch.2

ITMK0 [R/W]

00111111 11111111

ISMK0 [R/W]

01111111

ISBA0 [R/W]

00000000

IDAR0 [R/W]

00000000

ICCR0 [R/W]

00011111

⎯

IFN1 [R]

00000000

IFRN1 [R/W]

00000000

IFCR1 [R/W]

00-00000

IFDR1 [R/W]

00000000

IBCR1 [R/W]

00000000

IBSR1 [R]

00000000

ITBA1 [R, R/W]

00000000 00000000

ITMK1 [R/W]

00111111 11111111

ISMK1 [R/W]

01111111

ISBA1 [R/W]

00000000

IDAR1 [R/W]

00000000

ICCR1 [R/W]

00011111

⎯

IFN2 [R]

00000000

IFRN2 [R/W]

00000000

IFCR2 [R/W]

00-00000

IFDR2 [R/W]

00000000

IBCR2 [R/W]

00000000

IBSR2 [R]

00000000

ITBA2 [R, R/W]

00000000 00000000

ITMK2 [R/W]

00111111 11111111

ISMK2 [R/W]

01111111

ISBA2 [R/W]

00000000

IDA2R [R/W]

00000000

ICCR2 [R/W]

00011111

⎯

IFN3 [R]

00000000

IFRN3 [R/W]

00000000

IFCR3 [R/W]

00-00000

IFDR3 [R/W]

00000000

IBCR3 [R/W]

00000000

IBSR3 [R]

00000000

ITBA3 [R, R/W]

00000000 00000000

I²C interface ch.3

ITMK3 [R/W]

00111111 11111111

ISMK3 [R/W]

01111111

ISBA3 [R/W]

00000000

IDAR3 [R/W]

00000000

ICCR3 [R/W]

00011111

0000EC^H

0000F0^H

0000F4^H

⎯

Reserved

TCDT [R/W]

00000000 00000000

TCCS [R/W]

00000000

16-bit free-run

timer

(Continued)

38

MB91305

Register

Address

Block

+0

+1

+2

+3

IPCP1 [R]

XXXXXXXX XXXXXXXX

IPCP0 [R]

XXXXXXXX XXXXXXXX

0000F8^H

0000FC^H

000100^H

IPCP3 [R]

XXXXXXXX XXXXXXXX

IPCP2 [R]

XXXXXXXX XXXXXXXX

16-bit input

capture

ICS23 [R/W]

00000000

ICS01 [R/W]

00000000

⎯

000104^H

000108^H

00010C^H

⎯

Reserved

EIRR1 [R/W]

00000000

ENIR1 [R/W]

00000000

ELVR1 [R/W]

00000000 00000000

000110^H

External interrupt

Reserved

000114^H

to

00011F^H

⎯

PTMR0 [R]

11111111 11111111

PCSR0 [W]

XXXXXXXX XXXXXXXX

000120^H

000124^H

000128^H

00012C^H

000130^H

00134^H

PPG0

PPG1

PPG2

PDUT0 [W]

XXXXXXXX XXXXXXXX

PCNH0 [R/W]

00000000

PCNL0 [R/W]

00000000

PTMR1 [R]

11111111 11111111

PCSR1 [W]

XXXXXXXX XXXXXXXX

PDUT1 [W]

XXXXXXXX XXXXXXXX

PCNH1 [R/W]

00000000

PCNL1 [R/W]

00000000

PTMR2 [R]

11111111 11111111

PCSR2 [W]

XXXXXXXX XXXXXXXX

PDUT2 [W]

XXXXXXXX XXXXXXXX

PCNH2 [R/W]

00000000

PCNL2 [R/W]

00000000

PTMR3 [R]

11111111 11111111

PCSR3[W]

XXXXXXXX XXXXXXXX

000138^H

00013C^H

PPG3

PDUT3 [W]

XXXXXXXX XXXXXXXX

PCNH3 [R/W]

00000000

PCNL3 [R/W]

00000000

000140^H

to

0001FC^H

⎯

Reserved

DMACA0 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

000200^H

000204^H

DMAC

DMACB0 [R/W]

00000000 00000000 00000000 00000000

(Continued)

39

MB91305

Register

Address

Block

+0

+1

+2

+3

DMACA1 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

000208^H

00020C^H

000210^H

000214^H

000218^H

00021C^H

000220^H

DMACB1 [R/W]

00000000 00000000 00000000 00000000

DMACA2 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB2 [R/W]

00000000 00000000 00000000 00000000

DMACA3 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB3 [R/W]

00000000 00000000 00000000 00000000

DMAC

DMACA4 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB4 [R/W]

00000000 00000000 00000000 00000000

000224^H

000228^H

⎯

00022C^H

to

00023C^H

⎯

DMACR [R/W]

0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX

000240^H

000244^H

to

0002FC^H

⎯

Reserved

I-Cache

ISIZE[R/W]

------10

000304^H

⎯

000308^H

to

0003E0^H

⎯

Reserved

I-Cache

ICHCR[R/W]

0-000000

0003E4^H

0003E8^H

to

0003EC^H

⎯

Reserved

(Continued)

40

MB91305

Register

Address

Block

+0

+1

+2

+3

BSD0 [W]

0003F0^H

0003F4^H

0003F8^H

0003FC^H

000400^H

000404^H

000408^H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSD1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Bit Search

Module

BSDC [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSRR [R]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DDR2 [R/W]

00000000

DDR3 [R/W]

----0000

⎯

DDR4 [R/W]

00000000

DDR5 [R/W]

00000000

DDR6 [R/W]

--000000

DDR7 [R/W]

--000000

R-bus

Port Direction

Register

DDR8 [R/W]

---00000

DDR9 [R/W]

00000000

DDRA [R/W]

00000000

DDRB [R/W]

00000000

DDRC [R/W]

00000000

DDRD [R/W]

--000000

DDRE [R/W]

------00

DDRF [R/W]

00000000

00040C^H

000410^H

PFR0 [R/W]

0--00000

PFR1 [R/W]

00000000

PFR2 [R/W]

000---00

PFR3 [R/W]

----0000

PFR4 [R/W]

-----000

PFR5 [R/W]

11111111

PFR6 [R/W]

00000000

PFR7 [R/W]

-----000

000414^H

000418^H

00041C^H

R-bus

Port Function

Register

PFR9 [R/W]

11111111

PFRB [R/W]

00011-0-

⎯

PFRC [R/W]

1111--11

PFRD [R/W]

---101--

PCRA [R/W]

00000000

PCRB [R/W]

00000000

000420^H

to

00043C^H

⎯

Reserved

ICR00 [R/W]

---11111

ICR01 [R/W]

---11111

ICR02[R/W]

---11111

ICR03 [R/W]

---11111

000440^H

000444^H

000448^H

00044C^H

000450^H

000454^H

000458^H

ICR04 [R/W]

---11111

ICR05 [R/W]

---11111

ICR06 [R/W]

---11111

ICR07 [R/W]

---11111

ICR08 [R/W]

---11111

ICR09 [R/W]

---11111

ICR10 [R/W]

---11111

ICR11 [R/W]

---11111

ICR12 [R/W]

---11111

ICR13 [R/W]

---11111

ICR14 [R/W]

---11111

ICR15 [R/W]

---11111

Interrupt

Controller

ICR16 [R/W]

---11111

ICR17 [R/W]

---11111

ICR18 [R/W]

---11111

ICR19 [R/W]

---11111

ICR20 [R/W]

---11111

ICR21 [R/W]

---11111

ICR22 [R/W]

---11111

ICR23 [R/W]

---11111

ICR24 [R/W]

---11111

ICR25 [R/W]

---11111

ICR26 [R/W]

---11111

ICR27 [R/W]

---11111

(Continued)

41

MB91305

Register

Address

Block

+0

+1

+2

+3

ICR28 [R/W]

---11111

ICR29 [R/W]

---11111

ICR30 [R/W]

---11111

ICR31 [R/W]

---11111

00045C^H

000460^H

000464^H

000468^H

00046C^H

ICR32 [R/W]

---11111

ICR33 [R/W]

---11111

ICR34 [R/W]

---11111

ICR35 [R/W]

---11111

ICR36 [R/W]

---11111

ICR37 [R/W]

---11111

ICR38 [R/W]

---11111

ICR39 [R/W]

---11111

Interrupt

Controller

ICR40 [R/W]

---11111

ICR41 [R/W]

---11111

ICR42 [R/W]

---11111

ICR43 [R/W]

---11111

ICR44 [R/W]

---11111

ICR45 [R/W]

---11111

ICR46 [R/W]

---11111

ICR47 [R/W]

---11111

000470^H

to

00047C^H

⎯

Reserved

RSRR [R/W]

10000000 ^*2

STCR [R/W]

00110011 ^*2

TBCR [R/W]

00XXXX00 ^*1

CTBR [W]

XXXXXXXX

000480^H

000484^H

Clock Control

CLKR [R/W]

00000000 ^*1

WPR [W]

XXXXXXXX

DIVR0 [R/W]

00000011 ^*1

DIVR1[R/W]

00000000 ^*1

000488^H

00048C^H

000490^H

⎯

000494^H

to

0005FC^H

Reserved

⎯

000600^H

to

00063F^H

ASR0 [R/W]

ACR0 [R/W]

000640^H

000644^H

000648^H

00064C^H

000650^H

000654^H

000658^H

00000000 00000000 ^*1

1111XX00 00000000 ^*1

ASR1 [R/W]

XXXXXXXX XXXXXXXX ^*1

ACR1 [R/W]

XXXXXXXX XXXXXXXX ^*1

ASR2 [R/W]

XXXXXXXX XXXXXXXX ^*1

ACR2 [R/W]

XXXXXXXX XXXXXXXX ^*1

ASR3 [R/W]

XXXXXXXX XXXXXXXX ^*1

ACR3 [R/W]

XXXXXXXX XXXXXXXX ^*1

T-unit

ASR4 [R/W]

XXXXXXXX XXXXXXXX ^*1

ACR4 [R/W]

XXXXXXXX XXXXXXXX ^*1

ASR5 [R/W]

XXXXXXXX XXXXXXXX ^*1

ACR5 [R/W]

XXXXXXXX XXXXXXXX ^*1

ASR6 [R/W]

XXXXXXXX XXXXXXXX ^*1

ACR6 [R/W]

XXXXXXXX XXXXXXXX ^*1

(Continued)

42

MB91305

Register

Address

Block

+0

+1

+2

+3

ASR7 [R/W]

ACR7 [R/W]

00065C^H

000660^H

000664^H

000668^H

00066C^H

XXXXXXXX XXXXXXXX ^*1

AWR0 [R/W]

01111111 11111111 ^*1

AWR1 [R/W]

XXXXXXXX XXXXXXXX ^*1

AWR2 [R/W]

XXXXXXXX XXXXXXXX ^*1

AWR3 [R/W]

XXXXXXXX XXXXXXXX ^*1

AWR4 [R/W]

XXXXXXXX XXXXXXXX ^*1

AWR5 [R/W]

XXXXXXXX XXXXXXXX ^*1

AWR6 [R/W]

XXXXXXXX XXXXXXXX ^*1

AWR7 [R/W]

XXXXXXXX XXXXXXXX ^*1

T-unit

MCRA [R/W]

XXXXXXXX

MCRB [R/W]

XXXXXXXX

000670^H

000674^H

000678^H

00067C^H

000680^H

⎯

IOWR0 [R/W]

XXXXXXXX

IOWR1 [R/W]

XXXXXXXX

IOWR2 [R/W]

XXXXXXXX

⎯

CSER [R/W]

00000001

CHER [R/W]

11111111

TCR [R/W]

00000000

⎯

RCR [R/W]

00XXXXXX XXXX0XXX

000684^H

⎯

000688^H

to

0007F8^H

⎯

Reserved

⎯

MODR [W]

XXXXXXXX

0007FC^H

⎯

000800^H

to

000AFC^H

Reserved

ESTS0 [R/W]

X0000000

ESTS1 [R/W]

XXXXXXXX

ESTS2 [R]

1XXXXXXX

000B00^H

000B04^H

000B08^H

000B0C^H

000B10^H

ECTL0 [R/W]

0X000000

ECTL1 [R/W]

00000000

ECTL2 [W]

000X0000

ECTL3 [R/W]

00X00X11

ECNT0 [W]

XXXXXXXX

ECNT1 [W]

XXXXXXXX

EUSA [W]

XXX00000

EDTC [W]

0000XXXX

DSU

EWP1 [R]

00000000 00000000

⎯

EDTR0 [W]

XXXXXXXX XXXXXXXX

EDTR1 [W]

XXXXXXXX XXXXXXXX

(Continued)

43

MB91305

Register

Address

Block

+0

+1

+2

+3

000B14^H

to

000B1C^H

⎯

EIA0 [W]

000B20^H

000B24^H

000B28^H

000B2C^H

000B30^H

000B34^H

000B38^H

000B3C^H

000B40^H

000B44^H

000B48^H

000B4C^H

000B50^H

000B54^H

000B58^H

000B5C^H

000B60^H

000B64^H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA2 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA3 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA4 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA5 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA6 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA7 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EDTA [R/W]

DSU

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EDTM [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOA0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOA1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EPCR [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EPSR [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIAM0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIAM1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOAM0/EODM0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOAM1/EODM1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

(Continued)

44

MB91305

(Continued)

Register

Address

Block

+0

+1

+2

+3

EOD0 [W]

000B68^H

000B6C^H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DSU

EOD1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B70^H

to

000FFC^H

⎯

Reserved

DMASA0 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001000^H

001004^H

001008^H

00100C^H

001010^H

001014^H

001018^H

00101C^H

001020^H

001024^H

DMADA0 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMASA1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMADA1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMASA2 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMAC

DMADA2 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMASA3 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMADA3 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMASA4 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMADA4 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001028^H

to

007104^H

⎯

Reserved

*1 : Register whose initial value depends on the reset level. The registers at the INIT level are indicated.

*2 : Register whose initial value depends on the reset level. The registers at the INIT level due to the INIT pin are

indicated.

45

MB91305

Register

Address

Block

+0

+1

+2

+3

FIFO0o [R]

XXXXXXXX XXXXXXXX

FIFO0i [W]

XXXXXXXX XXXXXXXX

00060000^H

00060004^H

00060008^H

FIFO1 [R]

XXXXXXXX XXXXXXXX

FIFO2 [W]

XXXXXXXX XXXXXXXX

FIFO3 [R]

XXXXXXXX XXXXXXXX

-⎯

0006000C^H

to

0006001F^H

⎯

CONT1 [R/W]

000XX0XX XXX00000

00060020^H

00060024^H

00060028^H

0006002C^H

00060030^H

00060034^H

⎯

CONT2 [R/W]

XXXXXXXX XXX00000

CONT3 [R/W]

XXXXXXXX XXX00000

CONT4 [R/W]

XXXXXXXX XXX00000

CONT5 [R/W]

XXXXXXXX XXXX00XX

CONT6 [R/W]

XXXXXXXX XXXX00XX

CONT7 [R/W]

XXXXXXXX XXX00000

CONT8 [R/W]

XXXXXXXX XXX00000

CONT9 [R/W]

0XX0XXXX 0XXX0000

USB Function

CONT10 [R/W]

00000000 X00000XX

TTSIZE [R/W]

00010001 00010001

TRSIZE [R/W]

00010001 00010001

00060038^H

0006003C^H

00060040^H

⎯

RSIZE0 [R]

XXXXXXXX XXXX0000

⎯

RSIZE1 [R]

XXXXXXXX X0000000

00060044^H

00060048^H

to

0006005F^H

⎯

ST1 [R/W]

XXXXXX00 00000000

00060060^H

00060064^H

00060068^H

⎯

ST2 [R]

XXXXXXXX XXX00000

ST3 [R/W]

XXXXXXXX XXX00000

ST4 [R/W]

XXXXX000 00000000

ST5 [R/W]

XXXX0XXX XX000000

0006006C^H

(Continued)

46

MB91305

(Continued)

Register

Address

Block

+0

+1

+2

+3

00060070^H

to

0006007F^H

⎯

USB Function

00060080^H

to

0006FFFB^H

Reserved

USB reset

USBRST

-0------

0006FFFC^H

⎯

47

MB91305

■ INTERRUPT SOURCE TABLE

Interrupt number

Interrupt

level

Address of

TBR default

Resource

number

Interrupt source

Offset

Hexa-

Decimal

decimal

Reset

Mode vector

0

1

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

⎯

3FC^H

3F8^H

3F4^H

3F0^H

3EC^H

3E8^H

3E4^H

3E0^H

3DC^H

3D8^H

3D4^H

3D0^H

3CC^H

3C8^H

3C4^H

000FFFFC^H

000FFFF8^H

000FFFF4^H

000FFFF0^H

000FFFEC^H

000FFFE8^H

000FFFE4^H

000FFFE0^H

000FFFDC^H

000FFFD8^H

000FFFD4^H

000FFFD0^H

000FFFCC^H

000FFFC8^H

000FFFC4^H

⎯

Reserved for system

No-coprocessor trap

Coprocessor error trap

INTE instruction

2

3

4

5

6

7

8

9

Instruction break exception

Operand break trap

Step trace trap

10

11

12

13

14

NMI request (tool)

Undefined instruction exception

15 (F^H)

fixed

NMI request

15

0F

3C0^H

000FFFC0^H

⎯

External interrupt 0

External interrupt 1

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

3BC^H

3B8^H

3B4^H

3B0^H

3AC^H

3A8^H

3A4^H

3A0^H

39C^H

398^H

394^H

390^H

38C^H

388^H

384^H

380^H

000FFFBC^H

000FFFB8^H

000FFFB4^H

000FFFB0^H

000FFFAC^H

000FFFA8^H

000FFFA4^H

000FFFA0^H

000FFF9C^H

000FFF98^H

000FFF94^H

000FFF90^H

000FFF8C^H

000FFF88^H

000FFF84^H

000FFF80^H

⎯

8

External interrupt 2

External interrupt 3

External interrupt 4 (USB-function)

External interrupt 5

External interrupt 6

External interrupt 7

Reload timer 0

Reload timer 1

9

Reload timer 2

10

0

UART0 (Reception completed)

UART1 (Reception completed)

UART2 (Reception completed)

UART0 (Transmission completed)

UART1 (Transmission completed)

1

2

3

4

(Continued)

48

MB91305

Interrupt number

Interrupt

level

Address of

TBR default

Resource

number

Interrupt source

Offset

Hexa-

Decimal

decimal

UART2 (Transmission completed)

DMAC0 (end or error)

DMAC1 (end or error)

DMAC2 (end or error)

DMAC3 (end or error)

DMAC4 (end or error)

A/D

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

ICR16

ICR17

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

37C^H

378^H

374^H

370^H

36C^H

368^H

364^H

360^H

35C^H

358^H

354^H

350^H

34C^H

348^H

344^H

000FFF7C^H

000FFF78^H

000FFF74^H

000FFF70^H

000FFF6C^H

000FFF68^H

000FFF64^H

000FFF60^H

000FFF5C^H

000FFF58^H

000FFF54^H

000FFF50^H

000FFF4C^H

000FFF48^H

000FFF44^H

5

⎯

PPG0

PPG1

PPG2

PPG3

PWC

External interrupt 8/U-TIMER0

External interrupt 9/U-TIMER1

External interrupt 10/U-TIMER2

Timebase timer overflow /

U-TIMER3

47

2F

ICR31

340^H

000FFF40^H

⎯

External interrupt 11/U-TIMER4

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

ICR32

ICR33

ICR34

ICR35

ICR36

ICR37

ICR38

ICR39

ICR40

ICR41

ICR42

ICR43

ICR44

ICR45

ICR46

ICR47

33C^H

338^H

334^H

330^H

32C^H

328^H

324^H

320^H

31C^H

318^H

314^H

310^H

30C^H

308^H

304^H

300^H

000FFF3C^H

000FFF38^H

000FFF34^H

000FFF30^H

000FFF2C^H

000FFF28^H

000FFF24^H

000FFF20^H

000FFF1C^H

000FFF18^H

000FFF14^H

000FFF10^H

000FFF0C^H

000FFF08^H

000FFF04^H

000FFF00^H

⎯

16-bit free-run timer

⎯

I²C ch.0

⎯

I²C ch.1

⎯

I²C ch.2

⎯

I²C ch.3

⎯

UART3 (Reception completed)

UART4 (Reception completed)

UART3 (Transmission completed)

UART4 (Transmission completed)

External interrupt 12/Input capture 0

External interrupt 13/Input capture 1

External interrupt 14/Input capture 2

External interrupt 15/Input capture 3

Reserved for system

⎯

Delayed interrupt source bit

⎯

(Continued)

49

MB91305

(Continued)

Interrupt number

Interrupt

level

Address of

TBR default

Resource

number

Interrupt source

Offset

Hexa-

Decimal

decimal

Reserved for system

(used by REALOS)

64

65

40

41

⎯

2FC^H

2F8^H

000FFEFC^H

000FFEF8^H

⎯

Reserved for system

(used by REALOS)

Reserved for system

66

67

68

69

70

71

72

73

74

75

76

77

78

79

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

⎯

-

2F4^H

2F0^H

2EC^H

2E8^H

2E4^H

2E0^H

2DC^H

2D8^H

2D4^H

2D0^H

2CC^H

2C8^H

2C4^H

2C0^H

000FFEF4^H

000FFEF0^H

000FFEEC^H

000FFEE8^H

000FFEE4^H

000FFEE0^H

000FFEDC^H

000FFED8^H

000FFED4^H

000FFED0^H

000FFECC^H

000FFEC8^H

000FFEC4^H

000FFEC0^H

⎯

80

to

255

50

to

FF

2BC^H

to

000^H

000FFEBC^H

to

000FFC00^H

Used in INT instruction

⎯

50

MB91305

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Rating

Rating

Parameter

Symbol

Unit

Remarks

*2

Min

V^SS− 0.5

V^SS− 0.3

⎯

Max

V^SS+ 4.0

V^SS+ 2.2

V^SS+ 4.0

V^DDE+ 0.3

AV^CC+ 0.3

10

Power supply voltage*¹

V^DDE

V^DDI

AV^CC

AV^RH

V^I

V

Power supply voltage (Internal) *¹

Analog power supply voltage*¹

Analog reference voltage*¹

Input voltage*¹

*2

*3

V

Analog pin input voltage*¹

V^IA

V

Output voltage*¹

V^O

V

“L” level maximum output current

“L” level average output current

“L” level total maximum output current

“L” level total average output current

“H” level maximum output current

“H” level average output current

“H” level total maximum output current

“H” level total average output current

Power consumption

I^OL

mA

mW

°C

*4

*5

I^OLAV

ΣI^OL

ΣI^OLAV

I^OH

⎯

4

⎯

100

⎯

50

*6

*4

*5

⎯

−10

I^OHAV

ΣI^OH

ΣI^OHAV

P^D

⎯

−4

⎯

−50

⎯

−20

*6

⎯

750

Operating temperature

Ta

−10

+70

Storage temperature

T^STG

⎯

+150

*1 : This parameter is based on AV^SS= V^SS= 0.0 V.

*2 : V^DDEmust not be lower than V^SS− 0.3 V.

*3 : Be careful not to exceed V^DDE+ 0.3 V, for example, when power is turned on.

*4 : Maximum output current determines the peak value of any one of corresponding pins.

*5 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the

corresponding pins.

*6 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the

corresponding pins.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

51

MB91305

2. Recommended Operating Conditions

(V^SS= AV^SS= 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

3.0

Max

3.6

V^DDE

V^DDI

AV^CC

AV^RH

Ta

V

Power supply voltage

1.65

1.95

Analog power supply voltage

Analog reference voltage

Operating temperature

V^SS− 0.3

AV^SS

V^SS+ 3.6

AV^CC

+70

V

− 10

°C

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

52

MB91305

3. DC Characteristics

(1) CPU

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Sym-

bol

Parameter

Conditions

Unit

Remarks

Min

Typ

Max

V^IH

D31 to D16

Input ports

⎯

0.7 × V^DDE

⎯

V^DDE+ 0.3

V

“H” level

input voltage

Hysteresis

input

V^HISexcept for

D31 to D16

⎯

0.8 × V^DDE

V^SS

⎯

V^DDE+ 0.3

0.25 × V^DDE

0.2 × V^DDE

V

V^IL

D31 to D16

“L” level

input voltage

Input ports

except for

D31 to D16

Hysteresis

input

V^ILS

V^SS

⎯

V^DDE= 3.0 V

I^OH= −4.0 mA

“H” level

output voltage

V^OHAll output pins

V^DDE− 0.5

⎯

V^DDE

0.4

V

V^DDE= 3.0 V

I^OL= 4.0 mA

“L” level

output voltage

V^OL

All output pins

V^SS

Input leak

current

(High-Z

outputLeakage

current)

V^DDE= 3.6 V

All input pins 0.45 V < V^I<

V^DDE

I^LI

−5

⎯

+5

µA

Pull-up

resistance

V^DDE= 3.6 V

R^UP

*1

12

25

100

kΩ

VI = 0.45 V

Pull-down

resistance

V^DDE= 3.6 V

VI = 3.3 V

R^DOWN

*2

(Multiply by 4)

When

operating at

66 MHz

f^C= 16.5 MHz

V^DDE= 3.3 V

V^DDI= 1.8 V

I^CC

⎯

120

180

mA

Power supply

current

f^C= 16.5 MHz

VDDE, VDDI

I^CCS

V^DDE= 3.3 V

⎯

60

90

mA at sleep

V^DDI= 1.8 V

Ta = +25 °C

V^DDE= 3.3 V

V^DDI= 1.8 V

I^CCH

200

1000

µA at stop

Other than

Input

capacitance

VDDE, VSS

AVCC and

C^IH

⎯

10

⎯

pF

AVSS

*1 : Pins that the I/O circuit type is B and G

*2 : Pins that the I/O circuit type is J

53

MB91305

(2) USB

[1] DC characteristics

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Typ

Sym-

bol

Parameter

“H” level

Conditions

Unit

Remarks

Min

Max

V^OH

V^OL

⎯

I^OH= −100 µA

I^OL= 100 µA

V^DDE− 0.2

⎯

V^DDE

V

output voltage

“L” level

output voltage

0

−20

−6

20

6

0.2

⎯

Full Speed

V^OH= V^DDE− 0.4 V

“H” level

output voltage

I^OH

mA

Low Speed

V^OH= V^DDE− 0.4 V

⎯

Full Speed

V^OL= 0.4 V

⎯

“L” level

output voltage

I^OL

Low Speed

V^OL= 0.4 V

⎯

Output Short-

Circuit Current

I^OS

I^LZ

⎯

300

5

mA *1

Input leak

current

µA *2

*1 : < Output Short Circuit Current I^OS>

The output short circuit current I^OSis the maximum current that flows when the output pin is connected to VDDE

or VSS pin (within the maximum rating) .

Output Short Circuit Current : The output short circuit current’s value is the short-circuit current value of one

terminal in one side of the differential output terminal. As this USB I/O buffer is

a differential output, consider both of the pins.

Monitor short circuit current

“H” level

“H” output

Short-circuit to GND level

Short-circuit to V^DDElevel

3-State Enable "L"

“L” output

“L” level

Monitor short circuit current

3-State Enable "L"

54

MB91305

*2 : < Z leak current I^LZmeasurement >

The leak current when V^DDEor V^SSpotential is impressed to bi-directional pin at high-impedance state of USB

I/O buffer is the input leak current I^LZ.

Monitor leak current

Z output

Impressed 0 V, V^DDElevel to

output pin

3-State Enable "H"

55

MB91305

[2] DC Characteristics

Conform to USB Specification Revision 1.1

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Parameter

Symbol

Unit Remarks

Min

2.0

⎯

Max

⎯

High (driven)

V^IH

V^IL

V

*1

*2

*3

*4

Low

0.8

Input Levels

Differential Input Sensitivity

Common Mode Range

Low

V^DI

0.2

0.8

0.0

2.8

1.3

⎯

V^CM

V^OL

V^OH

V^CRS

R^PU

R^PD

2.5

0.3

Output Levels High (driven)

Differential Output Signal Voltage

3.6

2.0

Bus Pull-Up Resistor on Upstream Port

1.425

3.0

1.575

3.6

kΩ 1.5 kΩ 5%

Terminations Bus Pull-Down Resistor on Downstream Port

Termination Voltage for Upstream Port Pull-Up V^TERM

*1 : < Input Levels V^IHand V^IL>

V

*5

The switching-threshold voltage of the single-end-receiver in USB I/O buffer is set within the following range; V^IL

(Max) = 0.8 V, V^IH(Min) = 2.0 V (TTL input standard).

And, to fall the noise sensitivity, a little hysteresis is set.

56

MB91305

*2 : < Input Levels V^DIand V^CM>

Reception of the USB differential data signal uses the differential-receiver.

The differential input sensitivity of the differential-receiver is 200 mV, when the difference voltage between the

differrential data input and local ground reference level is the following ranges; 0.8 V to 2.5 V.

The voltage range above is called the common²mode input voltage range.

1.0

0.2

0.8

2.5

Common mode input voltage (V)

*3 : < Output Levels V^OLand V^OH>

The driver’s output driving ability is set to following;

- at low state (V^OL) : less than 0.3 V (vs. 3.6 V, 1.5 kΩ load)

- at high state (V^OH) : more than 2.8 V (vs. ground, 1.5 kΩ load)

*4 : < Output Levels V^CRS>

The cross voltage of the external differrencial output signal (D+/D−) in USB buffer is from 1.3 V to 2.0 V.

D+

Max 2.0 V

V^CRSstandard range

Min 1.3 V

D−

*5 : < Terminations V^TERM>

Pull-up voltage for the upstream port is shown.

57

MB91305

4. AC Characteristics

(1) Clock timing ratings

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Condi-

tions

Parameter

Clock frequency (1)

Clock cycle time

Symbol

Unit

Remarks

Min

37.5

12.5

⎯

Max

48

MHz

ns

X0

X1

f^C

16

⎯

Using PLL*¹

20.8

62.5

X0

X1

t^C

⎯

ns

X0

X1

Self-oscillation

(1/2 division input)

Clock frequency (2)

Clock frequency (3)

Clock cycle time

f^C

t^C

10

40

16

⎯

50

100

⎯

MHz

ns

X0

X1

X0

X1

At external clock

P^WH

P^WL

X0

X1

Input clock pulse width

ns

Input clock rise time

and fall time

t^CR

t^CF

X0

X1

8

ns

t^CR+ t^CF

f^CP

f^CPP

f^CPT

t^CP

3.125*²

15.6

64

32

MHz CPU

Internal operating clock

frequency

⎯

MHz Peripheral

MHz External bus

32

1280*²

ns

CPU

Internal operating clock

cycle time

t^CPP

t^CPT

31.2

Peripheral

External bus

31.2

*1 : This value is as follows;

- With USB function (MD pin = 0000^B)

: 37.5 MHz to 48 MHz And using USB: fixed to 48 MHz

(operation at a maximum internal speed of 64 MHz by

quadrupling a self-oscillation frequency of 48 MHz via PLL of

divided by 3.)

- Without USB function (MD pin = 0010^B) : 12.5 MHz to 16 MHz

(operation at a maximum internal speed of 64 MHz by

quadrupling a self-oscillation frequency of 16 MHz via PLL.)

*2 : The values shown represent a minimum clock frequency of 12.5 MHz input at the X0 pin, using the oscillation

circuit PLL and a gear ratio of 1/16.

12.5 [MHz] × 4 (multiply) × 1/16 (gear 1/16) = 3.125 [MHz]

58

MB91305

• Conditions for measuring the clock timing ratings

t

C

Output pin

0.8 VDDE

0.2 VDDE

C = 30 pF

P

WH

PWL

t

CF

tCR

• Operation Assurance Range

VDDI [V]

Operation Assurance Range (Ta = − 10 °C to + 70 °C)

VDDE = 3.0 V to 3.6 V

f^CPPis represented by the shaded area.

1.95

1.65

f

CP/fCPP

0

0.3125

33

66

[MHz]

Internal clock

59

MB91305

• External/internal clock setting range

Oscillation input clock

Without USB fc = 16 MHz

WIth USB fc = 48 MHz

[MHz]

fCP

fCPT

,

64

CPU :

Peripheral, External bus :

32

fCPP

16.5

CPU : Division ration

for peripheral

4 : 4

2 : 2

1 : 2

Notes : • When the PLL is used, the external clock input must fall between 12.5 MHz and 16.5 MHz.

• Set the PLL oscillation stabilization wait time longer than 500 µs.

• The internal clock gear setting should not exceed the relevant value in the table in (1) "Clock timing ratings”.

60

MB91305

(2) Clock output timing

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Condi-

tions

Parameter

Symbol

Unit

Remarks

Min

Max

MCLK

SYSCLK

Cycle time

t^CYC

t^CPT

⎯

ns

*1

MCLK (SYSCLK) ↑

→

MCLK

SYSCLK

t^CHCL

1/2 × t^CYC− 3

1/2 × t^CYC+ 3

ns

*2

*3

⎯

MCLK (SYSCLK) ↓

→

MCLK (SYSCLK) ↑

MCLK

SYSCLK

t^CLCL

t

CYC

t

CHCL

tCLCH

V

OH

VOH

MCLK

V

OL

SYSCLK

*1 : t^CYCis the frequency of one clock cycle after gearing.

*2 : The following ratings are for the gear ratio set to 1.

For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the

following equation.

t^CHCL= (1 / 2 × 1 / n) × t^CYC− 10

*3 : The following rating are for the gear ratio set to 1.

61

MB91305

(3) Reset and hardware standby input ratings

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Condi-

tions

Parameter

INIT input time

Symbol

Unit

Remarks

Min

Max

*

⎯

ns

(at power-on)

t^INTL

INIT

⎯

INIT input time

(other than at power-on)

t^CP× 5

⎯

ns

* : INIT input time (at power-on)

FAR resonator, ceramic oscillator : φ × 2¹⁵or greater recommended

Crystal : φ × 2²¹or greater recommended

φ : Power on → X0/X1 period × 2

t

INTL

INIT

0.2 Vcc

62

MB91305

(4-1) Normal bus access read/write operation

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Condi-

tions

Parameter

Symbol

Unit Remarks

Min

Max

CS0/CS1/CS4/CS5/

CS6/CS7 setup

t^CSLCH

t^CSHCH

3

⎯

ns

MCLK/SYSCLK

CS0 to CS7

CS0/CS1/CS4/CS5/

CS6/CS7 hold

3

t^CYC/ 2 + 6

Address setup

Address hold

t^ASCH

t^CHAX

3

⎯

ns

MCLK/SYSCLK

A23 to A0

t^CYC/ 2 + 6

Valid address →

Valid data input time

A23 to A0

D31 to D16

*1

ns

t^AVDV

⎯

3/2 × t^CYC− 15

*2

WR0 , WR1 delay time

t^CHWL

t^CHWH

⎯

6

ns

MCLK/SYSCLK

WR0, WR1

WR0 , WR1 minimum

pulse width

t^WLWH

t^DSWH

t^WHDX

WR0, WR1

t^CYC− 3

t^CYC

⎯

ns

Data setup → WRx ↑

WR0, WR1

D31 to D16

⎯

WRx ↑ → Data hold

time

5

RD delay time

t^CHRL

t^CHRH

⎯

6

ns

MCLK/SYSCLK

RD

RD ↓ →

Valid data input time

t^RLDV

⎯

t^CYC− 15

ns

*1

RD

D31 to D16

Data setup

→ RD ↑ Time

t^DSRH

t^RHDX

t^RLRH

15

0

⎯

ns

RD ↑ → Data hold time

RD minimum pulse

width

RD

t^CYC− 3

AS setup

AS hold

t^ASLCH

t^ASHCH

3

⎯

ns

MCLK/SYSCLK

AS

*1 : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (t^CYC× the number of

cycles added for the delay) to this rating.

*2 : The following ratings are for the gear ratio set to 1.

For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 and 1/8 for n in the

following equation.

t^AVDV: 3 / (2n) × t^CYC− 15

63

MB91305

t

CYC

BA1

V

OH

V

OH

V

OH

VOH

MCLK

SYSCLK

t

ASHCH

t

ASLCH

V

OH

AS

VOL

LBA

t

CSLCH

t

CSHCH

V

OH

V

OL

CS0 to CS7

A23 to A00

RD

ASCH

t

CHAX

V

OH

OL

V

OH

OL

t

CHRH

t

CHRL

t

RLRH

V

OL

V

OH

t

RHDX

t

RLDV

t

DSRH

t

AVDV

V

OH

OL

V

OH

OL

D31 to D16

t

CHWL

tCHWH

t

WLWH

V

OL

WR0, WR1

D31 to D16

V

OH

t

WHDX

DSWH

V

OH

OL

V

OH

write

V

VOL

64

MB91305

(4-2) Multiplex bus access read/write operation

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Condi-

tions

Parameter

Symbol

Unit Remarks

Min

Max

D31 to D16 address

setup time

→ MCLK (SYSCLK) ↑

t^ASCH

3

⎯

ns

MCLK/SYSCLK

D31 to D16

(address)

MCLK (SYSCLK) ↑ →

D31 to D16 address

hold time

t^CHAX

t^ASASH

t^ASHAX

3

12

t^CYC/ 2 + 6

ns

⎯

D31 to D16 address

setup time → AS ↑

⎯

ns

*

AS

D31 to D16

(address)

AS ↑ →

D31 to D16 address

hold time

t^CYC− 3

t^CYC+ 3

* : At CS → RD/WR setup extension = 1

Note : Use the same rating as normal bus interface except for this rating.

65

MB91305

• At CS → RD/WR setup extension = 1

t^CYC

BA1

BA2

BA3

BA1W

MCLK

VOH

SYSCLK

tASLCH

tASHCH

VOH

AS

VOL

tASASH

tASHAX

tCSLCH

tASCH

CS0 to CS7

D31 to D16

VOL

tCHAX

VOH

VOL

VOH

VOL

VIH

VIL

VIH

VIL

Address

Read data

tDSRH

tRHDX

VOH

tRLDV

VOL

RD

tRLRH

tCHRL

tCHRH

VOH

VOL

VOH

VOL

VOH

VOL

VOH

Write data

Address

D31 to D16

WR0, WR1

VOL

tDSWH

VOL

tWHDX

VOH

tWLWH

tCHWH

tCHWL

VOH

VOL

Address

A23 to A00

66

MB91305

• At CS → RD/WR setup extension = 0

t^CYC

BA1

BA2

BA3

MCLK

VOH

SYSCLK

VOH

VOL

AS

tASLCH

tCSLCH

tASHCH

CS0 to CS7

D31 to D16

VOL

tASCH

VOH

tCHAX

VIH

VIL

VOH

VOL

VIH

VIL

Address

Read data

VOL

tDSRH

tRHDX

VOH

tRLDV

VOL

RD

tRLRH

tCHRH

tCHRL

VOH

VOL

VOH

VOL

VOH

VOL

Address

Write data

D31 to D16

tDSWH

tWHDX

VOH

VOL

WR0, WR1

A23 to A00

tWLWH

tCHWL

tCHWH

VOH

VOL

Address

67

MB91305

(5) Ready input timings

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Condi-

tions

Parameter

Symbol

Unit

Remarks

Min

Max

MCLK

SYSCLK

RDY

RDY setup time →

MCLK (SYSCLK) ↓

t^RDYS

⎯

10

⎯

ns

MCLK

SYSCLK

RDY

MCLK (SYSCLK) ↓ →

RDY hold time

t^RDYH

0

⎯

ns

t

CYC

MCLK

V

OH

VOH

SYSCLK

V

OL

VOL

t

RDYS

t

RDYH

t

RDYS

tRDYH

RDY

with wait

V

OH

V

OH

V

OL

V

OL

RDY

without wait

OH

V

OH

V

OL

V

OL

68

MB91305

(6) Hold timing

Parameter

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Condi-

Symbol

Unit

Remarks

tions

Min

Max

MCLK

SYSCLK

BGRNT

BGRNT delay time

t^CHBGL

t^CHBGH

t^XHAL

t^HAHV

t^CYC/ 2 − 6 t^CYC/ 2 + 6

ns

⎯

Pin floating

→ BGRNT ↓ time

t^CYC− 10

t^CYC+ 10

ns

BGRNT

BGRNT ↑ →

Pin valid time

Note : It takes one cycle or more from when BRQ is captured until BGRNT changes.

t

CYC

V

OH

V

OH

V

OH

VOH

MCLK

SYSCLK

BRQ

t

CHBGL

tCHBGH

V

OH

BGRNT

V

OL

t

XHAL

t

HAHV

V

OH

OL

V

OH

OL

Each pin

V

High-impedance

69

MB91305

(7) UART timing

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

Serial clock cycle time

t^SCYC

t^SLOV

SCK0 to SCK4

8 t^CYCP

⎯

ns

SCLK ↓ →

SOUT delay time

SCK0 to SCK4

SOUT0 to SOUT4

−80

100

60

+80

⎯

Internal shift

clock mode

Valid SIN →

SCLK ↑

SCK0 to SCK4

SIN0 to SIN4

t^IVSH

t^SHIX

t^SHSL

t^SLSH

t^SLOV

t^IVSH

t^SHIX

ns

SCLK ↑ →

valid SIN hold time

SCK0 to SCK4

SIN0 to SIN4

⎯

Serial clock

“H” Pulse Width

SCK0 to SCK4

4 t^CYCP

⎯

Serial clock

“L” Pulse Width

⎯

External

shift clock

mode

SCLK ↓ →

SOUT delay time

SCK0 to SCK4

SOUT0 to SOUT4

150

⎯

Valid SIN →

SCLK ↑

SCK0 to SCK4

SIN0 to SIN4

60

SCLK ↑ →

valid SIN hold time

SCK0 to SCK4

SIN0 to SIN4

60

⎯

Notes : • Above rating is for CLK synchronous mode.

• t^CYCPindicates the peripheral clock cycle time.

70

MB91305

• Internal shift clock mode

tSCYC

VOL

VOH

SCK0 to SCK4

VOL

tSLOV

VOH

VOL

SOUT0 to SOUT4

tIVSH

tSHIX

VOH

VOL

VOH

VOL

SIN0 to SIN4

• External shift clock mode

tSLSH

tSHSL

VOL

SCK0 to SCK4

VOH

tSLOV

VOH

VOL

SOUT0 to SOUT4

tIVSH

VOH

VOL

VOH

VOL

SIN0 to SIN4

71

MB91305

(8) Timer clock Input Timing

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Parameter

Symbol

Conditions

Unit

Remarks

Min

Max

t^TIWH

t^TIWL

Input pulse width

TIN0 to TIN2

⎯

2 t^CYCP

⎯

ns

Note : t^CYCPindicates the peripheral clock cycle time.

VIH

VIL

tTIWH

tTIWL

(9) Trigger Input Timing

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Parameter

Symbol

Conditions

Unit

Remarks

Min

Max

A/D activation trigger input

time

t^ATG

ATRG

⎯

5 t^CYCP

⎯

ns

Note : t^CYCPindicates the peripheral clock cycle time.

tATG

VIH

ATRG

72

MB91305

(10) DMA controller timing

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Condi-

tions

Parameter

Symbol

Unit Remarks

Min

5 t^CYC

⎯

Max

⎯

6

DREQ Input pulse width

DACK delay time

t^DRWH

t^CLDL

t^CLDH

t^CLEL

DREQ0 to DREQ2

ns

MCLK/SYSCLK

DACK0 to DACK2

⎯

6

⎯

6

MCLK/SYSCLK

DEOP delay time

IORD delay time

IOWR delay time

ns

DEOP0 to DEOP2

t^CLEH

t^CLIRL

t^CLIRH

t^CLIWL

t^CLIWH

⎯

6

⎯

6

MCLK/SYSCLK

⎯

6

⎯

6

⎯

6

73

MB91305

tCYC

BA1

BA2

VOH

MCLK

VOL

SYSCLK

tCLDL

tCLDH

VOH

VOL

DACK0 to DACK2

tCLEL

tCLEH

VOL

DEOP0 to DEOP2

VOH

tCLIRL

tCLIRH

VOL

IORD

VOH

tCLIWL

tCLIWH

VOL

IOWR

VOH

tDRWH

VOL

DREQ0 to DREQ2

VOH

Note : The waveform of DACKx and DEOPx is the waveforms when the PFR register is set to FR30 compatible

timing.

When the setting is chip selection timing, The delay starts from the falling edge of MCLK/SYSCLK.

74

MB91305

(11) USB interface

Parameter

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Symbol Pin Conditions

Unit

Remarks

Min

Typ

Max

X0

⎯

Self oscillation

X1

2500 ppm accuracy*¹

Input clock

Tucyc

⎯

48*¹

⎯

MHz

External input

2500 ppm accuracy*¹

X0

⎯

UDP/

UDM

Rise Time

Fall Time

Tutfr

Tutff

Full Speed

⎯

4

⎯

20

ns *2

UDP/

UDM

Differential Rise and

Fall Timing Matching

UDP/

UDM

Tutfrfm

Tuzdrv

90

28

111.11

44

%

Ω

*2

*3

Driver Output

Resistance

UDP

UDM

Tucyc

V

IH

V

IH

X0

UDP

UDM

90%

10%

Tutfr

Tutff

*1 : AC characteristics for USB interface conform to USB Specification Revision 1.1.

*2 : < Driver Characteristics Tutfr, Tutff and Tutfrfm >

These are regulations of the rising / falling time of the differential data signal.

This time is defined at the time between 10% to 90% of the output signal voltage.

Forfull-speedbuffer, Tutfr/TutffisspecifiedsuchthattheTutfr/Tutffratiofallswithin 10%tominimizeRFIradiation.

75

MB91305

*3 : < Driver Characteristics ZDRV >

The USB Full-speed connection is done by 90 Ω 15% of characteristic impedance (Z0).

It is connected through the shielded twist 2-pair cable.

In this USB standard, both following conditions must be satisfied.

- The output impedance of USB Driver is from 28 Ω to 44 Ω.

- To balance, discrete series resistor (Rs) is added.

The output impedance of USB I/O Buffer of this LSI is about 3 Ω to 19 Ω.

Therefore, it is necessary to add the series resistance Rs of 25 Ω to 30 Ω (recommended value 27 Ω).

Rs

TxD+

28 Ω to 44 Ω Equiv. Imped.

Rs

TxD−

3-State

Driver output impedance 3 Ω to 19 Ω

Rs series resistance 25 Ω to 30 Ω

Resistance Rs of recommended value 27 Ω should be added.

76

MB91305

(12) I²C Timing

In the master mode operation

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Fast-mode*³

Standard-mode

Sym-

bol

Parameter

Condition

Unit

Remarks

Min

0

Max

100

⎯

Min

0

Max

400

⎯

SCL clock frequency

f^SCL

kHz

µs

“L” width of the SCL clock t^LOW

“H” width of the SCL clock t^HIGH

Bus free time between a

4.7

4.0

1.3

0.6

⎯

µs

STOP and START condi-

tion

t^BUS

4.7

⎯

5 × M*¹

⎯

1.3

⎯

5 × M*¹

⎯

µs

ns

µs

SCL ↓ → SDA

output delay time

t^DLDAT

Set-up time for a repeated

START condition

SCL↑ → SDA↓

t^SUSTA

4.7

0.6

R = 1 kΩ,

C = 50 pF*⁴

Hold time (repeated)

START condition

SDA↓ → SCL↓

The first clock

t^HDSTA

4.0

⎯

0.6

⎯

µs pulse is gener-

ated afterword.

Set-up time for STOP

condition

SCL↑ → SDA↑

t^SUSTO

µs

Data input hold time

(vs.SCL↓)

t^HDDAT

t^SUDAT

2 × M*¹

⎯

2 × M*¹

⎯

µs

Data input set-up time

(vs.SCL↑)

250

100*²

ns

*1 : M = Resource clock cycle (ns)

*2 : To use high-speed mode I²C bus device for standard mode I²C bus system, it must satisfy the request condition

(t^SUDAT= 250 ns). If a device does not extend "L" period of the SCL signal, the following data must be output to

the SDA line before 1250 ns (SCL line is opened, equal to SDA, SCL rise Max time + t^SUDATA).

*3 : To use it exceeding 100kHz, the resource clock is set to 6MHz or more.

*4 : R and C is the pull-up resistor and the load capacity for SCL and SDA output lines respectively.

77

MB91305

In the slave mode operation

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Fast-mode*³

Standard-mode

Sym-

bol

Parameter

Condition

Unit

Remarks

Min

0

Max

100

⎯

Min

0

Max

400

⎯

SCL clock frequency

f^SCL

kHz

µs

“L” width of the SCL clock t^LOW

“H” width of the SCL clock t^HIGH

4.7

4.0

1.3

0.6

⎯

µs

SCL ↓ → SDA

t^DLDAT

⎯

5 × M*¹

⎯

5 × M*¹

ns

output delay time

Bus free time between a

STOP and START

condition

t^BUS

4.7

⎯

1.3

⎯

µs

Data input hold time

(vs.SCL↓)

t^HDDAT

t^SUDAT

2 × M*¹

⎯

2 × M*¹

⎯

µs

R = 1 kΩ,

C = 50 pF*⁴

Data input set-up time

(vs.SCL↑)

250

100*²

ns

Set-up time for a repeated

START condition

SCL↑ → SDA↓

t^SUSTA

t^HDSTA

t^SUSTO

4.7

4.0

⎯

0.6

⎯

µs

Hold time for a repeated

START condition

SDA↓ → SCL↓

The first clock

µs pulse is gener-

ated afterword.

Set-up time for STOP

condition

SCL↑ → SDA↑

µs

*1 : M = Resource clock cycle (ns)

*2 : To use high-speed mode I²C bus device for standard mode I²C bus system, it must satisfy the request condition

(t^SUDAT= 250 ns). If a device does not extend "L" period of the SCL signal, the following data must be output

to the SDA line before 1250 ns (SCL line is opened, equal to SDA, SCL rise Max time + t^SUDATA).

*3 : To use it exceeding 100kHz, the resource clock is set to 6MHz or more.

*4 : R and C is the pull-up resistor and the load capacity for SCL and SDA output lines respectively.

78

MB91305

(13) SDRAM Timing

Parameter

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Condi-

tions

Symbol

Unit

Remarks

Min

⎯

12

⎯

2

Max

32

⎯

15

⎯

15

⎯

15

⎯

15

⎯

15

⎯

15

⎯

15

⎯

15

⎯

Output clock cycle time

“H” level clock pulse width

“L” level clock pulse width

MCLK ↑ → output delay time

Output hold time

t^CYCSD

t^CHSD

MHz

ns

MCLK

⎯

t^CLSD

t^ODSDCKE

t^OHSDCKE

t^ODSDRAS

t^OHSDRAS

t^ODSDCAS

t^OHSDCAS

t^ODSDWE

t^OHSDWE

t^ODSDCS

t^OHSDCS

t^ODSDA

MCLKE

SRAS

SCAS

SWR

MCLK ↑ → output delay time

Output hold time

⎯

2

MCLK ↑ → output delay time

Output hold time

⎯

2

MCLK ↑ → output delay time

Output hold time

⎯

2

⎯

MCLK ↑ → output delay time

Output hold time

⎯

2

CS6

CS7

MCLK ↑ → output delay time

Output hold time

⎯

2

A00 to A15

t^OHSDA

MCLK ↑ → output delay time

Output hold time

t^ODSDDQM

t^OHSDDQM

t^ODSDD

⎯

2

DQMUU

DQMUL

MCLK ↑ → output delay time

Output hold time

⎯

2

D16 to D31

t^OHSDD

Data input setup time

Data input hold time

t^ISSDD

15

2

⎯

t^IHSDD

79

MB91305

t

CYCSD

MCLK

V

OH

V

OH

V

OH

V

OL

V

OL

t

CHSD

tCLSD

V

OH

VOH

MCLK

t

ODSDCKE

ODSDRAS

ODSDCAS

ODSDWE

ODSDCS

ODSDA

MCLKE

SRAS

ODSDDQM

SCAS

SWR

CS6

V

OH

VOH

CS7

t

OHSDCKE

OHSDRAS

OHSDCAS

OHSDWE

OHSDCS

OHSDA

A00 to A15

DQMUU

DQMUL

OHSDDQM

t

ODSDD

VOH

VOL

VOH

VOL

D16 to D31

t

OHSDD

V

IH

IL

V

IH

IL

t

ISSDD

tIHSDD

80

MB91305

5. Electrical Characteristics for the A/D Converter

(V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0 V, Ta = −10 °C to +70 °C)

Value

Symbol

Parameter

Unit

Min

⎯

Typ

⎯

Max

10

Resolution

Total error

⎯

BIT

LSB

⎯

5.5

3.5

2.0

Nonlinear error

⎯

Differential linear error

⎯

AN0 to

AN9

Zero transition voltage

V^OT

−4.0

⎯

+6.0

LSB

AN0 to

AN9

Full-transition voltage

Conversion time

V^FST

⎯

AVRH − 5.5

8.18*¹

⎯

AVRH+3.0

LSB

µs

⎯

AN0 to

AN9

Analog port input current

I^AIN

⎯

0.1

10

µA

AN0 to

AN9

Analog input voltage

Reference voltage

V^AIN

AVSS

⎯

AVRH

V

⎯

I^A

AVRH

AVSS

⎯

3.6

⎯

AVCC

⎯

10*²

V

mA

µA

Power supply current

AVCC

I^AH

I^R

⎯

600

⎯

10*²

Reference voltage supply current

Variation between channels

AVRH

I^RH

⎯

AN0 to

AN9

⎯

5

LSB

*1 : For V^DDI= 1.8 V 0.15 V, V^DDE= AV^CC= 3.3 V 0.3 V, machine clock = 32 MHz

*2 : Current when A/D converter not operating (V^DDE= AV^CC= AVRH = 3.6 V, V^DDI= 1.95 V)

Notes : • The relative error increases as AVRH becomes smaller.

• If the output impedance of the external circuit is too high, the analog voltage sampling time may be too

short.

81

MB91305

• About the external impedance of the analog input and its sampling time

• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship

between the external impedance and minimum sampling time and either adjust the operating frequency or

decrease the external impedance so that the sampling time is longer than the minimum value.

And if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

• Analog input circuit model

R

Analog input

Comparator

C

During sampling : ON

R

C

4.9 kΩ (Max)

27 pF (Max)

Note : The values are reference values.

.

• The relationship between the external impedance and minimum sampling time

(External impedance = 0 kΩ to 100 kΩ)

(External impedance = 0 kΩ to 20 kΩ)

100

90

80

70

60

50

40

30

20

10

0

20

18

16

14

12

10

8

6

4

2

0

5

10

15

20

25

30

35

0

1

2

3

4

5

6

7

8

Minimum sampling time [µs]

• About the error

^{The accuracy gets worse as}| AVRH−AVSS | ^{becomes smaller.}

82

MB91305

• Definition of A/D Converter Terms

• Resolution

Analog variation that is recognized by an A/D converter.

• Linearity error

The deviation between the actual conversion characteristics and a straight line connecting the device's zero

transition point (“0000000000” ←→“0000000001”) and full scale transition point (“1111111110” ←→

“1111111111”).

• Differential linear error

Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

Linearity error

Differential linear error

Ideal characteristics

Actual conversion characteristic

3FF

3FE

3FD

H

N-1

N-2

N-1

N-2

Actual conversion

characteristic

H

{1 LSB × (N-1) + VTO

V^FST

(measure-

ment value)

V^NT

V (^N-¹) ^T

004H

(measure-

ment value)

003H

Actual conversion

characteristic

Ideal characteristics

V^NT

002

H

(measurement

value)

001

Actual conversion characteristic

V^TO(measurement value)

AVRL

AVRH

AVRL

AVRH

Analog input

V^NT− { 1LSB × (N − 1) + V^OT}

Linear error in digital output N =

[LSB]

1LSB

V (^N+ ¹) ^T− V^NT

Differential linear error in digital output N =

V^FST− V^OT

[LSB]

1LSB

1LSB =

[V]

1022

AV^RH− AV^RL

1LSB’ =

[V] (Ideal value)

1024

N

: A/D converter digital output value

V^OT: A voltage at which digital output transitions from (000)^Hto (001)^H.

V^FST: A voltage at which digital output transitions from (3FE)^Hto (3FF)^H.

V^NT: A voltage at which digital output transitions from (N − 1) to N.

83

MB91305

• Total error

This error indicates the difference between actual and ideal values, including the zero transition error/full-scale

transition error/linearity error.

Total error

Actual conversion characteristic

3FFH

1.5 LSB''

3FEH

3FDH

{1 LSB'' × (N−1) + 0.5 LSB''

V^NT

004H

003H

002H

001H

(measure-

ment value)

Actual conversion

characteristic

Ideal

characteristics

0.5 LSB''

AV^RL

AVRH

Analog input

V^NT− {1 LSB” × (N − 1) + 0.5 LSB”}

Total error of digital output N =

[LSB]

1 LSB”

N : A/D converter digital output value

V^OT” (Ideal value) = AV^RL+ 0.5 LSB" [V]

V^FST” (Ideal value) = AV^RH− 1.5 LSB" [V]

V^NT: A voltage at which digital output transitions from (N − 1) to N.

84

MB91305

■ EXAMPLE CHARACTERISTICS

I^CC-V^DDIexample characteristics

Ta = + 25 °C, fcp = 68 MHz

fcpp = 34 MHz, fcpt = 34 MHz

I^CC-f^CPexample characteristics

Ta = + 25 °C, V^DDE= 3.3 V

V^DDI= 1.8 V

120

100

80

60

40

20

0

120

100

80

60

40

20

0

10

20

30

40

50

60

70

80

1.5

1.7

1.9

2.1

fcp [MHz]

V

DDI [V]

(fcp : fcpp : fcpt = 2 : 1 : 1, PLL 4 multiplication)

I^CCS-V^DDIexample characteristics

I^CCH-V^DDIexample characteristics

Ta = + 25 °C

60

140

120

100

80

60

40

20

0

50

40

30

20

10

0

1.7

1.9

DDI [V]

2.1

1.5

1.7

1.9

VDDI [V]

2.1

V

V^OH-V^DDEexample characteristics

V^OL-V^DDEexample characteristics

Ta = + 25 °C

0.6

0.4

0.2

0

4

3

2

1

0

2

3

4

2

3

4

V

DDE [V]

V

DDE [V]

Note : Not including USB I/O

(Continued)

85

MB91305

Pull-up resistor example characteristics

Pull-down resistor example characteristics

Ta = + 25 °C

120

80

40

0

120

80

40

0

2

3

4

2

3

4

V

DDE [V]

VDDE [V]

I^CC-V^DDIexample characteristics

Ta = + 25 °C, fcp = 68 MHz

fcpp = 34 MHz, fcpt = 34 MHz

I^CC-f^CPexample characteristics

Ta = + 25 °C, V^DDE= 3.3 V

V^DDI= 1.8 V

120

100

80

60

40

20

0

120

100

80

60

40

20

0

1.5

1.7

1.9

2.1

0

10

20

30

40

50

60

70

80

V

DDI [V]

fcp [MHz]

(fcp : fcpp : fcpt = 2 : 1 : 1, PLL 4 multiplication)

I^CCS-V^DDIexample characteristics

I^CCH-V^DDIexample characteristics

Ta = + 25 °C

140

60

50

40

30

20

10

0

120

100

80

60

40

20

0

1.5

1.7

1.9

2.1

0

1.7

1.9

2.1

V

DDI [V]

VDDI [V]

Note : Not including USB I/O

(Continued)

86

MB91305

(Continued)

V^OH-V^DDEexample characteristics

V^OL-V^DDEexample characteristics

Ta = + 25 °C

4

3

2

1

0.6

0.4

0.2

0

2

3

4

2

3

4

VDDE [V]

V

DDE [V]

Pull-up resistor example characteristics

Pull-down resistor example characteristics

Ta = + 25 °C

120

80

40

0

120

80

40

0

2

3

4

2

3

4

VDDE [V]

Note : Not including USB I/O

87

MB91305

■ ORDERING INFORMATION

Part number

Package

Remarks

176-pin plastic LQFP

(FPT-176P-M07)

MB91305PMC

88

MB91305

■ PACKAGE DIMENSION

Note 1) * : Values do not include resin protrusion.

176-pin plastic LQFP

(FPT-176P-M07)

Resin protrusion is +0.25 (.010) Max (each side) .

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

26.00±0.20(1.024±.008)SQ

*24.00±0.10(.945±.004)SQ

0.145±0.055

(.006±.002)

132

89

133

88

0.08(.003)

Details of "A" part

1.50 –⁺0⁰.^.1²0⁰

(Mounting height)

.059 –⁺.^.0⁰0⁰4⁸

0.10±0.10

(.004±.004)

(Stand off)

0˚~8˚

INDEX

0.25(.010)

0.50±0.20

176

45

(.020±.008)

"A"

0.60±0.15

(.024±.006)

1

44

LEAD No.

0.50(.020)

0.22±0.05

(.009±.002)

M

0.08(.003)

C

2004 FUJITSU LIMITED F176013S-c-1-1

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

89

MB91305

The information for microcontroller supports is shown in the following homepage.

http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

Edited

Business Promotion Dept.

F0604


型号：	MB91305PMC
厂家：	FUJITSU
描述：	32-bit Microcontroller 32位微控制器微控制器和处理器外围集成电路时钟
文件：	总90页 (文件大小：860K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB91305PMC [FUJITSU]

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