MB95R107BPFV_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12617-1E

8-bit Proprietary Microcontrollers

CMOS

F²MC-8FX MB95100B Series

MB95107B/F108BS/F108BW/R107B/D108BS/

MB95D108BW/FV100D-101

■ DESCRIPTION

The MB95100B series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,

the microcontrollers contain a variety of peripheral functions.

Note : F²MC is the abbreviation of FUJITSU Flexible Microcontroller.

■ FEATURE

• F²MC-8FX CPU core

Instruction set optimized for controllers

• Multiplication and division instructions

• 16-bit arithmetic operations

• Bit test branch instruction

• Bit manipulation instructions etc.

• Clock

• Main clock

• Main PLL clock

• Sub clock (for dual clock product)

• Sub PLL clock (for dual clock product)

(Continued)

Be sure to refer to the “Check Sheet” for the latest cautions on development.

“Check Sheet” is seen at the following support page

URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system

development.

MB95100B Series

(Continued)

• Timer

• 8/16-bit compound timer × 2 channels

• 16-bit reload timer

• 8/16-bit PPG × 2 channels

• 16-bit PPG × 2 channels

• Timebase timer

• Watch prescaler (for dual clock product)

• FRAM

2K bytes FRAM is loaded (MB95R107B/MB95D108BS/MB95D108BW only)

• LIN-UART

• Full duplex double buffer

• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

• UART/SIO

• Full duplex double buffer

• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

• I²C*

Built-in wake-up function

• External interrupt

• Interrupt by edge detection (rising, falling, or both edges can be selected)

• Can be used to recover from low-power consumption (standby) modes.

• 8/10-bit A/D converter

8-bit or 10-bit resolution can be selected.

• Low-power consumption (standby) mode

• Stop mode

• Sleep mode

• Watch mode (for dual clock product)

• Timebase timer mode

• I/O port

• The number of maximum ports

• Single clock product : 55 ports

• Dual clock product : 53 ports

• Port configuration

• General-purpose I/O ports (N-ch open drain)

Other than MB95D108BS/MB95D108BW/MB95R107B : 6 ports

MB95D108BS/MB95D108BW/MB95R107B

• General-purpose I/O ports (CMOS)

Single clock product

: 4 ports

: 49 ports

: 47 ports

Dual clock product

* : Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use, these

components in an I²C system provided that the system conforms to the I²C Standard Specification as defined

by Philips.

2

MB95100B Series

■ PRODUCT LINEUP

Part number

MB95F108BS/

MB95F108BW

MB95D108BS/

MB95R107B*³

MB95107B

MB95D108BW

Parameter

MASK ROM

product

Flash memory

product

MASK ROM

product

Flash memory

product

Type

ROM capacity

RAM capacity

FRAM capacity

Reset output

48K bytes

60K bytes

48K bytes

60K bytes

2K bytes

No

2K bytes

Selectable

Clock system

Single/Dual clock*²

Single/Dual clock*¹

Low voltage

detection reset

No

Number of basic instructions

Instruction bit length

Instruction length

: 136

: 8 bits

: 1 to 3 bytes

: 1, 8, and 16 bits

CPU functions

Data bit length

Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz)

Interrupt processing time : 0.6 µs (at machine clock frequency 16.25 MHz)

General purpose • Single clock product : 55 ports (N-ch open drain *⁵: 4/6 ports, CMOS : 49 ports)

I/O ports

• Dual clock product : 53 ports (N-ch open drain *⁵: 4/6 ports, CMOS : 47 ports)

Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)

Reset generated cycle

Timebase timer

Watchdog timer

Wild register

At main oscillation clock 10 MHz

At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms

: Min 105 ms

Capable of replacing 3 bytes of ROM data

Master/slave sending and receiving

Bus error function and arbitration function

Detecting transmitting direction function

Start condition repeated generation and detection functions

Built-in wake-up function

I²C

Data transfer capable in UART/SIO

Full duplex double buffer, Variable data length (5/6/7/8-bit), built-in baud rate generator

NRZ type transfer format, error detected function

LSB-first or MSB-first can be selected.

UART/SIO

LIN-UART

Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

Dedicated reload timer allowing a wide range of communication speeds to be set.

Full duplex double buffer.

Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

LIN functions available as the LIN master or LIN slave.

8/10-bit A/D

converter

8-bit or 10-bit resolution can be selected.

(12 channels)

(Continued)

3

MB95100B Series

(Continued)

Part number

MB95107B

Parameter

MB95F108BS/

MB95F108BW

MB95D108BS/

MB95D108BW

MB95R107B*³

Two clock modes and two counter operating modes can be selected. Square wave form

output

Count clock : 7 internal clocks and external clock can be selected.

Counter operating mode : reload mode or one-shot mode can be selected.

16-bit reload timer

Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer × 1

channel”.

Built-in timer function, PWC function, PWM function, capture function and square

wave form output

8/16-bitcompound

timer (2 channels)

Count clock : 7 internal clocks and external clock can be selected.

PWM mode or one-shot mode can be selected.

Counter operating clock : Eight selectable clock sources

Support for external trigger start

16-bit PPG

(2 channels)

Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1

channel”.

Counter operating clock : Eight selectable clock sources

8/16-bit PPG

(2 channels)

Watch counter

(for dual clock

product)

Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)

Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting

clock source 1 second and setting counter value to 60)

Watch prescaler

(for dual clock

product)

4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)

External interrupt Interrupt by edge detection (rising, falling, or both edges can be selected.)

(12 channels)

Flash memory

Standby mode

Can be used to recover from standby modes.

Supports automatic programming, Embedded Algorithm^TM

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Number of write/erase cycles (Minimum) : 10000 times

Data retention time : 20 years

Erase can be performed on each block

Boot block configuration

Block protection with external programming voltage

Flash Security Feature for protecting the content of the Flash

*

6

Sleep, stop, watch (for dual clock product), and timebase timer

*1 : Specify clock mode when ordering MASK ROM.

*2 : MB95F108BS/MB95D108BS is single clock and MB95F108BW/MB95D108BW is dual clock.

*3 : This device is under development.

*4 : For details of option, refer to “■ MASK OPTION”.

*5 : MB95D108BS/D108BW/R107B contain 4 general-purpose I/O ports for N-ch open drain. Port number other

than MB95D108BS/D108BW/R107B has 6 general-purpose I/O ports for N-ch open drain.

*6 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

Note : Part number of the evaluation products in MB95100B series is MB95FV100D-101. When using it, the MCU

board (MB2146-301A) is required.

4

MB95100B Series

■ SELECT OF OSCILLATION STABILIZATION WAIT TIME (MASK ROM PRODUCT ONLY)

For the MASK ROM product, you can set the mask option when ordering MASK ROM to select the initial value

of main clock oscillation stabilization wait time from among the following four values.

Note that the evaluation and Flash memory products are fixed their initial value of main clock oscillation stabili-

zation wait time at the maximum value.

Select of oscillation stabilization wait time

Remarks

(2²− 2) /FCH

(2¹²− 2) /FCH

(2¹³− 2) /FCH

(2¹⁴− 2) /FCH

0.5 µs (at main oscillation clock 4 MHz)

Approx. 1.02 ms (at main oscillation clock 4 MHz)

Approx. 2.05 ms (at main oscillation clock 4 MHz)

Approx. 4.10 ms (at main oscillation clock 4 MHz)

■ PACKAGES AND CORRESPONDING PRODUCTS

Part number

MB95107B

MB95R107B

MB95F108BS/F108BW

MB95D108BS/D108BW

MB95FV100D-101

Package

FPT-64P-M03

FPT-64P-M09

BGA-224P-M08

: Available

: Unavailable

5

MB95100B Series

■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS

• Notes on Using Evaluation Products

The evaluation product has not only the functions of the MB95100B series but also those of other products to

support software development for multiple series and models of the F²MC-8FX family. The I/O addresses for

peripheral resources not used by the MB95100B series are therefore access-barred. Read/write access to these

access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in

unexpected malfunctions of hardware or software.

Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are

used, the address may be read or written unexpectedly).

Also, as the read values of prohibited addresses on the evaluation product are different to the values on the

Flash memory and MASK ROM products, do not use these values in the program.

The evaluation product do not support the functions of some bits in single-byte registers. Read/write access to

these bits does not cause hardware malfunctions. The evaluation, Flash memory, and MASK ROM products are

designed to behave completely the same way in terms of hardware and software.

• Difference of Memory Spaces

If the amount of memory on the evaluation product is different from that of the Flash memory or MASK ROM

product, carefully check the difference in the amount of memory from the model to be actually used when

developing software.

For details of memory space, refer to “■ CPU CORE”.

• Current Consumption

The current consumption of Flash memory product is greater than for MASK ROM product.

For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.

• Package

For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS” and

“■ PACKAGE DIMENSIONS”.

• Operating voltage

The operating voltage are different among the evaluation, Flash memory, and MASK ROM products.

For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”.

• Difference between RST and MOD pins

The input type of RST and MOD pins is CMOS input on the Flash memory product. The RST and MOD pins

are hysteresis inputs on the MASK ROM product. A pull - down resistor is provided for the MOD pin of the MASK

ROM product.

6

MB95100B Series

■ PIN ASSIGNMENT

(TOP VIEW)

64

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

AVcc

AVR

P64/EC1

P63/TO11

P62/TO10

P61/PPG11

P60/PPG10

P53/TRG1

P52/PPG1

P51/SDA0*²

P50/SCL0*²

P24/EC0

P23/TO01

P22/TO00

P21/PPG01

P20/PPG00

P14/PPG0

P13/TRG0/ADTG

PE3/INT13

PE2/INT12

PE1/INT11

PE0/INT10

P83

P82

P81

P80

P71/TI0

P70/TO0

MOD

X0

X1

Vss

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

(FPT-64P-M03, FPT-64P-M09)

*1 : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.

*2 : P50 and P51 cannot be used in MB95R107B, MB95D108BS, and MB95D108BW.

7

MB95100B Series

■ PIN DESCRIPTION

I/O

circuit

type*

Pin no.

Pin name

Function

A/D converter power supply pin

1

2

AV^CC

AVR

⎯

A/D converter reference input pin

3

PE3/INT13

PE2/INT12

PE1/INT11

PE0/INT10

P83

4

General-purpose I/O port

The pins are shared with the external interrupt input.

P

5

6

7

8

P82

O

H

General-purpose I/O port

9

P81

10

P80

General-purpose I/O port.

The pin is shared with 16 - bit reload timer ch.0 input.

11

12

P71/TI0

General-purpose I/O port.

The pin is shared with 16 - bit reload timer ch.0 output.

P70/TO0

13

14

15

16

17

18

MOD

X0

B

A

An operating mode designation pin

Main clock input oscillation pin

Main clock input/output oscillation pin

Power supply pin (GND)

X1

V^SS

⎯

H

VCC

PG0

Power supply pin

General-purpose I/O port.

Single-system product is general-purpose port (PG2).

Dual-system product is sub clock input/output oscillation pin (32 kHz).

19

20

PG2/X1A

PG1/X0A

H/A

B’

Single-system product is general-purpose port (PG1).

Dual-system product is sub clock input oscillation pin (32 kHz).

21

22

23

24

25

26

27

28

29

RST

Reset pin

P00/INT00

P01/INT01

P02/INT02

P03/INT03

P04/INT04

P05/INT05

P06/INT06

P07/INT07

General-purpose I/O port.

The pins are shared with external interrupt input. Large current port.

C

G

General-purpose I/O port.

The pin is shared with UART/SIO ch.0 data input.

30

P10/UI0

(Continued)

8

MB95100B Series

I/O

circuit

type*

Pin no.

Pin name

Function

General-purpose I/O port.

The pin is shared with UART/SIO ch.0 data output.

31

32

P11/UO0

General-purpose I/O port.

The pin is shared with UART/SIO ch.0 clock I/O.

P12/UCK0

H

General-purpose I/O port.

The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D

converter trigger input (ADTG).

P13/TRG0/

ADTG

33

General-purpose I/O port.

The pin is shared with 16-bit PPG ch.0 output.

34

P14/PPG0

35

36

37

38

P20/PPG00

P21/PPG01

P22/TO00

P23/TO01

General-purpose I/O port.

The pins are shared with 8/16-bit PPG ch.0 output.

General-purpose I/O port.

The pins are shared with 8/16-bit compound timer ch.0 output.

H

General-purpose I/O port.

The pin is shared with 8/16-bit compound timer ch.0 clock input.

39

P24/EC0

General-purpose I/O port (Except MB95R107B , MB95D108BS, and

MB95D108BW) .

40

P50/SCL0

The pin is shared with I²C ch.0 clock I/O.

I

General-purpose I/O port (Except MB95R107B, MB95D108BS, and

MB95D108BW) .

41

P51/SDA0

The pin is shared with I²C ch.0 data I/O.

General-purpose I/O port.

The pin is shared with 16-bit PPG ch.1 output.

42

43

P52/PPG1

P53/TRG1

H

General-purpose I/O port.

The pin is shared with 16-bit PPG ch.1 trigger input.

44

45

46

47

P60/PPG10

P61/PPG11

P62/TO10

P63/TO11

General-purpose I/O port.

The pins are shared with 8/16-bit PPG ch.1 output.

General-purpose I/O port.

The pins are shared with 8/16-bit compound timer ch.1 output.

General-purpose I/O port.

The pin is shared with 8/16-bit compound timer ch.1 clock input.

K

L

48

49

50

51

P64/EC1

P65/SCK

P66/SOT

P67/SIN

General-purpose I/O port.

The pin is shared with LIN-UART clock I/O.

General-purpose I/O port.

The pin is shared with LIN-UART data output.

General-purpose I/O port.

The pin is shared with LIN-UART data input.

(Continued)

9

MB95100B Series

(Continued)

I/O

circuit

type*

Pin no.

Pin name

Function

52

53

54

55

56

57

58

59

60

61

62

63

64

P43/AN11

P42/AN10

P41/AN09

P40/AN08

P37/AN07

P36/AN06

P35/AN05

P34/AN04

P33/AN03

P32/AN02

P31/AN01

P30/AN00

AV^SS

General-purpose I/O port.

The pins are shared with A/D converter analog input.

J

General-purpose I/O port.

The pins are shared with A/D converter analog input.

J

⎯

A/D converter power supply pin (GND)

* : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.

10

MB95100B Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Oscillation circuit

• High-speed side

Feedback resistance value : approx. 1 MΩ

• Low-speed side

X1 (X1A)

Clock

input

N-ch

X0 (X0A)

Feedback resistance : approx. 24 MΩ

(Evaluation product : approx. 10 MΩ)

Dumping resistance : approx. 144 kΩ

(Evaluation product : without dumping

resistance)

A

Standby control

• Only for input

Mode input

Reset input

Hysteresis input only for MASK ROM product

With pull-down resistor only for MASK ROM

product

B

R

• Hysteresis input only for MASK ROM product

B’

• CMOS output

P-ch

N-ch

• Hysteresis input

Digital output

C

Hysteresis

input

Standby control

External interrupt

enable

• CMOS output

• CMOS input

• Hysteresis input

• With pull-up control

R

P-ch

Pull-up control

P-ch

N-ch

Digital output

G

CMOS input

Hysteresis

input

Standby control

• CMOS output

• Hysteresis input

• With pull-up control

R

P-ch

Pull-up control

P-ch

N-ch

Digital output

H

Hysteresis

input

Standby control

(Continued)

11

MB95100B Series

Type

Circuit

Remarks

• N-ch open drain output

• CMOS input

• Hysteresis input

• P-ch transistor is existed in MB95D108BS,

MB95D108BW, and MB95R107B.

P-ch

N-ch

Digital output

I

CMOS input

Hysteresis

input

Standby control

• CMOS output

• Hysteresis input

• Analog input

R

P-ch

Pull-up control

P-ch

N-ch

• With pull-up control

Digital output

J

Analog input

Hysteresis

input

A/D control

Standby control

• CMOS output

• Hysteresis input

P-ch

N-ch

Digital output

K

Hysteresis

input

Standby control

• CMOS output

• CMOS input

• Hysteresis input

P-ch

N-ch

Digital output

L

CMOS input

Hysteresis

input

Standby control

• N-ch open drain output

• Hysteresis input

Digital output

N-ch

O

Hysteresis

input

(Continued)

12

MB95100B Series

(Continued)

Type

Circuit

Remarks

• CMOS output

• Hysteresis input

• With pull-up control

R

P-ch

Pull-up control

Digital output

P-ch

N-ch

P

Digital output

Hysteresis

input

Standby control

External

interrupt control

13

MB95100B Series

■ HANDLING DEVICES

• Preventing Latch-up

Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.

Latch-up may occur on CMOS ICs if voltage higher than V^CCor lower than VSS is applied to input and output pins

other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC

pin and VSS pins.

When latch-up occurs, power supply current increases rapidly and might thermally damage elements.

Also, take care to prevent the analog power supply voltage (AV^CC, AVR) and analog input voltage from exceeding

the digital power supply voltage (VCC) when the analog system power supply is turned on or off.

• Stable Supply Voltage

Supply voltage should be stabilized.

A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range

of the V^CCpower-supply voltage.

For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range

(50/60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transient

variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.

• Precautions for Use of External Clock

Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up

from sub clock mode or stop mode.

■ PIN CONNECTION

• Treatment of Unused Pin

Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent

damage.

Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/

output pins may be set to output mode and left open, or set to input mode and treated the same as unused input

pins. If there is an unused output pin, make it open.

• Treatment of Power Supply Pins on A/D Converter

Connect to be AV^CC= VCC and AVSS = AVR = VSS even if the A/D converter is not in use.

Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 µF ceramic capacitor

as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.

• Power Supply Pins

In products with multiple V^CCor VSS pins, the pins of the same potential are internally connected in the device

to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply

and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals

caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the V^CCand VSS pins of this device at the low impedance.

It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS pins

near this device.

14

MB95100B Series

• Mode Pin (MOD)

Connect the MOD pin directly to V^CCor VSS pins.

To prevent the device unintentionally entering the test mode due to noise, lay out the printed circuit board so as

to minimize the distance from the MOD pin to V^CCor VSS pin and to provide a low-impedance connection.

• Analog Power Supply

Always set the same potential to AV^CCand VCC pins. When VCC > AVCC, the current may flow through the AN00

to AN11 pins.

• Precautions for Use of FRAM

When the device is connected to I²C external pins (SCL0 and SDA0) , the device with the same slave addresses

(1010000B to 1010111B) as built-in FRAM cannot be used.

When built-in FRAM is used without connecting the device to I²C external pins, external pull-up resistor (1.1kΩ

or more) should be connected to SCL0 and SDA0 pins.

P50 and P51 cannot be used in MB95R107B , MB95D108BS, and MB95D108BW.

15

MB95100B Series

■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL

PROGRAMMER

• Supported Parallel Programmers and Adapters

The following table lists supported parallel programmers and adapters.

Package

Applicable adapter model

Parallel programmers

AF9708 (Ver 02.35G or more)

AF9709/B (Ver 02.35G or more)

AF9723+AF9834 (Ver 02.08E or more)

FPT-64P-M03

TEF110-108F35AP

FPT-64P-M09

TEF110-108F36AP

Note : For information on applicable adapter models and parallel programmers, contact the following:

Flash Support Group, Inc. TEL: +81-53-428-8380

• Sector Configuration

The individual sectors of Flash memory correspond to addresses used for CPU access and programming by

the parallel programmer as follows:

Flash memory

CPU address

1000^H

Programmer address*

71000H

SA1 (4K bytes)

1FFFH

2000H

71FFFH

72000H

SA2 (4K bytes)

SA3 (4K bytes)

SA4 (16K bytes)

SA5 (16K bytes)

SA6 (4K bytes)

SA7 (4K bytes)

SA8 (4K bytes)

SA9 (4K bytes)

2FFFH

3000^H

72FFFH

73000H

3FFFH

4000^H

73FFFH

74000H

7FFFH

8000^H

77FFFH

78000H

BFFFH

C000^H

7BFFFH

7C000H

CFFFH

D000^H

7CFFFH

7D000H

DFFFH

E000H

7DFFFH

7E000H

EFFFH

F000^H

7EFFFH

7F000H

FFFFH

7FFFFH

*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer

programs data into Flash memory.

These programmer addresses are used for the parallel programmer to program or erase data in Flash

memory.

• Programming Method

1) Set the type code of the parallel programmer to 17226.

2) Load program data to parallel programmer addresses 71000^Hto 7FFFFH.

3) Programmed by parallel programmer

16

MB95100B Series

■ BLOCK DIAGRAM

F²MC-8FX CPU

RST

Reset control

Clock control

ROM

RAM

X0,X1

PG2/X1A*¹

PG1/X0A*¹

PG0

Interrupt control

Wild register

Watch prescaler

Watch counter

P00/INT00 to P07/INT07

P52/PPG1

P53/TRG1

External interrupt ch.0 to ch.7

16-bit PPG ch.1

P10/UI0

P11/UO0

P12/UCK0

UART/SIO

P60/PPG10

P61/PPG11

8/16-bit PPG ch.1

P13/TRG0/ADTG

P14/PPG0

P62/TO10

P63/TO11

P64/EC1

16-bit PPG ch.0

8/16-bit compound

timer ch.1

P20/PPG00

P21/PPG01

8/16-bit PPG ch.0

P65/SCK

P66/SOT

P67/SIN

LIN-UART

P22/TO00

P23/TO01

P24/EC0

8/16-bit compound

timer ch.0

P70/TO0

P71/TI0

16-bit reload timer

P30/AN00 to P37/AN07

P40/AN08 to P43/AN11

P80 to P83

8/10-bit A/D

converter

AVCC

AVSS

AVR

PE0/INT10 to PE3/INT13

External interrupt ch.8 to ch.11

P50/SCL0*²

P51/SDA0*²

I ²C

FRAM*³

Port

Other pins

MOD, VCC, VSS

*1 : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.

*2 : P50 and P51 cannot be used in MB95R107B, MB95D108BS, and MB95D108BW.

*3 : MB95R107B, MB95D108BS, and MB95D108BW only

17

MB95100B Series

■ CPU CORE

1. Memory space

Memory space of the MB95100B series is 64 Kbytes and consists of I/O area, data area, and program area.

The memory space includes special-purpose areas such as the general-purpose registers and vector table.

Memory map of the MB95100B series is shown below.

• Memory Map

MB95F108BS

MB95107B

MB95R107B

MB95F108BW

MB95D108BS

MB95D108BW

MB95FV100D-101

I/O

0000

H

0000

H

0000

H

I/O

0080

0100

0200

H

0080

0100

0200

H

0080

0100

0200

H

RAM 2 Kbytes

Register

RAM 2 Kbytes

Register

RAM 3.75 Kbytes

Register

0880

H

0880

H

Access

prohibited

0F80

H

0F80

1000

H

0F80

1000

H

Extended I/O

1000

H

Access

prohibited

Flash

memory

60 Kbytes

memory

60 Kbytes

4000

H

MASK ROM

48 Kbytes

FFFF

H

FFFFH

FFFF

H

18

MB95100B Series

2. Register

The MB95100B series has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The dedicated registers are as follows:

Program counter (PC)

: A 16-bit register to indicate locations where instructions are stored

Accumulator (A)

: A 16-bit register for temporary storage of arithmetic operations. In the case of

an 8-bit data processing instruction, the lower 1 byte is used.

Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.

In the case of an 8-bit data processing instruction, the lower 1 byte is used.

Index register (IX)

Extra pointer (EP)

Stack pointer (SP)

Program status (PS)

: A 16-bit register for index modification

: A 16-bit pointer to point to a memory address

: A 16-bit register to indicate a stack area

: A 16-bit register for storing a register bank pointer, a direct bank pointer, and

a condition code register

Initial Value

16-bit

FFFD^H

0000H

0030H

: Program counter

: Accumulator

PC

A

T

: Temporary accumulator

: Index register

IX

EP

SP

PS

: Extra pointer

: Stack pointer

: Program status

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer

(DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.)

• Structure of the program status

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

R4

R3

R2

R1

R0 DP2 DP1 DP0

H

I

IL1

IL0

N

Z

PS

C

V

RP

DP

CCR

19

MB95100B Series

The RP indicates the address of the register bank currently being used. The relationship between the content

of RP and the real address conforms to the conversion rule illustrated below:

• Rule for Conversion of Actual Addresses in the General-purpose Register Area

RP upper

OP code lower

"0" "0" "0" "0" "0" "0" "0" "1"

R4 R3 R2 R1 R0 b2

b1

b0

Generated address

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct

addresses to 0080^Hto 00FFH.

Direct bank pointer (DP2 to DP0)

Specified address area

Mapping area

0000H to 007FH (without mapping)

0080H to 00FFH (without mapping)

0100H to 017FH

XXX^B(no effect to mapping)

0000H to 007FH

000^B(initial value)

001^B

010B

011B

100B

101B

110B

111B

0180H to 01FFH

0200H to 027FH

0080^Hto 00FFH

0280H to 02FFH

0300H to 037FH

0380H to 03FFH

0400H to 047FH

The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that

control CPU operations at interrupt.

H flag

I flag

Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.

Cleared to “0” otherwise. This flag is for decimal adjustment instructions.

Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.

The flag is cleared to “0” when reset.

Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level

is higher than the value indicated by these bits.

:

IL1, IL0

IL1

0

IL0

0

Interrupt level

Priority

0

1

2

3

High

0

1

0

Low = no interruption

1

N flag

Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the

bit is set to “0”.

:

Z flag

V flag

Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.

Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”

otherwise.

C flag

Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared

to “0” otherwise. Set to the shift-out value in the case of a shift instruction.

:

20

MB95100B Series

The following general-purpose registers are provided:

General-purpose registers: 8-bit data storage registers

The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8-

register. Up to a total of 32 banks can be used on the MB95100B series. The bank currently in use is specified

by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0)

to general-purpose register 7 (R7).

• Register Bank Configuration

8-bit

1F8_H

This address = 0100^H+ 8 × (RP)

R0

Address 100_H

R0

R1

R2

R3

R4

R5

R6

R7

R0

R1

R2

R3

R4

R5

R6

R7

R2

R3

R4

R5

R6

R7

1FF_H

Bank 31

107_H

32 banks

32 banks (RAM area)

The number of banks is

limited by the usable RAM

capacitance.

Bank 0

Memory area

21

MB95100B Series

■ FRAM

• Slave address of FRAM

FRAM operates as one of the slave devices connected to the I²C, and the I²C is used to read from or write to FRAM.

When data is transferred by the I²C, the slave address of FRAM is shown below.

Slave address (7 bits)

R/W bit

(1 bit)

Slave ID (4 bits)

Page select bit* (3 bits)

000^B: page 0

001B : page 1

010B : page 2

011B : page 3

100B : page 4

101B : page 5

110B : page 6

111B : page 7

0 : at write

1 : at read

1

0

1

0

* : Page select bit : Set the value corresponding to the accessed page

• Memory configuration of FRAM

The capacitance of the built-in FRAM is 2 Kbytes. The memory configuration of FRAM consists of 8 pages as

follows. The capacitance of each page is 256 bytes.

Page

Address

00^Hto FFH

00H to FFH

00^Hto FFH

00H to FFH

00^Hto FFH

00H to FFH

Capacitance

256 bytes

0

1

2

3

4

5

6

7

22

MB95100B Series

• Single byte write

Start Condition

MSB

Address & Data

MSB LSB

Stop Condition

Microcontroller

LSB

MSB

LSB

S

Slave Address 0

A

Address

A

Data Byte

A

P

FRAM

Acknowledge

• Compound byte write

Start Condition

MSB

Address & Data

MSB LSB

Stop Condition

LSB

Microcontroller

LSB

MSB

LSB

MSB

S

Slave Address 0

A

Address

A

Data Byte

A

Data Byte

A P

FRAM

Acknowledge

• Current address read

Start Condition

MSB

No Acknowledge

LSB

Address

Stop Condition

Microcontroller

LSB

MSB

Slave Address 1

Data Byte

S

A

1

P

FRAM

Acknowledge

Data

• Continuous address read

Start Condition

Address

No Acknowledge

LSB

Acknowledge

Stop Condition

Microcontroller

MSB

LSB

MSB

LSB

MSB

Slave Address 1

Data Byte

S

A

1 P

FRAM

Acknowledge

Data

• Select (random) read

Start Condition

Address

MSB

No Acknowledge

Start Condition

Address

Acknowledge

LSB MSB

Stop

Condition

Microcontroller

FRAM

MSB

LSB MSB

LSB

LSB MSB

LSB

A

A S

A

Data Byte 1 P

Slave Address 1

Data Byte

S

Slave Address 0

Address

Data

Acknowledge

Notes : • When the device is connected to I²C external pins (SCL0 and SDA0) , the device with the same addresses

(1010000B to 1010111B) as built-in FRAM cannot be used.

• When FRAM is used without connecting the device built into the pull-up resistor to I²C external pins,

external pull-up resistor (1.1 kΩ or more) should be connected to SCL0 and SDA0 pins.

• P50 and P51 cannot be used in MB95R107B, MB95D108BS, and MB95D108BW.

23

MB95100B Series

■ I/O MAP

Register

Address

Register name

R/W

Initial value

abbreviation

0000^H

0001H

0002H

0003H

0004H

0005^H

0006H

0007H

0008H

0009H

000AH

000BH

000CH

000DH

000E^H

000FH

0010H

0011H

0012H

0013H

0014H

0015H

0016H

0017H

0018H

0019H

001AH

001BH

PDR0

DDR0

PDR1

DDR1

⎯

Port 0 data register

Port 0 direction register

Port 1 data register

R/W

⎯

00000000B

⎯

Port 1 direction register

(Disabled)

WATR

PLLC

SYCC

STBC

RSRR

TBTC

WPCR

WDTC

⎯

Oscillation stabilization wait time setting register

PLL control register

R/W

R

11111111B

00000000B

1010X011B

00000000B

XXXXXXXXB

00000000B

⎯

System clock control register

Standby control register

Reset source register

Timebase timer control register

Watch prescaler control register

Watchdog timer control register

(Disabled)

R/W

⎯

PDR2

DDR2

PDR3

DDR3

PDR4

DDR4

PDR5

DDR5

PDR6

DDR6

PDR7

DDR7

PDR8

DDR8

Port 2 data register

R/W

00000000B

Port 2 direction register

Port 3 data register

Port 3 direction register

Port 4 data register

Port 4 direction register

Port 5 data register

Port 5 direction register

Port 6 data register

Port 6 direction register

Port 7 data register

Port 7 direction register

Port 8 data register

Port 8 direction register

001CH

to

0025H

⎯

(Disabled)

⎯

0026^H

0027H

PDRE

DDRE

Port E data register

R/W

00000000B

Port E direction register

0028H,

0029H

⎯

(Disabled)

⎯

002A^H

PDRG

Port G data register

R/W

00000000B

(Continued)

24

MB95100B Series

Register

abbreviation

Address

Register name

R/W Initial value

002B^H

002CH

002D^H

002EH

002FH

0030H

0031H

0032H

0033H

0034H

0035H

0036H

0037H

0038H

0039H

003AH

003BH

003CH

003DH

003EH

003FH

DDRG

⎯

Port G direction register

(Disabled)

R/W

⎯

00000000B

⎯

PUL1

Port 1 pull - up register

R/W

⎯

00000000B

⎯

PUL2

Port 2 pull - up register

PUL3

Port 3 pull - up register

PUL4

Port 4 pull - up register

PUL5

Port 5 pull - up register

PUL7

Port 7 pull - up register

⎯

(Disabled)

PULE

Port E pull - up register

R/W

00000000B

PULG

T01CR1

T00CR1

T11CR1

T10CR1

PC01

Port G pull - up register

8/16-bit compound timer 01 control status register 1 ch.0

8/16-bit compound timer 00 control status register 1 ch.0

8/16-bit compound timer 11 control status register 1 ch.1

8/16-bit compound timer 10 control status register 1 ch.1

8/16-bit PPG1 control register ch.0

8/16-bit PPG0 control register ch.0

8/16-bit PPG1 control register ch.1

8/16-bit PPG0 control register ch.1

16-bit reload timer control status register (Upper byte) ch.0

16-bit reload timer control status register (Lower byte) ch.0

PC00

PC11

PC10

TMCSRH0

TMCSRL0

0040H,

0041H

⎯

(Disabled)

⎯

0042^H

0043H

0044H

0045H

PCNTH0

PCNTL0

PCNTH1

PCNTL1

16-bit PPG control status register (Upper byte) ch.0

16-bit PPG control status register (Lower byte) ch.0

16-bit PPG control status register (Upper byte) ch.1

16-bit PPG control status register (Lower byte) ch.1

R/W

00000000B

0046H,

0047H

⎯

(Disabled)

⎯

0048^H

0049H

004AH

004BH

004CH

004DH

EIC00

EIC10

EIC20

EIC30

EIC01

EIC11

External interrupt circuit control register ch.0/ch.1

External interrupt circuit control register ch.2/ch.3

External interrupt circuit control register ch.4/ch.5

External interrupt circuit control register ch.6/ch.7

External interrupt circuit control register ch.8/ch.9

External interrupt circuit control register ch.10/ch.11

R/W

00000000B

(Continued)

25

MB95100B Series

Register

Address

Register name

R/W Initial value

abbreviation

004E^H,

⎯

(Disabled)

⎯

004FH

0050H

0051H

0052H

0053H

0054H

0055H

0056H

0057H

0058H

0059H

005AH

SCR

SMR

LIN-UART serial control register

LIN-UART serial mode register

R/W

R

00000000B

00001000B

00000000B

00000100B

000000XXB

00000000B

00100000B

00000001B

00000000B

SSR

LIN-UART serial status register

RDR/TDR

ESCR

ECCR

SMC10

SMC20

SSR0

LIN-UART reception/transmission data register

LIN-UART extended status control register

LIN-UART extended communication control register

UART/SIO serial mode control register 1 ch.0

UART/SIO serial mode control register 2 ch.0

UART/SIO serial status register ch.0

TDR0

UART/SIO serial output data register ch.0

UART/SIO serial input data register ch.0

RDR0

005BH

to

005F^H

⎯

(Disabled)

⎯

0060^H

0061H

0062H

0063H

0064H

0065H

IBCR00

IBCR10

IBSR0

IDDR0

IAAR0

ICCR0

I²C bus control register 0 ch.0

I²C bus control register 1 ch.0

I²C bus status register ch.0

I²C data register ch.0

I²C address register ch.0

I²C clock control register ch.0

R/W

R

00000000B

R/W

0066H

to

006B^H

⎯

(Disabled)

⎯

006CH

006DH

006EH

006FH

0070H

0071H

0072^H

0073H

0074H

0075H

0076H

0077H

ADC1

ADC2

ADDH

ADDL

WCSR

⎯

8/10-bit A/D converter control register 1

8/10-bit A/D converter control register 2

8/10-bit A/D converter data register (Upper byte)

8/10-bit A/D converter data register (Lower byte)

Watch counter status register

R/W

⎯

00000000B

⎯

(Disabled)

FSR

Flash memory status register

R/W

⎯

000X0000B

00000000B

⎯

SWRE0

SWRE1

⎯

Flash memory sector writing control register 0

Flash memory sector writing control register 1

(Disabled)

WREN

WROR

Wild register address compare enable register

Wild register data test setting register

R/W

00000000B

(Continued)

26

MB95100B Series

Register

abbreviation

Address

Register name

R/W Initial value

Mirror of register bank pointer (RP) and

direct bank pointer (DP)

0078^H

⎯

0079^H

007AH

007BH

007CH

007DH

007EH

007FH

0F80H

0F81H

0F82H

0F83H

0F84H

0F85H

0F86H

0F87H

0F88H

ILR0

ILR1

Interrupt level setting register 0

Interrupt level setting register 1

R/W

⎯

11111111B

⎯

ILR2

Interrupt level setting register 2

ILR3

Interrupt level setting register 3

ILR4

Interrupt level setting register 4

ILR5

Interrupt level setting register 5

⎯

(Disabled)

WRARH0

WRARL0

WRDR0

WRARH1

WRARL1

WRDR1

WRARH2

WRARL2

WRDR2

Wild register address setting register (Upper byte) ch.0

Wild register address setting register (Lower byte) ch.0

Wild register data setting register ch.0

Wild register address setting register (Upper byte) ch.1

Wild register address setting register (Lower byte) ch.1

Wild register data setting register ch.1

Wild register address setting register (Upper byte) ch.2

Wild register address setting register (Lower byte) ch.2

Wild register data setting register ch.2

R/W

00000000B

0F89H

to

0F91^H

⎯

(Disabled)

⎯

0F92^H

0F93H

0F94H

0F95H

T01CR0

T00CR0

T01DR

T00DR

8/16-bit compound timer 01 control status register 0 ch.0

8/16-bit compound timer 00 control status register 0 ch.0

8/16-bit compound timer 01 data register ch.0

R/W

00000000B

8/16-bit compound timer 00 data register ch.0

8/16-bit compound timer 00/01 timer mode control register

ch.0

0F96H

TMCR0

R/W

00000000B

0F97H

0F98H

0F99H

0F9AH

T11CR0

T10CR0

T11DR

T10DR

8/16-bit compound timer 11 control status register 0 ch.1

8/16-bit compound timer 10 control status register 0 ch.1

8/16-bit compound timer 11 data register ch.1

R/W

00000000B

8/16-bit compound timer 10 data register ch.1

8/16-bit compound timer 10/11 timer mode control register

ch.1

0F9BH

TMCR1

R/W

00000000B

0F9CH

0F9DH

0F9EH

0F9FH

PPS01

PPS00

PDS01

PDS00

8/16-bit PPG1 cycle setting buffer register ch.0

8/16-bit PPG0 cycle setting buffer register ch.0

8/16-bit PPG1 duty setting buffer register ch.0

8/16-bit PPG0 duty setting buffer register ch.0

R/W

11111111B

(Continued)

27

MB95100B Series

Register

Address

Register name

R/W Initial value

abbreviation

0FA0^H

0FA1H

0FA2H

0FA3H

0FA4H

0FA5H

PPS11

PPS10

PDS11

PDS10

PPGS

REVC

8/16-bit PPG1 cycle setting buffer register ch.1

8/16-bit PPG0 cycle setting buffer register ch.1

8/16-bit PPG1 duty setting buffer register ch.1

8/16-bit PPG0 duty setting buffer register ch.1

8/16-bit PPG start register

R/W

11111111B

00000000B

8/16-bit PPG output inversion register

TMRH0/

TMRLRH0

16-bit timer register (Upper byte) ch.0/

16-bit reload register (Upper byte) ch.0

0FA6H

0FA7H

R/W

⎯

00000000B

00000000^B

⎯

TMRL0/

TMRLRL0

16-bit timer register (Lower byte) ch.0/

16-bit reload register (Lower byte) ch.0

0FA8H,

0FA9H

⎯

(Disabled)

0FAA^H

0FABH

0FACH

0FADH

0FAEH

0FAFH

0FB0H

0FB1H

0FB2H

0FB3H

0FB4H

0FB5H

PDCRH0

PDCRL0

PCSRH0

PCSRL0

PDUTH0

PDUTL0

PDCRH1

PDCRL1

PCSRH1

PCSRL1

PDUTH1

PDUTL1

16-bit PPG down counter register (Upper byte) ch.0

16-bit PPG down counter register (Lower byte) ch.0

16-bit PPG cycle setting buffer register (Upper byte) ch.0

16-bit PPG cycle setting buffer register (Lower byte) ch.0

16-bit PPG duty setting buffer register (Upper byte) ch.0

16-bit PPG duty setting buffer register (Lower byte) ch.0

16-bit PPG down counter register (Upper byte) ch.1

16-bit PPG down counter register (Lower byte) ch.1

16-bit PPG cycle setting buffer register (Upper byte) ch.1

16-bit PPG cycle setting buffer register (Lower byte) ch.1

16-bit PPG duty setting buffer register (Upper byte) ch.1

16-bit PPG duty setting buffer register (Lower byte) ch.1

R

00000000B

11111111B

00000000B

11111111B

11111111^B

R

R/W

R

R/W

0FB6H

to

0FBBH

⎯

(Disabled)

⎯

0FBC^H

0FBDH

BGR1

BGR0

LIN-UART baud rate generator register 1

LIN-UART baud rate generator register 0

R/W

00000000B

UART/SIO dedicated baud rate generator

prescaler select register ch.0

0FBEH

0FBFH

PSSR0

BRSR0

⎯

R/W

⎯

00000000B

UART/SIO dedicated baud rate generator baud rate

setting register ch.0

0FC0H,

0FC1H

(Disabled)

⎯

0FC2H

0FC3H

AIDRH

AIDRL

A/D input disable register (Upper byte)

A/D input disable register (Lower byte)

R/W

00000000B

(Continued)

28

MB95100B Series

(Continued)

Register

abbreviation

Address

Register name

R/W Initial value

0FC4^H

to

0FE2^H

⎯

WCDR

⎯

(Disabled)

Watch counter data register

(Disabled)

⎯

R/W

⎯

00111111B

⎯

0FE3^H

0FE4H

to

0FEDH

0FEE^H

0FEFH

ILSR

Input level select register

R/W

00000000B

01000000B

WICR

Interrupt pin control register

0FF0H

to

0FFFH

⎯

(Disabled)

⎯

• R/W access symbols

R/W : Readable/Writable

R

W

: Read only

: Write only

• Initial value symbols

0

1

X

: The initial value of this bit is “0”.

: The initial value of this bit is “1”.

: The initial value of this bit is undefined.

Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.

29

MB95100B Series

■ INTERRUPT SOURCE TABLE

Vector table address

Same level

priority order

(atsimultaneous

occurrence)

Interrupt

request

number

Bit name of

interrupt level

setting register

Interrupt source

Upper

FFFA^H

FFF8^H

FFF6^H

FFF4^H

Lower

FFFBH

FFF9H

FFF7H

FFF5H

External interrupt ch.0

External interrupt ch.4

External interrupt ch.1

External interrupt ch.5

External interrupt ch.2

External interrupt ch.6

External interrupt ch.3

External interrupt ch.7

UART/SIO ch.0

High

IRQ0

IRQ1

IRQ2

IRQ3

L00 [1 : 0]

L01 [1 : 0]

L02 [1 : 0]

L03 [1 : 0]

IRQ4

IRQ5

FFF2^H

FFF0H

FFEEH

FFEC^H

FFEAH

FFE8H

FFE6^H

FFE4H

FFE2^H

FFE0H

FFDEH

FFDC^H

FFDAH

FFD8H

FFD6^H

FFD4^H

FFD2H

FFF3H

FFF1H

FFEFH

FFEDH

FFEBH

FFE9H

FFE7H

FFE5H

FFE3H

FFE1H

FFDFH

FFDDH

FFDBH

FFD9H

FFD7H

FFD5H

FFD3H

L04 [1 : 0]

L05 [1 : 0]

L06 [1 : 0]

L07 [1 : 0]

L08 [1 : 0]

L09 [1 : 0]

L10 [1 : 0]

L11 [1 : 0]

L12 [1 : 0]

L13 [1 : 0]

L14 [1 : 0]

L15 [1 : 0]

L16 [1 : 0]

L17 [1 : 0]

L18 [1 : 0]

L19 [1 : 0]

L20 [1 : 0]

8/16-bit compound timer ch.0 (Lower)

8/16-bit compound timer ch.0 (Upper)

LIN-UART (reception)

LIN-UART (transmission)

8/16-bit PPG ch.1 (Lower)

8/16-bit PPG ch.1 (Upper)

16-bit reload timer ch.0

8/16-bit PPG ch.0 (Upper)

8/16-bit PPG ch.0 (Lower)

8/16-bit compound timer ch.1 (Upper)

16-bit PPG ch.0

IRQ6

IRQ7

IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

IRQ16

IRQ17

IRQ18

IRQ19

IRQ20

I²C ch.0

16-bit PPG ch.1

8/10-bit A/D converter

Timebase timer

Watch timer/Watch counter

External interrupt ch.8

External interrupt ch.9

External interrupt ch.10

External interrupt ch.11

8/16-bit compound timer ch.1 (Lower)

Flash memory

IRQ21

FFD0^H

FFD1H

L21 [1 : 0]

IRQ22

IRQ23

FFCE^H

FFCCH

FFCFH

FFCDH

L22 [1 : 0]

L23 [1 : 0]

Low

30

MB95100B Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Parameter

Power supply voltage*¹

Input voltage*¹

Symbol

Unit

Remarks

Min

Max

VCC

AVCC

VSS − 0.3

VSS + 4.0

*2

V

AVR

VI1

V^SS− 0.3

VSS − 0.3

− 2.0

VSS + 4.0

VSS + 6.0

VSS + 4.0

+ 2.0

*2

Other than P80 to P83*³

V

VI2

P80 to P83

*3

Output voltage*¹

VO

Maximum clamp current

I^CLAMP

mA Applicable to pins*⁴

Total maximum clamp

current

Σ|ICLAMP|

⎯

20

mA Applicable to pins*⁴

I^OL1

I^OL2

15

Other than P00 to P07

“L” level maximum

output current

mA

P00 to P07

Other than P00 to P07

Average output current =

I^OLAV1

4

operating current × operating ratio

(1 pin)

mA

“L” level average

current

⎯

P00 to P07

Average output current =

operating current × operating ratio

(1 pin)

I^OLAV2

12

“L” level total maximum

output current

ΣIOL

⎯

100

50

mA

Total average output current =

mA operating current × operating ratio

(Total of pins)

“L” level total average

output current

ΣI^OLAV

IOH1

− 15

Other than P00 to P07

“H” level maximum

output current

⎯

mA

I^OH2

P00 to P07

Other than P00 to P07

Average output current =

IOHAV1

− 4

− 8

operating current × operating ratio

(1 pin)

mA

“H” level average

current

⎯

P00 to P07

Average output current =

operating current × operating ratio

(1 pin)

I^OHAV2

“H” level total maximum

output current

ΣI^OH

⎯

− 100

− 50

mA

Total average output current =

mA operating current × operating ratio

(Total of pins)

“H” level total average

output current

ΣI^OHAV

(Continued)

31

MB95100B Series

(Continued)

Rating

Parameter

Symbol

Unit

Remarks

Min

⎯

Max

320

Power consumption

Pd

T^A

mW

Operating temperature

− 40

+ 85

°C

MB95107B, MB95F108BS,

MB95F108BW

− 55

− 40

+ 150

+ 125

Storage temperature

T^STG

°C

MB95R107B, MB95D108BS,

MB95D108BW

*1 : The parameter is based on AV^SS= VSS = 0.0 V.

*2 : Apply equal potential to AV^CCand VCC. AVR should not exceed AVCC + 0.3 V.

*3 : VI1 and Vo should not exceed VCC + 0.3 V. VI1 must not exceed the rating voltage. However, if the maximum

current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the

VI1 rating.

*4 : Applicable to pins : P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53, P70, P71,

PE0 to PE3, PG0

• Use within recommended operating conditions.

• Use at DC voltage (current).

• The + B signal is an input signal that exceeds V^CCvoltage. The + B signal should always be applied a limiting

resistance placed between the + B signal and the microcontroller.

• The value of the limiting resistance should be set so that when the + B signal is applied the input current

to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the VCC pin, and this affects

other devices.

• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power

supply is provided from the pins, so that incomplete operation may result.

• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the

resulting power supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the + B input pin open.

• Sample recommended circuits :

• Input/Output Equivalent circuits

Protective diode

Vcc

Limiting

P-ch

resistance

+ B input (0 V to 16 V)

N-ch

R

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

32

MB95100B Series

2. Recommended Operating Conditions

Sym-

(AVSS = VSS = 0.0 V)

Value

Parameter

Pin name Condition

Unit

Remarks

bol

Min

Max

At normal operating,

Flash memory product,

TA = −10 °C to +85 °C

⎯

1.8*

3.3

At normal operating,

MASK ROM product,

TA = −10 °C to +85 °C

1.8*

2.0*

3.6

3.3

3.6

At normal operating,

Flash memory product,

T^A= −40 °C to +85 °C

At normal operating,

MASK ROM product,

T^A= −40 °C to +85 °C

Power supply

voltage

V^CC,

AVCC

At normal operating,

Flash memory product,

At FRAM access,

V

⎯

2.7

3.3

3.6

T^A= −40 °C to +85 °C

At normal operating,

MASK ROM product,

At FRAM access,

TA = −40 °C to +85 °C

MB95FV100D-101

T^A= + 5 °C to +35 °C

⎯

2.6

1.5

3.6

3.3

3.6

Retain status in stop mode,

Flash memory product

Retain status in stop mode,

MASK ROM product

A/D converter

reference input

voltage

AVR

⎯

1.8

AV^CC

V

Operating temperature

TA

− 40

+ 85

°C

* : The values vary with the operating frequency.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device

is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

33

MB95100B Series

3. DC Characteristics

Sym-

(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Parameter

Pin name

Conditions

Unit

Remarks

bol

Min

Typ

Max

At selecting CMOS

input level

V^IH1P10, P67

*1

0.7 VCC

⎯

VCC + 0.3

V

At selecting CMOS

input level

MB95F108BS,

MB95F108BW,

MB95107B,

⎯

VSS + 5.5

VCC + 0.3

MB95FV100D-101

V^IH2P50, P51

⎯

0.7 VCC

V

At selecting CMOS

input level

MB95D108BS,

MB95D108BW,

MB95R107B

P00 to P07,

P10 to P14,

P20 to P24,

P30 to P37,

P40 to P43,

V^IHS1P52, P53,

P60 to P67,

P70, P71,

*1

0.8 VCC

⎯

VCC + 0.3

V

Hysteresis input

“H” level input

voltage

PE0 to PE3,

PG0, PG1*²,

PG2*²

V^IHS2P80 to P83

*1

0.8 VCC

⎯

VSS + 5.5

V

Hysteresis input

MB95F108BS,

MB95F108BW,

MB95107B,

MB95FV100D-101

V^IHS3P50, P51

⎯

Hysteresis input

MB95D108BS,

MB95D108BW,

MB95R107B

⎯

V^SS+ 5.0

CMOS input

(Flash memory

product)

⎯

0.7 V^CC

0.8 V^CC

⎯

VCC + 0.3

V

V^IHMRST, MOD

Hysteresis input

(MASK ROM

product)

(Continued)

34

MB95100B Series

(V^CC= AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Remarks

Min

Typ

Max

At selecting CMOS

input level

(Hysteresis input)

P10, P50, P51,

P67

V^IL

*1

VSS − 0.3

⎯

0.3 VCC

V

P00 to P07,

P10 to P14,

P20 to P24,

P30 to P37,

P40 to P43,

P50 to P53,

P60 to P67,

P70, P71,

P80 to P83,

PE0 to PE3,

PG0, PG1*²,

PG2*²

V^ILS

*1

VSS − 0.3

⎯

0.2 VCC

V

Hysteresis input

“L” level input

voltage

CMOS input

(Flash memory

product)

⎯

V^SS− 0.3

⎯

0.3 VCC

0.2 VCC

V

V^ILMRST, MOD

Hysteresis input

(MASK ROM

product)

Input leakage

current (Hi-Z

output leakage

current)

Port other than

P50, P51,

P80 to P83

When the pull-up is

prohibition setting

I^LI

0.0 V < VI < VCC

− 5

⎯

+ 5

µA

Output pin other

than P00 to P07

V^OH1

IOH = − 4.0 mA

IOH = − 8.0 mA

IOL = 4.0 mA

2.4

⎯

V

“H” level output

voltage

V^OH2P00 to P07

Output pin other

than P00 to P07

V^OL1

0.4

“L” level output

voltage

V^OL2P00 to P07

VD1 P80 to P83

IOL = 12 mA

⎯

0.4

⎯

VSS − 0.3

VSS + 5.5

MB95F108BS,

MB95F108BW,

MB95107B

Open-drain

output

application

voltage

V^SS+ 5.5

V^CC+ 0.3

5

V

V^D2P50, P51

⎯

VSS − 0.3

⎯

MB95D108BS,

MB95D108BW,

MB95R107B

Open-drain

output leakage

current

P50, P51,

I^LIOD

0.0 V < VI <

VSS + 5.5 V

⎯

µA

P80 to P83

(Continued)

35

MB95100B Series

(V^CC= AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

P10 to P14,

Conditions

Unit

Remarks

Min

Typ

Max

P20 to P24,

P30 to P37,

P40 to P43,

P52, P53,

When the pull-up is

permission setting

Pull-up resistor R^PULL

VI = 0.0 V

25

50

100

kΩ

P70, P71,

PE0 to PE3,

PG0, PG1*², PG2*²

Pull-down

resistor

MASK ROM

product

R^MODMOD

VI = VCC

25

50

5

100

15

kΩ

Input

capacitance

Other than AVCC,

CIN

f = 1 MHz

⎯

pF

AVSS, AVR, VCC, VSS

MB95F108BS,

MB95F108BW

⎯

11.0 14.0 mA (at other than Flash

memory writing and

F^CH= 20 MHz

FMP = 10 MHz

Main clock mode

(divided by 2)

erasing)

MB95F108BS,

MB95F108BW

(at Flash memory

writing and erasing)

⎯

30.0 35.0 mA

7.3

10.0 mA MB95107B

MB95F108BS,

MB95F108BW

⎯

17.6 22.4 mA (at other than Flash

memory writing and

FCH = 32 MHz

erasing)

Power supply

current*³

VCC (External clock FMP = 16 MHz

ICC

operation)

Main clock mode

(divided by 2)

MB95F108BS,

MB95F108BW

(at Flash memory

writing and erasing)

⎯

38.1 44.9 mA

11.7 16.0 mA MB95107B

MB95D108BS,

MB95D108BW

11.1 15.0 mA (at other than Flash

memory writing and

FCH = 20 MHz

FMP = 10 MHz

Main clock mode

(divided by 2)

When FRAM

read and write

(f^SCL= 400 kHz)

⎯

erasing)

MB95D108BS,

MB95D108BW

(at Flash memory

write and erase)

⎯

30

35

mA

7.4

11.0 mA MB95R107B

(Continued)

36

MB95100B Series

(V^CC= AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Remarks

Min

Typ

Max

MB95D108BS,

MB95D108BW

17.7 22.5 mA (at other than Flash

memory writing and

F^CH= 32 MHz

FMP = 16 MHz

Main clock mode

(divided by 2)

When FRAM read

and write

⎯

erasing)

ICC

MB95D108BS,

MB95D108BW

(at Flash memory

write and erase)

⎯

38.1 44.9 mA

(fSCL = 400 kHz)

11.8 16.1 mA MB95R107B

FCH = 20 MHz

FMP = 10 MHz

Main Sleep mode

(divided by 2)

4.5

7.2

6.0

9.6

mA

I^CCS

F^CH= 32 MHz

FMP = 16 MHz

Main Sleep mode

(divided by 2)

⎯

FCL = 32 kHz

Power supply

current*³

VCC (External

clock operation)

FMPL = 16 kHz

Sub clock mode

(divided by 2) ,

TA = + 25 °C

I^CCL

25

7

35

15

µA

FCL = 32 kHz

FMPL = 16 kHz

Sub sleep mode

(divided by 2) ,

T^A= + 25 °C

I^CCLS

⎯

µA

FCL = 32 kHz

Watch mode

Main stop mode

T^A= + 25 °C

Flash memory

product

⎯

2

1

10

5

I^CCT

µA MASK ROM product

FCH = 4 MHz

Flash memory

product

10

6.7

14

mA

FMP = 10 MHz

Main PLL mode

(multiplied by 2.5)

10.0 mA MASK ROM product

Flash memory

I^CCMPLL

F^CH= 6.4 MHz

FMP = 16 MHz

Main PLL mode

(multiplied by 2.5)

16.0 22.4 mA

product

10.8 16.0 mA MASK ROM product

(Continued)

37

MB95100B Series

(Continued)

(V^CC= AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Remarks

Min Typ Max

F^CL= 32 kHz

FMPL = 128 kHz

Sub PLL mode

(multiplied by 4) ,

TA = + 25 °C

ICCSPLL

⎯

190

0.4

250

0.5

µA

VCC (External

clock operation)

FCH = 10 MHz

Timebase timer

mode

ICTS

mA

TA = + 25 °C

Power supply

current*³

Sub stop mode

TA = + 25 °C

I^CCH

⎯

1

5

µA

FCH = 10 MHz

AtoperatingofA/D

conversion

IA

1.3

2.2

mA

AVCC

FCH = 10 MHz

At stopping of A/D

conversion

I^AH

⎯

1

5

µA

TA = + 25 °C

*1 : P10, P50, P51, and P67 can switch the input level to either the “CMOS input level” or “hysteresis input level”.

The switching of the input level can be set by the input level selection register (ILSR).

*2 : Single clock product only

*3 : Power supply current is regulated by external clock.

• Refer to “4. AC characteristics (1) Clock Timing” for F^CHand FCL.

• Refer to “4. AC characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.

38

MB95100B Series

4. AC Characteristics

(1) Clock Timing

(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name Conditions

Unit

Remarks

Min

Typ

Max

When using main

oscillation circuit

1.00

⎯

16.25 MHz

1.00

3.00

⎯

32.50 MHz When using external clock

10.00 MHz Main PLL multiplied by 1

8.13 MHz Main PLL multiplied by 2

6.50 MHz Main PLL multiplied by 2.5

4.06 MHz Main PLL multiplied by 4

When using sub

F^CH

X0, X1

Clock frequency

⎯

32.768

⎯

kHz

oscillation circuit

When using sub PLL

Flash memory product :

F^CLX0A, X1A

⎯

32.768

⎯

kHz V^CC= 2.3 V to 3.3 V

MASK ROM product :

VCC = 2.3 V to 3.6 V

⎯

When using main

oscillation circuit

61.5

30.8

⎯

1000 ns

t^HCYL

X0, X1

1000 ns When using external clock

Clock cycle time

When using sub

t^LCYLX0A, X1A

⎯

30.5

⎯

µs oscillation circuit,

When using external clock

t^WH1

tWL1

X0

61.5

⎯

15.2

⎯

10

ns

When using external

clock, duty ratio is about

30% to 70%.

Input clock pulse width

tWH2

X0A

tWL2

µs

Input clock rise time

and fall time

tCR

X0, X0A

tCF

⎯

ns When using external clock

39

MB95100B Series

• Input wave form for using external clock (main clock)

tHCYL

tWH1

tWL1

tCR

tCF

0.8 VCC 0.8 VCC

X0

0.2 VCC

• Figure of main clock Input port external connection

When using a crystal or

ceramic oscillator

When using external clock

Microcontroller

X0

X1

X0

X1

Open

F^CH

C2

F^CH

C1

• Input wave form for using external clock (sub clock)

tLCYL

tWH2

tWL2

tCR

tCF

0.8 VCC 0.8 VCC

X0A

0.1 VCC

• Figure of sub clock input port external connection

When using a crystal or

ceramic oscillator

When using external clock

Microcontroller

X0A

X1A

X0A

X1A

Open

F^CL

C2

F^CL

C1

40

MB95100B Series

(2) Source Clock/Machine Clock

(V^CC= 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Typ

Sym- Pin

Parameter

Unit

Remarks

bol name

Min

Max

When using main clock

61.5

⎯

2000

ns Min : F^CH= 8.125 MHz, PLL multiplied by 2

Source clock cycle

time*¹

(Clock before setting

division)

Max : F^CH= 1 MHz, divided by 2

tSCLK

⎯

When using sub clock

7.6

61.0

µs Min : FCL = 32 kHz, PLL multiplied by 4

Max : F^CL= 32 kHz, divided by 2

FSP

⎯

0.5

⎯

16.25 MHz When using main clock

131.072 kHz When using sub clock

When using main clock

Source clock

frequency

FSPL

16.384

100

7.6

⎯

32000

ns Min : F^SP= 16.25 MHz, no division

Machine clock cycle

time*²

(Minimuminstruction

execution time)

Max : FSP = 0.5 MHz, divided by 16

t^MCLK

⎯

When using sub clock

976.5

µs Min : F^SPL= 131 kHz, no division

Max : F^SPL= 16 kHz, divided by 16

FMP

0.031

1.024

⎯

16.250 MHz When using main clock

131.072 kHz When using sub clock

Machine clock

frequency

⎯

FMPL

*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This

source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes

the machine clock. Further, the source clock can be selected as follow.

• Main clock divided by 2

• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)

• Sub clock divided by 2

• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)

*2 : Operation clock of the microcontroller. Machine clock can be selected as follow.

• Source clock (no division)

• Source clock divided by 4

• Source clock divided by 8

• Source clock divided by 16

41

MB95100B Series

• Outline of clock generation block

F

CH

Divided by 2

(main oscillation)

Main PLL

× 1

× 2

× 2.5

× 4

Division

circuit

× 1

SCLK

(source clock)

MCLK

(machine clock)

× 1/4

× 1/8

F

CL

Divided by 2

× 1/16

(sub oscillation)

Clock mode select bit

(SYCC: SCS1, SCS0)

Sub PLL

× 2

× 3

× 4

42

MB95100B Series

• Operating voltage - Operating frequency (When T^A= − 10 °C to + 85 °C)

• MB95107B, MB95R107B

Sub PLL operation guarantee range

FRAM operating guarantee range

Main clock mode and main PLL mode

operation guarantee range

Sub clock mode and

watch mode

3.6

2.7

2.3

1.8

0.5 MHz 3 MHz 5 MHz

16.25 MHz

16.384 kHz

32 kHz

131.072 kHz

PLL operation guarantee range

PLL operation

Source clock frequency (F^SPL)

Main clock operation guarantee range

Source clock frequency (FSP)

• MB95F108BS, MB95F108BW, MB95D108BS, MB95D108BW

Sub PLL operation guarantee range

Sub clock mode and watch mode

operation guarantee range

FRAM operating guarantee range

Main clock mode and main PLL mode

operation guarantee range

3.3

2.7

2.3

1.8

16.384 kHz

32 kHz

131.072 kHz

0.5 MHz 3 MHz

7.5 MHz

16.25 MHz

PLL operation guarantee range

Main clock operation guarantee range

Source clock frequency (FSP)

Source clock frequency (F^SPL)

43

MB95100B Series

• Operating voltage - Operating frequency (When T^A= − 40 °C to + 85 °C)

• MB95107B, MB95R107B

Sub PLL operation guarantee range

FRAM operating guarantee range

Main clock mode and main PLL mode

operation guarantee range

Sub clock mode and watch mode

operation guarantee range

3.6

2.7

2.3

1.8

0.5 MHz 3 MHz 5 MHz

16.25 MHz

16.384 kHz

32 kHz

131.072 kHz

PLL operation guarantee range

Main clock operation guarantee range

PLL operation guarantee range

Source clock frequency (F^SPL)

Source clock frequency (FSP)

• MB95F108BS, MB95F108BW, MB95D108BS, MB95D108BW

Sub PLL operation guarantee range

Sub clock mode and watch mode

operation guarantee range

FRAM operating guarantee range

Main clock mode and main PLL mode

operation guarantee range

3.3

2.7

2.3

2.0

0.5 MHz 3 MHz 5 MHz

16.25 MHz

16.384 kHz

32 kHz

131.072 kHz

PLL operation guarantee range

Main clock operation guarantee range

Source clock frequency (FSP)

Source clock frequency (F^SPL)

44

MB95100B Series

• Operating voltage - Operating frequency (T^A= + 5 °C to + 35 °C)

• MB95FV100D-101

FRAM, Main clock mode and main PLL

mode operation guarantee range

Sub PLL, Sub clock mode and watch

mode operation guarantee range

3.6

3.3

2.6

16.384 kHz

32 kHz

131.072 kHz

0.5 MHz 3 MHz

10 MHz

16.25 MHz

PLL operation guarantee range

Main clock operation guarantee range

Source clock frequency (FSP)

Source clock frequency (FSPL)

45

MB95100B Series

• Main PLL operation frequency

[MHz]

16.25

16

15

× 4

12

× 2.5

10

× 1

× 2

7.5

6

5

3

[MHz]

10

0

3

4 4.062

5

6.4 6.5

8

8.125

Machine clock frequency (F^MP)

46

MB95100B Series

(3) External Reset

Parameter

(V^CC= 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Symbol

Unit

Remarks

Min

Max

2 tMCLK*¹

⎯

ns At normal operating

RST “L” level pulse

width

Oscillation time of oscillator*²

At stop mode, sub clock mode,

ns

tRSTL

⎯

+ 2 tMCLK*¹

sub sleep mode, and watch mode

*1 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

*2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the

oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between

hundreds of µs and several ms. In the external clock, the oscillation time is 0 ms.

• At normal operating

tRSTL

RST

0.2 VCC

• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on

tRSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal

operating

clock

2 tMCLK

Oscillation time

of oscillator

Oscillation stabilization wait time

Execute instruction

Internal reset

47

MB95100B Series

(4) Power-on Reset

(AV^SS= VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Parameter

Symbol

Conditions

Unit

Remarks

Min

Max

Power supply rising time

Power supply cutoff time

t^R

⎯

36

ms

Waiting time until

power-on

t^OFF

1

⎯

Note : The power supply must be turned on within the selected oscillation stabilization time.

tR

t

OFF

1.5 V

0.2 V

VCC

Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power

supply voltages during operation, set the slope of rising within 20 mV/ms as shown below.

VCC

Limiting the slope of rising within

20 mV/ms is recommended.

1.5 V

Hold Condition in stop mode

VSS

48

MB95100B Series

(5) Peripheral Input Timing

(V^CC= 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Parameter

Symbol

tILIH

Pin name

Unit

ns

Min

Max

Peripheral input “H” pulse width

Peripheral input “L” pulse width

INT00 to INT07,

INT10 to INT13,

EC0, EC1, TI0, TRG0/ADTG,

TRG1

2 t^MCLK*

⎯

tIHIL

2 tMCLK*

⎯

ns

* : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

tILIH

tIHIL

INT00 to INT07,

INT10 to INT13, EC0, EC1,

TI0, TRG0/ADTG, TRG1

0.8 VCC 0.8 VCC

0.2 VCC

49

MB95100B Series

(6) UART/SIO, Serial I/O Timing

(V^CC= 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Min

Max

⎯

Serial clock cycle time

UCK ↓ → UO time

t^SCYC

t^SLOV

t^IVSH

tSHIX

t^SHSL

t^SLSH

tSLOV

t^IVSH

tSHIX

UCK0

UCK0, UO0

UCK0, UI0

UCK0

4 t^MCLK*

− 190

ns

Internal clock

operation output pin :

C^L= 80 pF + 1TTL.

+ 190

⎯

Valid UI → UCK ↑

2 tMCLK*

4 t^MCLK*

4 tMCLK*

0

UCK ↑ → valid UI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

UCK ↓ → UO time

⎯

UCK0

⎯

External clock

UCK0, UO0 operation output pin :

190

⎯

C^L= 80 pF + 1TTL.

Valid UI → UCK ↑

UCK0, UI0

2 tMCLK*

UCK ↑ → valid UI hold time

UCK0, UI0

⎯

* : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

• Internal shift clock mode

tSCYC

2.4 V

UCK0

0.8 V

tSLOV

UO0

UI0

2.4 V

0.8 V

tIVSH

tSHIX

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

• External shift clock mode

UCK0

tSHSL

0.8 VCC 0.8 VCC

tSLSH

0.2 VCC 0.2 VCC

tSLOV

UO0

UI0

2.4 V

0.8 V

tIVSH

tSHIX

0.8 V^CC0.8 VCC

0.2 VCC 0.2 VCC

50

MB95100B Series

(7) LIN-UART Timing

Sampling at the rising edge of sampling clock*¹and prohibited serial clock delay*²

(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)

(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

5 t^MCLK*³

−95

Max

Serial clock cycle time

SCK ↑→ SOT delay time

Valid SIN→SCK↑

t^SCYC

SCK

⎯

ns

Internal clock

operation output pin :

C^L= 80 pF + 1 TTL.

tSLOVI SCK, SOT

+ 95

t^IVSHI

t^SHIXI

tSLSH

t^SHSL

SCK, SIN

SCK

tMCLK*³+ 190

⎯

SCK↑→ valid SIN hold time

Serial clock “L” pulse width

Serial clock “H” pulse width

SCK ↓→SOT delay time

Valid SIN→SCK↑

0

3 t^MCLK*³− tR

tMCLK*³+ 95

⎯

SCK

⎯

t^SLOVESCK, SOT

2 tMCLK*³+ 95

External clock

t^IVSHESCK, SIN operationoutputpin:

190

⎯

10

C^L= 80 pF + 1 TTL.

SCK↑→ valid SIN hold time

SCK fall time

t^SHIXESCK, SIN

tMCLK*³+ 95

⎯

t^F

SCK

SCK rise time

t^R

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the

serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

51

MB95100B Series

• Internal shift clock mode

t

SCYC

2.4 V

SCK

0.8 V

tSLOVI

2.4 V

SOT

0.8 V

t

IVSHI

tSHIXI

0.8 VCC 0.8 VCC

SIN

0.2 VCC 0.2 VCC

• External shift clock mode

tSLSH

tSHSL

0.8 VCC

SCK

SOT

SIN

0.2 VCC

t^R

tF

tSLOVE

2.4 V

0.8 V

tIVSHE

t^SHIXE

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

52

MB95100B Series

Sampling at the falling edge of sampling clock*¹and prohibited serial clock delay*²

(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)

(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

5 t^MCLK*³

−95

Max

Serial clock cycle time

SCK↑→ SOT delay time

Valid SIN→SCK↓

t^SCYC

t^SHOVI

tIVSLI

t^SLIXI

t^SHSL

tSLSH

SCK

SCK, SOT

SCK, SIN

SCK

⎯

ns

Internal clock

operation output pin :

C^L= 80 pF + 1 TTL.

+ 95

tMCLK*³+ 190

⎯

SCK↓→ valid SIN hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK↑ →SOT delay time

Valid SIN→SCK↓

0

3 t^MCLK*³− tR

tMCLK*³+ 95

⎯

SCK

⎯

t^SHOVESCK, SOT

2 tMCLK*³+ 95

External clock

t^IVSLE

t^SLIXE

t^F

SCK, SIN operation output pin :

190

⎯

10

C^L= 80 pF + 1 TTL.

SCK↓→ valid SIN hold time

SCK fall time

SCK, SIN

tMCLK*³+ 95

⎯

SCK

SCK rise time

t^R

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the

serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

53

MB95100B Series

• Internal shift clock mode

t

SCYC

2.4 V

SCK

0.8 V

tSHOVI

2.4 V

SOT

SIN

0.8 V

tSLIXI

t

IVSLI

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

• External shift clock mode

tSHSL

tSLSH

SCK

0.8 VCC

0.2 VCC

tR

0.2 VCC

t^F

tSHOVE

2.4 V

0.8 V

SOT

SIN

tIVSLE

t^SLIXE

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

54

MB95100B Series

Sampling at the rising edge of sampling clock*¹and enabled serial clock delay*²

(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)

(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

Max

⎯

Serial clock cycle time

SCK↑→ SOT delay time

Valid SIN→SCK↓

t^SCYC

t^SHOVI

tIVSLI

SCK

5 tMCLK*³

ns

SCK, SOT

−95

+ 95

⎯

Internal clock

SCK, SIN operation output pin : tMCLK*³+ 190

CL = 80 pF + 1 TTL.

SCK↓→ valid SIN hold time

SOT→SCK↓ delay time

t^SLIXI

SCK, SIN

SCK, SOT

0

⎯

4 tMCLK*³

t^SOVLI

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the

serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

tSCYC

2.4 V

SCK

0.8 V

tSHOVI

tSOVLI

2.4 V

0.8 V

2.4 V

0.8 V

SOT

SIN

tSLIXI

tIVSLI

0.8 VCC

0.2 VCC

55

MB95100B Series

Sampling at the falling edge of sampling clock*¹and enabled serial clock delay*²

(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)

(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

Max

⎯

Serial clock cycle time

SCK↓→SOT delay time

Valid SIN→SCK↑

t^SCYC

t^SLOVI

tIVSHI

t^SHIXI

t^SOVHI

SCK

5 tMCLK*³

ns

SCK, SOT

−95

+ 95

⎯

Internal clock

SCK, SIN operating output pin : tMCLK*³+ 190

CL = 80 pF + 1 TTL.

SCK↑ → valid SIN hold time

SOT→SCK↑ delay time

SCK, SIN

SCK, SOT

0

⎯

4 tMCLK*³

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the

serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

tSCYC

2.4 V

SCK

0.8 V

tSOVHI

t^SLOVI

2.4 V

0.8 V

2.4 V

0.8 V

SOT

SIN

tIVSHI

tSHIXI

0.8 V^CC

0.2 VCC

0.8 VCC

0.2 VCC

56

MB95100B Series

(8) I²C Timing

(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Parameter

Symbol Pin name Conditions Standard-mode

Fast-mode

Unit

Min

Max

Min

Max

SCL clock frequency

f^SCL

SCL0

0

100

0

400

kHz

(Repeat) Start condition hold

time SDA ↓ → SCL ↓

SCL0

SDA0

tHD;STA

4.0

⎯

0.6

⎯

µs

SCL clock “L” width

SCL clock “H” width

t^LOW

t^HIGH

SCL0

4.7

4.0

⎯

1.3

0.6

⎯

µs

(Repeat) Start condition set-

up time SCL ↑ → SDA ↓

SCL0

SDA0

tSU;STA

t^HD;DAT

t^SU;DAT

t^SU;STO

tBUF

4.7

0

⎯

3.45*²

⎯

0.6

0

⎯

0.9*³

⎯

µs

R = 1.7 kΩ,

C = 50 pF*¹

Data hold time SCL ↓ → SDA

↓ ↑

SCL0

SDA0

Data setup time SDA ↓ ↑ →

SCL ↑

SCL0

SDA0

0.25

4

0.1

0.6

1.3

Stop condition setup time SCL

↑ → SDA ↑

SCL0

SDA0

⎯

Bus free time between stop

condition and start condition

SCL0

SDA0

4.7

⎯

*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : The maximum t^HD;DAThave only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.

*3 : A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement

t^SU;DAT≥ 250 ns must then be met.

tWAKEUP

SDA0

SCL0

t

HD;STA

t

HD;DAT

t

HIGH

t

BUF

t

LOW

t

SU;STO

t

HD;STA

tSU;DAT

tSU;STA

57

MB95100B Series

(V^CC= 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)

Value*²

Sym- Pin

bol name

Condi-

tions

Parameter

Unit

Remarks

Min

Max

SCL clock

“L” width

(2 + nm / 2) tMCLK − 20

⎯

t^LOW

SCL0

ns Master mode

SCL clock

“H” width

(nm / 2) tMCLK − 20

(nm / 2 ) tMCLK + 20

(−1 + nm) tMCLK + 20

tHIGH

ns Master mode

Master mode

Maximum value is

applied when m,

ns n = 1, 8.

Startcondition

hold time

SCL0

SDA0

(−1 + nm / 2) tMCLK − 20

t^HD;STA

Otherwise, the

minimum value is

applied.

Stopcondition

setup time

SCL0

SDA0

(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns Master mode

t^SU;STO

Startcondition

setup time

SCL0

SDA0

t^SU;STA

Bus free time

between stop

condition and

start condition

SCL0

SDA0

tBUF

(2 nm + 4) tMCLK − 20

3 tMCLK − 20

⎯

ns

SCL0

SDA0

Data hold time t^HD;DAT

ns Master mode

R = 1.7 kΩ,

C = 50 pF*¹

Master mode

When assuming

that “L” of SCL is not

extended, the

Data setup

t^SU;DAT

SCL0

SDA0

minimum value is

(−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20 ns

time

applied to first bit of

continuous data.

Otherwise,

the maximum value

is applied.

Minimum value is

applied to interrupt

at 9th SCL↓.

Maximum value is

applied to interrupt

at 8th SCL↓.

Setup time

between

clearing

interrupt and

SCL rising

(nm / 2) tMCLK − 20

(1 + nm / 2) tMCLK + 20

tSU;INT SCL0

ns

SCL clock “L”

width

4 tMCLK − 20

⎯

t^LOW

t^HIGH

SCL0

ns At reception

SCL clock “H”

width

Undetected when 1

ns tMCLK is used at

reception

Startcondition

detection

SCL0

SDA0

2 tMCLK − 20

⎯

t^HD;STA

(Continued)

58

MB95100B Series

(Continued)

(V^CC= 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)

Value*²

Sym-

bol

name

Condi-

tions

Parameter

Unit

Remarks

Min

Max

Undetected when 1

ns tMCLK is used at

reception

Stop condition

detection

SCL0

SDA0

2 tMCLK − 20

⎯

t^SU;STO

Undetected when 1

ns tMCLK is used at

reception

Restart condition

detection condition

SCL0

SDA0

2 tMCLK − 20

⎯

t^SU;STA

SCL0

SDA0

Bus free time

tBUF

2 tMCLK − 20

tLOW − 3 tMCLK − 20

0

⎯

ns At reception

SCL0

SDA0

At slave transmission

mode

Data hold time

Data setup time

Data hold time

Data setup time

t^HD;DAT

t^SU;DAT

t^HD;DAT

tSU;DAT

ns

R = 1.7 kΩ,

C = 50 pF*¹

SCL0

SDA0

At slave transmission

mode

ns

SCL0

SDA0

ns At reception

SCL0

SDA0

tMCLK − 20

Oscillationstabilization

wait time +

SDA↓→SCL↑

(at wakeup function)

SCL0

SDA0

⎯

t^WAKEUP

ns

2 t^MCLK− 20

*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : • Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

• m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR) .

• n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR) .

• Actual timing of I²C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of

ICCR0 register.

• Standard-mode :

m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.

Setting of m and n determines the machine clock that can be used below.

(m, n) = (1, 8)

: 0.9 MHz < tMCLK ≤ 1 MHz

(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz

(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz

(m, n) = (1, 98)

• Fast-mode :

: 0.9 MHz < tMCLK ≤ 10 MHz

m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.

Setting of m and n determines the machine clock that can be used below.

(m, n) = (1, 8)

(m, n) = (1, 22) , (5, 4)

(m, n) = (6, 4)

: 3.3 MHz < tMCLK ≤ 4 MHz

: 3.3 MHz < tMCLK ≤ 8 MHz

: 3.3 MHz < tMCLK ≤ 10 MHz

59

MB95100B Series

5. A/D Converter

(1) A/D Converter Electrical Characteristics

(AV^CC= VCC = 1.8 V to 3.3 V [Flash memory product], AVCC = VCC = 1.8 V to 3.6 V [MASK ROM product],

AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Sym-

Parameter

Resolution

Unit

Remarks

bol

Min

Typ

Max

10

⎯

bit

Total error

− 3.0

− 2.5

⎯

+ 3.0

+ 2.5

LSB

⎯

Linearity error

⎯

Differential linear

error

− 1.9

⎯

+ 1.9

LSB

Flashmemoryproduct:

2.7 V ≤ AV^CC≤ 3.3 V

MASK ROM product :

2.7 V ≤ AVCC ≤ 3.6 V

AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB

AVSS − 0.5 LSB AVSS + 1.5 LSB AVSS + 3.5 LSB

AVR − 3.5 LSB AVR − 1.5 LSB AVR + 0.5 LSB

AVR − 2.5 LSB AVR − 0.5 LSB AVR + 1.5 LSB

V

Zero transition

voltage

V^OT

V^FST

⎯

1.8 V ≤ AVCC < 2.7 V

Flashmemoryproduct:

2.7 V ≤ AV^CC≤ 3.3 V

MASK ROM product :

2.7 V ≤ AVCC ≤ 3.6 V

V

Full-scale transition

voltage

V

1.8 V ≤ AVCC < 2.7 V

Flashmemoryproduct:

2.7 V ≤ AV^CC≤ 3.3 V

MASK ROM product :

2.7 V ≤ AVCC ≤ 3.6 V

1.3

20

⎯

140

µs

Compare time

Sampling time

1.8 V ≤ AVCC < 2.7 V

Flashmemoryproduct:

2.7 V ≤ AVCC ≤ 3.3 V

MASK ROM product :

2.7 V ≤ AVCC ≤ 3.6 V ex-

ternal impedance < at

1.8 kΩ

0.4

⎯

∞

µs

⎯

1.8 V ≤ AV^CC< 2.7 V

µs external impedance <

at 14.8 kΩ

30

⎯

∞

Analog input current

Analog input voltage

Reference voltage

IAIN

VAIN

⎯

−0.3

AVSS

⎯

+ 0.3

AVR

AVCC

µA

V

AVSS + 1.8

V

AVR pin

AVR pin,

During A/D operation

IR

⎯

400

600

5

µA

Reference voltage

supply current

AVR pin,

At stop mode

IRH

⎯

µA

60

MB95100B Series

(2) Notes on Using A/D Converter

• About the external impedance of analog input and its sampling time

• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship

between the external impedance and minimum sampling time and either adjust the register value and operating

frequency or decrease the external impedance so that the sampling time is longer than the minimum value.

Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

• Analog input equivalent circuit

R

Analog input pin

Comparator

C

During sampling : ON

R

C

2.7 V ≤ AV^CC≤ 3.6 V

1.8 V ≤ AV^CC< 2.7 V

1.7 kΩ (Max)

84 kΩ (Max)

14.5 pF (Max)

25.2 pF (Max)

Note : The values are reference values.

• The relationship between external impedance and minimum sampling time

(External impedance = 0 kΩ to 20 kΩ)

(External impedance = 0 kΩ to 100 kΩ)

AV^CC≥ 2.7 V

100

20

90

80

70

60

18

16

14

12

10

8

AVCC ≥ 1.8 V

50

40

30

20

10

0

6

4

2

0

5

10 15 20 25 30 35 40

0

1

2

3

4

Minimum sampling time [µs]

• About errors

As |AVR − AV^SS| becomes smaller, values of relative errors grow larger.

61

MB95100B Series

(3) Definition of A/D Converter Terms

• Resolution

The level of analog variation that can be distinguished by the A/D converter.

When the number of bits is 10, analog voltage can be divided into 2¹⁰= 1024.

• Linearity error (unit : LSB)

The deviation between the value along a straight line connecting the zero transition point

(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point

(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.

• Differential linear error (Unit : LSB)

Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

• Total error (unit: LSB)

Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,

linearity error, quantum error, and noise.

Ideal I/O characteristics

Total error

V

FST

3FF

H

3FFH

3FE

H

3FE

H

Actual conversion

characteristic

1.5 LSB

3FD

H

3FD

H

{1 LSB × (N − 1) + 0.5 LSB}

004

003

002

001

H

004

003

002

001

H

V

NT

V

OT

Actual conversion

characteristic

1 LSB

0.5 LSB

Ideal characteristics

AV^SS

AVSS

AVR

Analog input

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

AVR − AV^SS

1024

Total error of

digital output N

=

1 LSB =

(V)

[LSB]

1 LSB

N

: A/D converter digital output value

VNT : A voltage at which digital output transits from (N - 1) to N.

(Continued)

62

MB95100B Series

(Continued)

Full-scale transition error

Zero transition error

Ideal

004

003

002

001

H

characteristics

Actual conversion

characteristic

3FF

3FE

3FD

H

Actual conversion

characteristic

Ideal

characteristics

VFST

(measurement

value)

Actual conversion

characteristic

Actual conversion

characteristic

3FC

H

VOT (measurement value)

AVSS

AVR

AVSS

AVR

Analog input

Linearity error

Differential linear error

Actual conversion

characteristic

Ideal characteristics

3FF

3FE

3FD

H

N+1

H

Actual conversion

characteristic

{1 LSB × N + VOT

}

H

V

(N+1)T

V^FST

N

(measurement

value)

V

NT

004

003

002

001

H

N-1

V

NT

Actual conversion

characteristic

Actual conversion

characteristic

Ideal characteristics

N-2H

VOT (measurement value)

AV^SS

AVR

AVSS

AVR

Analog input

V^NT− {1 LSB × N + VOT}

V ^(N+ 1) T − VNT

Linear error in

digital output N

Differential linear error

in digital output N

=

− 1

1 LSB

N

: A/D converter digital output value

VNT : A voltage at which digital output transits from (N - 1) to N.

VOT (Ideal value) = AVSS + 0.5 LSB [V]

VFST (Ideal value) = AVR − 1.5 LSB [V]

63

MB95100B Series

6. Flash Memory Program/Erase Characteristics

Value

Parameter

Unit

Remarks

Min

Typ

Max

Sector erase time

(4K bytes sector)

⎯

0.2*¹

3.0*²

s

Excludes 00H programming prior erasure.

Sector erase time

(16K bytes sector)

⎯

0.5*¹

12.0*²

Byte programming time

Program/erase cycle

⎯

32

3600

µs Excludes system-level overhead.

cycle

10000

⎯

Power supply voltage at

program/erase

2.7

⎯

3.3

V

Flash memory data retention

time

20*³

⎯

year Average TA = +85 °C

*1 : TA = + 25 °C, VCC = 3.0 V, 10000 cycles

*2 : T^A= + 85 °C, VCC = 2.7 V, 10000 cycles

*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at +85 °C) .

7. FRAM Program Characteristics

Value

Parameter

Unit

Remarks

Min

Typ

Max

Read/write cycle*

10¹⁰

⎯

cycle

V

Power supply voltage at

read/write

2.7

10

⎯

3.6

Data retention time

⎯

year T^A= 0 °C to +55 °C

* : Number of data read/write

64

MB95100B Series

■ MASK OPTION

MB95107B

MB95R107B

MB95F108BS

MB95D108BS

MB95F108BW

MB95FV100D-101

MB95D108BW

Part number

No.

Specify when

ordering MASK

Specifying procedure

Setting disabled Setting disabled Setting disabled

Clock mode select*¹

• Single-system clock mode

• Dual-system clock mode

Changing by the

switch on MCU

board

Single-system

clock mode

Dual-system

clock mode

1

2

Selectable

FRAM*¹

• With load of FRAM

• Without load of FRAM

Low voltage detection reset*²

• With low voltage detection

reset

• Without low voltage

detection reset

Specify by

part number

Specify by

part number

Specify by

part number

No

3

4

5

No

Clock supervisor*²

• With clock supervisor

• Without clock supervisor

Selection of oscillation

stabilization wait time

Selectable

Fixed to oscillation Fixed to oscillation Fixed to oscillation

stabilization wait stabilization wait stabilization wait

1 : (2²− 2) /FCH

• Selectable the initial value 2 : (2¹²− 2) /FCH

time of

of main clock oscillation

stabilization wait time

3 : (2¹³− 2) /FCH

4 : (2¹⁴− 2) /FCH

(2¹⁴− 2) /FCH

*1 : Refer to table below about clock mode select and load of FRAM.

*2 : Low voltage detection reset and clock supervisor are options of 5-V products.

Part number

MB95107B/R107B

Clock mode select

Single-system

Dual-system

Load of FRAM

No

MB95F108BS

MB95D108BS

MB95F108BW

MB95D108BW

No

Single-system

Dual-system

Yes

No

Yes

No

Single-system

Dual-system

MB95FV100D-101

No

65

MB95100B Series

■ ORDERING INFORMATION

Part number

Package

MB95107BPFV

MB95F108BSPFV

MB95F108BWPFV

MB95R107BPFV

MB95D108BSPFV

MB95D108BWPFV

64-pin plastic LQFP

(FPT-64P-M03)

MB95107BPFM

MB95F108BSPFM

MB95F108BWPFM

MB95R107BPFM

MB95D108BSPFM

MB95D108BWPFM

64-pin plastic LQFP

(FPT-64P-M09)

MCU board

224-pin plastic PFBGA

(BGA-224P-M08)

MB2146-301A

(MB95FV100D-101PBT)

(

)

66

MB95100B Series

■ PACKAGE DIMENSIONS

64-pin plastic LQFP

Lead pitch

0.50 mm

10.0 × 10.0 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Weight

Plastic mold

1.70 mm MAX

0.32g

Code

(Reference)

(FPT-64P-M03)

P-LFQFP64-10×10-0.50

64-pin plastic LQFP

(FPT-64P-M03)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

12.00 0.20(.472 .008)SQ

*

10.00 0.10(.394 .004)SQ

0.145 0.055

(.006 .002)

48

33

49

32

Details of "A" part

0.08(.003)

1.50 –⁺0⁰.^.1²0⁰

(Mounting height)

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

INDEX

0.10 0.10

(.004 .004)

(Stand off)

0˚~8˚

64

17

"A"

0.25(.010)

0.50 0.20

(.020 .008)

1

16

LEAD No.

0.60 0.15

(.024 .006)

0.50(.020)

0.20 0.05

(.008 .002)

M

0.08(.003)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2003 FUJITSU LIMITED F64009S-c-5-8

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

(Continued)

67

MB95100B Series

(Continued)

64-pin plastic LQFP

Lead pitch

0.65 mm

12 × 12 mm

Package width ×

package length

Lead shape

Sealing method

Mounting height

Gullwing

Plastic mold

1.70 mm MAX

P-LQFP64-12×12-0.65

Code

(Reference)

(FPT-64P-M09)

64-pin plastic LQFP

(FPT-64P-M09)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

14.00 0.20(.551 .008)SQ

*12.00 0.10(.472 .004)SQ

0.145 0.055

(.0057 .0022)

48

33

49

32

0.10(.004)

Details of "A" part

1.50 ⁺^–0⁰^.^.¹²⁰⁰

(Mounting height)

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

0.25(.010)

INDEX

0~8˚

64

17

0.50 0.20

(.020 .008)

0.10 0.10

(.004 .004)

(Stand off)

"A"

1

16

0.60 0.15

(.024 .006)

0.65(.026)

0.32 0.05

(.013 .002)

M

0.13(.005)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2003 FUJITSU LIMITED F64018S-c-3-5

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

68

MB95100B Series

The information for microcontroller supports is shown in the following homepage.

http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

The company names and brand names herein are the trademarks or

registered trademarks of their respective owners.

Edited

Business Promotion Dept.

F0612


型号：	MB95R107BPFV
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontrollers 8位微控制器专用微控制器和处理器外围集成电路时钟
文件：	总69页 (文件大小：825K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB95R107BPFV [FUJITSU]

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