GPLB38B-NnnV-C [GENERALPLUS]
LCD Controller with 512KB ROM;
| 型号： | GPLB38B-NnnV-C |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | LCD Controller with 512KB ROM CD |
| 文件： | 总13页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPLB38B
LCD Controller with 512KB
ROM
MAY 10, 2010
Version 1.3
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPLB38B
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3
2. FEATURES.................................................................................................................................................................................................. 3
3. BLOCK DIAGRAM ...................................................................................................................................................................................... 3
4. APPLICATION FIELD.................................................................................................................................................................................. 3
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 4
5.1. PAD ASSIGNMENT ................................................................................................................................................................................. 5
6. FUNCATIONAL DESCRIPTIONS ............................................................................................................................................................... 6
6.1. MEMORIES ............................................................................................................................................................................................ 6
6.2. MAP OF MEMORY AND I/OS .................................................................................................................................................................... 6
6.3. OPERATION MODES ............................................................................................................................................................................... 6
6.4. OPERATING MODE ................................................................................................................................................................................. 6
6.5. STANDBY MODE..................................................................................................................................................................................... 6
6.6. HALT MODE ........................................................................................................................................................................................... 6
6.7. SPEECH AND MELODY............................................................................................................................................................................ 7
6.8. LCD CONTROLLER/DRIVER.................................................................................................................................................................... 7
6.9. LCD VOLTAGE GENERATION................................................................................................................................................................... 7
6.10.AUDIO OUTPUT...................................................................................................................................................................................... 7
6.11.LOW VOLTAGE DETECTION..................................................................................................................................................................... 7
6.12.KEY SCAN FUNCTION............................................................................................................................................................................. 7
6.13.WATCHDOG TIMER (WDT) ..................................................................................................................................................................... 7
6.14.MASK OPTIONS...................................................................................................................................................................................... 7
6.14.1. 32768 oscillator .................................................................................................................................................................... 7
6.14.2. Watchdog timer .................................................................................................................................................................... 7
6.14.3. Low voltage reset ................................................................................................................................................................. 7
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................... 8
7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................... 8
7.2. DC CHARACTERISTICS(TA=25℃)........................................................................................................................................................... 8
8. APPLICATION CIRCUITS........................................................................................................................................................................... 9
8.1. 1024 DOTS LCD DRIVER, 64 SEGMENTS × 16 COMMONS, 1/5 BIAS - (1)................................................................................................. 9
8.2. AUDIO OUTPUT CONNECTIONS - (2)...................................................................................................................................................... 10
9. PACKAGE/ORDERING INFORMATION................................................................................................................................................... 11
9.1. ORDERING INFORMATION ......................................................................................................................................................................11
10.DISCLAIMER............................................................................................................................................................................................. 12
11. REVISION HISTORY ................................................................................................................................................................................. 13
© Generalplus Technology Inc.
Proprietary & Confidential
2
MAY 10, 2010
Version: 1.3
GPLB38B
LCD CONTROLLER WITH 512KB ROM
1. GENERAL DESCRIPTION
The GPLB38B, an 8-bit CMOS microprocessor, contains 1216
bytes working RAM, 512K bytes ROM, 12 I/Os, interrupt/wakeup
controller, and automatic display controller/driver for LCD. It also
features one PWM driver with two audio channels to produce
attractive sound effects easily. Its large ROM area can be used
to store both program and audio data. Furthermore, a SLEEP
(power-down) function is also built in to extend power life. The
GPLB38B is designed with GENERALPLUS state-of-the-art
technology to fulfill LCD application needs, especially for
hand-held products.
Peripherals
─ Dedicated I/Os: PA[0:7], PC[4:7]
─ 32.768KHz oscillator circuit for RTC
─ RC-oscillator (only one resistor is needed)
─ Two 16-bit reloadable timer/counters
─ 2-channel PWM audio outputs
─ Watchdog Timer for reliable operation
Wide operating voltage range:
─ 2.4V - 3.6V
3. BLOCK DIAGRAM
2. FEATURES
32KHz
ROSC
ROSC32
Built in 8-bit processor
─ 1216 bytes SRAM
RC-Oscillator
32 KHz
Oscillator
&
AUDA
AUDB
PWM Driver
─ 512K bytes ROM
System Clock Gen.
Time base
─ Max. operating speed: 8.0MHz @ 2.4V - 3.6V
─ Programmable CPU clock: /1, /2, /4, /8, /16, /32, /64 of
Power Supply
Voltage Detect
ROSC Frequency.
─ 5 wake-up sources
─ 5 interrupt sources
Two 16-bit /
Auto-reload
Timers
512K bytes
ROM
(I/O)
PA[7:0]
Key scan function
8
4
Max.12
─ SEG[15:0] can be used to send key scan output
I/O Ports
8-bit
1216 bytes
RAM
PC[7:4]
micro-processor
Programmable LCD driver
─ 64 segments, 16 commons, maximum 1024 dots
─ 1/5 bias; 1/16 duty capability
LCD RAM 128 bytes
16 Commons X 64 Segments LCD Driver
─ 128 bytes dedicated LCD RAM
─ Built-in voltage regulator to generate VLCD for LCD driver
─ 27-level contrast control (2.98V - 5.75V, in 1/5 bias)
COM[15:0]
SEG[63:0]
Power saving SLEEP mode
Low Voltage Detector
─ 6-level 2.9V - 2.4V detection
─ 2.2V Low voltage reset
4. APPLICATION FIELD
Handheld game
Low power consumption:
Scientific calculator
─ 1.2mA typical @ 3.0V, FCPU = 2.0MHz, FOSC = 8.0MHz
─ 30μA typical halt current @ 3.0V
Talking calculator, Talking clock
Talking instrument controller
General speech synthesizer
Data bank
─ <1μA typical standby current @ 3.0V
© Generalplus Technology Inc.
Proprietary & Confidential
3
MAY 10, 2010
Version: 1.3
GPLB38B
5. SIGNAL DESCRIPTIONS
Total: 107pins
Mnemonic
SEG63 - 0
PIN No.
Type
Description
63-108,1-18
19-34
O
O
LCD driver segment output.
LCD driver common output.
COM15 - 0
PA7 - 0
62-55
I/O
Port A is a bi-directional I/O port, which can be software programmed as wake
up I/O.
PC7 - 4
ROSC
54-51
41
I/O
Port C is a bi-directional I/O port.
I
I
R-oscillator input, connect to VDD through a resistor.
System reset input, low active.
40
RESET
AUDA, AUDB
X32I
38,37
44
O
I
PWM audio output.
32.768KHz crystal input or connects to VDD through a resistor (option).
X32O
TEST
CUP2 - 1
V2X
43
O
I
32.768KHz crystal output.
Test input.
42
47,46
48
P
P
P
P
P
P
P
LCD voltage generation. Charge pump capacitor inter-connection pins.
Pump 2X output.
VLCD
VDD
50
LCD voltage generation.
49
Power supply voltage input.
Ground reference.
VSS
45
PVDD
PVSS
NC
35
PWM driver power.
36
PWM driver ground reference.
39
Legend: I = Input, O = Output, P = Power
© Generalplus Technology Inc.
Proprietary & Confidential
4
MAY 10, 2010
Version: 1.3
GPLB38B
5.1. PAD Assignment
The IC substrate should be connected to VSS
Note1: To ensure that the IC functions properly, please bond all of VDD and VSS pins.
Note2: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible.
© Generalplus Technology Inc.
Proprietary & Confidential
5
MAY 10, 2010
Version: 1.3
GPLB38B
6. FUNCATIONAL DESCRIPTIONS
6.1. Memories
The GPLB38B contains 512K-byte ROM and 1216-byte SRAM.
6.2. Map of Memory and I/Os
CPU View
ROM View
*NMI SOURCE:
─ LV DETECT
0H
0L
1H
$00000 - $03FFF
$04000 - $07FFF
$08000 - $0BFFF
$0C000 - $0FFFF
$10000 - $13FFF
$14000 - $17FFF
I/O &
Reg.
0
$0000-$003F
─ TIMER1
$0040-$04FF
RAM
1
2
*INT SOURCE:
1L
─ EXT INT
DPRAM
$3E00-$3FFF
2H
2L
─ TBL (2/4/8/16Hz)
─ TBH (128/256/512/1KHz)
ROM
─ TIMER0
─ TIMER1
$4000-$7FFF
$8000-$BFFF
(Bank)L
. . .
16
ROM
$78000 - $7BFFF
$7C000 - $7FFFF
15H
15L
(Bank)H
15
ROM
$C000-$FFF9
$FFFA-$FFFF
0L
Bank Address: $0
$C000-$FFFF always mapping into 0L
Interrupt
Note1: User program should start from $C800. $C000-$C7FF is the test program area.
Note2: User program interrupt vector: $FFFA ~ $FFFF
Note3: Test program interrupt vector: $FFF2 ~ $FFF7
6.3. Operation Modes
6.5. Standby Mode
There are three operation modes involved in GPLB38B: standby,
halt and operating. The following table shows the differences
between these modes.
The standby mode is a mode where the device is placed in its
lowest current consumption state. In standby mode, all functions
are turned off; in addition, RAM and I/Os will remain in their
previous states.
Operating
ON
Halt
OFF
Standby
OFF
6.6. Halt Mode
CPU
In halt mode, CPU clock halts and waits for an event (key press,
timer overflow) to wake up. The 32768Hz related functions, such
as timer/counter and LCD driver, may remain active in the halt
mode.
32768Hz oscillator
LCD driver
ON
ON
OFF
ON
ON/OFF
OFF
6.4. Operating Mode
In operating state, all functions (CPU, 32768Hz oscillator,
timer/counter, LCD driver…) are activated. Generally speaking,
this mode consumes the highest power.
© Generalplus Technology Inc.
Proprietary & Confidential
6
MAY 10, 2010
Version: 1.3
GPLB38B
6.10. Audio Output
The following figure is the GPLB38B state diagram:
Internally, the GPLB38B supports PWM audio output. The
GPLB38B has a pair of PWM drivers, supporting two sound
channels. Each channel is able to play speech or tone
individually. The PWM drivers can directly drive speaker or
buzzer without buffer or amplification circuit.
Write $07h to
CPU_Clk_Ctrl register,
32768 oscillator OFF
OPERATING
STANDBY
Wake-up or user reset
6.11. Low Voltage Detection
The GPLB38B provides a 6-level (software programmable) low
voltage detector to detect a low voltage event. Users can turn on
the low detection to monitor VDD periodically to check if it is lower
than the given value. In addition, if LV NMI is enabled, a NMI will
be issued to notify CPU if power voltage drops below the given
value. Also, the voltage detector will generate a system reset if
power supply voltage drops below 2.2V.
HALT
GPLB38B State Diagram
6.7. Speech and Melody
6.12. Key Scan Function
For speech synthesis, the GPLB38B provides several timer
interrupts for a precise sampling frequency. The sound data can
be stored into ROM and be played back. Several algorithms are
recommended for high fidelity and good compression of sound
such as PCM and ADPCM.
GPLB38B supports key scan function. The LCD driver will
generate a key strobe signal in the period of every common.
When PA receives this strobe signal, a wake-up is issued. Then,
program can send the key scan signal through SEG [15:0] to
determine the location of the depressed key.
For melody synthesis, the GPLB38B provides a dual tone mode.
Once in the dual tone mode, users only need to program the tone
frequency for each channel by writing to the timer/counter TM0
and TM1, and set the envelope of each channel. The hardware
will toggle the tone wave automatically.
6.13. Watchdog Timer (WDT)
An on-chip watchdog timer is also available in the GPLB38B.
The WDT is designed to recover the system from abnormal
operation. In some cases, if WDT is not cleared for one second,
the WDT will generate a system reset to restart system. If WDT
is enabled, the WDT should be cleared every 0.5 second to avoid
accidental reset. The WDT can be cleared through software
programming. Note that the WDT only works when 32768Hz
clock is activated.
6.8. LCD Controller/Driver
The GPLB38B contains
a 1024-dot LCD controller/driver.
Programmers are able to define the LCD configuration by setting
up the LCD Control Register. Once the LCD configuration is
completed, the desired pattern can be displayed by filling the LCD
buffer with proper data. The LCD driver can also operate during
sleep by keeping 32768 oscillator running. The LCD driver in
GPLB38B supports 1/16 duty and 1/5 bias.
6.14. Mask Options
6.14.1. 32768 oscillator
1). X’TAL
2). R-oscillator
6.9. LCD Voltage Generation
6.14.2. Watchdog timer
The GPLB38B offers a voltage regulator and a charge-pumping
circuit. The voltage regulator provides a reference voltage for the
1). Enable
2). Disable
charge-pumping circuit to generate VLCD
.
Users can get the
6.14.3. Low voltage reset
desired VLCD by changing the output reference voltage (writing to
register) of the voltage regulator. Enabling the voltage regulator
and charge-pumping circuit gets a stable VLCD that will not be
affected by VDD. The VLCD is adjustable from 2.98V to 5.75V in
1/5 bias.
1). Enable
2). Disable
© Generalplus Technology Inc.
Proprietary & Confidential
7
MAY 10, 2010
Version: 1.3
GPLB38B
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
Symbol
Ratings
DC Supply Voltage
V+
VIN
TA
< 7.0V
Input Voltage Range
Operating Temperature
Storage Temperature
-0.5V to V+ + 0.5V
0℃ to + 60℃
-50℃ to + 150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational
conditions, see AC/DC Electrical Characteristics.
7.2. DC Characteristics(TA=25℃)
Limit
Characteristics
Operating Voltage
Symbol
Unit
Test Condition
Min.
Typ.
Max.
VDD
IOP
2.4
-
3.6
V
For 2-battery
CPU = 2.0MHz @ 3.0V
F
Operating Current
-
-
1.2
30
-
mA
FOSC = 8.0MHz, no load
VDD = 3.0V, 32K X’TAL ON,
LCD ON, no LCD panel
VDD = 3.0V, all off
Halt Current
IHALT
ISTBY
IOH
45
μA
Standby Current
-
-
-20
-40
20
40
-
1.0
μA
mA
mA
mA
mA
V
-
-
-
VDD = 3.0V, VOH = 2.5V
VDD = 3.0V, VOH = 2.0V
VDD = 3.0V, VOL = 0.5V
VDD = 3.0V, VOL = 1.0V
VDD = 3.0V
Audio Output Current (PWM)
-
-
-
Audio Output Current (PWM)
IOL
-
-
Input High Level
VIH
VIL
IOH
IOL
2.0
-
-
0.8
-
Input Low Level
-
V
VDD = 3.0V
Output High Current (I/O)
Output Sink Current (I/O)
LCD Driver Voltage
(VLCD - VSS)
-1.0
1.0
-
mA
mA
VDD = 3.0V, VOH = 2.4V
VDD = 3.0V, VOL = 0.8V
-
-
VLCD
ROSC
FCPU
2.98
-
5.75
V
VDD = 3.0V, 1/5 bias, no load
OSC Resistor
-
-
-
32K
-
Ω
FOSC = 8.0MHz @ 3.0V
FCPU = FOSC/1 @ 2.2~2.4V
FCPU = FOSC/1 @ 2.4~3.6V
-
-
7.0
8.0
MHz
MHz
CPU Clock
Note: VLCD should be higher than VDD to prevent forward biasing the p-n junction of I/O output PMOS.
© Generalplus Technology Inc.
Proprietary & Confidential
8
MAY 10, 2010
Version: 1.3
GPLB38B
8. APPLICATION CIRCUITS
8.1. 1024 Dots LCD Driver, 64 Segments × 16 Commons, 1/5 Bias - (1)
Note*1: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
© Generalplus Technology Inc.
Proprietary & Confidential
9
MAY 10, 2010
Version: 1.3
GPLB38B
8.2. Audio Output Connections - (2)
PWM Audio Output
VDD
PVDD
47μF
0.1μF
PVSS
AUDA
AUDB
© Generalplus Technology Inc.
Proprietary & Confidential
10
MAY 10, 2010
Version: 1.3
GPLB38B
9. PACKAGE/ORDERING INFORMATION
9.1. Ordering Information
Product Number
Package Type
GPLB38B-NnnV-C
Chip form
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
© Generalplus Technology Inc.
Proprietary & Confidential
11
MAY 10, 2010
Version: 1.3
GPLB38B
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
Proprietary & Confidential
12
MAY 10, 2010
Version: 1.3
GPLB38B
11. REVISION HISTORY
Date
Revision #
Description
Page
MAY 10, 2010
AUG.15, 2008
1.3
1.2
Modify 2. FEATURES.
3
4
5
7
9
3
1. Modify 5. SIGNAL DESCRIPTION.
2. Modify 5.1 Pad Assignment.
NOV. 30, 2007
AUG. 07, 2007
1.1
1.0
1. Modify DC characteristics of max. halt mode current.
2. Modify diagram of section 8.1.
1. Modify Features:
(1) Modify max. operating frequency to 8MHz.
(2) Modify “8 wake-up source” to “5 wake-up source”.
(3) Modify “32-level LCD contrast control level” to “27-level LCD contrast control level”.
(4) Modify operation current “600uA @ FOSC=4.0MHz” to “1.2mA @ FOSC=8.0MHz”.
(5) Modify I/Os from “PA[0:7],PB[0:3]” to “PA[0:7], PC[4:7]”.
2. Modify block diagram, “PC[3:0]” to “PC[7:4]”.
3. Modify signal description table: “PIN Number”
4. Modify DC characteristic stable:
3
4
7
(1) Modify operation current “600uA @ FOSC=4.0MHz” to “1.2mA @ FOSC=8.0MHz”.
(2) Modify ROSC resistor from “180K” to “32K”.
5. Add pad diagram.
10
5
JUN. 13, 2007
DEC. 5, 2006
0.2
0.1
1. Remove serial interface description.
2. Remove INT source of UART.
Original
© Generalplus Technology Inc.
Proprietary & Confidential
13
MAY 10, 2010
Version: 1.3
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