GLS27SF020 [GREENLIANT]
Many-Time Programmable Flash;
| 型号： | GLS27SF020 |
| 厂家： | 
Greenliant |
| 描述： | Many-Time Programmable Flash |
| 文件： | 总23页 (文件大小：951K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
GLS27SF512 / 010 / 0205.0V-Read 512Kb / 1Mb / 2Mb (x8) MTP flash memories
Data Sheet
FEATURES:
•
•
•
Organized as 64K x8 / 128K x8 / 256K x8
4.5-5.5V Read Operation
•
Fast Byte-Program Operation
– Byte-Program Time: 20 µs (typical)
– Chip Program Time:
Superior Reliability
1.4 seconds (typical) for GLS27SF512
2.8 seconds (typical) for GLS27SF010
5.6 seconds (typical) for GLS27SF020
– Endurance: At least 1000 Cycles
– Greater than 100 years Data Retention
•
•
Low Power Consumption
•
Electrical Erase Using Programmer
– Active Current: 20 mA (typical)
– Standby Current: 10 µA (typical)
– Does not require UV source
– Chip-Erase Time: 100 ms (typical)
Fast Read Access Time
•
•
•
TTL I/O Compatibility
– 70 ns
JEDEC Standard Byte-wide EPROM Pinouts
Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 32-pin PDIP for GLS27SF010/020
•
All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The GLS27SF512/010/020 are a 64K x8 / 128K x8 / 256K
x8 CMOS, Many-Time Programmable (MTP) low cost
flash, manufactured with high performance SuperFlash
technology. The split-gate cell design and thick oxide tun-
neling injector attain better reliability and manufacturability
compared with alternate approaches. These MTP devices
can be electrically erased and programmed at least 1000
times using an external programmer with a 12V power sup-
ply. They have to be erased prior to programming. These
devices conform to JEDEC standard pinouts for byte-wide
memories.
To meet surface mount and conventional through hole
requirements, the GLS27SF512 are offered in 32-lead
PLCC, 32-lead TSOP, and 28-pin PDIP packages. The
GLS27SF010/020 are offered in 32-pin PDIP, 32-lead
PLCC, and 32-lead TSOP packages. See Figures 3, 4,
and 5 for pin assignments.
Device Operation
The GLS27SF512/010/020 are a low cost flash solution
that can be used to replace existing UV-EPROM, OTP,
and mask ROM sockets. These devices are functionally
(read and program) and pin compatible with industry
standard EPROM products. In addition to EPROM func-
tionality, these devices also support electrical Erase
operation via an external programmer. They do not
require a UV source to erase, and therefore the pack-
ages do not have a window.
Featuring
high-performance
Byte-Program,
the
GLS27SF512/010/020 provide a Byte-Program time of 20
µs. Designed, manufactured, and tested for a wide spec-
trum of applications, these devices are offered with an
endurance of at least 1000 cycles. Data retention is rated at
greater than 100 years.
The GLS27SF512/010/020 are suited for applications that
require infrequent writes and low power nonvolatile stor-
age. These devices will improve flexibility, efficiency, and
performance while matching the low cost in nonvolatile
applications that currently use UV-EPROMs, OTPs, and
mask ROMs.
Read
The Read operation of the GLS27SF512/010/020 is con-
trolled by CE# and OE#. Both CE# and OE# have to be
low for the system to obtain data from the outputs. Once
the address is stable, the address access time is equal to
the delay from CE# to output (TCE). Data is available at the
output after a delay of TOE from the falling edge of OE#,
assuming that CE# pin has been low and the addresses
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
www.greenliant.com
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
have been stable for at least TCE-TOE. When the CE# pin is
high, the chip is deselected and a typical standby current of
10 µA is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when either CE# or OE# is high.
Product Identification Mode
The Product Identification mode identifies the devices as
the GLS27SF512, GLS27SF010 and GLS27SF020 and
manufacturer as Greenliant. This mode may be accessed
by the hardware method. To activate this mode for
GLS27SF010/020, the programming equipment must force
VH (11.4-12V) on address A9 with VPP pin at VDD (4.5-5.5V)
or VSS. To activate this mode for GLS27SF512, the pro-
gramming equipment must force VH (11.4-12V) on address
A9 with OE#/VPP pin at VIL. Two identifier bytes may then
be sequenced from the device outputs by toggling address
line A0. For details, see Tables 3 and 4 for hardware opera-
tion.
Byte-Program Operation
The GLS27SF512/010/020 are programmed by using an
external programmer. The programming mode for
GLS27SF010/020 is activated by asserting 11.4-12V on
VPP pin, VDD = 4.5-5.5V, VIL on CE# pin, and VIH on OE#
pin. The programming mode for GLS27SF512 is activated
by asserting 11.4-12V on OE#/VPP pin, VDD = 4.5-5.5V,
and VIL on CE# pin. These devices are programmed byte-
by-byte with the desired data at the desired address using
a single pulse (CE# pin low for GLS27SF512 and PGM#
pin low for GLS27SF010/020) of 20 µs. Using the MTP
programming algorithm, the Byte-Programming process
continues byte-by-byte until the entire chip has been pro-
grammed.
TABLE 1: Product Identification
Address
Data
Manufacturer’s ID
Device ID
0000H
BFH
GLS27SF512
GLS27SF010
GLS27SF020
0001H
0001H
0001H
A4H
A5H
A6H
Chip-Erase Operation
T1.2 1152
The only way to change a data from a “0” to “1” is by electri-
cal erase that changes every bit in the device to “1”. Unlike
traditional EPROMs, which use UV light to do the Chip-
Erase, the GLS27SF512/010/020 uses an electrical Chip-
Erase operation. This saves a significant amount of time
(about 30 minutes for each Erase operation). The entire
chip can be erased in a single pulse of 100 ms (CE# pin
low for GLS27SF512 and PGM# pin for GLS27SF010/
020). In order to activate the Erase mode for
GLS27SF010/020, the 11.4-12V is applied to VPP and A9
pins, VDD = 4.5-5.5V, VIL on CE# pin, and VIH on OE# pin.
In order to activate Erase mode for GLS27SF512, the 11.4-
12V is applied to OE#/VPP and A9 pins, VDD = 4.5-5.5V,
and VIL on CE# pin. All other address and data pins are
“don’t care”. The falling edge of CE# (PGM# for
GLS27SF010/020) will start the Chip-Erase operation.
Once the chip has been erased, all bytes must be verified
for FFH. Refer to Figures 13 and 14 for the flowcharts.
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
2
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
SuperFlash
Memory
X-Decoder
A
- A
0
15
Address Buffer
Y-Decoder
I/O Buffers
CE#
OE#/V
Control Logic
PP
A
9
DQ - DQ
7
0
1152 B2.1
FIGURE 1: Functional Block Diagram - GLS27SF512
SuperFlash
Memory
X-Decoder
A
- A
0
Address Buffer
MS
Y-Decoder
I/O Buffers
CE#
OE#
Control Logic
A
9
V
PP
DQ - DQ
7
0
PGM#
A
= A for GLS27SF020, A for GLS27SF010
MS
17
16
1152 B3.2
FIGURE 2: Functional Block Diagram - GLS27SF010/020
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
3
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
GLS27SF020
GLS27SF010
GLS27SF512
GLS27SF010/020 GLS27SF512
GLS27SF512
GLS27SF010/020
4
3
2
1
32 31 30
5
29
28
27
26
25
24
23
22
21
A7
A6
A6
A5
A8
A14
A13
A8
6
A9
7
A5
A4
A11
NC
8
A4
A3
A9
32-lead PLCC
Top View
9
A3
A2
OE#/V
PP
A11
OE#
A10
CE#
DQ7
10
11
12
13
A2
A1
A10
A1
A0
CE#
DQ7
DQ6
A0
NC
DQ0
DQ0
14 15 16 17 18 19 20
GLS27SF512
GLS27SF010/020
1152 32-plcc P1.5
FIGURE 3: Pin Assignments for 32-lead PLCC
GLS27SF020 GLS27SF010 GLS27SF512
GLS27SF512 GLS27SF010 GLS27SF020
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#/V
OE#
OE#
PP
2
A10
A8
3
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A13
A14
NC
NC
4
5
A17
NC
6
St an d ard Pi n o u t
To p Vi ew
PGM#
PGM#
7
V
8
DD
NC
V
V
9
V
PP
PP
SS
Die Up
A16
A16
NC
A15
A12
A7
10
11
12
13
14
15
16
DQ2
DQ1
DQ0
A0
A6
A1
A5
A2
A4
A3
1152 32-tsop P2.3
FIGURE 4: Pin Assignments for 32-lead TSOP (8mm x 14mm)
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
4
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
GLS27SF020 GLS27SF010
GLS27SF010 GLS27SF020
GLS27SF512
GLS27SF512
V
V
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
V
PP
PP
DD
DD
PGM#
A17
A14
A13
A8
A16
A15
A12
A7
A16
A15
A12
A7
2
PGM#
NC
A15
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
3
2
A14
A13
A8
4
A14
A13
A8
3
5
A6
4
32-pin
PDIP
A6
A6
6
A5
5
A9
A5
A5
7
A9
A9
28-pin
PDIP
A4
6
A11
OE#/V
A4
A4
8
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
To p Vi ew
A3
7
PP
A3
A3
9
A2
8
A10
CE#
To p View
A2
A2
10
11
12
13
14
15
16
A1
9
A1
A1
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
A0
A0
DQ0
DQ1
DQ2
DQ0
DQ1
DQ2
DQ0
DQ1
DQ2
V
SS
V
SS
V
SS
1152 28-pdip P3.2
1152 32-pdip P4.2
FIGURE 5: Pin Assignments for 28-pin and 32-pin PDIP
TABLE 2: Pin Description
Symbol
AMS1-A0
DQ7-DQ0
Pin Name
Functions
Address Inputs
Data Input/output
To provide memory addresses
To output data during Read cycles and receive input data during Program cycles
The outputs are in tri-state when OE# or CE# is high.
CE#
Chip Enable
To activate the device when CE# is low
OE#
Output Enable
For GLS27SF010/020, to gate the data output buffers during Read operation
OE#/VPP
Output Enable/VPP For GLS27SF512, to gate the data output buffers during Read operation and high voltage
pin during Chip-Erase and programming operation
VPP
Power Supply for
Program or Erase
For GLS27SF010/020, high voltage pin during Chip-Erase and programming operation
11.4-12V
VDD
VSS
NC
Power Supply
Ground
To provide 5.0V supply (4.5-5.5V)
No Connection
Unconnected pins.
T2.4 1152
1. AMS = Most significant address
AMS = A15 for GLS27SF512, A16 for GLS27SF010, and A17 for GLS27SF020
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
5
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
TABLE 3: Operation Modes Selection for GLS27SF512
Mode
CE#
VIL
VIL
VIL
VIH
VIL
VIH
VIL
OE#/VPP
VIL
A9 DQ
Address
Read
AIN DOUT
X1 High Z
AIN DIN
AIN
X
Output Disable
Program
VIH
VPPH
X
AIN
X
Standby
X
High Z
VH High Z
High Z
Chip-Erase
Program/Erase Inhibit
Product Identification
VPPH
VPPH
VIL
X
X
X
VH Manufacturer’s ID (BFH)
Device ID (A4H)
A15-A1=VIL, A0=VIL
A15-A1=VIL, A0=VIH
T3.2 1152
1. X can be VIL or VIH, but no other value.
Note: VPPH = 11.4-12V, VH = 11.4-12V
TABLE 4: Operation Modes Selection for GLS27SF010/020
Mode
CE# OE# PGM# A9 VPP
DQ
AIN VDD or VSS DOUT
VDD or VSS High Z
AIN VPPH DIN
VDD or VSS High Z
Address
Read
VIL
VIL
VIL
VIH
VIL
VIH
VIL
VIL
VIH
VIH
X
X1
AIN
AIN
AIN
X
Output Disable
Program
X
X
VIL
X
Standby
X
Chip-Erase
Program/Erase Inhibit
Product Identification
VIH
X
VIL
X
VH VPPH
VPPH
High Z
High Z
X
X
X
VIL
X
VH VDD or VSS Manufacturer’s ID (BFH)
Device ID2
AMS3 - A1=VIL, A0=VIL
AMS3 - A1=VIL, A0=VIH
T4.2 1152
1. X can be VIL or VIH, but no other value.
2. Device ID = A5H for GLS27SF010 and A6H for GLS27SF020
3. AMS = Most significant address
A
MS = A16 for GLS27SF010 and A17 for GLS27SF020
Note: VPPH = 11.4-12V, VH = 11.4-12V
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
6
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Voltage on A9 and VPP Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Through Hole Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . 10 ns
Output Load . . . . . . . . . . . . . . . . . CL = 30 pF for 70 ns
See Figures 11 and 12
Range
Ambient Temp
0°C to +70°C
VDD
VPP
Commercial
4.5-5.5V
11.4-12V
TABLE 5: Read Mode DC Operating Characteristics for GLS27SF512/010/020
V
DD = 4.5-5.5V, VPP=VDD or VSS (TA = 0°C to +70°C (Commercial))
Limits
Symbol Parameter
Min
Max
Units
Test Conditions
IDD
VDD Read Current
Address input=VILT/VIHT at f=1/TRC Min
VDD=VDD Max
30
mA
CE#=OE#=VIL, all I/Os open
IPPR
VPP Read Current
Address input=VILT/VIHT at f=1/TRC Min
VDD=VDD Max, VPP=VDD
100
3
µA
CE#=OE#=VIL, all I/Os open
CE#=VIH, VDD=VDD Max
ISB1
ISB2
Standby VDD Current
(TTL input)
mA
Standby VDD Current
(CMOS input)
100
µA
CE#=VDD-0.3
VDD=VDD Max
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
10
µA
µA
V
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILO
VIL
VIH
VOL
VOH
IH
0.8
Input High Voltage
2.0
2.4
VDD+0.5
0.2
V
VDD=VDD Max
Output Low Voltage
Output High Voltage
Supervoltage Current for A9
V
IOL=2.1 mA, VDD=VDD Min
IOH=-400 µA, VDD=VDD Min
CE#=OE#=VIL, A9=VH Max
V
200
µA
T5.6 1152
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
7
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
TABLE 6: Program/Erase DC Operating Characteristics for GLS27SF512
V
DD=4.5-5.5V, VPP=VPPH (TA=25°C±5°C)
Limits
Symbol Parameter
Min Max Units Test Conditions
IDD
IPP
ILI
VDD Erase or Program Current
30
mA CE#=VIL, OE#/VPP=11.4-12V, VDD=VDD Max
mA CE#=VIL, OE#/VPP=11.4-12V, VDD=VDD Max
VPP Erase or Program Current
Input Leakage Current
3
1
µA
µA
V
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
CE#=OE#/VPP=VIL,
ILO
VH
IH
Output Leakage Current
Supervoltage for A9
10
11.4 12
200
Supervoltage Current for A9
High Voltage for OE#/VPP Pin
µA
V
CE#=OE#/VPP=VIL, A9=VH Max
VPPH
11.4 12
T6.5 1152
TABLE 7: Program/Erase DC Operating Characteristics for GLS27SF010/020
DD=4.5-5.5V, VPP=VPPH (TA=25°C±5°C)
V
Limits
Symbol Parameter
Min Max Units Test Conditions
IDD
VDD Erase or Program Current
30
mA
CE#=PGM#=VIL, OE#=VIH, VPP=11.4-12V,
DD=VDD Max
CE#=PGM#=VIL, OE#=VIH, VPP=11.4-12V,
DD=VDD Max
V
IPP
VPP Erase or Program Current
3
mA
V
ILI
Input Leakage Current
Output Leakage Current
Supervoltage for A9
1
µA
µA
V
VIN =GND to VDD, VDD=VDD Max
VOUT =GND to VDD, VDD=VDD Max
CE#=OE#=VIL,
ILO
VH
IH
10
12
11.4
11.4
Supervoltage Current for A9
High Voltage for VPP Pin
200
12
µA
V
CE#=OE#=VIL, A9=VH Max
VPPH
T7.5 1152
TABLE 8: Recommended System Power-up Timings
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
1
TPU-WRITE
100
µs
T8.1 1152
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: Capacitance (TA = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
12 pF
6 pF
1
CIN
VIN = 0V
T9.0 1152
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: Reliability Characteristics
Symbol
Parameter
Minimum Specification
Units
Cycles
Years
Test Method
1
NEND
Endurance
1000
100
JEDEC Standard A117
JEDEC Standard A103
1
TDR
Data Retention
T10.3 1152
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
8
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
AC CHARACTERISTICS
TABLE 11: Read Cycle Timing Parameters VDD = 4.5-5.5V (TA = 0°C to +70°C (Commercial))
Symbol Parameter
Min
Max
Units
ns
TRC
TCE
TAA
Read Cycle Time
70
Chip Enable Access Time
Address Access Time
70
70
35
ns
ns
TOE
TCLZ
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
1
0
0
ns
TOLZ
TCHZ
ns
1
1
25
25
ns
TOHZ
ns
1
TOH
0
ns
T11.3 1152
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: Program/Erase Cycle Timing Parameters for GLS27SF512
Symbol Parameter
Min
1
Max
Units
µs
TAS
Address Setup Time
TAH
Address Hold Time
1
µs
TPRT
TVPS
TVPH
TPW
TEW
TDS
OE#/VPP Pulse Rise Time
OE#/VPP Setup Time
50
1
ns
µs
OE#/VPP Hold Time
1
µs
CE# Program Pulse Width
CE# Erase Pulse Width
Data Setup Time
20
100
1
30
µs
500
ms
µs
TDH
TVR
Data Hold Time
1
µs
OE#/VPP and A9 Recovery Time
A9 Rise Time to 12V during Erase
A9 Setup Time during Erase
A9 Hold Time during Erase
1
µs
TART
TA9S
TA9H
50
1
ns
µs
1
µs
T12.0 1152
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
9
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
TABLE 13: Program/Erase Cycle Timing Parameters for GLS27SF010/020
Symbol Parameter Min
Max
Units
µs
µs
µs
µs
ns
µs
µs
µs
ms
µs
µs
µs
ns
TCES
TCEH
TAS
CE# Setup Time
CE# Hold Time
Address Setup Time
Address Hold Time
1
1
1
TAH
1
TPRT
TVPS
TVPH
TPW
TEW
TDS
VPP Pulse Rise Time
VPP Setup Time
VPP Hold Time
PGM# Program Pulse Width
PGM# Erase Pulse Width
Data Setup Time
50
1
1
20
100
1
30
500
TDH
Data Hold Time
1
TVR
A9 Recovery Time for Erase
A9 Rise Time to 12V during Erase
A9 Setup Time during Erase
A9 Hold Time during Erase
1
50
1
TART
TA9S
TA9H
µs
µs
1
T13.0 1152
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
10
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
T
T
AA
RC
ADDRESS
CE#
T
CE
T
OE
OE#
T
OHZ
T
T
OLZ
OH
T
CHZ
HIGH-Z
DATA VALID
DATA VALID
DQ
7-0
T
CLZ
1152 F03.0
FIGURE 6: Read Cycle Timing Diagram for GLS27SF512/010/020
ADDRESS
(EXCEPT A )
9
CE#
T
EW
DQ
7-0
T
T
VPH
VR
T
VPS
V
PPH
V
OE#/V
DD
PP
V
SS
T
PRT
T
VR
T
A9S
V
PPH
V
A
9
IH
V
IL
T
T
ART
A9H
1152 F04b.1
FIGURE 7: Chip-Erase Timing Diagram for GLS27SF512
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
11
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
ADDRESS
(EXCEPT A )
9
T
CEH
CE#
OE#
V
IH
DQ
7-0
T
T
VPS
VPH
V
PPH
V
V
V
PP
DD
SS
T
PRT
T
VR
T
A9S
V
PPH
A
9
V
IH
V
IL
T
T
T
ART
A9H
EW
PGM#
T
1152 F04c.1
CES
FIGURE 8: Chip-Erase Timing Diagram for GLS27SF010/020
ADDRESS VALID
ADDRESS
CE#
T
T
AH
AS
T
PW
T
T
DS
DH
HIGH-Z
DQ
DATA VALID
7-0
T
T
VR
VPS
V
PPH
OE#/V
V
DD
PP
V
SS
T
T
VPH
PRT
1152 F05b.2
FIGURE 9: Byte-Program Timing Diagram for GLS27SF512
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
12
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
ADDRESS
CE#
ADDRESS VALID
T
T
AH
AS
T
CEH
OE#
V
IH
T
T
DH
DS
HIGH-Z
DQ
7-0
DATA VALID
T
VPS
V
PPH
V
V
DD
PP
V
SS
T
T
PW
T
VPH
PRT
PGM#
1152 F05c.1
T
CES
FIGURE 10: Byte-Program Timing Diagram for GLS27SF010/020
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
13
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
V
IHT
V
V
HT
HT
INPUT
REFERENCE POINTS
OUTPUT
V
V
LT
LT
V
ILT
1152 F06.0
AC test inputs are driven at VIHT (2.4 V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for
inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% 90%) are <10 ns.
Note: VHT - VHIGHTest
V
V
V
LT - VLOW Test
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
FIGURE 11: AC Input/Output Reference Waveforms
V
DD
TO TESTER
R
L HIGH
TO DUT
C
L
R
L LOW
1152 F07.1
FIGURE 12: A Test Load Example
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
14
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
Start
A
= V
H
9
OE#/V
= V
PPH
PP
Erase 100ms pulse
(CE# = V
)
IL
OE#/V
= V
= V or V
IL
or V
SS
IH
PP
DD
A
9
Wait for OE#/V
and
PP
Recovery Time
A
9
Read Device
(CE# = OE# = V
)
IL
No
Compare All
bytes to FFH
Yes
Device Passed
Device Failed
1152 F08b.2
FIGURE 13: Chip-Erase Algorithm for GLS27SF512
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
15
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
Start
A
= V , V
= V
PP
PPH
9
H
CE# = V , OE# = V
IL
IH
Erase 100ms pulse
(PGM# = V
)
IL
PGM# = V
IH
A
= V or V
IL
9
IH
Wait A Recovery Time
9
Read Device
No
Compare all
bytes to FFH
Yes
Device Passed
Device Failed
1152 F08c.1
FIGURE 14: Chip-Erase Algorithm for GLS27SF010/020
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
16
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
Start
Erase*
OE#/V
= V
PPH
PP
Address = First Location
Program 20µs pulse
(CE# = V )
IL
Increment Address
OE#/V
= V
or V
DD SS
Last Address?
PP
No
Yes
Wait for OE#/V
PP
RecoveryTime
Read Device
(CE# = OE# = V
)
IL
No
Compare all bytes
to original data
Yes
Device Passed
Device Failed
1152 F09b.2
* See Figure 13
FIGURE 15: Byte-Program Algorithm for GLS27SF512
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
17
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
Start
Erase*
V
= V
PPH
PP
Address = First Location
CE# = V , OE# = V
IL IH
Program 20µs pulse
(PGM# = V
)
IL
Increment Address
Last Address?
No
Yes
Read Device
No
Compare all bytes
to original data
Yes
Device Passed
Device Failed
1152 F09c.1
* See Figure 14
FIGURE 16: Byte-Program Algorithm for GLS27SF010/020
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
18
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
PRODUCT ORDERING INFORMATION
GLS 27 SF
020
-
70
-
3C
-
NH
E
XX XX XXXX - XXX
-
XX - XXX
X
Environmental Attribute
E1 = non-Pb
Package Modifier
H = 32 pins or leads
Package Type
N = PLCC
P = PDIP
W = TSOP (type 1, die up, 8mm x 14mm)
Temperature Range
C = Commercial = 0°C to +70°C
Minimum Endurance
3 = 1,000 cycles
Read Access Speed
70 = 70 ns
Device Density - x8 Organization
020 = 2 Mbit
010 = 1 Mbit
512 = 512 Kbit
Voltage Range
S = 4.5-5.5V
Product Series
27 = Many-Time Programmable Flash
OTP/EPROM replacement with
EPROM pinout
1. Environmental suffix “E” denotes non-Pb solder.
Greenliant non-Pb solder devices are “RoHS Compli-
ant”.
Valid combinations for GLS27SF512
GLS27SF512-70-3C-NHE GLS27SF512-70-3C-WHE
Valid combinations for GLS27SF010
GLS27SF010-70-3C-NHE GLS27SF010-70-3C-WHE GLS27SF010-70-3C-PHE
Valid combinations for GLS27SF020
GLS27SF020-70-3C-NHE GLS27SF020-70-3C-WHE GLS27SF020-70-3C-PHE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your Greenliant sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
19
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
SIDE VIEW
BOTTOM VIEW
.495
.485
.112
.106
.453
.447
Optional
Pin #1
Identifier
.048
.042
.029
.023
.040
.030
.020 R.
MAX.
x 30˚
R.
2
1
32
.042
.048
.021
.013
.400
BSC
.530
.490
.595 .553
.585 .547
.032
.026
.050
BSC
.015 Min.
.095
.075
.050
BSC
.032
.026
.140
.125
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
4. Coplanarity: 4 mils.
32-plcc-NH-3
FIGURE 17: 32-lead Plastic Lead Chip Carrier (PLCC)
Greenliant Package Code: NH
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
20
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
1.05
0.95
Pin # 1 Identifier
0.50
BSC
8.10
7.90
0.27
0.17
0.15
0.05
12.50
12.30
DETAIL
1.20
max.
0.70
0.50
14.20
13.80
0˚- 5˚
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
32-tsop-WH-7
1mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
FIGURE 18: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm
Greenliant Package Code: WH
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
21
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
32
C
L
1
Pin #1 Identifier
.625
.600
.550
.530
1.655
1.645
.075
.065
7˚
4 PLCS.
Base
Plane
.200
.170
Seating
Plane
.050
.015
0˚
15˚
.012
.008
.150
.120
.100 BSC
.022
.016
.080
.070
.600 BSC
.065
.045
Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32-pdip-PH-3
FIGURE 19: 32-pin Plastic Dual In-line Pins (PDIP)
Greenliant Package Code: PH
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
22
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
TABLE 14: Revision History
Number
02
Description
Date
Feb 2002
Apr 2002
Jul 2002
Sep 2003
Nov 2003
•
•
•
•
•
•
•
•
•
•
•
2002 Data Book
03
Document Control Release (SST Internal): No technical changes
Corrected IH Supervoltage Current for A9 from 100 µA to 200 µA in Tables 5, 6, and 7
Corrected the Test Conditions for IDD and IPPR in Table 5 on page 7
Corrected the Max value for IPP from 1 mA to 3 mA (See Tables 6 and 7)
Added MPNs for non-PB packages (See page 19)
04
05
06
07
Nov 2003
2004 Data Book
Corrected caption for Figure 7 from “Read Cycle” to “Chip-Erase”
Removed 256 Kbit parts - refer to EOL Product Data Sheet S71152(02)
Removed all 90 ns parts - refer to EOL Product Data Sheet S71152(03)
08
09
Apr 2004
Mar 2005
Added RoHS compliance information on page 1 and in the “Product Ordering Infor-
mation” on page 19
•
Added the solder reflow temperature to the “Absolute Maximum Stress Ratings” on
page 7.
10
11
12
May 2005
Sep 2005
Sep 2008
•
•
•
•
•
Removed obsolete Latch-up parameter from Table 10 on page 8
Corrected VPP voltage from 11.4-12.6V to 11.4-12V
Removed leaded parts. See S71152(04)
End-of-Life PG package and PG valid combination. See S71152(04)
Transferred from SST to Greenliant
13
May 2010
© 2010 Greenliant Systems, Ltd. All rights reserved.
Greenliant, the Greenliant logo and NANDrive are trademarks of Greenliant Systems, Ltd.
All trademarks and registered trademarks are the property of their respective owners.
These specifications are subject to change without notice.
MTP is a trademark and SuperFlash is a registered trademark of Silicon Storage Technology, Inc., a wholly owned subsidiary of
Microchip Technology Inc.
©2010 Greenliant Systems, Ltd.
S71152-13-000
05/10
23
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