HSD32M32M4V-F13 [HANBIT]
Synchronous DRAM Module 128Mbyte ( 32M x 32-Bit ) 72-Pin SIMM based on 32Mx8, 4Banks, 8K Ref., 3.3V; 同步DRAM模组128Mbyte （ 32M ×32位）， 72引脚SIMM基于32Mx8 ， 4Banks ， 8K参考， 3.3V
| 型号： | HSD32M32M4V-F13 |
| 厂家： | 
HANBIT ELECTRONICS CO.,LTD |
| 描述： | Synchronous DRAM Module 128Mbyte ( 32M x 32-Bit ) 72-Pin SIMM based on 32Mx8, 4Banks, 8K Ref., 3.3V |
| 文件： | 总10页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HANBit
HSD32M32M4V
Synchronous DRAM Module 128Mbyte ( 32M x 32-Bit ) 72-Pin SIMM based on
32Mx8, 4Banks, 8K Ref., 3.3V
Part No. HSD32M32M4V
GENERAL DESCRIPTION
The HSD32M32M4V is a 32M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists
of four CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II packages mounted on a 72-pin, FR-4-printed circuit
board. Two 0.01uF decoupling capacitor is mounted on the printed circuit board in parallel for each SDRAM. The
HSD32M32M4V is a SIMM designed. Synchronous design allows precise cycle control with the use of system clock. I/O
transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high performance memory system applications All module components
may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
PIN ASSIGNMENT
FEATURES
• Part Identification
PIN SYMBOL PIN
SYMBOL
DQ14
DQ15
DQM1
NC
PIN SYMBOL
HSD32M32M4V-13/F13 :133MHz ( CL=3)
HSD32M32M4V-12/F12: 125MHz (CL=3)
HSD32M32M4V-10/F10: 100MHz (CL=2)
HSD32M32M4V-10L/F10L: 100MHz
F means Auto & Self refresh with Low – Power (3.3V)
1
2
Vss
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM0
Vcc
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
A5
A6
3
A7
4
A8
5
/WE
A9
6
/CAS
Vcc
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM3
NC
7
• Burst mode operation
8
/RAS
/CS0
NC
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge
of the system clock
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
NC
CLK0
CKE0
Vss
A0
A1
A2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM2
Vcc
A3
A10/AP
A11
A4
• FR4-PCB design
Vss
A12
• 72-Pin SIMM Package
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
• The used device is 8Mx8bitx4Bank SRAM
• Pin assignment is compatible with
- HSD8M32M4V
BA0
BA1
NC
- HSD16M32M4V
NC
Vss
72-PIN SIMM TOP VIEW
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REV.1.0 (August.2002)
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HANBit Electronics Co.,Ltd
HANBit
HSD32M32M4V
FUNCTIONAL BLOCK DIAGRAM
DQ0-31
CKE0
/CAS
CLK0
CKE
CAS
RAS
CE
CLK
DQ0-7
DQM0
BA0-1
U1
DQM0
/RAS
/CE1
WE
A0-A12
CLK0
CKE
CAS
RAS
CE
CLK
DQ8-15
DQM0
BA0-1
U2
DQM1
WE
A0-A12
CKE
CAS
RAS
CE
CLK
DQ16-23
DQM0
CLK0
U3
DQM2
WE
A0-A12
BA0-1
CKE
CAS
RAS
CE
CLK
DQ24-31
DQM0
CLK0
U4
DQM3
WE
A0-A12
BA0-1
/WE
A0 - A12
BA0-1
Vcc
Vss
Two 0.01uF Capacitor
per each SDRAM
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REV.1.0 (August.2002)
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HANBit Electronics Co.,Ltd
HANBit
HSD32M32M4V
PIN FUNCTION DESCRIPTION
Pin
Name
System clock
Chip enable
Input Function
CLK
/CE
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
A0 ~ A12
BA0 ~ BA1
/RAS
Address
Bank select address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
/CAS
Column
address Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
strobe
/WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 3
Data
input/output Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
mask
DQ0 ~ 31
VDD/VSS
Data input/output
Power
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
SYMBOL
VIN ,OUT
Vcc
RATING
-1V to 4.6V
-1V to 4.6V
4W
PD
o
o
Storage Temperature
TSTG
-55 C to 150 C
Short Circuit Output Current
IOS
50mA
Notes :
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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REV.1.0 (August.2002)
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HANBit Electronics Co.,Ltd
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HSD32M32M4V
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) )
PARAMETER
Supply Voltage
SYMBOL
Vcc
VIH
MIN
3.0
2.0
-0.3
2.4
-
TYP.
MAX
3.6
UNIT
V
NOTE
3.3
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
3.0
Vcc+0.3
0.8
V
1
VIL
0
-
V
2
VOH
VOL
-
V
IOH = -2mA
IOL = 2mA
3
-
0.4
V
Input leakage current
I LI
-10
-
10
uA
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
DESCRIPTION
Address(A0~A12, BA0~BA1)
/RAS, /CAS, /WE
SYMBOL
CADD
C IN
MIN
15
15
15
7.5
15
6.5
7
MAX
25
UNITS
pF
pF
pF
pF
pF
pF
pF
25
CKE(CKE0)
CCKE
CCLK
25
Clock (CLK0)
9
/CE (/CE1)
CCS
25
DQM (DQM0 ~ DQM3)
DQ (DQ0 ~ DQ32)
CDQM
COUT
7.5
8.5
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
TEST
VERSION
PARAMETER
SYMBOL
UNIT NOTE
CONDITION
Burst length = 1
-A
-8
-H
-L
Operating current
ICC1
tRC ³ tRC(min)
IO = 0mA
480 480
440
440
mA
1
(One bank active)
CKE £ VIL(max)
tCC=10ns
ICC2
P
8
8
mA
mA
Precharge standby current in
power-down mode
CKE & CLK £ VIL(max)
tCC=¥
ICC2PS
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HANBit Electronics Co.,Ltd
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HSD32M32M4V
CKE ³ VIH(min)
CS* ³ VIH(min), tCC=10ns
Input signals are changed
one time during 20ns
CKE ³ VIH(min)
ICC2
N
64
Precharge standby current in
non power-down mode
mA
mA
mA
ICC2NS
CLK £ VIL(max), tCC=¥
Input signals are stable
CKE £ VIL(max), tCC=10ns
CKE&CLK £ VIL(max)
tCC=¥
56
ICC3
P
24
24
Active standby current in
power-down mode
ICC3PS
CKE³ VIH(min),
CS*³ VIH(min), tCC=10ns
Input signals are changed
one time during 20ns
CKE³ VIH(min)
ICC3
N
120
100
Active standby current in
non power-down mode
(One bank active)
ICC3NS
CLK £VIL(max), tCC=¥
Input signals are stable
IO = 0 mA
Operating current
(Burst mode)
Page burst
ICC4
560
840
560
840
460
800
460
800
mA
1
4Banks Activated
tCCD = 2CLKs
Refresh current
ICC5
ICC6
tRC ³ tRC(min)
mA
mA
mA
2
G
F
20
8
Self refresh current
CKE £ 0.2V
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
AC OPERATING TEST CONDITIONS
(vcc = 3.3V ± 0.3V, TA = 0 to 70°C)
PARAMETER
Value
2.4/0.4
1.4
UNIT
AC Input levels (Vih/Vil)
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
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REV.1.0 (August.2002)
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HANBit Electronics Co.,Ltd
HANBit
HSD32M32M4V
+3.3V
V =1.4V
tt
1200W
50pF*
50W
DOUT
DOUT
870W
Z0=50W
50pF
V
V
(DC) = 2.4V, I = -2mA
OH
OH
(DC) = 0.4V, I = 2mA
OL
OL
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER
SYMBOL
UNIT
NOTE
-A
15
20
20
45
-8
-H
20
20
20
50
-L
20
20
20
50
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRP(min)
16
20
20
48
ns
ns
ns
ns
1
1
1
1
Row precharge time
tRP(min)
tRAS(min)
tRAS(max)
Row active time
100
2
ns
Row cycle time
tRC(min)
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
65
68
70
70
ns
CLK
-
1
2.5
5
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
2 CLK + 20 ns
1
1
1
2
CLK
CLK
CLK
2
2
Col. address to col. address delay
3
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
-
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
(Recommand : tRDL=2CLK and tDAL=2CLK & 20ns.)
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REV.1.0 (August.2002)
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HANBit Electronics Co.,Ltd
HANBit
HSD32M32M4V
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
-A
MAX MIN
-8
-H
-L
PARAMETER
SYMBOL
UNIT
NOTE
MIN
MAX MIN
MAX MIN
MAX
CLK cycle time CAS
7.5
8
-
10
1000
10
12
latency=3
tCC
1000
1000
1000
ns
ns
ns
1
CAS
-
10
latency=2
CAS
CLK to valid
output delay
5.4
-
6
-
6
6
6
7
latency=3
CAS
tSAC
1,2
latency=2
CAS
Output data
hold time
2.7
-
3
-
3
3
3
3
latency=3
CAS
tOH
2
latency=2
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
0.8
1
3
3
2
1
1
3
3
2
1
1
3
3
2
1
1
ns
ns
ns
ns
ns
3
3
3
3
3
tSS
tSH
tSLZ
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
CAS
5.4
-
6
-
6
6
6
7
ns
ns
2
latency=3
CAS
tSHZ
latency=2
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to
the parameter.
SIMPLIFIED TRUTH TABLE
/R
A
S
/C
A
S
D
Q
M
CKE
CKE
n
/C
S
/W
E
BA
0,1
A10/
AP
A11,A12,
A9~A0
n-1
COMMAND
NOTE
Register
Refresh
Mode register set
Auto refresh
H
H
X
H
L
L
L
L
L
L
X
OP code
X
1,2
3
L
L
H
X
Entry
3
Self
refres
h
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
X
X
X
X
3
Bank active & row addr.
H
V
Row address
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HSD32M32M4V
Auto
precharge
precharge
Read &
column
address
L
Column
Address
(A0 ~ A9)
4
disable
Auto
H
H
X
X
L
L
H
H
L
L
H
L
X
X
V
V
H
4,5
disable
Column
Address
(A0 ~ A9)
Auto
precharge
precharge
Write &
column
address
L
4
disable
Auto
H
4,5
6
disable
Burst Stop
H
H
X
X
L
L
L
L
H
H
L
L
X
X
X
Precharg Bank selection
V
X
L
X
e
All banks
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock suspend or
active power down
X
X
X
H
L
Entry
H
Precharge power
down mode
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
X
7
H
L
X
H
X
X
H
No operation command
H
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
TIMING DIAGRAMS
Please refer to timing diagram chart (II)
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REV.1.0 (August.2002)
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HANBit Electronics Co.,Ltd
HANBit
HSD32M32M4V
PACKAGING INFORMATION
Unit : mm
107.95 ± 20
17.8 ± 0.2
3.38
3.2
10.16
6.35
2.03
44.45
1.27
1.00
95.25
6.35
6.35
2.54
MIN
0.25 MAX
1.27±0.08
Gold: 1.04±0.10
1.27
Solder: 0.914
±0.10
(Solder & Gold Plating)
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REV.1.0 (August.2002)
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HANBit Electronics Co.,Ltd
HANBit
HSD32M32M4V
ODERING INFORMATION
Part Number
Density
Org.
Package
Ref.
Vcc
Feature
MAX.frq
72 Pin
SIMM
72 Pin
SIMM
72 Pin
SMM
133MHz
(CL=3)
HSD32M32M4V-13
HSD32M32M4V-F13
HSD32M32M4V-12
HSD32M32M4V-F12
HSD32M32M4V-10
HSD32M32M4V-F10
HSD32M32M4V-10L
HSD32M32M4V-F10L
128MByte
128MByte
128MByte
128MByte
128MByte
128MByte
128MByte
128MByte
32Mx 32
32Mx 32
32Mx 32
32Mx 32
32Mx 32
32Mx 32
32Mx 32
32Mx 32
8K
8K
8K
8K
8K
8K
8K
8K
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
Low
133MHz
(CL=3)
Power
125MHz
(CL=3)
72 Pin
SIMM
72 Pin
SIMM
72 Pin
SIMM
72 Pin
SIMM
72 Pin
SIMM
Low
125MHz
(CL=3)
Power
100MHz
(CL=2)
Low
100MHz
(CL=2)
Power
100MHz
100MHz
Low
Power
F means Auto & Self refresh with Low – Power (3.3V)
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REV.1.0 (August.2002)
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