HD74ALVCH162543TEL [HITACHI]
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HD74ALVCH162543
16-bit Registered Transceivers with 3-state Outputs
ADE-205-183 (Z)
Preliminary
1st. Edition
December 1996
Description
The HD74ALVCH162543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate
latch enable (LEAB or LEBA) and output enable (OEAB or OEBA) inputs are provided for each
register to permit independent control in either direction of data flow. The A to B enable (CEAB)
input must be low in order to enter data from A or to output data from B. If CEAB is low and LEAB is
low, the A to B latches are transparent; a subsequent low to high transition of LEAB puts the A latches
in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the
data present at the output of the A latches. Data flow from B to A is similar but requires using CEBA,
LEBA, and OEBA. Active bus hold circuitry is provided to hold unused or floating data inputs at a
valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce
overshoot and undershoot.
Features
•
•
•
•
•
•
VCC = 2.3 V to 3.6 V
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current ±12 mA (@VCC = 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
All outputs have equivalent 26 Ω series resistors, so no external resistors are required.
HD74ALVCH162543
Function Table *2
Inputs
Output B
CEAB
LEAB
OEAB
A
X
X
X
L
H
X
L
L
L
X
X
H
L
X
H
L
L
L
Z
Z
*1
B0
L
L
H
H
H : High level
L : Low level
X : Immaterial
Z : High impedance
Notes: 1. Output level before the indicated steady state input conditions were established.
2. A to B data flow is shown; B to A flow control is the same except that it uses CEBA, LEBA,
and OEBA.
HD74ALVCH162543
Pin Arrangement
1OEBA
56
1OEAB
1
1LEAB 2
55 1LEBA
54
53
52
51
1CEBA
GND
1B1
1CEAB
GND
1A1
3
4
5
6
1B2
1A2
VCC
7
50 VCC
49 1B3
8
1A3
1A4
1A5
GND
1A6
1B4
1B5
GND
9
48
47
46
10
11
12
45 1B6
1B7
1B8
2B1
44
43
42
1A7 13
1A8 14
2A1
2A2
2A3
15
41 2B2
2B3
16
17
40
39 GND
38 2B4
37 2B5
GND
2A4
18
19
20
2A5
2A6 21
2B6
36
35
34
33
32
31
30
29
VCC
2A7
22
23
24
25
26
27
28
VCC
2B7
2A8
2B8
GND
2CEBA
2LEBA
2OEBA
GND
2CEAB
2LEAB
2OEAB
(Top view)
HD74ALVCH162543
Absolute Maximum Ratings
Item
Symbol
Ratings
–0.5 to 4.6
–0.5 to 4.6
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–50
Unit
V
Conditions
Supply voltage
Input voltage *1, 2
VCC
VI
V
Except I/O ports
I/O ports
Output voltage *1, 2
VO
IIK
V
Input clamp current
Output clamp current
Continuous output current
mA
mA
mA
IOK
IO
±50
VO < 0 or VO > VCC
VO = 0 to VCC
±50
±100
Maximum power dissipation
PT
1
W
TSSOP
at Ta = 55°C (in still air) *3
Storage temperature
Tstg
–65 to 150
°C
Notes:
Stresses beyond those listed under “absolute maximum ratings” may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute maximum rated conditions for extended
periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output
clamp current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of
150°C and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol
VCC
Min
2.3
0
Max
3.6
VCC
VCC
–6
–8
–12
6
Unit
V
Conditions
Supply voltage
Input voltage
VI
V
Output voltage
High level output current
VO
0
V
IOH
—
—
—
—
—
—
0
mA
VCC = 2.3 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3.0 V
Low level output current
IOL
mA
8
12
10
85
Input transition rise or fall rate
Operating temperature
∆t / ∆v
ns / V
Ta
–40
°C
Note: Unused control inputs must be held high or low to prevent them from floating.
HD74ALVCH162543
Logic Diagram
56
1OEBA
54
55
1
1CEBA
1LEBA
1OEAB
1CEAB
3
2
1LEAB
C1
1D
5
1A1
52
1B1
C1
1D
To seven other channels
29
2OEBA
2CEBA
31
30
28
2LEBA
2OEAB
2CEAB
26
27
2LEAB
C1
1D
15
2A1
42
2B1
C1
1D
To seven other channels
HD74ALVCH162543
Electrical Characteristics (Ta = –40 to 85°C)
Item
Symbol VCC (V) *1
Min
Max
—
Unit Test Conditions
Input voltage
VIH
2.3 to 2.7 1.7
2.7 to 3.6 2.0
V
—
VIL
2.3 to 2.7
2.7 to 3.6
—
—
0.7
0.8
—
Output voltage
VOH
Min to Max VCC–0.2
V
IOH = –100 µA
2.3
2.3
3.0
2.7
3.0
1.9
1.7
2.4
2.0
2.0
—
IOH = –4 mA, VIH = 1.7 V
IOH = –6 mA, VIH = 1.7 V
IOH = –6 mA, VIH = 2.0 V
IOH = –8 mA, VIH = 2.0 V
IOH = –12 mA, VIH = 2.0 V
IOL = 100 µA
—
—
—
—
VOL
Min to Max —
0.2
0.4
0.55
0.55
0.6
0.8
±5
2.3
—
IOL = 4 mA, VIL = 0.7 V
IOL = 6 mA, VIL = 0.7 V
IOL = 6 mA, VIL = 0.8 V
IOL = 8 mA, VIL = 0.8 V
IOL = 12 mA, VIL = 0.8 V
VIN = VCC or GND
VIN = 0.7 V
2.3
—
3.0
—
2.7
—
3.0
—
Input current
IIN
3.6
—
µA
IIN (hold)
2.3
45
–45
75
–75
—
—
2.3
—
VIN = 1.7 V
3.0
—
VIN = 0.8 V
3.0
—
VIN = 2.0 V
3.6
±500
±10
40
VIN = 0 to 3.6 V
Off state output current *2 IOZ
Quiescent supply current ICC
3.6
—
µA
µA
µA
VOUT = VCC or GND
VIN = VCC or GND
3.6
—
∆ICC
3.0 to 3.6
—
750
VIN = one input at (VCC–0.6)
V,
other inputs at VCC or GND
Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended
operating conditions.
2. For I/O ports, the parameter IOZ includes the input leakage current.
HD74ALVCH162543
Switching Characteristics (Ta = –40 to 85°C)
Item
Symbol VCC (V) Min
Typ
Max
Unit FROM
(Input)
TO
(Output)
Propagation delay time
tPLH
tPHL
2.5±0.2 1.0
2.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.5
7.0
6.2
5.5
4.9
7.6
6.9
5.6
8.2
7.6
6.2
7.8
7.0
5.9
6.8
6.7
5.6
6.4
5.3
5.1
—
ns
ns
ns
ns
ns
ns
A or B
B or A
A or B
A or B
A or B
A or B
A or B
—
3.3±0.3 1.0
2.5±0.2 1.1
LE
2.7
—
3.3±0.3 1.1
2.5±0.2 1.0
Output enable time
Output disable time
Setup time
tZH
tZL
CE
2.7
—
3.3±0.3 1.0
2.5±0.2 1.0
OE
2.7
—
3.3±0.3 1.0
2.5±0.2 2.0
tHZ
tLZ
CE
2.7
—
3.3±0.3 1.5
2.5±0.2 1.6
OE
2.7
—
3.3±0.3 1.1
2.5±0.2 1.2
tsu
Data before CE↑
2.7
1.5
—
3.3±0.3 1.2
2.5±0.2 1.2
—
—
Data before LE↑
CE “L”
2.7
1.5
—
3.3±0.3 1.2
2.5±0.2 1.2
—
Hold time
th
—
Data after CE↑
2.7
0.8
—
3.3±0.3 1.3
2.5±0.2 1.2
—
—
Data after LE↑
CE “L”
2.7
0.8
—
3.3±0.3 1.3
2.5±0.2 3.3
—
Pulse width
tw
—
CE or LE “L”
2.7
3.3
—
3.3±0.3 3.3
—
Input capacitance
Output capacitance
CIN
3.3
3.3
—
—
—
pF
pF
Control inputs
A or B ports
CIN / O
—
HD74ALVCH162543
• Test Circuit
See under table
500 Ω
S1
OPEN
GND
*1
CL= 50 pF
500 Ω
Load Circuit for Outputs
Vcc=2.7V,
Vcc=2.5±0.2V
Symbol
3.3±0.3V
tPLH/ tPHL
tsu / th / tw
OPEN
OPEN
tZH/ tHZ
tZL / tLZ
GND
4.6 V
GND
6.0 V
Note: 1. CL includes probe and jig capacitance.
HD74ALVCH162543
• Waveforms – 1
tr
tf
V
IH
90 %
Vref
90 %
Vref
Input
10 %
10 %
GND
tPHL
tPLH
VOH
Output
Vref
Vref
VOL
• Waveforms – 2
tr
V
IH
90 %
Vref
Timing Input
10 %
tsu
GND
th
V
IH
Vref
Vref
Data Input
GND
tw
V
IH
Vref
Vref
Input
GND
HD74ALVCH162543
• Waveforms – 3
tf
tr
V
IH
90 %
90 %
Vref
Output
Control
Vref
10 %
tZL
10 %
GND
tLZ
≈VOH1
Vref
Waveform - A
Waveform - B
VOL + 0.3 V
VOH– 0.3 V
VOL
VOH
tZH
tHZ
Vref
≈VOL1
Vcc=2.7V,
Vcc=2.5±0.2V
2.3 V
TEST
3.3±0.3V
VIH
2.7 V
Vref
1.2 V
1.5 V
3.0 V
GND
VOH1
VOL1
2.3 V
GND
Notes: 1. All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
2. Waveform – A is for an output with internal conditions such that the output is low
except when disabled by the output control.
3. Waveform – B is for an output with internal conditions such that the output is high
except when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
HD74ALVCH162543
Package Dimensions
Unit : mm
+0.3
–0.1
14.00
56
29
28
1
0.50
0.08
+0.1
M
0.20
–0.05
8.10 ± 0.3
0.40 Max
10° Max
0.10
0.50 ± 0.1
Hitachi code
EIAJ code
JEDEC code
TTP-56D
—
—
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
Europe
: http:semiconductor.hitachi.com/
: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore)
Asia (Taiwan)
: http://www.has.hitachi.com.sg/grp3/sicd/index.htm
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
Hitachi Europe GmbH
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Electronic components Group
Dornacher Stra§e 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
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