HD74LV374T [HITACHI]
Bus Driver, LV/LV-A/LVX/H Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, TSSOP-20;
| 型号： | HD74LV374T |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Bus Driver, LV/LV-A/LVX/H Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, TSSOP-20 触发器 |
| 文件： | 总15页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74LV374A
Octal Edge-Triggered D-type Flip-Flops with 3-state Outputs
ADE-205-275 (Z)
1st Edition
April 1999
Description
The HD74LV374A has eight edge trigger D type flip flops with three state outputs in a 20 pin package.
Data at the D inputs meeting set up requirements, are transferred to the Q outputs on positive going
transitions of the clock input. When the clock input goes low, data at the D inputs will be retained at the
outputs until clock input returns high again. When a high logic level is applied to the output control input,
all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the
state of the storage elements. Low-voltage and high-speed operation is suitable for the battery-powered
products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features
•
•
•
•
•
•
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V)
Function Table
Inputs
OE
H
L
CLK
D
X
L
Output Q
X
↑
↑
↓
Z
L
L
H
X
H
Q0
L
Note: H: High level
L: Low level
X: Immaterial
Z: High impedance
Q0: Output level before the indicated steady state input conditions were established.
HD74LV374A
Pin Arrangement
1
2
3
4
5
6
7
8
9
20 VCC
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
19
18
17
16
15
14
13
12
11
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
GND 10
(Top view)
2
HD74LV374A
Absolute Maximum Ratings
Item
Symbol
Ratings
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
Unit
V
Conditions
Supply voltage range
Input voltage range*1
Output voltage range*1, 2
VCC
VI
V
VO
V
Output: H or L
VCC: OFF or Output: Z
VI < 0
Input clamp current
IIK
mA
mA
mA
mA
Output clamp current
IOK
±50
VO < 0 or VO > VCC
VO = 0 to VCC
Continuous output current
IO
±35
Continuous current through
ICC or IGND
±70
V
CC or GND
Maximum power dissipation
PT
835
mW
SOP
at Ta = 25°C (in still air)*3
757
TSSOP
Storage temperature
Tstg
–65 to 150
°C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,
no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
3
HD74LV374A
Recommended Operating Conditions
Item
Symbol
VCC
Min
2.0
0
Max
5.5
5.5
VCC
5.5
–50
–2
Unit
V
Conditions
Supply voltage range
Input voltage range
Output voltage range
VI
V
VO
0
V
H or L
0
High impedance state
VCC = 2.0 V
Output current
IOH
—
—
—
—
—
—
—
—
0
µA
mA
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.0 V
–8
–16
50
IOL
µA
2
mA
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
8
16
Input transition rise or fall rate
∆t /∆v
200
100
20
ns/V
0
0
Operating free-air temperature Ta
–40
85
°C
Note: Unused or floating inputs must be held high or low.
Logic Diagram
1
OE
11
CLK
C1
2
1Q
3
1D
1D
To Seven Other Channels
4
HD74LV374A
DC Electrical Characteristics
•
Ta = –40 to 85°C
Item
Symbol
VCC (V)*
2.0
Min
Typ
—
—
—
—
—
—
—
—
—
Max
—
Unit
Test Conditions
Input voltage
VIH
1.5
V
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
2.0
V
V
V
CC × 0.7
—
CC × 0.7
CC × 0.7
—
—
VIL
—
0.5
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
—
V
V
V
CC × 0.3
—
CC × 0.3
CC × 0.3
—
Output voltage VOH
Min to
Max
VCC – 0.1
—
V
IOH = –50 µA
2.3
3.0
4.5
2.0
2.48
3.8
—
—
—
—
—
—
—
—
0.1
IOH = –2 mA
IOH = –8 mA
IOH = –16 mA
IOL = 50 µA
VOL
Min to
Max
2.3
—
—
—
—
—
—
—
—
—
—
0.4
0.44
0.55
±1
IOL = 2 mA
3.0
IOL = 8 mA
4.5
IOL = 16 mA
Input current
IIN
0 to 5.5
5.5
µA
µA
VIN = 5.5 V or GND
VO = VCC or GND
Off-state
IOZ
±5
output current
Quiescent
ICC
5.5
0
—
—
—
—
20
5
µA
µA
pF
VIN = VCC or GND, IO = 0
VI or VO = 0 to 5.5 V
VI = VCC or GND
supply current
Output leakage IOFF
current
—
Input
CIN
3.3
2.9
—
capacitance
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
5
HD74LV374A
Switching Characteristics
•
VCC = 2.5 ± 0.2 V
Ta = 25°C
Ta = –40 to 85°C
FROM
(Input)
TO
Item
Symbol Min Typ
Max
Min
Max
Unit
Test Conditions
(Output)
Maxi-
mum
clock
fre-
tmax
60
105
—
50
—
MHz
CL = 15 pF
quency
50
—
85
—
40
—
CL = 50 pF
CL = 15 pF
Propa-
gation
delay
time
tPLH
9.7
16.3
1.0
19.0
ns
CLK
Q
tPHL
tZH
tZL
—
—
—
—
—
5.0
11.8
8.9
10.9
6.3
8.2
—
19.3
15.9
18.8
12.6
17.3
—
1.0
1.0
1.0
1.0
1.0
5.5
23.0
19.0
22.0
15.0
19.0
—
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
Enable
time
ns
ns
OE
OE
Q
Q
Disable
time
tHZ
tLZ
Setup
time
tSU
ns
ns
ns
Data before CLK ↑
Data after CLK ↑
CLK: "H" or "L"
Hold
time
th
2.5
6.0
—
—
—
—
2.5
7.0
—
—
Pulse
width
tw
6
HD74LV374A
Switching Characteristics (cont)
•
VCC = 3.3 ± 0.3 V
Ta = 25°C
Ta = –40 to 85°C
FROM
(Input)
TO
Item
Symbol Min Typ
Max
Min
Max
Unit
Test Conditions
(Output)
Maxi-
mum
clock
fre-
tmax
80
150
—
70
—
MHz
CL = 15 pF
quency
55
—
110
6.8
—
50
—
CL = 50 pF
CL = 15 pF
Propa-
gation
delay
time
tPLH
12.7
1.0
15.0
ns
CLK
Q
tPHL
tZH
tZL
—
—
—
—
—
4.5
8.3
6.3
7.7
4.7
5.9
—
16.2
11.0
14.5
10.5
14.0
—
1.0
1.0
1.0
1.0
1.0
4.5
18.5
13.0
16.5
12.5
16.0
—
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
Enable
time
ns
ns
OE
OE
Q
Q
Disable
time
tHZ
tLZ
Setup
time
tSU
ns
ns
ns
Data before CLK ↑
Data after CLK ↑
CLK: "H" or "L"
Hold
time
th
2.0
5.0
—
—
—
—
2.0
5.5
—
—
Pulse
width
tw
7
HD74LV374A
Switching Characteristics (cont)
•
VCC = 5.0 ± 0.5 V
Ta = 25°C
Ta = –40 to 85°C
FROM
(Input)
TO
Item
Symbol Min Typ
Max
Min
Max
Unit
Test Conditions
(Output)
Maxi-
mum
clock
fre-
tmax
130 205
—
110
—
MHz
CL = 15 pF
quency
85
—
170
4.9
—
75
—
CL = 50 pF
CL = 15 pF
Propa-
gation
delay
time
tPLH
8.1
1.0
9.5
ns
CLK
Q
tPHL
tZH
tZL
—
—
—
—
—
3.0
5.9
4.6
5.5
3.4
4.0
—
10.1
7.6
9.6
6.8
8.8
—
1.0
1.0
1.0
1.0
1.0
3.0
11.5
9.0
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
Enable
time
ns
ns
OE
OE
Q
Q
11.0
8.0
Disable
time
tHZ
tLZ
10.0
—
Setup
time
tSU
ns
ns
ns
Data before CLK ↑
Data after CLK ↑
CLK: "H" or "L"
Hold
time
th
2.0
5.0
—
—
—
—
2.0
5.0
—
—
Pulse
width
tw
8
HD74LV374A
Output-skew Characteristics
•
CL = 50 pF
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol VCC = (V)
Min
—
Max
2.0
1.5
1.0
Min
—
Max
Unit
Output skew
tsk (O)
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
2.0
1.5
1.0
ns
—
—
—
—
Note: Skew between any outputs of the same package switching in the same direction. This parameter is
warranted but not production tested.
Operating Characteristics
•
CL = 50 pF
Ta = 25°C
Min
Item
Symbol VCC = (V)
Typ
Max
Unit
Test Conditions
Power
CPD
3.3
—
21.1
—
pF
f = 10 MHz
dissipation
capacitance
5.0
—
22.8
—
Noise Characteristics
•
CL = 50 pF
Ta = 25°C
Min
Item
Symbol VCC = (V)
Typ
Max
Unit
Test Conditions
Quiet output, VOL (P)
maximum
dynamic VOL
3.3
3.3
3.3
3.3
3.3
—
0.6
0.8
V
Quiet output, VOL (V)
minimum
dynamic VOL
—
–0.5
2.9
—
–0.8
—
Quiet output, VOH (V)
minimum
dynamic VOH
—
High-level
dynamic
VIH (D)
2.31
—
—
input voltage
Low-level
dynamic
VIL (D)
—
0.99
input voltage
9
HD74LV374A
Test Circuit
Output
1 kΩ
OPEN
GND
VCC
S2
CL
TEST
tPLH/tPHL
tZH/tHZ
tZL /tLZ
S2
OPEN
GND
VCC
Note: CL includes the probe and jig capacitance.
10
HD74LV374A
• Waveform – 1
Input CLK
tr
tf
VCC
90 % 90 %
50 %VCC
10 %
tr
50 %VCC
10 %
tf
GND
VCC
90 %
10 %
90 %
Input D
10 %
GND
VOH
tPHL
tPLH
Output Q
50 %VCC
50 %VCC
VOL
• Waveform – 2
Input CLK
tr
tf
VCC
GND
VCC
90 % 90 %
50 %VCC
50 %
VCC
50 %
VCC
10 %
tsu
10 %
tw
tw
th
50 %VCC
50 %VCC
Input D
GND
VCC
• Waveform – 3
tf
tr
90 %
50 %VCC
10 %
90 %
50 %VCC
10 %
Input OE
GND
VCC
tZL
tLZ
50 %VCC
tZH
Waveform – A
Waveform – B
VOL + 0.3 V
VOL
VOH
tHZ
VOH– 0.3 V
50 %VCC
GND
Notes:
1. tr ≤ 3 ns, tf ≤ 3 ns
2. Input waveform: PRR ≤ 1 MHZ, duty cycle 50%
3. Waveform-A is for an output with internal conditions such that the output is low except
when disabled by the output control.
4. Waveform-B is for an output with internal conditions such that the output is high except
when disabled by the output control.
11
HD74LV374A
Package Dimensions
12.6
13 Max
11
10
20
1
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0° – 8°
1.27
0.70 ± 0.20
0.42 ± 0.08
0.40 ± 0.06
0.15
0.12 M
Hitachi Code
JEDEC
FP-20DA
—
EIAJ
Conforms
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.31 g
12
HD74LV374A
Unit: mm
12.8
13.2 Max
11
10
20
1
+ 0.25
– 0.40
10.40
0.935 Max
1.45
0° – 8°
+ 0.57
– 0.30
1.27
0.70
*0.42 ± 0.08
0.40 ± 0.06
0.15
M
0.12
Hitachi Code
JEDEC
EIAJ
FP-20DB
Conforms
—
*Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.52 g
13
HD74LV374A
6.50
6.80 Max
20
11
1
10
0.65
1.0
+0.08
–0.07
0.22
0.13
M
0.20 ± 0.06
6.40 ± 0.20
0.65 Max
0° – 8°
0.50 ± 0.10
0.10
Hitachi Code
TTP-20DA
JEDEC
EIAJ
—
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.07 g
14
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
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Europe
: http:semiconductor.hitachi.com/
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Asia (Taiwan)
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Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
Hitachi Europe GmbH
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Hitachi Asia Pte. Ltd.
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Tel: 535-2100
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Germany
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Tel: <886> (2) 2718-3666
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Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
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