HM5116405S-7 [HITACHI]
16M EDO DRAM (4-MWORD X 4-BIT) 4K REFRESH / 2K REFRESH; 16M EDO DRAM （ 4 - MWORD X 4 - BIT）刷新4K / 2K刷新
| 型号： | HM5116405S-7 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | 16M EDO DRAM (4-MWORD X 4-BIT) 4K REFRESH / 2K REFRESH |
| 文件： | 总35页 (文件大小：313K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM5116405 Series
HM5117405 Series
16 M EDO DRAM (4-Mword 4-bit)
4 k Refresh/2 k Refresh
ADE-203-633D (Z)
Rev. 4.0
Nov. 1997
Description
The Hitachi HM5116405 Series, HM5117405 Series are CMOS dynamic RAMs organized 4,194,304-word
4-bit. They employ the most advanced CMOS technology for high performance and low power. The
HM5116405 Series, HM5117405 Series offer Extended Data Out (EDO) Page Mode as a high speed
access mode. They have package variations of standard 26-pin plastic SOJ and standard 26-pin plastic
TSOP II.
Features
Single 5 V ( 10%)
Access time: 50 ns/60 ns/70 ns (max)
Power dissipation
Active mode : 495 mW/440 mW/385 mW (max) (HM5116405 Series)
: 550 mW/495 mW/440 mW (max) (HM5117405 Series)
Standby mode : 11 mW (max)
:
0.83 mW (max) (L-version)
EDO page mode capability
Long refresh period
4096 refresh cycles : 64 ms (HM5116405 Series)
: 128 ms (L-version)
2048 refresh cycles : 32 ms (HM5117405 Series)
: 128 ms (L-version)
3 variations of refresh
-only refresh
-before-
refresh
Hidden refresh
HM5116405 Series, HM5117405 Series
Battery backup operation (L-version)
Test function
16-bit parallel test mode
Ordering Information
Type No.
Access time
Package
HM5116405S-5
HM5116405S-6
HM5116405S-7
50 ns
60 ns
70 ns
300-mil 26-pin plastic SOJ
(CP-26/24DB)
HM5116405LS-5
HM5116405LS-6
HM5116405LS-7
50 ns
60 ns
70 ns
HM5117405S-5
HM5117405S-6
HM5117405S-7
50 ns
60 ns
70 ns
HM5117405LS-5
HM5117405LS-6
HM5117405LS-7
50 ns
60 ns
70 ns
HM5116405TS-5
HM5116405TS-6
HM5116405TS-7
50 ns
60 ns
70 ns
300-mil 26-pin plastic TSOP II
(TTP-26/24DA)
HM5116405LTS-5
HM5116405LTS-6
HM5116405LTS-7
50 ns
60 ns
70 ns
HM5117405TS-5
HM5117405TS-6
HM5117405TS-7
50 ns
60 ns
70 ns
HM5117405LTS-5
HM5117405LTS-6
HM5117405LTS-7
50 ns
60 ns
70 ns
2
HM5116405 Series, HM5117405 Series
Pin Arrangement
HM5116405S/LS Series
HM5116405TS/LTS Series
VCC
I/O1
I/O2
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
VCC
I/O1
I/O2
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
A9
A11
A9
A11
A10
A0
A1
A2
A3
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
A10
A0
A1
A2
A3
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
9
9
10
11
12
13
10
11
12
13
VCC
VCC
(Top view)
(Top view)
Pin Description
Pin name
Function
Address input
A0 to A11
A0 to A11
A0 to A9
Row/Refresh address
Column address
I/O1 to I/O4
Data input/Data output
Row address strobe
Column address strobe
Write enable
Output enable
VCC
VSS
Power supply
Ground
3
HM5116405 Series, HM5117405 Series
Pin Arrangement
HM5117405S/LS Series
HM5117405TS/LTS Series
VCC
I/O1
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
VCC
I/O1
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
I/O2
I/O2
NC
A9
NC
A9
A10
A0
A1
A2
A3
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
A10
A0
A1
A2
A3
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
9
9
10
11
12
13
10
11
12
13
VCC
VCC
(Top view)
(Top view)
Pin Description
Pin name
Function
Address input
A0 to A10
A0 to A10
A0 to A10
Row/Refresh address
Column address
I/O1 to I/O4
Data input/Data output
Row address strobe
Column address strobe
Write enable
Output enable
VCC
VSS
NC
Power supply
Ground
No connection
4
HM5116405 Series, HM5117405 Series
Block Diagram (HM5116405 Series)
Timing and control
A0
Column decoder
4M array
A1
to
Column
address
buffers
•
•
•
A9
4M array
I/O1
to
I/O4
•
•
•
I/O buffers
4M array
4M array
Row
address
buffers
A10
A11
5
HM5116405 Series, HM5117405 Series
Block Diagram (HM5117405 Series)
Timing and control
A0
A1
to
Column decoder
4M array
Column
address
buffers
•
•
•
A10
4M array
4M array
4M array
I/O1
to
I/O4
I/O buffers
•
•
•
Row
address
buffers
6
HM5116405 Series, HM5117405 Series
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–1.0 to +7.0
–1.0 to +7.0
50
VCC
V
Iout
PT
mA
W
C
1.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
C
Recommended DC Operating Conditions (Ta = 0 to +70 C)
Parameter
Symbol
VCC
Min
4.5
Typ
5.0
—
Max
5.5
6.5
0.8
Unit
Note
Supply voltage
Input high voltage
Input low voltage
V
V
V
1
1
1
VIH
2.4
VIL
–1.0
—
Note: 1. All voltage referred to VSS.
7
HM5116405 Series, HM5117405 Series
DC Characteristics
(Ta = 0 to +70 C, VCC = 5 V 10%, VSS = 0 V) (HM5116405 Series)
HM5116405
-5
-6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Test conditions
tRC = min
1
2
,
Operating current*
Standby current
*
ICC1
ICC2
—
—
90
2
—
—
80
2
—
—
70 mA
2
mA
mA
A
TTL interface
,
= VIH
Dout = High-Z
—
—
1
—
—
1
—
—
1
CMOS interface
,
VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
150
150
150
CMOS interface
,
VCC – 0.2 V
Dout = High-Z
-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
90
5
—
—
80
5
—
—
70 mA
mA
tRC = min
5
= VIH
= VIL
Dout = enable
-before-
current
EDO page mode current*1, *3 ICC7
refresh
ICC6
—
90
—
80
—
70 mA
65 mA
tRC = min
—
—
80
—
—
70
—
—
tHPC = min
Battery backup current
ICC10
350
350
350
A
CMOS interface
Dout = High-Z, CBR
refresh: tRC = 31.3
s
tRAS 0.3
s
Input leakage current
Output leakage current
ILI
–10 10 –10 10 –10 10
–10 10 –10 10 –10 10
A
A
0 V Vin 7 V
ILO
0 V Vin 7 V
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4 VCC 2.4 VCC 2.4 VCC
V
High Iout = –2 mA
0
0.4
0
0.4
0
0.4
V
Low Iout = 2 mA
Notes : 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while
3. Address can be changed once or less while
= VIL.
= VIH.
8
HM5116405 Series, HM5117405 Series
DC Characteristics
(Ta = 0 to +70 C, VCC = 5 V 10%, VSS = 0 V) (HM5117405 Series)
HM5117405
-5
-6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Test conditions
tRC = min
1
2
,
Operating current*
Standby current
*
ICC1
ICC2
—
—
100
2
—
—
90
2
—
—
80 mA
2
mA
mA
A
TTL interface
,
= VIH
Dout = High-Z
—
—
1
—
—
1
—
—
1
CMOS interface
,
VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
150
150
150
CMOS interface
,
VCC – 0.2 V
Dout = High-Z
-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
100
5
—
—
90
5
—
—
80 mA
mA
tRC = min
5
= VIH
= VIL
Dout = enable
-before-
current
EDO page mode current*1, *3 ICC7
refresh
ICC6
—
100
—
90
—
80 mA
75 mA
tRC = min
—
—
90
—
—
80
—
—
tHPC = min
Battery backup current
ICC10
350
350
350
A
CMOS interface
Dout = High-Z, CBR
refresh: tRC = 62.5
s
tRAS 0.3
s
Input leakage current
Output leakage current
ILI
–10 10 –10 10 –10 10
–10 10 –10 10 –10 10
A
A
0 V Vin 7 V
ILO
0 V Vin 7 V
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4 VCC 2.4 VCC 2.4 VCC
V
High Iout = –2 mA
0
0.4
0
0.4
0
0.4
V
Low Iout = 2 mA
Notes : 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while
3. Address can be changed once or less while
= VIL.
= VIH.
9
HM5116405 Series, HM5117405 Series
Capacitance (Ta = 25 C, VCC = 5 V 10%)
Parameter
Symbol
CI1
Typ
—
Max
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (Clocks)
5
7
7
1
CI2
—
pF
1
Output capacitance (Data-in, Data-out) CI/O
—
pF
1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. = VIH to disable Dout.
10
HM5116405 Series, HM5117405 Series
AC Characteristics (Ta = 0 to +70 C, VCC = 5 V 10%, VSS = 0 V) *1, *2, *18
Test Conditions
Input rise and fall time: 2 ns
Input levels: VIL = 0 V, VIH = 3 V
Input timing reference levels: 0.8 V, 2.4 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5116405/HM5117405
-5
-6
-7
Parameter
Symbol Min Max
Min Max
Min Max
Unit
ns
Notes
Random read or write cycle time
precharge time
tRC
84
30
7
—
—
—
104
40
—
—
—
124
50
—
—
—
tRP
ns
precharge time
tCP
10
13
ns
pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
50
7
10000 60
10000 10
10000 70
10000 13
10000 ns
10000 ns
pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
0
—
—
—
—
37
25
—
—
—
—
—
—
50
0
—
—
—
—
45
30
—
—
—
—
—
—
50
0
—
—
—
—
52
35
—
—
—
—
—
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
10
0
10
0
0
7
10
14
12
13
40
5
13
14
12
13
45
5
to
delay time
11
9
3
4
to column address delay time tRAD
hold time
hold time
tRSH
tCSH
tCRP
tOED
tDZO
tDZC
tT
10
35
5
to
precharge time
to Din delay time
delay time from Din
delay time from Din
Transition time (rise and fall)
13
0
15
0
18
0
5
6
6
7
0
0
0
2
2
2
11
HM5116405 Series, HM5117405 Series
Read Cycle
HM5116405/HM5117405
-5
-6
-7
Parameter
Symbol Min
Max Min
Max Min
Max Unit
Notes
Access time from
Access time from
tRAC
tCAC
—
—
50
13
—
—
60
15
—
—
70
18
ns
ns
8, 9, 20
9, 10, 17,
20
Access time from address
tAA
—
25
—
30
—
35
ns
9, 11, 17,
20
Access time from
tOEA
tRCS
tRCH
tRCHR
—
0
13
—
—
—
—
0
15
—
—
—
—
0
18
—
—
—
ns
ns
ns
ns
9, 20
Read command setup time
Read command hold time to
Read command hold time from
0
0
0
12
50
60
70
Read command hold time to
tRRH
0
—
—
—
—
—
—
13
13
—
—
13
13
—
—
—
0
—
—
—
—
—
—
15
15
—
—
15
15
—
—
—
0
—
—
—
—
—
—
15
15
—
—
15
15
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
22
Column address to
lead time tRAL
lead time tCAL
25
15
0
30
18
0
35
23
0
Column address to
to output in low-Z
tCLZ
Output data hold time
Output data hold time from
Output buffer turn-off time
Output buffer turn-off to
to Din delay time
tOH
3
3
3
tOHO
tOFF
tOEZ
tCDD
tOHR
tOFR
tWEZ
tWED
tRDD
tRNCD
3
3
3
—
—
13
3
—
—
15
3
—
—
18
3
13, 22
13
5
Output data hold time from
Output buffer turn-off to
Output buffer turn-off to
to Din delay time
22
—
—
13
13
50
—
—
15
15
60
—
—
18
18
70
22
to Din delay time
next
delay time
12
HM5116405 Series, HM5117405 Series
Write Cycle
HM5116405/HM5117405
-5
-6
-7
Parameter
Symbol Min
Max Min
Max Min
Max Unit
Notes
Write command setup time
Write command hold time
Write command pulse width
tWCS
tWCH
tWP
0
7
7
7
7
0
7
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
14
10
10
10
10
0
13
10
13
13
0
Write command to
Write command to
Data-in setup time
Data-in hold time
lead time
lead time
tRWL
tCWL
tDS
15
15
tDH
10
13
Read-Modify-Write Cycle
HM5116405/HM5117405
-5
Symbol Min
-6
-7
Parameter
Max Min
Max Min
Max Unit
Notes
Read-modify-write cycle time
tRWC
111
67
—
—
—
—
—
135
79
—
—
—
—
—
161
92
—
—
—
—
—
ns
ns
ns
ns
ns
to
to
delay time
delay time
tRWD
tCWD
14
14
14
30
34
40
Column address to
hold time from
delay time tAWD
tOEH
42
49
57
13
15
18
Refresh Cycle
HM5116405/HM5117405
-5
Symbol Min
-6
-7
Parameter
Max Min
Max Min
Max Unit
Notes
setup time (CBR refresh cycle) tCSR
hold time (CBR refresh cycle) tCHR
5
7
0
7
5
—
—
—
—
—
5
—
—
—
—
—
5
—
—
—
—
—
ns
ns
ns
ns
ns
10
0
10
0
setup time (CBR refresh cycle) tWRP
hold time (CBR refresh cycle) tWRH
10
5
10
5
precharge to
hold time
tRPC
13
HM5116405 Series, HM5117405 Series
EDO Page Mode Cycle
HM51W16405/HM51W17405
-5
-6
-7
Parameter
Symbol Min Max
Min Max
Min Max
Unit
Notes
21
EDO page mode cycle time
tHPC
20
—
—
28
3
—
25
100000 —
—
30
—
ns
EDO page mode
Access time from
hold time from
pulse width tRASP
precharge tCPA
precharge tCPRH
100000 — 100000 ns
16
28
—
—
—
—
—
—
35
3
35
—
—
—
—
—
—
40
3
40
—
—
—
—
—
ns
ns
ns
ns
ns
ns
9, 17, 20
Output data hold time from
hold time referred
low tDOH
tCOL
9, 17
7
10
5
13
5
to
setup time
tCOP
5
Read command hold time from
precharge
tRCHC
28
35
40
EDO Page Mode Read-Modify-Write Cycle
HM5116405/HM5117405
-5
Symbol Min
-6
-7
Parameter
Max Min
Max Min
Max Unit
Notes
EDO page mode read- modify-write tHPRWC
cycle time
57
—
68
—
79
ns
delay time from
precharge tCPW
45
—
54
—
62
ns
14
Test Mode Cycle *19
HM5116405/HM5117405
-5
Symbol Min
-6
-7
Parameter
Max Min
Max Min
Max Unit
Notes
Test mode
Test mode
setup time
hold time
tWTS
tWTH
0
7
—
—
0
—
—
0
—
—
ns
ns
10
10
Refresh (HM5116405 Series)
Parameter
Symbol
tREF
Max
Unit
ms
Notes
Refresh period
64
4096 cycles
4096 cycles
Refresh period (L-version)
tREF
128
ms
14
HM5116405 Series, HM5117405 Series
Refresh (HM5117405 Series)
Parameter
Symbol
tREF
Max
32
Unit
ms
Notes
Refresh period
2048 cycles
2048 cycles
Refresh period (L-version)
tREF
128
ms
Notes: 1. AC measurements assume tT = 2 ns.
2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing -only refresh or -before- refresh). If
-before- refresh cycles are
the internal refresh counter is used, a minimum of eight
required.
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC
.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max).
11. Assumes that tRAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD
tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW
tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
15. These parameters are referred to
edge in delayed write or read-modify-write cycles.
16. tRASP defines pulse width in EDO page mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tCPA
leading edge in early write cycles and to
leading
.
18. In delayed write or read-modify-write cycles,
to device.
must disable output buffer prior to applying data
19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M
4 are don’t care during test mode. Test mode is set by performing a -and- -before-
(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1
to I/O4) and read out from each I/O.
If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read
cycle, then the device has passed. If they are not equal, data output pin is a low state, then the
device has failed.
Refresh during test mode operation can be performed by normal read cycles or by WCBR
refresh cycles.
15
HM5116405 Series, HM5117405 Series
To get out of test mode and enter a normal operation mode, perform either a regular
-
before-
refresh cycle or
-only refresh cycle.
20. In a test mode read cycle, the value of tRAC, tAA, tCAC and tCPA is delayed by 2 ns to 5 ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
21. tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode
cycle (EDO
page mode mix cycle (1), (2)), minimum value of
than the specified tHPC (min) value. The value of
shown in EDO page mode mix cycle (1) and (2).
cycle (tCAS + tCP + 2 tT) becomes greater
cycle time of mixed EDO page mode is
Data output turns off and becomes high impedance from later risting edge of
Hold time and turn off time are specified by the timing specifications of later rising edge of
and between tOHR and tOH, and between tOFR and tOFF
22. Data output turns off and becomes high impedance from later rising edge of
Hold time and turn off time are specified by the timing specifications of later rising edge of
and between tOHR and tOH and between tOFR and tOFF
and
.
.
and
.
.
23. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min)
///////: Invalid Dout
V
VIL (max))
IN
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
16
HM5116405 Series, HM5117405 Series
Timing Waveforms*23
Read Cycle
t
t
RC
t
RAS
RP
t
t
CSH
CRP
t
t
t
RCD
RSH
CAS
t
T
t
t
t
RAD
RAL
CAL
t
t
t
CAH
ASR
Row
ASC
t
RAH
Address
Column
t
RRH
t
RCHR
t
t
RCH
CDD
t
RCS
t
WED
t
DZC
t
RDD
High-Z
Din
t
t
t
OED
DZO
OEA
t
OEZ
t
OHO
t
CAC
t
OFF
t
AA
t
OH
t
t
RAC
OFR
t
t
CLZ
OHR
t
WEZ
Dout
Dout
Early Write Cycle
17
HM5116405 Series, HM5117405 Series
tRC
tRAS
tRP
tCSH
tCRP
tRCD
tRSH
tCAS
tT
tASR tRAH
tASC
tCAH
Row
Column
Address
tWCS
tWCH
tDS
tDH
Din
Din
High-Z*
Dout
t
t
(min)
WCS
WCS
*
18
HM5116405 Series, HM5117405 Series
Delayed Write Cycle*18
t
t
RC
t
RAS
RP
RAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
CAS
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
Address
t
t
t
CWL
RWL
WP
t
RCS
WE
Din
t
t
t
DH
DZC
DS
High-Z
Din
t
t
OEH
DZO
t
OED
OE
t
OEZ
t
CLZ
High-Z
Dout
Invalid Dout
19
HM5116405 Series, HM5117405 Series
Read-Modify-Write Cycle*18
t
t
RWC
RAS
t
RP
t
T
t
t
t
CRP
RCD
CAS
t
RAD
t
t
t
t
CAH
ASR
RAH
ASC
Address
Row
Column
t
t
t
t
t
CWD
CWL
t
RCS
AWD
RWD
RWL
t
WP
t
t
DZC
DH
t
DS
High-Z
Din
Din
t
OED
t
OEH
t
DZO
t
OEA
t
CAC
t
t
OEZ
OHO
t
t
AA
t
RAC
High-Z
Dout
Dout
CLZ
-Only Refresh Cycle
20
HM5116405 Series, HM5117405 Series
t
RC
t
t
RAS
RP
t
T
t
t
t
CRP
CRP
RPC
t
t
RAH
ASR
Address
Row
t
OFR
t
OFF
High-Z
Dout
21
HM5116405 Series, HM5117405 Series
-Before-
Refresh Cycle
t
RC
t
t
t
RP
RP
RAS
t
t
t
t
CRP
t
CSR
CHR
RPC
RPC
t
T
t
CP
t
t
t
WRH
CP
WRP
Address
t
OFR
t
OFF
High-Z
Dout
22
HM5116405 Series, HM5117405 Series
Hidden Refresh Cycle
t
t
t
RC
RC
RC
t
t
t
t
t
t
RP
RAS
RP
RAS
RP
RAS
t
T
t
t
t
CRP
RSH
CHR
t
RCD
t
t
RAL
RAD
t
t
t
t
CAH
RAH
ASR
ASC
Address
Row
Column
t
t
t
RRH
t
WRH
t
WRP
RCH
t
RRH
t
WRH
WRP
t
t
RCS
DZC
t
WED
t
t
CDD
RDD
High-Z
Din
t
t
OED
DZO
t
OEA
t
OEZ
t
CAC
t
t
WEZ
OHO
t
AA
t
t
t
RAC
OFF
OH
t
CLZ
Dout
Dout
t
OFR
t
OHR
23
HM5116405 Series, HM5117405 Series
EDO Page Mode Read Cycle
t
RP
t
t
RNCD
t
HPC
t
RASP
t
t
t
CRP
HPC
HPC
t
CPRH
CP
t
t
T
t
CSH
t
t
CP
CP
t
RSH
t
t
t
CAS
CAS
CAS
CAS
t
RCHC
t
RCHR
tRCS
tRCH
t
t
RRH
RCH
tRCS
t
RAL
t
t
t
tCAH
tCAH
tASC
tCAH
WED
tASC
tRAH
CAH
ASC
tASC
tASR
Address
Row
Column 1
Column 2
t
Column 3
t
CAL
Column 4
t
t
CAL
CAL
CAL
t
t
RDD
CDD
t
DZC
High-Z
Din
t
t
t
COP
COL
DZO
t
OED
t
t
OFR
CPA
t
CPA
t
OEA
t
t
t
CPA
AA
t
OHR
OEZ
AA
t
t
OEZ
AA
t
t
CAC
t
CAC
t
OEZ
t
t
t
OHO
CAC
AA
t
t
t
t
t
WEZ
CAC
OHO
OFF
OH
tOEA
t
t
RAC
OEA
t
DOH
t
OHO
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
24
HM5116405 Series, HM5117405 Series
EDO Page Mode Early Write Cycle
tRASP
tRP
tT
tCSH
tHPC
tRSH
tCAS
tCP
tCAS
tCP
tCRP
tCAS
tRCD
tRAH
tASR
tASC tCAH
tASC
tCAH
tCAH
tASC
Row
Column 1
Column 2
Column N
Address
tWCH
tWCH
tWCS
tWCS
tWCS tWCH
tDS
tDH
tDS
tDH
tDS
tDH
Din 1
Din 2
Din N
Din
High-Z*
Dout
t
t
(min)
WCS
*
WCS
25
HM5116405 Series, HM5117405 Series
EDO Page Mode Delayed Write Cycle*18
t
RASP
t
RP
t
t
t
t
CP
CRP
T
CP
t
t
t
t
CSH
HPC
RSH
CAS
t
t
t
CAS
RCD
CAS
t
RAD
t
t
t
t
ASR
ASC
t
ASC
t
ASC
t
t
RAH
CAH
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
CWL
CWL
t
CWL
t
RWL
t
t
RCS
RCS
RCS
t
t
t
WP
WP
WP
t
t
t
t
t t
DZC DS
DZC DS
DZC DS
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
DZO
DZO
DZO
t
OED
t
t
OED
OED
t
t
t
OEH
OEH
OEH
t
t
t
CLZ
CLZ
CLZ
t
t
t
OEZ
OEZ
OEZ
High-Z
Dout
Invalid Dout
Invalid Dout
Invalid Dout
26
HM5116405 Series, HM5117405 Series
EDO Page Mode Read-Modify-Write Cycle*18
t
RASP
t
RP
t
t
T
HPRWC
t
t
t
t
RSH
CAS
t
CRP
CP
CP
t
t
t
CAS
RCD
CAS
t
RAD
t
t
t
t
ASC
t
CAH
ASR
ASC
RAH
ASC
t
t
t
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
t
t
t
CWL
RWD
AWD
CWL
CPW
AWD
CWL
CPW
AWD
t
RWL
t
t
t
t
t
CWD
CWD
RCS
CWD
RCS
t
t
t
t
t
WP
t
DS
RCS
DZO
WP
DS
WP
t
t
t
DS
t
DZC
DZC
DZC
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
OED
OED
OED
t
t
t
DZO
DZO
t
t
t
OEH
OEH
OEH
t
t
t
OHO
OHO
OHO
t
t
t
t
t
t
OEA
CAC
OEA
CAC
OEA
CAC
t
t
t
AA
AA
AA
t
t
CPA
CPA
t
t
RAC
t
t
t
OEZ
t
t
OEZ
OEZ
CLZ
CLZ
CLZ
High-Z
Dout
Dout 1
Dout 2
Dout N
27
HM5116405 Series, HM5117405 Series
EDO Page Mode Mix Cycle (1)
t
RP
t
RASP
t
CRP
t
T
t
t
t
CP
CP
CP
t
t
t
t
CAS
CAS
CAS
CAS
t
CSH
t
RSH
tRCD
tWCS
t
t
tRCS
RRH
RCH
tRCS
tWCH
t
tWP
CPW
t
AWD
t
RAL
tCAH
tASC
tRAH
tASC
t
tASC tCAH
tCAH
CAH
tASC
tASR
Address
Row
Column 1
t
Column 2
t
Column 3
t
Column 4
CAL
CAL
CAL
t
RDD
t
CAL
t
t
CDD
DH
t
t
DH
Din 1
DS
t
DS
High-Z
Din
Din 3
t
OED
t
WED
t
t
OFR
WEZ
t
CPA
CPA
t
t
t
t
CPA
t
AA
t
AA
t
OEZ
OEZ
t
t
AA
t
OEA
CAC
OHO
t
CAC
tOHO
t
t
OEA
CAC
t
t
OFF
OH
t
DOH
Dout
Dout3
Dout 2
Dout 4
28
HM5116405 Series, HM5117405 Series
EDO Page Mode Mix Cycle (2)
t
RNCD
t
RP
t
RASP
t
CRP
t
t
T
t
t
CSH
CP
CP
t
t
t
t
CAS
CAS
CAS
CAS
tRCD
tRCS
tRCHR
t
RSH
t
RCS
t
t
tWCS
tWCH
t
RRH
RCH
RCS
tRCH
tWP
t
CPW
t
RAL
tASC
tRAH
t
CAH
tASC
tCAH
tCAH
tCAH
tASC
tASR
tASC
Address
Row
Column 1
Column 2
t
Column 3
t
Column 4
t
t
CAL
CAL
CAL
CAL
t
DS
t
t
RDD
CDD
t
t
t
DH
DS
DH
High-Z
Din
Din 2
Din 3
t
t
OED
t
COP
OED
t
WED
t
COL
t
OFR
WEZ
t
t
OEA
t
t
t
t
CPA
t
AA
t
CPA
t
OEA
AA
OEZ
t
t
AA
OEZ
t
CAC
t
t
CAC
OEZ
OHO
t
t
CAC
RAC
t
OEA
t
t
t
OFF
OH
t
OHO
OHO
Dout
Dout 1
Dout 4
Dout3
29
HM5116405 Series, HM5117405 Series
Test Mode Cycle *19
*,**
Reset Cycle
Set Cycle**
Test Mode Cycle
Normal Mode
RAS
CAS
WE
*
CBR or RAS-only refresh
** Address, Din, OE: H or L
30
HM5116405 Series, HM5117405 Series
Test Mode Set Cycle
t
RC
t
t
t
RP
RP
RAS
t
t
t
t
t
CRP
RPC
CSR
CHR
RPC
t
T
t
t
t
t
CP
CP
WTS
WTH
Address
t
OFR
t
OFF
High-Z
Dout
31
HM5116405 Series, HM5117405 Series
Package Dimensions
HM5116405S/LS Series
HM5117405S/LS Series (CP-26/24DB)
Unit: mm
16.90
17.27 Max
26
1
21 19
14
13
6
8
0.74
1.30 Max
+ 0.19
– 0.18
1.27
0.10
6.79
0.43 0.10
0.41 0.08
2.54
Hitachi Code
JEDEC
EIAJ
CP-26/24DB
Conforms
Conforms
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.8 g
32
HM5116405 Series, HM5117405 Series
HM5116405TS/LTS Series
HM5117405TS/LTS Series (TTP-26/24DA)
Unit: mm
17.14
17.54 Max
26
1
21
19
14
13
6
8
1.27
0.80
0.42 0.08
0.40 0.06
M
0.21
1.15 Max
9.22 0.20
0 – 5
0.50 0.10
2.54
0.10
Hitachi Code
JEDEC
EIAJ
TTP-26/24DA
Conforms
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.30 g
33
HM5116405 Series, HM5117405 Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi Semiconductor
(America) Inc.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1897
U S A
Hitachi Europe GmbH
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 01628-585000
Fax: 01628-585160
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Tel: 800-285-1601
Fax:303-297-0447
Tel: 089-9 91 80-0
Fax: 089-9 29 30-00
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
34
HM5116405 Series, HM5117405 Series
Revision Record
Rev. Date
Contents of Modification
Drawn by Approved by
Y. Kasama M. Mishima
Y. Kasama Y. Matsuno
1.0
2.0
Oct. 14, 1996
Nov. 8, 1996
Initial issue
Addition of HM5116405-5 Series
Addition of HM5117405-5 Series
Power dissipation (active)
550/495 mW(max) to 495/440/385 mW (max)
(HM5116405 Series)
605/550 mW(max) to 550/495/440 mW (max)
(HM5117405 Series)
DC Characteristics (HM5116405 Series)
ICC7 max: 110/100 mA to 80/70/65 mA
DC Characteristics (HM5117405 Series)
ICC1 max: 110/100 mA to 100/90/80 mA
ICC3 max: 110/100 mA to 100/90/80 mA
ICC6 max: 110/100 mA to 100/90/80 mA
ICC7 max: 110/100 mA to 90/80/75 mA
AC Characteristics
tRCD min: 20/20 ns to 11/14/14 ns
tRAD min: 15/15 ns to 9/12/12 ns
tRSH min: 15/18 ns to 10/13/13 ns
tRRH min: 0/0 ns to 5/5/5 ns
tRWC min: 149/175 ns to 111/135/161 ns
tRWD min: 82/95 ns to 67/79/92 ns
tCWD min: 37/43 ns to 30/34/40 ns
tAWD min: 52/60 ns to 42/49/57 ns
tRPC min: 0/0 ns to 5/5/5 ns
tHPRWC min: 79/90 ns to 57/68/79 ns
Timing Waveforms
Addition of tRNCD timing to EDO page mode mix
cycle (2)
3.0
4.0
Feb. 27, 1997
Nov. 1997
AC Characteristics
tRRH min: 5/5/5 ns to 0/0/0 ns
Y. Kasama Y. Matsuno
Change of Subtitle
35
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