HN29V102414T-50H_技术文档

HN29V102414T-50H

•

Erase mode

Single sector erase ((2048 + 64) byte unit)

•

Fast serial read access time:

First access time: 50 µs (max)

Serial access time: 50 ns (max)

•

Low power dissipation:

I_CC1= 2 mA (typ) (Read) (1-chip operation)

I_CC1= 4 mA (typ) (Read) (2-chip operation)

I_CC2= 20 mA (max) (Read) (1-chip operation)

I_CC2= 40 mA (max) (Read) (2-chip operation)

I_SB2= 50 µA (max) (Standby) (1-chip operation)

I_SB2= 100 µA (max) (Standby) (2-chip operation)

I_CC3/I_CC4= 40 mA (max) (Erase/Program) (1-chip operation)

I_CC3/I_CC4= 80 mA (max) (Erase/Program) (2-chip operation)

I_SB3= 20 µA (max) (Deep standby) (1-chip operation)

I_SB3= 40 µA (max) (Deep standby) (2-chip operation)

The following architecture is required for data reliability.

Error correction: more than 3-bit error correction per each sector read

Spare sectors: 1.8% (579 sectors)/chip (min) within usable sectors

•

Ordering Information

Type No.

Available sector

Package

HN29V102414T-50H

More than 64,226 sectors 12.0 × 20.00 mm²0.5 mm pitch

48-pin plastic TSOP I (TFP-48DA)

2

HN29V102414T-50H

Pin Arrangement

48-pin TSOP

2

3

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

V

NC*

*

V

*

1

CC

1, 2

1, 3

NC*

2

NC*

3

NC*

4

2

*

3

*

V

5

SS

2

3

RES*

RDY/Busy*

SC*

RES*

6

3

RDY/Busy*

7

3

SC*

8

3

OE*

I/O0*

9

3

I/O0*

I/O1*

I/O2*

I/O3*

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

3

I/O1*

3

I/O2*

3

I/O3*

3

V

*

V

*

CC

3

V

*

SS

3

I/O4*

I/O5*

I/O6*

I/O7*

CDE*

WE*

I/O4*

I/O5*

I/O6*

I/O7*

3

CDE*

3

WE*

CE*

NC*

3

CE*

1, 2

1, 3

NC*

V

2

*

3

*

V

SS

(Top view)

Note: 1. This pin can be used as the V_SSpin.

2. Upper chip.

3. Lower chip.

3

HN29V102414T-50H

Pin Description

Pin name

I/O0 to I/O7

CE

Function

Input/output

Chip enable

Output enable

Write enable

Command data enable

Power supply

Ground

OE

WE

CDE

V_CC*¹

V_SS*¹

RDY/Busy

RES

Ready/Busy

Reset

SC

Serial clock

No connection

NC

Note: 1. All V_CCand V_SSpins should be connected to a common power supply and a ground, respectively.

4

HN29V102414T-50H

Block Diagram

Upper chip

2048 + 64

Sector

address

buffer

X-decoder

32768 × (2048 + 64) × 8

memory matrix

Data register (2048 + 64)

• •

I/O0

to

I/O7

Data

input

buffer

Input

data

control

Data

output

buffer

•

Y-gating

Multiplexer

Y-decoder

• •

• • •

RDY/Busy

Y-address

counter

•

V

CC

V

SS

CE

OE

Read/Program/Erase control

Control

signal

buffer

WE

SC

RES

CDE

Lower chip

2048 + 64

Sector

address

X-decoder

32768 × (2048 + 64) × 8

buffer

memory matrix

Data register (2048 + 64)

• •

I/O0

to

I/O7

Data

input

buffer

Input

data

control

Data

output

buffer

•

Y-gating

Multiplexer

Y-decoder

• •

• • •

RDY/Busy

Y-address

counter

•

V

CC

V

SS

CE

OE

Read/Program/Erase control

Control

signal

buffer

WE

SC

RES

CDE

5

HN29V102414T-50H

Memory Map and Address

Sector address

2048 bytes

64 bytes

7FFFH

7FFEH

7FFDH

2048 bytes

64 bytes

0002H

0001H

2048 bytes

0000H

000H

Column address

83FH

800H

2048 + 64 bytes

Control bytes

Address

Cycles

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

A0 A1 A2 A3 A4 A5 A6 A7

Sector address SA (1): First cycle

SA (2): Second cycle A8 A9 A10 A11 A12 A13 A14 ×*²

Column address CA (1): First cycle A0 A1 A2 A3 A4 A5 A6 A7

CA (2): Second cycle A8 A9 A10 A11

×

Notes: 1. Some failed sectors may exist in the device. The failed sectors can be recognized

by reading the sector valid data written in a part of the column address 800 to 83F

(The specific address is TBD.). The sector valid data must be read and kept outside

of the sector before the sector erase. When the sector is programmed, the sector

valid data should be written back to the sector.

2. An × means "Don't care". The pin level can be set to either V or V , referred

IL

IH

to DC characteristics.

6

HN29V102414T-50H

Pin Function

CE: CE is used to select the device. The status returns to the standby at the rising edge of CE in the reading

operation. However, the status does not return to the standby at the rising edge of CE in the busy state in

programming and erase operation.

OE: Memory data and status register data can be read, when OE is V_IL.

WE: Commands and address are latched at the rising edge of WE.

SC: Programming and reading data is latched at the rising edge of SC.

RES: RES pin must be kept at the V_ILR(V_SS± 0.2 V) level when V_CCis turned on and off. In this way, data

in the memory is protected against unintentional erase and programming. RES must be kept at the V_IHR(V_CC

± 0.2 V) level during any operations such as programming, erase and read.

CDE: Commands and data are latched when CDE is V_ILand address is latched when CDE is V_IH.

RDY/Busy: The RDY/Busy indicates the program/erase status of the flash memory. The RDY/Busy signal

is initially at a high impedance state. It turns to a V_OLlevel after the (40H) command in programming

operation or the (B0H) command in erase operation. After the erase or programming operation finishes, the

RDY/Busy signal turns back to the high impedance state.

I/O0 to I/O7: The I/O pins are used to input data, address and command, and are used to output memory data

and status register data.

Mode Selection

Mode

CE

×*⁴

V_IH

V_IL

OE

×

WE

×

SC

×

RES CDE RDY/Busy*³I/O0 to I/O7

Deep standby

Standby

V_ILR

V_IHR

×

V_OH

High-Z

×

High-Z

Output disable

Status register read*¹

Command write*²

V_IH

V_IL

V_IH

V_IL

×

High-Z

×

Status register outputs

Din

V_IL

V_IHRV_IL

Notes: 1. Default mode after the power on is the status register read mode (refer to status transition). From

I/O0 to I/O7 pins output the status, when CE = V_ILand OE = V_IL(conventional read operation

condition).

2. Refer to the command definition. Data can be read, programmed and erased after commands are

written in this mode.

3. The RDY/Busy bus should be pulled up to V_CCto maintain the V_OHlevel while the RDY/Busy pin

outputs a high impedance.

4. An × means “Don’t care”. The pin level can be set to either V_ILor V_IHreferred to DC characteristics.

7

HN29V102414T-50H

Command Definition*^{1, 2}

First bus cycle

Second bus cycle

Bus

cycles mode*³

Operation Data in Operation Data in Data out

Command

mode

Write

Read

Serial read (1) (Without CA)

(With CA)

3

Write

00H

F0H

90H

01H

SA (1)*⁴

3 + 2h*⁶Write

Serial read (2)

3

1

Write

Read identifier codes

Data recovery read

ID*^{8, 9}

Recovery

data

Auto erase

Single sector

4

Write

20H

10H

Write

SA (1)*⁴

Auto program Program (1) (Without

CA*⁷)

(With CA*⁷)

4 + 2h*⁶Write

10H

1FH

0FH

11H

FFH

50H

12H

Write

SA (1)*⁴

Program (2)*¹⁰

4

Write

Program (3) (Control bytes)*⁷4

Program (4) (WithoutCA*⁷) 4

(With CA*⁷)

4 + 2h*⁶Write

Reset

1

4

Write

Clear status register

Data recovery write

Write

SA (1)*⁴

8

HN29V102414T-50H

Third bus cycle

Fourth bus cycle

Bus

Operation Data in

mode

Command

cycles mode

Write

3 + 2h*⁶Write

Read

Serial read (1) (Without CA)

(With CA)

3

SA (2)*⁴

Write

CA (1)*⁵

Serial read (2)

3

1

4

Write

Read identifier codes

Data recovery read

Single sector

Auto erase

Write

SA (2)*⁴

Write

B0H*¹¹

40H^{*11, 12}

Auto program Program (1) (Without

CA*⁷)

(With CA*⁷)

4 + 2h*⁶Write

SA (2)*⁴

Write

CA (1)

Program (2)*¹⁰

4

Write

40H^{*11, 12}

CA (1)

Program (3) (Control bytes)*⁷4

Program (4) (WithoutCA*⁷) 4

(With CA*⁷)

4 + 2h*⁶Write

Reset

1

Clear status register

Data recovery write

4

Write

SA (2)*⁴

Write

40H^{*11, 12}

9

HN29V102414T-50H

Fifth bus cycle

Sixth bus cycle

Bus

cycles mode

Operation Data in

mode

Command

Read

Serial read (1) (Without CA)

(With CA)

3

3 + 2h*⁶Write

CA (2)*⁵

Serial read (2)

3

1

4

Read identifier codes

Data recovery read

Single sector

Auto erase

Auto program Program (1) (Without

CA*⁷)

(With CA*⁷)

4 + 2h*⁶Write

4

CA (2)*⁵

CA (2)

Write

40H^{*11, 12}

Program (2)*¹⁰

Program (3) (Control bytes)*⁷4

Program (4) (WithoutCA*⁷) 4

(With CA*⁷)

4 + 2h*⁶Write

40H^{*11, 12}

Reset

1

4

Clear status register

Data recovery write

Notes: 1. Commands and sector address are latched at rising edge of WE pulses. Program data is latched

at rising edge of SC pulses.

2. The chip is in the read status register mode when RES is set to V_IHRfirst time after the power up.

3. Refer to the command read and write mode in mode selection.

4. SA (1) = Sector address (A0 to A7), SA (2) = Sector address (A8 to A14).

5. CA (1) = Column address (A0 to A7), CA (2) = Column address (A8 to A11).

(0 ≤ A11 to A0 ≤ 83FH)

6. The variable h is the input number of times of set of CA (1) and CA (2) (1 ≤ h ≤ 2048 + 64).

Set of CA (1) and CA (2) can be input without limitation.

7. By using program (1) and (3), data can additionally be programmed maximum 15 times for each

sector before erase.

8. ID = Identifier code; Manufacturer code (07H), Device code (9DH).

9. The manufacturer identifier code is output when CDE is low and the device identifier code is output

when CDE is high.

10. Before program (2) operations, data in the programmed sector must be erased.

11. No commands can be written during auto program and erase (when the RDY/Busy pin outputs a

V_OL).

12. The fourth or sixth cycle of the auto program comes after the program data input is complete.

10

HN29V102414T-50H

Mode Description

Read

Serial Read (1): Memory data D0 to D2111 in the sector of address SA is sequentially read. Output data is

not valid after the number of the SC pulse exceeds 2112. When CA is input, memory data D (m) to D (m + j)

in the sector of address SA is sequentially read. Then output data is not valid after the number of the SC pulse

exceeds (2112 to m). The mode turns back to the standby mode at any time when CE is V_IH.

Serial Read (2): Memory data D2048 to D2111 in the sector of address SA is sequentially read. Output data

is not valid after the number of the SC pulse exceeds 64. The mode turns back to the standby mode at any

time when CE is V_IH.

Automatic Erase

Single Sector Erase: Memory data D0 to D2111 in the sector of address SA is erased automatically by

internal control circuits. After the sector erase starts, the erasure completion can be checked through the

RDY/Busy signal and status data polling. All the bits in the sector are "1" after the erase. The sector valid

data stored in a part of memory data D2048 to D2111 must be read and kept outside of the sector before the

sector erase.

Automatic Program

Program (1): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by

internal control circuits. When CA is input, program data PD (m) to PD (m + j) is programmed from CA into

the sector of address SA automatically by internal control circuits. By using program (1), data can

additionally be programed 15 times for each sector before the following erase. When the column is

programmed, the data of the column must be [FF]. After the programming starts, the program completion can

be checked through the RDY/Busy signal and status data polling. Programmed bits in the sector turn from

"1" to "0" when they are programmed. The sector valid data should be included in the program data PD2048

to PD2111.

Program (2): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by

internal control circuits. After the programming starts, the program completion can be checked through the

RDY/Busy signal and status data polling. Programmed bits in the sector turn from "1" to "0" when they are

programmed. The sector must be erased before programming. The sector valid data should be included in the

program data PD2048 to PD2111.

Program (3): Program data PD2048 to PD2111 is programmed into the sector of address SA automatically

by internal control circuits. By using program (3), data can additionally be programed 15 times for each

sector befor the following erase. When the column is programmed, the data of the column must be [FF].

After the programming starts, the program completion can be checked through the RDY/Busy signal and

status data polling. Programmed bits in the sector turn from "1" to "0" when they are programmed.

11

HN29V102414T-50H

Program (4): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by

internal control circuits. When CA is input, program data PD (m) to PD (m + j) is programmed from CA into

the sector of address SA automatically by internal control circuits. By using program (4), data can be

rewritten for each sector before the following erase. So the column data before programming operation are

either "1" or "0". In this mode, E/W number of times must be counted whenever program (4) execute. After

the programming starts, the program completion can be checked through the RDY/Busy signal and status data

polling. The sector valid data should be included in the program data PD2048 to PD2111.

32767

Sector

address

Sector

address

Sector

address

Memory array

0

2111

2048

Column address

Register

Serial read (1) (Without CA)

Program (1) (Without CA)

Program (2)

Serial read (1) (With CA)

Program (1) (With CA)

Serial read (2)

Program (3)

Status Register Read

The status returns to the status register read mode from standby mode, when CE and OE is V_IL. In the status

register read mode, I/O pins output the same operation status as in the status data polling defined in the

function description.

Identifier Read

The manufacturer and device identifier code can be read in the identifier read mode. The manufacturer and

device identifier code is selected with CDE V_ILand V_IH, respectively.

12

HN29V102414T-50H

Data Recovery Read

When the programming was an error, the program data can be read by using data recovery read. When an

additional programming was an error, the data compounded of the program data and the origin data in the

sector address SA can be read. Output data are not valid after the number of SA pulse exeeds 2112. The

mode turns back to the standby mode at any time when CE is V_IH. The read data are invalid when addresses

are latched at a rising edge of WE pulse after the data recovery read command is written.

Data Recovery Write

When the programming into a sector of address SA was an error, the program data can be rewritten

automatically by internal control circuit into the other selected sector of address SA’. Since the data recovery

write mode is internally Program (4) mode, rewritten sector of address SA’ needs no sector erase before

rewrite. After the data recovery write mode starts, the program completion can be checked through the

RDY/Busy signal and the status data polling.

13

HN29V102414T-50H

Command/Address/Data Input Sequence

Serial Read (1) (With CA before SC)

Command

00H

SA (1)

SA (2)

CA (1)

CA (2)

CA (1)'

CA (2)'

/Address

CDE

WE

Low

SC

Data output

Serial Read (1) (With CA after SC)

Command

/Address

00H

SA (1)

SA (2)

CA (1)

CA (2)

CA (1)'

CA (2)'

CDE

WE

Low

SC

Data output

Serial Read (1) (Without CA), (2)

Command/Address

00H/F0H

SA (1)

SA (2)

CDE

WE

Low

SC

Data output

Single Sector Erase

Command/Address

20H

SA (1)

SA (2)

B0H

CDE

WE

SC

Low

Erase start

14

HN29V102414T-50H

Program (1), (4) (With CA before SC)

Command

/Address

10H/11H

SA (1)

SA (2)

CA (1)

CA (2)

CA (1)'

CA (2)'

40H

CDE

WE

Low

SC

Data input

Program start

Program (1), (4) (With CA after SC)

Command

/Address

10H/11H

SA (1)

SA (2)

CA (1)

CA (2)

CA (1)'

CA (2)'

40H

CDE

WE

Low

SC

Data input

Program start

Program (1), (4) (Without CA)

Command/Address

10H/11H

SA (1)

SA (2)

40H

CDE

WE

SC

Low

Data input

Program start

Program (2)

Command/Address

1FH

SA (1)

SA (2)

40H

CDE

WE

SC

Low

Data input

Program start

15

HN29V102414T-50H

Program (3)

Command/Address

0FH

SA (1)

SA (2)

40H

CDE

WE

SC

Low

Data input

Program start

ID Read Mode

Command/Address

90H

CDE

WE

SC

Low

Manufacture Device code Manufacture

code output output

code output

Data Recovery Read Mode

Command/Address

01H

CDE

WE

SC

Low

Data output

Data Recovery Write Mode

Command/Address

12H

SA (1)

SA (2)

40H

CDE

WE

SC

Low

Program start

16

HN29V102414T-50H

Status Transition

V

Column address

Deep

standby

CC

Power off

00H/F0H

input

OE

SC

CA(1)'

CA(2)'

CA(1)

CA(2)

RES

SA (1), SA (2)

OE, SC

Read (1) / (2)

setup

Sector address

input

Read (1) / (2)

FFH

CE

90H

CDE, OE

ID read setup

ID read

FFH

CE

BUSY

OE

SA (1), SA (2)

Erase finish

20H

FFH

B0H

Status register

read

Sector

Erase setup

Sector

address input

Erase

start

SC, CDE

PD(m)

to

Column address

input

CA(1)'

CA(1)

CA(2)

PD(m+j)

CA(2)'

PD0 to

10H

/11H

SA (1),

SA (2)

PD2111

CE

OE

40H

Output

disable

Program

(1)/(4) setup

Status register

read

Sector address

input

Program

data input

Program

start

Standby

FFH

SC, CDE

Program finish

PD0 to

PD2111*3

1FH

/0FH

SA (1),

SA (2)

40H

Status register

read

Sector address

input

Program

data input

Program

start

Program (2)/(3)

setup

SC, CDE

FFH

Program finish

Program error or

Erase error

Status register clear 50H

2

CE*

2

FFH*

ERROR

1

01H*

OE, SC

Data recovery

read setup

Data recovery

read

SA(1)

SA(2)

CE

1

Error

standby

12H*

40H

Output

disable

Data recovery

write setup

Sector address

input

FFH

OE

Status register

read

OE

Status register

read

Notes: 1. (01H)/(12H) Data recovery read/write can be used only for Program (1), (2), (3), (4) errors.

2. When reset is done by CE or FFH, error status flag is cleared.

3. When Program (3) mode, input data is PD2048 to PD2111.

17

HN29V102414T-50H

Absolute Maximum Ratings

Parameter

Symbol

V_CC

Value

Unit

V

Notes

V_CCvoltage

–0.6 to +4.6

0

1

V_SSvoltage

V_SS

V

All input and output voltages

Operating temperature range

Storage temperature range

Storage temperature under bias

Notes: 1. Relative to V_SS.

Vin, Vout

Topr

–0.6 to +4.6

0 to +70

–65 to +125

–10 to +80

V

1, 2

3

˚C

Tstg

Tbias

2. Vin, Vout = –2.0 V for pulse width ≤ 20 ns.

3. Device storage temperature range before programming.

Capacitance (Ta = 25˚C, f = 1 MHz)

Parameter

Symbol

Cin

Min Typ Max Unit Test conditions

Input capacitance

Output capacitance

—

6

pF

Vin = 0 V

Cout

12

Vout = 0 V

18

HN29V102414T-50H

DC Characteristics (V_CC= 2.7 V to 3.6 V, Ta = 0 to +70˚C)

Parameter

Symbol Min

Typ

—

Max

Unit

Test conditions

Vin = V_SSto V_CC

Vout = V_SSto V_CC

CE = V_IH

Input leakage current

Output leakage current

I_LI

—

2

1

µA

mA

I_LO

I_SB1

—

Standby V_CCcurrent

(1-chip operation)

0.3

(2-chip operation)

(1-chip operation)

I_SB1

I_SB2

—

0.6

30

2

mA

µA

50

CE = V_CC± 0.2 V,

RES = V_CC± 0.2 V

(2-chip operation)

I_SB2

I_SB3

—

60

1

100

20

µA

Deep standby V_CCcurrent

(1-chip operation)

RES = V_SS± 0.2 V

(2-chip operation)

I_SB3

I_CC1

—

2

40

20

µA

Operating V_CCcurrent

(1-chip operation)

mA

Iout = 0 mA, f = 0.2 MHz

(2-chip operation)

(1-chip operation)

(2-chip operation)

I_CC1

I_CC2

I_CC3

—

4

40

20

40

mA

10

20

Iout = 0 mA, f = 20 MHz

In programming

Operating V_CCcurrent (Program)

(1-chip operation)

(2-chip operation)

I_CC3

I_CC4

—

40

20

80

40

mA

Operating V_CCcurrent (Erase)

(1-chip operation)

In erase

(2-chip operation)

Input voltage

I_CC4

V_IL

—

–0.3*^{1, 2}

40

—

80

mA

V

0.8

V_IH

2.0

V_CC+ 0.3*³V

Input voltage (RES pin)

V_ILR

V_IHR

–0.2

0.2

V

V_CC

0.2

–

V_CC+ 0.2

Output voltage

V_OL

V_OH

—

0.4

—

V

I_OL= 2 mA

2.4

I_OH= –2 mA

Notes: 1. V_ILmin = –1.0 V for pulse width ≤ 50 ns in the read operation. V_ILmin = –2.0 V for pulse width ≤ 20

ns in the read operation.

2. V_ILmin = –0.6 V for pulse width ≤ 20 ns in the erase/data programming operation.

3. V_IHmax = V_CC+ 1.5 V for pulse width ≤ 20 ns. If V_IHis over the specified maximum value, the

operations are not guaranteed.

19

HN29V102414T-50H

AC Characteristics (V_CC= 2.7 V to 3.6 V, Ta = 0 to +70˚C)

Test Conditions

•

Input pulse levels: 0.4 V/2.4 V

Input pulse levels for RES: 0.2 V/V_CC– 0.2 V

Input rise and fall time: ≤ 5 ns

Output load: 1 TTL gate + 100 pF (Including scope and jig.)

Reference levels for measuring timing: 0.8 V, 1.8 V

20

HN29V102414T-50H

Power on and off, Serial Read Mode

Parameter

Symbol

t_CWC

t_SCC

t_CES

t_CEH

t_WP

Min

120

50

0

Typ

—

Max

—

50

—

40

—

Unit

ns

Test conditions

Notes

Write cycle time

Serial clock cycle time

CE setup time

CE hold time

0

Write pulse time

60

40

50

10

50

10

—

0

CE = V_IL, OE = V_IH

Write pulse high time

Address setup time

Address hold time

Data setup time

t_WPH

t_AS

t_AH

t_DS

Data hold time

t_DH

SC to output delay

OE setup time for SC

OE low to output low-Z

OE setup time before read

t_SAC

t_OES

t_OEL

t_OER

t_OEWS

CE = OE = V_IL, WE = V_IH

0

100

0

OE setup time before

command write

SC to output hold

t_SH

15

—

50

0.3

50

20

0

—

40

—

ns

µs

ms

ns

µs

ns

CE = OE = V_IL, WE = V_IH

CE = V_IL, WE = V_IH

OE high to output float

WE to SC delay time

RES to CE setup time

SC to OE hold time

SC pulse width

t_DF

1

2

t_WSD

t_RP

t_SOH

t_SP

SC pulse low time

t_SPL

t_SCS

t_CDS

t_CDH

t_VRS

t_VRH

t_CESR

SC setup time for CE

CDE setup time for WE

CDE hold time for WE

V_CCsetup time for RES

RES to V_CChold time

CE setup time for RES

0

20

1

CE = V_IH

1

RDY/Busy undefined for V_CCt_DFP

off

0

RES high to device ready

CE pulse high time

t_BSY

t_CPH

—

200

0

—

0.3

—

ms

ns

CE, WE setup time for RES t_CWRS

RES to CE, WE hold time t_CWRH

0

21

HN29V102414T-50H

Parameter

Symbol

Min

50

0

Typ

—

Max

—

Unit

ns

Test conditions

Notes

SC setup for WE

t_SW

CE hold time for OE

SA (2) to CA (2) delay time

RDY/Busy setup for SC

Time to device busy

Busy time on read mode

t_COH

t_SCD

t_RS

—

ns

—

30

µs

200

—

ns

t_DB

—

150

—

ns

t_RBSY

—

45

µs

Notes: 1. t_DFis a time after which the I/O pins become open.

2. t_WSD(min) is specified as a reference point only for SC, if t_WSDis greater than the specified t_WSD(min)

limit, then access time is controlled exclusively by t_SAC

.

22

HN29V102414T-50H

Program, Erase and Erase Verify

Parameter

Symbol Min

Typ

—

Max

—

Unit Test conditions

Note

Write cycle time

Serial clock cycle time

CE setup time

t_CWC

t_SCC

t_CES

t_CEH

t_WP

t_WPH

t_AS

120

50

0

ns

CE hold time

0

Write pulse time

Write pulse high time

Address setup time

Address hold time

Data setup time

Data hold time

60

40

50

10

50

10

0

t_AH

t_DS

t_DH

OE setup time before command t_OEWS

write

OE setup time before status

polling

t_OEPS

40

—

ns

OE setup time before read

Time to device busy

Auto erase time

t_OER

t_DB

t_ASE

t_ASP

100

—

ns

—

150

10.0

20.0

ns

—

1.0

1.5

ms

Auto program time

Program(1), (3)

—

Program(2)

t_ASP

—

1.0

2.0

20.0

30.0

ms

Program(4),

Data recovery write

WE to SC delay time

CE pulse high time

SC pulse width

t_WSD

t_CPH

t_SP

50

200

20

0

—

µs

ns

SC pulse low time

Data setup time for SC

Data hold time for SC

SC setup for WE

t_SPL

t_SDS

t_SDH

t_SW

30

50

0

CDE = V_IL

SC setup for CE

t_SCS

t_SCHW

SC hold time for WE

20

23

HN29V102414T-50H

Parameter

Symbol Min

Typ

—

45

Max

120

60

40

—

Unit Test conditions

Note

CE to output delay

t_CE

—

0.3

0

ns

ms

ns

µs

ns

µs

OE to output delay

t_OE

OE high to output float

RES to CE setup time

CDE setup time for WE

CDE hold time for WE

CDE setup time for SC

CDE hold time for SC

Next cycle ready time

CDE to OE hold time

CDE to output delay

CDE to output invalid

CE hold time for OE

OE setup time for SC

OE low to output low-Z

SC to output delay

t_DF

1

t_RP

t_CDS

t_CDH

t_CDSS

t_CDSH

t_RDY

t_CDOH

t_CDAC

t_CDF

t_COH

t_OES

t_OEL

t_SAC

t_SH

—

20

1.5

30

0

—

50

—

0

—

50

100

—

0

—

0

40

50

—

15

200

—

SC to output hold

RDY/Busy setup for SC

Busy time on read mode

t_RS

—

t_RBSY

—

Note: 1. t_DFis a time after which the I/O pins become open.

24

HN29V102414T-50H

Timing Waveforms

Power on and off Sequence

V

CC

t

VRS

CE

t

RP

t

RP

CES

CEH CESR

CES

CEH

CESR

WE

t

CWRH

t

CWRS

t

DFP

VRH

1

2

*

1

RES

*

t

BSY

Ready

High-Z

RDY

/Busy

Notes: 1. RES must be kept at the V

level referred to DC characteristics at the rising and falling edges of V

CC

ILR

to guarantee data stored in the chip.

2. RES must be kept at the V

level referred to DC characteristics while I/O7 outputs the V level in the

IHR

OL

status data polling and RDY/Busy outputs the V level.

OL

3.

: Undefined

25

HN29V102414T-50H

Serial Read (1) (2) Timing Waveform

1

3

*

t

COH

CE

t

CPH

t

CEH

CES

OE

WE

t

CWC

t

CWC

t

OER

WPH

OEWS

t

CDS

t

CDH

t

WP

t

CDS

t

CDE

OES

t

WSD

t

SOH

2

SCC

t

SCC

*

t

CDS

CDH

t

SC

t

SP

t

AH

t

SAC

DS DH

DH

t

AH

t

DF

SAC

SPL

SAC

t

AS

SCS

SAC SH

SH

DS

AS

t

OEL

I/O0 to I/O7

00H

/F0H

SA(1)

SA(2)

DB

D0out/D2048out D1out/D2049out

D2111out/D2111out

FFH

2

*

RES

t

RBSY

t

RP

RS

t

High-Z

RDY

/Busy

Notes: 1. The status returns to the standby at the rising edge of CE.

2. Output data is not valid after the number of the SC pulse exceeds 2112 and 64 in the serial read mode (1)and (2), respectively.

3. After any commands are written, the status can return to the standby after the command FFH is input and CE turns to the V level.

IH

Serial Read (1) with CA before SC Timing Waveform

5

*

h-1 cycle

1

*

t

COH

CE

OE

t

4

CPH

t

*

t

CES

t

CEH

t

OEWS

t

CWC

t

CWC

t

CWC

t

CWC

t

OER

t

WPH

OEWS

WE

CDE

SC

t

SW

t

WP

CDS

t

WP

CDS

WP

t

CDH

WP

t

SCD

OES

t

2

3

t

SOH

t

*

t

SCC

t

SOH

SCC

OES

SCC

WSD

t

CDH

CDS

t

SP

t

AS

t

DF

t

SAC

t

SPL

t

DS

t

SP

t

DF

t

SCS

t

SAC

t

AH

SAC

SPL

DS DH

00H

t

SAC

AS AH

AS

SAC

AS AH

DH

t

OEL

t

SH

AH

SH

t

OEL

I/O0 to I/O7

3

SA(1)

CA(1)

CA(2)

D(n)out

D(n+1)out

D(n+i)out

CA(1)'

CA(2)'

D(m)out

D(m+1)out

D(m+j)out

FFH

2

*

SA(2)

*

t

RP

RES

t

High-Z

DB

RS

t

RBSY

RDY

/Busy

Notes: 1. The status returns to the Standby at the rising edge of CE.

2. Output data is not valid after the number of the SC pulse exceeds (2112-n). (i ≤ 2111-n, 0 ≤ n ≤ 2111)

3. Output data is not valid after the number of the SC pulse exceeds (2112-m). (j ≤ 2111-m, 0 ≤ m ≤ 2111)

4. After any commands are written, the status can return to the standby after the command FFH is input and CE turns

to the V level.

IH

5. This interval can be repeated (h-1) cycle. (1≤ h ≤ 2048 + 64)

26

HN29V102414T-50H

Serial Read (1) with CA after SC Timing Waveform

5

*

h cycle

t

1

t

COH

*

CE

4

*

CPH

t

CES

CEH

t

OE

t

OEWS

CWC

t

CWC

t

CWC

t

OER

t

OER

t

WPH

OEWS

WE

CDE

SC

t

SW

t

WP

t

WP

t

CDH

WP

t

WP

t

OES

t

CDH

OES

t

SOH

t

SCC

t

SCC

2

SOH

3

SCC

WSD

SCC

*

t

CDS

t

SP

t

SAC

DF

t

SAC

t

SAC

t

DF

SP SPL

SAC

t

AH

SPL

SAC

t

AH

t

SCS

t

AS

t

DS

t

OEL

t

DH

DS DH

AS AH

AS

SH

t

SH

t

OEL

I/O0 to I/O7

2

D(k)out

3

D(m+j)out

*

FFH

00H

SA(1)

D0out

D1out

CA(1)

CA(2)

D(m)out

D(m+1)out

SA(2)

*

t

RP

RES

t

RBSY

t

DB

High-Z

RS

RDY

/Busy

Notes: 1. The status returns to the Standby at the rising edge of CE.

2. Output data is not valid after the number of the SC pulse exceeds 2112. (0 ≤ k ≤ 2111)

3. Output data is not valid after the number of the SC pulse exceeds (2112-m). (j ≤ 2111-m, 0 ≤ m ≤ 2111)

4. After any commands are written, the status can return to the standby after the command FFH is input and CE turns to the V level.

IH

5. This interval can be repeated h cycle. (1≤ h ≤ 2048 + 64)

Erase and Status Data Polling Timing Waveform (Sector Erase)

CE

t

CE

CEH

t

CES

t

OE

t

OE

WE

t

CWC

t

CWC

t

OEPS

t

RDY

ASE

t

WPH

OEWS

t

CDS

t

CDS

t

WP

tWP

WP

t

CDS

t

CDS

CDE

t

CDH

SCHW

t

CDH

SC

t

DH

t

AH

t

DF

t

DF

t

DS

SCS

DS

AS

I/O0 to I/O7

RES

IO7 = V

OH

20H

SA(1)

SA(2)

B0H

OL

2

*

t

DB

RP

High-Z

RDY

/Busy

1

*

Notes: 1. Any commands,including reset command FFH, cannot be input while RDY/Busy outputs a V

2. The status returns to the standby status after RDY/Busy returns to High-Z.

.

OL

27

HN29V102414T-50H

Program (1) and Status Data Polling Timing Waveform

CE

t

CES

CEH

t

CE

t

OE

t

OEWS CWC

CWC

t

OEPS

RDY

WPH

OE

WE

t

CDS

t

ASP

t

CDSS

t

CDS

t

WP

CDS

t

WP

t

SW

WP

CDE

t

SCC

t

CDH

t

1

CDH

t

*

t

SCHW

SPL

SC

t

DF

t

DH

AH

DF

SDH

t

DS

t

SP

DS

DH

SCS

SP

t

AS

SDS

I/O0 to I/O7

10H

SA (1) SA (2)

High-Z

PD0

PD1

PD2111

40H

I/O7 = V

OH

OL

RES

t

3

DB

*

t

High-Z

RP

RDY

/Busy

2

*

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 2112.

2. Any commands, including reset command FFH, cannot be input while RDY/Busy is V

3. The status returns to the standby status after RDY/Busy returns to High-Z.

.

OL

4. By using program (1), data can be programmed additionally for each sector before erase.

28

HN29V102414T-50H

Program (1) with CA before SC and Status Data Polling Timing Waveform

6

h–1 cycle*

CE

t_CES

t_CEHt_CE

OE

t_CWC

t_WPH

t_CWC

t_WPH

t_CWC

t_WPH

t_CWC

t_WPH

t_CWC

t_WPH

t_OEWS

t_OEPS

t_OE

t_RDY

WE

t_SW

t_CDS

t_WP

t_SW

t_ASP

t_CDS

t_CDSS

CDE

t_CDH

t_SCHW

t_SCC

t_SPL

t_SCC

t_SPL

t_SCS

t_CDSH

t_AS

1

t_CDH

1

*

2

*

SC

t_AH

t_ASt_SDS

t_SDH

t_AH

t_SDS

t_SDH

t_DH

t_DF

t_SP

t_DS

t_AS

t_DS

t_AS

t_DH

t_AS

I/O0 to I/O7

2

10H

SA(1)

SA(2)

CA(1)

CA(2) PD(n) PD(n+1)

CA(1)' CA(2)' PD(m) PD(m+1)

PD(m+j)* 40H

PD(n+i)*

I/O7=V_OL

I/O7=V_OH

RES

t_RP

t_DB

4

High-Z

High-Z*

RDY

/Busy

3

*

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – n).(i ≤ 2111 – n, 0 ≤ n ≤ 2111)

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)

3. Any commands, including reset command FFH, cannot be input while RDY/Busy is V_OL

.

4. The status returns to the standby status after RDY/Busy returns to High-Z.

5. By using program (1), data can be programmed additionally for each sector before erase.

6. This interval can be repeated (h – 1) cycle.(1 ≤ h ≤ 2048 + 64)

Program (1) with CA after SC and Status Data Polling Timing Waveform

6

h cycle*

CE

t_CES

t_CEHt_CE

OE

t_CWC

t_WPH

t_CWC

t_WPH

t_CWC

t_WPH

t_OEWS

t_OEPS

t_OE

t_RDY

WE

t_SW

t_CDS

t_WP

t_SW

t_ASP

t_CDS

t_CDSS

CDE

t_CDH

t_SCHW

t_SCC

t_SPL

t_SCC

t_SPL

t_SCS

t_CDSH

t_CDH

1

*

2

*

SC

t_AH

t_SDH

t_AH

t_SDH

t_DH

t_DF

t_SP

t_AS

t_DS

t_AS

t_DH

t_AS

t_SDS

I/O0 to I/O7

1

2

10H

SA(1)

SA(2)

PD0

PD1

CA(1)

CA(2) PD(m) PD(m+1)

PD(m+j)* 40H

PD(k)*

I/O7=V_OL

I/O7=V_OH

RES

t_RP

t_DB

4

High-Z

High-Z*

RDY

/Busy

3

*

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds 2112.(0 ≤ k ≤ 2111)

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)

3. Any commands, including reset command FFH, cannot be input while RDY/Busy is V_OL

4. The status returns to the standby status after RDY/Busy returns to High-Z.

.

5. By using program (1), data can be programmed additionally for each sector before erase.

6. This interval can be repeated h cycle.(1 ≤ h ≤ 2048 + 64)

29

HN29V102414T-50H

Program (2) and Status Data Polling Timing Waveform

CE

t

CES

CEH

t

CE

t

OE

t

OEWS CWC

CWC

t

RDY

OEPS

WPH

OE

WE

t

ASP

t

CDS

t

CDSS

t

CDS

t

WP

CDS

t

WP

t

SW

WP

CDE

t

SCC

t

CDH

t

1

CDH

t

*

t

SCHW

SPL

SC

t

DF

t

DH

AH

DF

SDH

t

DS

t

SP

DS

DH

SCS

SP

t

AS

SDS

I/O0 to I/O7

1FH

SA (1) SA (2) PD0

PD1

PD2111

40H

I/O7 = V

OH

OL

RES

t

DB

3

*

t

High-Z

RP

RDY

/Busy

2

*

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 2112.

2. Any commands, including reset command FFH, cannot be input while RDY/Busy is V

3. The status returns to the standby status after RDY/Busy returns to High-Z.

.

OL

4. By using program (2), the programmed data of each sector must be erased before programming next data.

30

HN29V102414T-50H

Program (3) and Status Data Polling Timing Waveform

CE

t

CES

CEH

t

CE

OE

t

CWC

OEWS CWC

t

OEPS

t

WPH

t

RDY

OE

WE

t

ASP

t

CDS

t

CDSS

t

CDS

t

WP

CDS

t

WP

t

SW

WP

CDE

t

SCC

t

CDH

t

1

CDH

t

*

t

SCHW

SPL

SC

t

DF

t

DH

AH

DF

SDH

t

DS

t

SP

DS

DH

SCS

SP

t

AS

SDS

I/O0 to I/O7

0FH

SA (1) SA (2) PD2048 PD2049 PD2111

40H

I/O7 = V

OH

OL

RES

t

DB

3

*

t

High-Z

RP

RDY

/Busy

2

*

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 64.

2. Any commands, including reset command FFH, cannot be input while RDY/Busy is V

3. The status returns to the standby status after RDY/Busy returns to High-Z.

.

OL

4. By using program (3), the data can be programmed additionally for each sector before erase.

31

HN29V102414T-50H

Program (4) and Status Data Polling Timing Waveform

CE

t

CES

CEH

t

CE

t

OE

t

OEWS CWC

CWC

t

RDY

OEPS

WPH

OE

WE

t

ASP

t

CDS

t

CDSS

t

CDS

t

WP

CDS

t

WP

t

SW

WP

CDE

t

SCC

t

CDH

t

1

CDH

t

*

t

SCHW

SPL

SC

WSD

t

DF

t

DH

AH

DF

SDH

t

DS

t

SP

DS

DH

SCS

SP

t

AS

SDS

I/O0 to I/O7

11H

SA (1) SA (2) PD0

PD1

PD2111

40H

I/O7 = V

OH

OL

RES

t

DB

3

DB

*

t

RS

High-Z

RP

RDY

2

*

/Busy

t

RBSY

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 2112.

2. Any commands, including reset command FFH, cannot be input while RDY/Busy is V

3. The status returns to the standby status after RDY/Busy returns to High-Z.

4. By using program (4), data can be rewritten for each sector.

.

OL

32

HN29V102414T-50H

Program (4) with CA before SC and Status Data Polling Timing Waveform

6

h–1 cycle*

CE

t_CES

t_CEHt_CE

OE

t_CWC

t_WPH

t_CWC

t_WPH

t_CWC

t_WPH

t_CWC

t_WPH

t_CWC

t_WPH

t_OEWS

t_OEPS

t_OE

t_RDY

WE

t_SW

t_CDS

t_WP

t_SW

t_ASP

t_CDS

t_CDSS

CDE

t_CDH

t_SCHW

t_SCC

t_SPL

t_SCC

t_SPL

t_SCS

t_CDSH

t_AS

1

t_CDH

1

*

2

t_WSD

*

SC

t_AH

t_ASt_SDS

t_SDH

t_AH

t_SDS

t_SDH

t_DH

t_DF

t_SP

t_DS

t_AS

t_DS

t_AS

t_DH

t_AS

I/O0 to I/O7

2

11H

SA(1)

SA(2)

CA(1)

CA(2) PD(n) PD(n+1)

CA(1)' CA(2)' PD(m) PD(m+1)

PD(m+j)* 40H

PD(n+i)*

I/O7=V_OL

I/O7=V_OH

RES

t_RP

t_DB

t_RS

t_RBSY

4

High-Z

High-Z*

RDY

/Busy

3

*

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – n).(i ≤ 2111 – n, 0 ≤ n ≤ 2111)

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)

3. Any commands, including reset command FFH, cannot be input while RDY/Busy is V_OL

4. The status returns to the standby status after RDY/Busy returns to High-Z.

5. By using program (4), data can be rewritten for each sector.

.

6. This interval can be repeated (h – 1) cycle.(1 ≤ h ≤ 2048 + 64)

Program (4) with CA after SC and Status Data Polling Timing Waveform

6

h cycle*

CE

t_CES

t_CEHt_CE

OE

t_CWC

t_WPH

t_CWC

t_WPH

t_CWC

t_WPH

t_OEWS

t_OEPS

t_OE

t_RDY

WE

t_SW

t_CDS

t_WP

t_SW

t_ASP

t_CDS

t_CDSS

CDE

t_CDH

t_SCHW

t_SCC

t_SPL

t_CDH

t_WSD

t_SCC

t_SPL

t_SCS

t_CDSH

t_CDH

1

*

2

*

SC

t_AH

t_SDH

t_AH

t_SDH

t_DH

t_DF

t_SP

t_AS

t_DS

t_AS

t_DH

t_AS

t_SDS

I/O0 to I/O7

1

2

11H

SA(1)

SA(2)

PD0

PD1

CA(1)

CA(2) PD(m) PD(m+1)

PD(m+j)* 40H

PD(k)*

I/O7=V_OL

I/O7=V_OH

RES

t_RBSY

t_DB

t_RP

t_DB

t_RS

4

High-Z

High-Z*

RDY

/Busy

3

*

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds 2112.(0 ≤ k ≤ 2111)

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)

3. Any commands, including reset command FFH, cannot be input while RDY/Busy is V_OL

4. The status returns to the standby status after RDY/Busy returns to High-Z.

5. By using program (4), data can be rewritten for each sector.

.

6. This interval can be repeated h cycle.(1 ≤ h ≤ 2048 + 64)

33

HN29V102414T-50H

ID and Status Register Read Timing Waveform

1

*

CE

t

CES

t

COH

OE

t

OEPS

OEWS

WE

CDE

t

CDOH

t

CDH

CDS

WP

t

CE

SCHW

SC

t

CDAC

t

CDAC

CDF

DF

t

DH

t

DF

t

SCS

OE

SCS

DS

OE

CDF

I/O0 to I/O7

RES

Status

register

Manufacturer Device Manufacturer

code code code

90H

t

RP

High-Z

RDY

/Busy

Note: 1. The status returns to the standby at the rising edge of CE.

34

HN29V102414T-50H

Data Recovery Read Timing Waveform

3

*

1

*

t

CPH

CE

t

CES

t

COH

CEH

OE

t

OER

OEWS

WE

CDE

SC

t

CDH

t

CDS

t

WP

CDH

t

OES

t

SOH

SCC

t

2

CDS

*

t

SP

t

SPL

t

DH

DF

t

SAC

t

SAC

t

SAC

SCS

DH

t

SH

t

DS

SH

OEL

I/O0 to I/O7

D0out

D1out

D2111out

High

2

01H

FFH

*

RES

High-Z

RDY

/Busy

Notes: 1. The status returns to the standby at the rising edge of CE.

2. Output data is not valid after the number of the SC pulse exceed 2112 in the recovery data read mode.

3. After any commands are written, the status can turns to the standby after the command FFH is input

and CE turns to the V_IHlevel.

35

HN29V102414T-50H

Data Recovery Write Timing Waveform

CE

t

CE

CEH

t

CES

t

OE

WE

t

CWC

t

CWC

t

CWC

t

OEPS

t

RDY

t

WPH

OEWS

t

CDS

t

ASP

CDS

t

WP

tWP

WP

t

CDS

t

CDS

CDE

t

CDH

SCHW

t

CDH

t

SC

t

DH

AH

t

DF

t

DF

t

DS

SCS

DS

AS

I/O0 to I/O7

IO7 = V

OH

12H

SA(1)

High

SA(2)

40H

OL

RES

2

*

t

DB

High-Z

RDY

/Busy

1

*

Notes: 1. Any commands,including reset command FFH, cannot be input while RDY/Busy is V

2. The status returns to the standby status after RDY/Busy returns to High-Z.

.

OL

36

HN29V102414T-50H

Clear Status Register Timing Waveform

1

*

CE

t_CPH

t_CES

OE

t_CEH

t_OEWS

t_WPH

WE

CDE

SC

t_CDS

t_CDH

t_WP

t_CDH

t_WP

t_CDS

t_SCS

t_DS

t_DH

tDS tDH

I/O0 to I/O7

50H

RES

High

High-Z

RDY

/Busy

Note 1. The status returns to the standby at the rising edge of CE.

37

HN29V102414T-50H

Function Description

Status Register: The HN29V102414T-50H outputs the operation status data as follows: I/O7 pin outputs a

V_OLto indicate that the memory is in either erase or program operation. The level of I/O7 pin turns to a V_OH

when the operation finishes. I/O5 and I/O4 pins output V_OLs to indicate that the erase and program operations

complete in a finite time, respectively. If these pins output V_OHs, it indicates that these operations have timed

out. If I/O6 pin outputs V_OH, it indicates a possibility that can be corrected by ECC, choose data correction by

ECC or not by reading out the data. When these pins monitor, I/O7 pin must turn to a V_OH. To execute other

erase and program operation, the status data must be cleared after a time out occurs. From I/O0 to I/O3 pins

are reserved for future use. The pins output V_OLs and should be masked out during the status data read mode.

The function of the status register is summarized in the following table.

I/O

Flag definition

Definition

I/O7

I/O6

Ready/Busy

V_OH= Ready, V_OL= Busy

Program/Erase ECC When I/O7 outputs V_OH, V_OH= ECC available, V_OL= ECC not available.

check

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

Erase check

Program check

Reserved

V_OH= Fail, V_OL= Pass

Outputs a V_OLand should be masked out during the status data poling mode.

Reserved

ECC Applicability

I/O7

V_OH

I/O6

I/O5

V_OH

V_OL

I/O4

V_OL

V_OH

System data correction by ECC

V_OH

V_OL

V_OH

V_OL

Needed

Not needed. Sector replacement

Needed

Not needed. Sector replacement

This device needs to be corrected failure data by ECC on system or Spare sectors, by reading out again the

failure sector data when program/erase error occures.

38

HN29V102414T-50H

Requirement for System

Specifications

Program/Erase Endurance: 3 × 10⁵cycles

Item

Min

64,226

579

Typ

—

Max

Unit

Usable sectors (initially)

Spare sectors (1-chip operation)

(2-chip operation)

65,536

—

sector

—

sector

1158

3

—

sector

ECC (Error Correction Code)

—

bit/sector

39

HN29V102414T-50H

Unusable Sector

Initially, the HN29V102414T-50H includes unusable sectors. The unusable sectors must be distinguished

from the usable sectors by the system as follows.

1. Check the partial invalid sectors in the devices on the system. The usable sectors were programmed the

following data. Refer to the flowchart “Indication of unusable sectors”.

Initial Data of Usable Sectors

Column address 0H to 81FH 820H

Data FFH 1CH

821H

822H

823H

824H

825H

826H to 83FH

71H

C7H

1CH

71H

C7H

FFH

2. Do not erase and program to the partial invalid sectors by the system.

START

Sector number = 0

Read data

Column address = 820H to 825H

No

Sector number =

Sector number + 1

Bad sector*²

Check data*¹

Yes

Sector number = 32,767

Yes

END

Notes: 1. Refer to table "Initial data of usable sectors".

2. Bad sectors are installed in system.

The Unusable Sector Indication Flow (1-chip)

40

HN29V102414T-50H

Requirements for High System Reliability

The device may fail during a program, erase or read operation due to write or erase cycles. The following

architecture will enable high system reliability if a failure occurs.

1. For an error in read operation: An ECC (Error Correction Code) or a similar function which can correct

3-bits per each sectors is required for data reliability. When error occurs, data must not be corrected by

replacing to spare sector.

2. For errors in program or erase operations: The device may fail during a program or erase operation due to

write or erase cycles. The status register indicates if the erase and program operation complete in a finite

time. When an error occured in the sector, try to reprogram the data into another sector. Avoid further

system access to the sector that error happens. Typically, recommended number of a spare sectors are

1.8% (579 sectors/chip (min)) of initial usable 32,113 sectors/chip (min.) by each device. For the

reprogramming, do not use the data from the failed sectors, because the data from the failed sectors are not

fixed. So the reprogram data must be the data reloaded from the external buffer, or use the Data recovery

read mode or the Data recovery write mode (see the “Mode Description” and under figure “Spare Sector

Replacement Flow after Program Error”). To avoid consecutive sector failures, choose addresses of spare

sectors as far as possible from the failed sectors. In this case, 10⁵cycles of program/erase endurance is

guaranteed.

3. Prolongation of flash memory life: Due to the life of the memory prolongation, to do ware leveling at

about 5000 each. The write/erase endurance is 3 × 10⁵cycles under the condition of the 3-bit error

correction and of ware leveling at 5000 each.

41

HN29V102414T-50H

START

Program start

Set an usable sector

Program end

Check RDY/Busy

No

Check status

Yes

Clear status register

Load data from

external buffer

Data recovery read

Data recovery write

Set another

usable sector

Program start

Program end

Check RDY/Busy

No

Check status

Yes

Check status: Status register read

END

Spare Sector Replacement Flow after Program Error

42

HN29V102414T-50H

For Errors in program or erase operations

The device may fail during a program or erase operation. Failure mode can be confirmed by read out the

status register after complete the erase and program operations. There are two failure modes specified by

each codes:

1: Status register error flag: I/O6 = V_OL

Replace sector under the “Spare Sectors Replacement Flow at Status Register I/O6 Read”. Replacement must

be applied to one sector(2k bytes) which contains failure bits.

2: Status register error flag: I/O6 = V_OH

Escape the program data temporary under the “Replacement Flow at Status Register I/O6 Read”. If failure

data can be corrected by ECC, do not replace to spare sector. If failure data can not be corrected by ECC,

replace to spare sector. Replacement must be applied to one sector(2k bytes) which contains failure bits.

START

Check status: Status register read

Check I/O6: I/O6 output monitor

Check ECC: Correct by ECC?

Program start

Set an usable sector

Program end

Check RDY/Busy

No

Check status

Yes

V_OH

Check I/O6

V_OL

Escape program deta*¹

Read error sector

Sector Replacement

Program end

No

Sector Replacement

Program end

Check status

Yes

Check ECC

Yes

No

Check status

Yes

END

Note: 1. Refer to 'Spare sector replacement flow after program error' to escape the deta.

Spare Sectors Replacement Flow at Status Register I/O6 Read

43

HN29V102414T-50H

Memory Structure

bit

sector

byte (8 bits)

2,112 bytes (16,896 bits)

Bit: Minimum unit of data.

Byte: Input/output data unit in programming and reading. (1 byte = 8 bits)

Sector: Page unit in erase, programming and reading. (1 sector = 2,112 bytes = 16,896 bits)

Device: 1 device = 32,768 sectors.

44

HN29V102414T-50H

Package Dimensions

HN29V102414T-50H (TFP-48DA)

As of January, 2002

12.00

12.40 Max

48

Unit: mm

25

1

24

0.50

*0.22 ± 0.08

0.20 ± 0.06

0.80

M

0.08

0.45 Max

20.00 ± 0.20

0˚ – 8˚

0.50 ± 0.10

0.10

Hitachi Code

JEDEC

JEITA

Mass (reference value)

TFP-48DA

Conforms

0.52 g

*Dimension including the plating thickness

Base material dimension

45


型号：	HN29V102414T-50H
厂家：	HITACHI SEMICONDUCTOR
描述：	Flash, 64MX16, 50ns, PDSO48, 12 X 20 MM, 0.50 MM PITCH, PLASTIC, TSOP1-48 光电二极管内存集成电路
文件：	总46页 (文件大小：360K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HN29V102414T-50H [HITACHI]

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