HN58X2402SFP [HITACHI]

EEPROM, 256X8, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, SOP-8;


型号：	HN58X2402SFP
厂家：	HITACHI SEMICONDUCTOR
描述：	EEPROM, 256X8, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, SOP-8 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件：	总21页 (文件大小：88K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HN58X2402S/HN58X2404S

Two-wire serial interface

2k EEPROM (256-word ´ 8-bit)

4k EEPROM (512-word ´ 8-bit)

ADE-203-1016A (Z)

Preliminary

Rev. 0.1

May. 26, 1999

Description

HN58X24xxS series are two-wire serial interface EEPROM (Electrically Erasable and Programmable

ROM). They realize high speed, low power consumption and a high level of reliability by employing

advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also

have a 8-byte page programming function to make their write operation faster.

Features

Single supply: 1.8 V to 5.5 V

Two-wire serial interface (I²C^TMserial bus*¹)

Clock frequency: 400 kHz

Power dissipation:

¾ Standby: 3 µA(max)

¾ Active (Read): 1 mA(max)

¾ Active (Write): 3 mA(max)

Automatic page write: 8-byte/page

Write cycle time: 10 ms (2.7 V to 5.5 V )/15ms (1.8 V to 2.7 V )

Preliminary: The specification of this device are subject to change without notice. Please contact your

nearest Hitachi’s Sales Dept. regarding specification.

HN58X2402S/HN58X2404S

Features (cont.)

Endurance: 10⁵Cycles (Page write mode)

Data retention: 10 Years

Small size packages: TSSOP-8pin and SOP-8pin (Die shipment is also available)

Note: 1. I²C is a trademark of Philips Corporation.

Ordering Information

Type No.

Internal organization Operating voltage Frequency

Package

HN58X2402SFP 2k bit (256 ´ 8-bit)

1.8 V to 5.5 V

400 kHz

150 mil 8-pin plastic SOP

(FP-8DB)

HN58X2404SFP 4k bit (512 ´ 8-bit)

HN58X2402ST

2k bit (256 ´ 8-bit)

1.8 V to 5.5 V

400 kHz

8-pin plastic TSSOP

(TTP-8D)

HN58X2404ST

4k bit (512 ´ 8-bit)

Note: Industrial versions (Temperature range: –20 to +85 C, –40 to +85 C) are also available.

Specifications of the industrial versions are identical with the specifications of the 0 to +70 C

version.

HN58X2402S/HN58X2404S

Pin Arrangement

Pin Description

Pin name

A0 to A2

SCL

Function

Device address

Serial clock input

Serial data input/output

Write protect

SDA

V_CC

Power supply

V_SS

Ground

HN58X2402S/HN58X2404S

Block Diagram

Absolute Maximum Ratings

Parameter

Symbol

V_CC

Value

Unit

Supply voltage relative to V_SS

Input voltage relative to V_SS

Operating temperature range*¹

Storage temperature range

–0.6 to +7.0

–0.5*²to +7.0*³

0 to +70

Vin

Topr

Tstg

–65 to +125

Notes: 1. Including electrical characteristics and data retention.

2. Vin (min): –3.0 V for pulse width 50 ns.

3. Should not exceed V_CC+ 1.0 V.

HN58X2402S/HN58X2404S

DC Operating Conditions

Parameter

Symbol

V_CC

Min

1.8

Typ

—

Max

Unit

Supply voltage

5.5

V_SS

Input high voltage

Input low voltage

V_IH

_CC´ 0.7

—

V_CC+ 1.0

V_IL

–0.3*¹

V_CC´ 0.3

Operating temperature

Topr

Notes: 1. V_IL(min): –1.0 V for pulse width 50 ns.

DC Characteristics (Ta = 0 to +70 C, V_CC= 1.8 V to 5.5 V)

Parameter

Symbol Min

Typ

—

Max

2.0

3.0

1.0

3.0

0.4

Unit

µA

Test conditions

Input leakage current

Output leakage current

Standby V_CCcurrent

Read V_CCcurrent

Write V_CCcurrent

Output low voltage

I_LI

—

V_CC= 5.5 V, Vin = 0 to 5.5 V

V_CC= 5.5 V, Vout = 0 to 5.5 V

Vin = V_SSor V_CC

I_LO

—

I_SB

1.0

—

I_CC1

I_CC2

V_OL2

V_CC= 5.5 V, Read at 400 kHz

V_CC= 5.5 V, Write at 400 kHz

—

V_CC= 4.5 to 5.5 V, I_OL= 1.6 mA

V_CC= 2.7 to 4.5 V, I_OL= 0.8 mA

V_CC= 1.8 to 2.7 V, I_OL= 0.4 mA

V_OL1

—

0.2

V_CC= 1.8 to 2.7 V, I_OL= 0.2 mA

Capacitance (Ta = 25 C, f = 1 MHz)

Test

Parameter

Symbol Min

Typ

Max

6.0

Unit

conditions

Input capacitance (A0 to A2, SCL, WP) Cin*¹

—

Vin = 0 V

Output capacitance (SDA)

C_I/O

6.0

Vout = 0 V

Note: 1. This parameter is sampled and not 100% tested.

HN58X2402S/HN58X2404S

AC Characteristics (Ta = 0 to +70 C, V_CC= 1.8 to 5.5 V)

Test Conditions

Input pules levels:

¾ V_IL= 0.2 ´ V_CC

¾ V_IH= 0.8 ´ V_CC

Input rise and fall time: 20 ns

Input and output timing reference levels: 0.5 ´ V_CC

Output load: TTL Gate + 100 pF

Parameter

Symbol Min

Typ

—

Max

400

—

Unit

kHz

Notes

Clock frequency

Clock pulse width low

Clock pulse width high

Noise suppression time

Access time

f_SCL

—

t_LOW

t_HIGH

t_I

1200

600

—

t_AA

100

1200

600

900

—

Bus free time for next mode

Start hold time

t_BUF

t_HD.STA

t_SU.STA

t_HD.DAT

t_SU.DAT

t_R

—

Start setup time

—

Data in hold time

Data in setup time

Input rise time

—

100

—

300

—

Input fall time

t_F

—

Stop setup time

t_SU.STO

t_DH

V_CC= 2.7 V to 5.5 V t_WC

V_CC= 1.8 V to 2.7 V t_WC

600

Data out hold time

—

Write cycle time

—

Notes: 1. This parameter is sampled and not 100% tested.

2. t_WCis the time from a stop condition to the end of internally controlled write cycle.

HN58X2402S/HN58X2404S

Timing Waveforms

Bus Timing

Write Cycle Timing

HN58X2402S/HN58X2404S

Pin Function

Serial Clock (SCL)

The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock

data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400

kHz.

Serial Input/Output data (SDA)

The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that

pin is open-drain driven structure. Use proper resistor value for your system by considering V_OL, I_OLand the

SDA pin capacitance. Except for a start condition and a stop condition which will be discussed later, the

SDA transition needs to be completed during SCL low period.

Data Validity (SDA data change timing waveform)

Note:

High-to-low and low-to-high change of SDA should be done during SCL low periods.

Device address (A0, A1, A2)

Eight devices can be wired for one common data bus line as maximum. Device address pins are used to

distinguish each device and device address pins should be connected to V_CCor V_SS. When device address

code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one

device can be activated. As for 4k EEPROM, some device address pins don't need to be fixed since device

address code provided from the SDA pin is used as memory address signal.

HN58X2402S/HN58X2404S

Pin Connections for A0 to A2

Pin connection

A2 A1

Max connect

Memory size number

Notes

2k bit

V_CC/V_SS* V_CC/V_SSV_CC/V_SS

4k bit

V_CC/V_SSV_CC/V_SS´ *²

Use A0 for memory address a8

Notes: 1. “V_CC/V_SS” means that device address pin should be connected to V_CCor V_SS

2. ´ = Don’t care (Open is also approval.)

Write Protect (WP)

When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in

the following table. When the WP is low, write operation for all memory arrays are allowed. The read

operation is always activated irrespective of the WP pin status. WP should be fixed high or low during

operations since WP does not provide a latch function.

Write Protect Area

Write protect area

WP pin status

2k bit

4k bit

V_IH

V_IL

Entire (2k bit)

Upper 1/2 (2k bit)

Normal read/write operation

HN58X2402S/HN58X2404S

Functional Description

Start Condition

A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation. (See

start condition and stop condition)

Stop Condition

A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts

after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the

write data inputs and place the device in a internally-timed write cycle to the memories. After the

internally-timed write cycle which is specified as t_WC, the device enters a standby mode. (See write cycle

timing)

Start Condition and Stop Condition

Acknowledge

All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero

to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter

keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation,

EEPROM sends a zero to acknowledge after receiving every 8-bit words. In the read operation, EEPROM

sends a zero to acknowledge after receiving the device address word. After sending read data, the

EEPROM waits acknowledgment by keeping bus open. If the EEPROM receives zero as an acknowledge, it

sends read data of next address. If the EEPROM receives acknowledgment "1" (no acknowledgment) and a

following stop condition, it stops the read operation and enters a stand-by mode. If the EEPROM receives

neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus open without sending read data.

HN58X2402S/HN58X2404S

Acknowledge Timing Waveform

Device Addressing

The EEPROM device requires an 8-bit device address word following a start condition to enable the chip

for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address

code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to

distinguish device type and this EEPROM uses “1010” fixed code. The device address word is followed by

the 3-bit device address code in the order of A2, A1, A0. The device address code selects one device out of

all devices which are connected to the bus. This means that the device is selected if the inputted 3-bit

device address code is equal to the corresponding hard-wired A2-A0 pin status. As for the 4kbit

EEPROMs, some bits of their device address code may be used as the memory address bits. For example,

A0 is used as a8 of memory address for the 4kbit. The eighth bit of the device address word is the

read/write(R/W) bit. A write operation is initiated if this bit is low and a read operation is initiated if this bit

is high. Upon a compare of the device address word, the EEPROM enters the read or write operation after

outputting the zero as an acknowledge. The EEPROM turns to a stand-by state if the device code is not

“1010” or device address code doesn’t coincide with status of the correspond hard-wired device address

pins A0 to A2.

Device Address Word

Device address word (8-bit)

Device code (fixed)

Device address code*¹

R/W code*²

R/W

Notes: 1. A2 to A0 are device address and a8 are memory address.

2. R/W=“1” is read and R/W = “0” is write.

HN58X2402S/HN58X2404S

Write Operations

Byte Write:

A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends

acknowledgment "0" at the ninth clock cycle. After these, EEPROMs receive 8-bit memory address word.

Upon receipt of this memory address, the EEPROM outputs acknowledgment "0" and receives a following

8-bit write data. After receipt of write data, the EEPROM outputs acknowledgment "0". If the EEPROM

receives a stop condition, the EEPROM enters an internally-timed write cycle and terminates receipt of

SCL, SDA inputs until completion of the write cycle. The EEPROM returns to a standby mode after

completion of the write cycle.

Byte Write Operation

HN58X2402S/HN58X2404S

Page Write:

The EEPROM is capable of the page write operation which allows any number of bytes up to 8 bytes to be

written in a single write cycle. The page write is the same sequence as the byte write except for inputting the

more write data. The page write is initiated by a start condition, device address word, memory address(n)

and write data(Dn) with every ninth bit acknowledgment. The EEPROM enters the page write operation if

the EEPROM receives more write data(Dn+1) instead of receiving a stop condition. The a0 to a2 address

bits are automatically incremented upon receiving write data(Dn+1). The EEPROM can continue to receive

write data up to 8 bytes. If the a0 to a2 address bits reaches the last address of the page, the a0 to a2

address bits will roll over to the first address of the same page and previous write data will be overwritten.

Upon receiving a stop condition, the EEPROM stops receiving write data and enters internally-timed write

cycle.

Page Write Operation

HN58X2402S/HN58X2404S

Acknowledge Polling:

Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not.

This features is initiated by the stop condition after inputting write data. This requires the 8-bit device

address word following the start condition during a internally-timed write cycle. Acknowledge polling will

operate R/W code = “0”. Acknowledgment “1” (no acknowledgment) shows the EEPROM is in a

internally-timed write cycle and acknowledgment “0” shows that the internally-timed write cycle has

completed. See Write Cycle Polling using ACK.

Write Cycle Polling using ACK

HN58X2402S/HN58X2404S

Read Operation

There are three read operations: current address read, random read, and sequential read. Read operations are

initiated the same way as write operations with the exception of R/W = “1”.

Current Address Read:

The internal address counter maintains the last address accessed during the last read or write operation,

with incremented by one. Current address read accesses the address kept by the internal address counter.

After receiving a start condition and the device address word(R/W is “1”), the EEPROM outputs the 8-bit

current address data from the most significant bit following acknowledgment “0” If the EEPROM receives

acknowledgment “1” (no acknowledgment) and a following stop condition, the EEPROM stops the read

operation and is turned to a standby state. In case the EEPROM have accessed the last address of the last

page at previous read operation, the current address will roll over and returns to zero address. In case the

EEPROM have accessed the last address of the page at previous write operation, the current address will

roll over within page addressing and returns to the first address in the same page. The current address is

valid while power is on. The current address after power on will be indefinite. The random read operation

described below is necessary to define the memory address.

Current Address Read Operation

Random Read:

This is a read operation with defined read address. A random read requires a dummy write to set read

address. The EEPROM receives a start condition, device address word(R/W=0) and memory address

sequentially. The EEPROM outputs acknowledgment “0” after receiving memory address then enters a

current address read with receiving a start condition. The EEPROM outputs the read data of the address

which was defined in the dummy write operation. After receiving acknowledgment “1”(no

acknowledgment) and a following stop condition, the EEPROM stops the random read operation and

returns to a standby state.

HN58X2402S/HN58X2404S

Random Read Operation

Sequential Read:

Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives

acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are

coming out. This operation can be continued as long as the EEPROM receives acknowledgment “0”. The

address will roll over and returns address zero if it reaches the last address of the last page. The sequential

read can be continued after roll over. The sequential read is terminated if the EEPROM receives

acknowledgment “1” (no acknowledgment) and a following stop condition.

Sequential Read Operation

HN58X2402S/HN58X2404S

Notes

Data protection at V_CCOn/Off

When V_CCis turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc)

may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional

programming, this EEPROM have a power on reset function. Be careful of the notices described below in

order for the power on reset function to operate correctly.

SCL and SDA should be fixed to V_CCor V_SSduring V_CCon/off. Low to high or high to low transition

during V_CCon/off may cause the trigger for the unintentional programming.

V_CCshould be turned off after the EEPROM is placed in a standby state.

V_CCshould be turned on from the ground level(V_SS) in order for the EEPROM not to enter the

unintentional programming mode.

V_CCturn on speed should be longer than 10 us.

Write/Erase Endurance and Data retention Time

The endurance is 10⁵cycles in case of page programming and 10⁴cycles in case of byte programming (1%

cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed

less than 10⁴cycles.

Noise Suppression Time

This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than

50 ns. Be careful not to allow noise of width more than 50 ns.

HN58X2402S/HN58X2404S

Package Dimensions

HN58X2402SFP/HN58X2404SFP (FP-8DB)

HN58X2402S/HN58X2404S

Package Dimensions (cont.)

HN58X2402ST/HN58X2404ST (TTP-8D)

HN58X2402S/HN58X2404S

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,

Hitachi bears no responsibility for problems that may arise with third party’s rights, including

intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi’s sales office before using the product in an application that demands especially high

quality and reliability or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,

traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation

conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used

beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure

rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that

the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential

damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor

products.

HN58X2402S/HN58X2404S

Revision Record

Rev. Date

Contents of Modification

Drawn by

Approved by

0.0

0.1

Feb. 19, 1999

May. 26, 1999

Initial issue

T. Okada

M. Terasawa

Pin Function: Change of Write Protect Area

2k bit V_IH: Upper 1/2 (1k bit) to Entire (2k bit)

HN58X2402SFP [HITACHI]

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