BH66F2650 [HOLTEK]
Body Fat Measurment Flash MCU;型号: | BH66F2650 |
厂家: | HOLTEK SEMICONDUCTOR INC |
描述: | Body Fat Measurment Flash MCU |
文件: | 总223页 (文件大小:9155K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Body Fat Measurment Flash MCU
BH66F2650/BH66F2660
Revision: V1.10 Date: �anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Table of Contents
Features................................................................................................................7
CPU Featꢀꢁes ..............................................................................................................................7
Peꢁipheꢁal Featꢀꢁes......................................................................................................................7
General Description.............................................................................................8
Selection Table.....................................................................................................9
Block Diagram......................................................................................................9
Pin Assignment..................................................................................................10
Pin Description .................................................................................................. 11
Absolute Maximum Ratings..............................................................................15
D.C. Characteristics...........................................................................................15
Opeꢁating Voltage Chaꢁacteꢁistics..............................................................................................15
Standbꢂ Cꢀꢁꢁent Chaꢁacteꢁistics ................................................................................................16
Opeꢁating Cꢀꢁꢁent Chaꢁacteꢁistics..............................................................................................17
A.C. Characteristics...........................................................................................18
High Speed Inteꢁnal Oscillatoꢁ – HIRC – Fꢁeqꢀencꢂ Accꢀꢁacꢂ..................................................1ꢆ
Low Speed Inteꢁnal Oscillatoꢁ Chaꢁacteꢁistics – LIRC ...............................................................1ꢆ
Opeꢁating Fꢁeqꢀencꢂ Chaꢁacteꢁistic Cꢀꢁves..............................................................................19
Sꢂstem Staꢁt Up Time Chaꢁacteꢁistics .......................................................................................19
Input/Output Characteristics ............................................................................20
Memory Characteristics....................................................................................22
LVD/LVR Electrical Characteristics..................................................................22
24-bit A/D Converter Electrical Characteristics .............................................. 23
12-bit D/A Converter Electrical Characteristics .............................................. 24
Operational Amplifier Electrical Characteristics (Body Fat Circuit) ............. 24
Power-on Reset Characteristics.......................................................................25
System Architecture..........................................................................................25
Clocking and Pipelining..............................................................................................................ꢅ5
Pꢁogꢁam Coꢀnteꢁ........................................................................................................................ꢅ6
Stack ..........................................................................................................................................ꢅ7
Aꢁithmetic and Logic Unit – ALU ................................................................................................ꢅ7
Flash Program Memory.....................................................................................28
Stꢁꢀctꢀꢁe.....................................................................................................................................ꢅꢆ
Special Vectoꢁs ..........................................................................................................................ꢅꢆ
Look-ꢀp Table.............................................................................................................................ꢅ9
Table Pꢁogꢁam Example.............................................................................................................ꢅ9
In Ciꢁcꢀit Pꢁogꢁamming – ICP ....................................................................................................30
On-Chip Debꢀg Sꢀppoꢁt – OCDS ..............................................................................................31
In Application Pꢁogꢁamming – IAP .............................................................................................31
Rev. 1.10
ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
RAM Data Memory.............................................................................................40
Stꢁꢀctꢀꢁe.....................................................................................................................................ꢃ0
Data Memoꢁꢂ Addꢁessing...........................................................................................................ꢃ1
Geneꢁal Pꢀꢁpose Data Memoꢁꢂ .................................................................................................ꢃ1
Special Pꢀꢁpose Data Memoꢁꢂ ..................................................................................................ꢃ1
Special Function Register Description............................................................44
Indiꢁect Addꢁessing Registeꢁs – IAR0ꢄ IAR1ꢄ IARꢅ ....................................................................ꢃꢃ
Memoꢁꢂ Pointeꢁs – MP0ꢄ MP1Lꢄ MP1Hꢄ MPꢅLꢄ MPꢅH..............................................................ꢃꢃ
Pꢁogꢁam Memoꢁꢂ Bank Pointeꢁ – PBP.......................................................................................ꢃ6
Accꢀmꢀlatoꢁ – ACC ...................................................................................................................ꢃ6
Pꢁogꢁam Coꢀnteꢁ Low Registeꢁ – PCL ......................................................................................ꢃ6
Look-ꢀp Table Registeꢁs – TBLPꢄ TBHPꢄ TBLH .........................................................................ꢃ6
Statꢀs Registeꢁ – STATUS ........................................................................................................ꢃ7
EEPROM Data Memory......................................................................................49
EEPROM Data Memoꢁꢂ Stꢁꢀctꢀꢁe .............................................................................................ꢃ9
EEPROM Registeꢁs ...................................................................................................................ꢃ9
Reading Data fꢁom the EEPROM ..............................................................................................51
Wꢁiting Data to the EEPROM.....................................................................................................51
Wꢁite Pꢁotection..........................................................................................................................51
EEPROM Inteꢁꢁꢀpt .....................................................................................................................51
Pꢁogꢁamming Consideꢁations.....................................................................................................5ꢅ
Oscillators ..........................................................................................................53
Oscillatoꢁ Oveꢁview ...................................................................................................................53
System Clock Configurations ....................................................................................................53
External High Speed Crystal Oscillator − HXT...........................................................................5ꢃ
Internal RC Oscillator − HIRC....................................................................................................55
External 32.768kHz Crystal Oscillator − LXT.............................................................................55
Internal 32kHz Oscillator − LIRC................................................................................................56
Operating Modes and System Clocks .............................................................56
Sꢂstem Clocks ...........................................................................................................................56
Sꢂstem Opeꢁation Modes...........................................................................................................57
Contꢁol Registeꢁs .......................................................................................................................5ꢆ
Opeꢁating Mode Switching.........................................................................................................61
Standbꢂ Cꢀꢁꢁent Consideꢁations................................................................................................65
Wake-ꢀp.....................................................................................................................................65
Watchdog Timer.................................................................................................66
Watchdog Timeꢁ Clock Soꢀꢁce...................................................................................................66
Watchdog Timeꢁ Contꢁol Registeꢁ..............................................................................................66
Watchdog Timeꢁ Opeꢁation ........................................................................................................67
Reset and Initialisation......................................................................................68
Reset Fꢀnctions .........................................................................................................................6ꢆ
Reset Initial Conditions .............................................................................................................7ꢅ
Rev. 1.10
3
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Input/Output Ports.............................................................................................76
Pꢀll-high Resistoꢁs .....................................................................................................................76
Poꢁt A Wake-ꢀp ..........................................................................................................................77
I/O Poꢁt Contꢁol Registeꢁs..........................................................................................................77
I/O Poꢁt Soꢀꢁce Cꢀꢁꢁent Contꢁol.................................................................................................7ꢆ
Pin-shaꢁed Fꢀnctions .................................................................................................................79
I/O Pin Stꢁꢀctꢀꢁes.......................................................................................................................ꢆ3
Pꢁogꢁamming Consideꢁations ....................................................................................................ꢆꢃ
Timer Modules – TM ..........................................................................................84
Intꢁodꢀction ................................................................................................................................ꢆꢃ
TM Opeꢁation .............................................................................................................................ꢆ5
TM Clock Soꢀꢁce........................................................................................................................ꢆ5
TM Inteꢁꢁꢀpts..............................................................................................................................ꢆ5
TM Exteꢁnal Pins........................................................................................................................ꢆ5
TM Inpꢀt/Oꢀtpꢀt Pin Selection ...................................................................................................ꢆ6
Pꢁogꢁamming Consideꢁations.....................................................................................................ꢆ7
Standard Type TM – STM ..................................................................................88
Standaꢁd TM Opeꢁation..............................................................................................................ꢆꢆ
Standaꢁd Tꢂpe TM Registeꢁ Descꢁiption ....................................................................................ꢆ9
Standaꢁd Tꢂpe TM Opeꢁation Modes.........................................................................................93
Periodic Type TM – PTM..................................................................................103
Peꢁiodic TM Opeꢁation .............................................................................................................103
Peꢁiodic Tꢂpe TM Registeꢁ Descꢁiption....................................................................................103
Peꢁiodic Tꢂpe TM Opeꢁating Modes ........................................................................................10ꢆ
Analog to Digital Converter – ADC................................................................. 117
A/D Oveꢁview ...........................................................................................................................117
Inteꢁnal Poweꢁ Sꢀpplꢂ .............................................................................................................117
A/D Data Rate Definition..........................................................................................................11ꢆ
A/D Conveꢁteꢁ Registeꢁ Descꢁiption.........................................................................................119
A/D Opeꢁation ..........................................................................................................................1ꢅ7
Sꢀmmaꢁꢂ of A/D Conveꢁsion Steps..........................................................................................1ꢅꢆ
Pꢁogꢁamming Consideꢁations...................................................................................................1ꢅ9
A/D Tꢁansfeꢁ Fꢀnction ..............................................................................................................1ꢅ9
A/D Conveꢁted Data.................................................................................................................130
A/D Conveꢁted Data to Voltage................................................................................................131
A/D Pꢁogꢁamming Example......................................................................................................131
Tempeꢁatꢀꢁe Sensoꢁ.................................................................................................................13ꢅ
Serial Interface Module – SIM.........................................................................132
SPI Inteꢁface ............................................................................................................................13ꢅ
IꢅC Inteꢁface .............................................................................................................................139
Serial Peripheral Interface – SPIA..................................................................148
SPIA Inteꢁface Opeꢁation .........................................................................................................1ꢃꢆ
SPIA Registeꢁs.........................................................................................................................150
Rev. 1.10
ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
SPIA Commꢀnication ...............................................................................................................15ꢅ
SPIA Bꢀs Enable/Disable.........................................................................................................155
SPIA Opeꢁation ........................................................................................................................155
Eꢁꢁoꢁ Detection.........................................................................................................................156
UART Interface.................................................................................................157
UART Exteꢁnal Pin Inteꢁfacing .................................................................................................157
UART Data Tꢁansfeꢁ Scheme...................................................................................................157
UART Statꢀs and Contꢁol Registeꢁs.........................................................................................15ꢆ
Baꢀd Rate Geneꢁatoꢁ...............................................................................................................163
UART Setꢀp and Contꢁol..........................................................................................................165
UART Tꢁansmitteꢁ.....................................................................................................................166
UART Receiveꢁ ........................................................................................................................167
Managing Receiveꢁ Eꢁꢁoꢁs .......................................................................................................169
UART Modꢀle Inteꢁꢁꢀpt Stꢁꢀctꢀꢁe.............................................................................................170
UART Poweꢁ Down and Wake-ꢀp............................................................................................17ꢅ
Body Fat Measurement Function...................................................................173
Sine Wave Geneꢁatoꢁ...............................................................................................................173
Bodꢂ Fat Measꢀꢁement Registeꢁs............................................................................................176
Interrupts..........................................................................................................180
Inteꢁꢁꢀpt Registeꢁs....................................................................................................................1ꢆ0
Inteꢁꢁꢀpt Opeꢁation...................................................................................................................1ꢆ5
Exteꢁnal Inteꢁꢁꢀpt......................................................................................................................1ꢆ6
LVD Inteꢁꢁꢀpt............................................................................................................................1ꢆ7
EEPROM Inteꢁꢁꢀpt ...................................................................................................................1ꢆ7
A/D Conveꢁteꢁ Inteꢁꢁꢀpt............................................................................................................1ꢆ7
Mꢀlti-fꢀnction Inteꢁꢁꢀpts............................................................................................................1ꢆ7
Seꢁial Inteꢁface Modꢀle Inteꢁꢁꢀpt..............................................................................................1ꢆꢆ
SPIA Inteꢁꢁꢀpt...........................................................................................................................1ꢆꢆ
UART Inteꢁꢁꢀpt.........................................................................................................................1ꢆꢆ
Time Base Inteꢁꢁꢀpts................................................................................................................1ꢆꢆ
Timeꢁ Modꢀle Inteꢁꢁꢀpts...........................................................................................................190
Inteꢁꢁꢀpt Wake-ꢀp Fꢀnction......................................................................................................190
Pꢁogꢁamming Consideꢁations...................................................................................................191
Low Voltage Detector – LVD ...........................................................................192
LVD Registeꢁ............................................................................................................................19ꢅ
LVD Opeꢁation..........................................................................................................................193
16-bit Multiplication Division Unit – MDU...................................................... 194
MDU ꢁegisteꢁs ..........................................................................................................................19ꢃ
Mꢀltiplication Division Unit Opeꢁation.......................................................................................195
Application Circuits.........................................................................................197
Instruction Set..................................................................................................199
Intꢁodꢀction ..............................................................................................................................199
Instꢁꢀction Timing.....................................................................................................................199
Rev. 1.10
5
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Moving and Tꢁansfeꢁꢁing Data..................................................................................................199
Aꢁithmetic Opeꢁations...............................................................................................................199
Logical and Rotate Opeꢁation ..................................................................................................ꢅ00
Bꢁanches and Contꢁol Tꢁansfeꢁ ................................................................................................ꢅ00
Bit Opeꢁations ..........................................................................................................................ꢅ00
Table Read Opeꢁations ............................................................................................................ꢅ00
Otheꢁ Opeꢁations......................................................................................................................ꢅ00
Instruction Set Summary ................................................................................201
Table Conventions....................................................................................................................ꢅ01
Extended Instꢁꢀction Set..........................................................................................................ꢅ03
Instruction Definition.......................................................................................205
Extended Instruction Definition ................................................................................................ꢅ1ꢃ
Package Information .......................................................................................221
ꢃꢆ-pin LQFP (7mm×7mm) Oꢀtline Dimensions .......................................................................ꢅꢅꢅ
Rev. 1.10
6
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Features
CPU Features
•ꢀ OperatingꢀVoltage
ꢀ
♦
ꢀ
♦
ꢀ
♦
ꢀ
♦
fSYS=4MHz:ꢀ2.2V~5.5V
fSYS=8MHz:ꢀ2.2V~5.5V
fSYS=12MHz:ꢀ2.7V~5.5V
fSYS=16MHz:ꢀ3.3V~5.5V
•ꢀ Upꢀtoꢀ0.25μsꢀinstructionꢀcycleꢀwithꢀ16MHzꢀsystemꢀclockꢀatꢀVDD=5V
•ꢀ Powerꢀdownꢀandꢀwake-upꢀfunctionsꢀtoꢀreduceꢀpowerꢀconsumption
•ꢀ FourꢀOscillators:
ꢀ
♦
ꢀ
♦
ꢀ
♦
ꢀ
♦
HighꢀSpeedꢀInternalꢀRCꢀ–ꢀHIRC
Externalꢀ32.768kHzꢀCrystalꢀ–ꢀLXT
HighꢀSpeedꢀExternalꢀCrystalꢀ–ꢀHXT
Internalꢀ32kHzꢀRCꢀ–ꢀLIRC
•ꢀ Multi-modeꢀoperation:ꢀFAST,ꢀSLOW,ꢀIDLEꢀandꢀSLEEP
•ꢀ Fullyꢀintegratedꢀinternalꢀ4MHz,ꢀ8MHzꢀorꢀ12MHzꢀoscillatorꢀrequiresꢀnoꢀexternalꢀcomponents
•ꢀ Allꢀinstructionsꢀexecutedꢀinꢀ1~3ꢀinstructionꢀcycles
•ꢀ Tableꢀreadꢀinstructions
•ꢀ 115ꢀpowerfulꢀinstructions
•ꢀ 8-levelꢀsubroutineꢀnesting
•ꢀ Bitꢀmanipulationꢀinstruction
Peripheral Features
•ꢀ FlashꢀProgramꢀMemory:ꢀ8K×16ꢀ~ꢀ16K×16
•ꢀ RAMꢀDataꢀMemory:ꢀ256×8ꢀ~ꢀ1024×8
•ꢀ TrueꢀEEPROMꢀMemory:ꢀ64×8ꢀ~ꢀ256×8
•ꢀ WatchdogꢀTimerꢀfunction
•ꢀ InꢀApplicationꢀProgrammingꢀ–ꢀIAP
•ꢀ Upꢀtoꢀ28ꢀbidirectionalꢀI/Oꢀlines
•ꢀ 2ꢀdifferentialꢀorꢀ4ꢀsingle-endꢀchannelsꢀ24-bitꢀresolutionꢀDeltaꢀSigmaꢀA/Dꢀconverter
•ꢀ Twoꢀpin-sharedꢀexternalꢀinterrupts
•ꢀ MultipleꢀTimerꢀModulesꢀforꢀtimeꢀmeasure,ꢀinputꢀcapture,ꢀcompareꢀmatchꢀoutput,ꢀPWMꢀoutputꢀorꢀ
singleꢀpulseꢀoutputꢀfunction
•ꢀ SerialꢀInterfaceꢀModuleꢀwithꢀDualꢀSPIꢀandꢀI2Cꢀinterfacesꢀ–ꢀSIM
•ꢀ SingleꢀSerialꢀPeripheralꢀInterfaceꢀ–ꢀSPIA
•ꢀ UARTꢀInterfaceꢀforꢀfullꢀduplexꢀasynchronousꢀcommunication
•ꢀ DualꢀTime-Baseꢀfunctionsꢀforꢀgenerationꢀofꢀfixedꢀtimeꢀinterruptꢀsignals
•ꢀ LowꢀVoltageꢀResetꢀfunctionꢀ–ꢀLVR
•ꢀ LowꢀVoltageꢀDetectꢀfunctionꢀ–ꢀLVD
•ꢀ BodyꢀFatꢀCircuit
•ꢀ 16-bitꢀMultiplicationꢀDivisionꢀUnit
•ꢀ Packageꢀtype:ꢀ48-pinꢀLQFP
Rev. 1.10
7
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
General Description
Thisꢀseriesꢀofꢀdevicesꢀareꢀspecificallyꢀdesignedꢀforꢀeight-electrodeꢀACꢀBodyꢀFatꢀScaleꢀapplications.ꢀ
MeasuringꢀbodyꢀfatꢀusesꢀaꢀtechniqueꢀwherebyꢀanꢀACꢀcurrentꢀflowingꢀthroughꢀtheꢀhumanꢀbodyꢀisꢀ
measuredꢀandꢀthenꢀusedꢀtoꢀcalculateꢀaꢀbodyꢀfatꢀvalue.ꢀTheꢀspecialisedꢀcircuitsꢀtoꢀdoꢀthisꢀareꢀaꢀweightꢀ
measurementꢀcircuitꢀandꢀaꢀfatꢀmeasurementꢀcircuit.ꢀTheꢀweightꢀmeasurementꢀcircuitꢀusesꢀanꢀexternalꢀloadꢀ
cellꢀtoꢀoutputꢀaꢀsignal,ꢀwhichꢀafterꢀamplificationꢀbyꢀanꢀoperationalꢀamplifier,ꢀandꢀthenꢀconversionꢀusingꢀanꢀ
A/Dꢀconverter,ꢀreadsꢀtheꢀcorrespondingꢀvalueꢀasꢀtheꢀcalculatedꢀweight.ꢀTheꢀfatꢀmeasurementꢀcircuitꢀ
usesꢀanꢀACꢀsignalꢀviaꢀanꢀelectrodeꢀsliceꢀtoꢀflowꢀthroughꢀhumanꢀbody.ꢀAfterꢀamplificationꢀbyꢀanꢀinternalꢀ
operationalꢀamplifier,ꢀandꢀthenꢀconversionꢀbyꢀanꢀA/Dꢀconverter,ꢀtheꢀmeasuredꢀvalueꢀisꢀoneꢀrepresentingꢀ
bodyꢀimpedance,ꢀwhichꢀisꢀusedꢀtoꢀcalculateꢀtheꢀcorrespondingꢀbodyꢀfatꢀvalue.
ThisꢀseriesꢀofꢀdevicesꢀareꢀFlashꢀMemoryꢀI/Oꢀtypeꢀ8-bitꢀhighꢀperformanceꢀRISCꢀarchitectureꢀ
microcontrollerꢀwhichꢀincludesꢀaꢀmulti-channelꢀ24-bitꢀDeltaꢀSigmaꢀA/Dꢀconverter,ꢀdesignedꢀforꢀ
applicationsꢀthatꢀinterfaceꢀdirectlyꢀtoꢀanalogꢀsignalsꢀandꢀwhichꢀrequireꢀaꢀlowꢀnoiseꢀandꢀhighꢀaccuracyꢀ
analog-to-digitalꢀconverter.ꢀOfferingꢀusersꢀtheꢀconvenienceꢀofꢀFlashꢀMemoryꢀmulti-programmingꢀ
features,ꢀtheꢀdevicesꢀalsoꢀincludesꢀaꢀwideꢀrangeꢀofꢀfunctionsꢀandꢀfeatures.ꢀOtherꢀmemoryꢀincludesꢀanꢀ
areaꢀofꢀRAMꢀDataꢀMemoryꢀasꢀwellꢀasꢀanꢀareaꢀofꢀtrueꢀEEPROMꢀmemoryꢀforꢀstorageꢀofꢀnon-volatileꢀ
dataꢀsuchꢀasꢀserialꢀnumbers,ꢀcalibrationꢀdataꢀetc.
Analogꢀfeaturesꢀincludeꢀaꢀmulti-channelꢀ24-bitꢀDeltaꢀSigmaꢀA/Dꢀconverter,ꢀPGAꢀandꢀLDOꢀandꢀotherꢀ
circuitryꢀspecificallyꢀdesignedꢀforꢀBodyꢀFatꢀScaleꢀapplications.ꢀMultipleꢀandꢀextremelyꢀflexibleꢀ
TimerꢀModulesꢀprovideꢀtiming,ꢀpulseꢀgenerationꢀandꢀPWMꢀgenerationꢀfunctions.ꢀCommunicationꢀ
withꢀtheꢀoutsideꢀworldꢀisꢀprovidedꢀbyꢀincludingꢀfullyꢀintegratedꢀSPI,ꢀI2CꢀandꢀUARTꢀinterfaceꢀ
functions,ꢀpopularꢀinterfacesꢀwhichꢀprovideꢀdesignersꢀwithꢀaꢀmeansꢀofꢀeasyꢀcommunicationꢀwithꢀ
externalꢀperipheralꢀhardware.ꢀProtectiveꢀfeaturesꢀsuchꢀasꢀanꢀinternalꢀWatchdogꢀTimer,ꢀLowꢀVoltageꢀ
ResetꢀandꢀLowꢀVoltageꢀDetectorꢀcoupledꢀwithꢀexcellentꢀnoiseꢀimmunityꢀandꢀESDꢀprotectionꢀensureꢀ
thatꢀreliableꢀoperationꢀisꢀmaintainedꢀinꢀhostileꢀelectricalꢀenvironments.ꢀ
Aꢀfullꢀchoiceꢀofꢀexternal,ꢀinternalꢀandꢀhighꢀandꢀlowꢀoscillatorsꢀfunctionsꢀareꢀprovidedꢀincludingꢀtwoꢀ
fullyꢀintegratedꢀsystemꢀoscillatorsꢀwhichꢀrequireꢀnoꢀexternalꢀcomponentsꢀforꢀtheirꢀimplementation.ꢀ
Theꢀabilityꢀtoꢀoperateꢀandꢀswitchꢀdynamicallyꢀbetweenꢀaꢀrangeꢀofꢀoperatingꢀmodesꢀusingꢀdifferentꢀ
clockꢀsourcesꢀgivesꢀusersꢀtheꢀabilityꢀtoꢀoptimiseꢀmicrocontrollerꢀoperationꢀandꢀminimiseꢀpowerꢀ
consumption.
Theꢀdevicesꢀalsoꢀincludeꢀaꢀmultiplication/divisionꢀunit.ꢀTheꢀinclusionꢀofꢀflexibleꢀI/Oꢀprogrammingꢀ
features,ꢀTime-Baseꢀfunctionsꢀalongꢀwithꢀmanyꢀotherꢀfeaturesꢀensureꢀthatꢀonlyꢀaꢀminimumꢀofꢀ
externalꢀcomponentsꢀisꢀrequiredꢀforꢀapplicationꢀimplementation,ꢀresultingꢀinꢀreducedꢀcomponentꢀ
costsꢀandꢀreductionsꢀinꢀcircuitꢀboardꢀareas.
Rev. 1.10
ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Selection Table
Mostꢀfeaturesꢀareꢀcommonꢀtoꢀbothꢀdevices.ꢀTheꢀmainꢀfeaturesꢀdistinguishingꢀthemꢀareꢀMemoryꢀ
capacity.ꢀTheꢀfollowingꢀtableꢀsummarisesꢀtheꢀmainꢀfeaturesꢀofꢀeachꢀdevice.
A/D
Converter
Part No.
VDD
ROM
RAM
EEPROM
I/O
Ext.Int.
BH66Fꢅ650
BH66Fꢅ660
ꢅ.ꢅV~5.5V
ꢆK×16
ꢅ56×ꢆ
6ꢃ×ꢆ
ꢅꢆ
ꢅꢆ
ꢅ
ꢅ
ꢅꢃ-bit×ꢃ
ꢅꢃ-bit×ꢃ
ꢅ.ꢅV~5.5V 16K×16
10ꢅꢃ×ꢆ
ꢅ56×ꢆ
Part No.
Timer Module
Interface
MDU Time Base Stack
Package
10-bit PTM×3
16-bit STM×1
BH66Fꢅ650
SIM/UART/SPIA
SIM/UART/SPIA
√
√
ꢅ
ꢅ
ꢆ
ꢆ
ꢃꢆLQFP
10-bit PTM×3
16-bit STM×1
BH66Fꢅ660
ꢃꢆLQFP
Block Diagram
Exteꢁnal
HXT/LXT
Oscillatoꢁs
Inteꢁnal
HIRC/LIRC
Oscillatoꢁs
Watchdog
Timeꢁ
ꢆ-bit
RISC
MCU
Coꢁe
Reset
Ciꢁcꢀit
Flash/EEPROM
Pꢁogꢁamming Ciꢁcꢀitꢁꢂ
Low
Low
Voltage
Detect
Voltage
Reset
Inteꢁꢁꢀpt
Contꢁolleꢁ
EEPROM
Data
Memoꢁꢂ
Flash
Pꢁogꢁam
Memoꢁꢂ
RAM Data
Memoꢁꢂ
Time
Base
IAP
Bodꢂ Fat
Ciꢁcꢀit
ꢅꢃ-bit
Delta Sigma
A/D Conveꢁteꢁ
Mꢀltiplication/
Division
Unit
Timeꢁ
Modꢀles
I/O
UART
SPIA
SPI/IꢅC
LDO/PGA
Rev. 1.10
9
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Pin Assignment
ꢃ5
ꢃꢆ ꢃ7 ꢃ6
ꢃꢃ ꢃ3 ꢃꢅ ꢃ1 ꢃ0 39 3ꢆ 37
36
35
3ꢃ
33
1
ꢅ
PC0/PTP1/PTP1I
PC1/PTCK1
PCꢅ/PTPꢅ/PTPꢅI
PC3/PTCKꢅ
PD0
VOREG/VREFP
AVSS/VREFN
VCM
AN0
3
ꢃ
5
3ꢅ
31
AN1
ANꢅ
AN3
RFC
CP0N
TO
FVR
BH66F2650/BH66V2650
BH66F2660/BH66V2660
48 LQFP-A
6
7
PD1
30
ꢅ9
ꢅꢆ
ꢅ7
ꢅ6
ꢅ5
PB3/SDO/SDIA/RX
PC5/SDOA/TX
PBꢅ/SCS/SCKA
PCꢃ/SCSA
PD2/RX
ꢆ
9
10
11
1ꢅ
PD3/TX
FIR
13 1ꢃ 1516 17 1ꢆ 19 ꢅ0 ꢅ1 ꢅꢅ ꢅ3 ꢅꢃ
45
48 47 46
44 43 42 41 40 39 38 37
36
1
2
PC0/PTP1/PTP1I
PC1/PTCK1
PC2/PTP2/PTP2I
PC3/PTCK2
PD0
VOREG/VREFP
AVSS/VREFN
VCM
35
34
33
3
4
5
AN0
AN1
AN2
AN3
RFC
CP0N
TO
HVR
HIR
32
31
BH66F2650-8/BH66V2650-8
BH66F2660-8/BH66V2660-8
48 LQFP-B
6
7
PD1
30
29
28
27
26
25
PB3/SDO/SDIA/RX
PC5/SDOA/TX
PB2/SCS/SCKA
PC4/SCSA
PD2/RX
8
9
10
11
12
PD3/TX
13 14 15 16 17 18 19 20 21 22 23 24
Note:ꢀ1.ꢀIfꢀtheꢀpin-sharedꢀpinꢀfunctionsꢀhaveꢀmultipleꢀoutputs,ꢀtheꢀdesiredꢀpin-sharedꢀfunctionꢀisꢀdeterminedꢀbyꢀtheꢀ
correspondingꢀsoftwareꢀcontrolꢀbits.
2.ꢀTheꢀOCDSDAꢀandꢀOCDSCKꢀpinsꢀareꢀsuppliedꢀasꢀdedicatedꢀOCDSꢀpinsꢀandꢀasꢀsuchꢀonlyꢀavailableꢀforꢀ
theꢀBH66V2650/BH66V2660ꢀdevicesꢀwhichꢀareꢀtheꢀOCDSꢀEVꢀchipꢀforꢀtheꢀBH66F2650/BH66F2660ꢀ
devices.
Rev. 1.10
10
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Pin Description
Pin Name
Function OPT
I/T
O/T
Descriptions
Geneꢁal pꢀꢁpose I/O.
PAWU
PA0
PAPU
PAS0
ST CMOS
Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.
XT1
PTP0
PAS0 LXT
—
LXT input pin
PA0/XT1/PTP0/PTP0I/
OCDSDA/ICPDA
PAS0
PAS0
—
—
CMOS PTM0 oꢀtpꢀt
PTM0 captꢀꢁe inpꢀt
PTP0I
ST
—
OCDSDA
ICPDA
ST CMOS OCDS addꢁess/data lineꢄ foꢁ EV chip onlꢂ
ST CMOS ICP addꢁess/data line
—
PAWU
PAPU
PAS0
Geneꢁal pꢀꢁpose I/O.
ST CMOS
PA1
Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.
PAS0
INT0
INTEG ST
INTC0
—
—
Exteꢁnal inteꢁꢁꢀpt 0
LVD inpꢀt
PA1/INT0/LVDIN/
PTP0B/STCK
LVDIN
PAS0
PAS0
AN
—
PTP0B
CMOS PTM0 inveꢁting oꢀtpꢀt
PAS0
IFS0
STCK
ST
—
STM clock inpꢀt
PAWU
PAPU
PAS0
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.
PAꢅ
ST CMOS
PA2/XT2/PTCK0/
OCDSCK/ICPCK
XT2
PAS0
PAS0
—
—
ST
ST
ST
LXT LXT output pin
PTCK0
OCDSCK
ICPCK
—
—
—
PTM0 clock inpꢀt
OCDS clock inpꢀtꢄ foꢁ EV chip onlꢂ
ICP clock line
—
PAWU
PAPU
PAS0
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.
PA3
ST CMOS
OSCꢅ
SDOA
PTP1
PAS0
PAS0
PAS0
—
—
—
HXT HXT output pin
CMOS SPIA seꢁial data oꢀtpꢀt
CMOS PTM1 oꢀtpꢀt
PA3/OSCꢅ/SDOA/
PTP1/PTP1I
PAS0
IFS0
PTP1I
ST
—
PTM1 captꢀꢁe inpꢀt
PAWU
PAPU
PAS1
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.
PAꢃ
ST CMOS
OSC1
SCSA
PTPꢅ
PTPꢅI
PAS1 HXT
—
HXT input pin
PAꢃ/OSC1/SCSA/
PTPꢅ/PTPꢅI
PAS1
IFS1
ST CMOS SPIA slave select pin
PAS1
—
CMOS PTMꢅ oꢀtpꢀt
PTMꢅ captꢀꢁe inpꢀt
PAS1
IFS0
ST
—
PAWU
PAPU
PAS1
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.
PA5
ST CMOS
TX
PAS1
—
CMOS UART TX serial data output pin
SPIA seꢁial clock inpꢀt
PA5/TX/SCKA/STP/
STPI
PAS1
IFS1
SCKA
ST
—
STP
PAS1
PAS1
—
CMOS STM oꢀtpꢀt
STM captꢀꢁe inpꢀt
STPI
ST
—
Rev. 1.10
11
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Pin Name
Function OPT
I/T
O/T
Descriptions
PAWU
PAPU
PAS1
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.
PA6
ST CMOS
PAS1
IFS1
RX
ST
ST
ST
—
—
—
UART RX serial data input pin
SPIA seꢁial data inpꢀt
STM clock inpꢀt
PA6/RX/SDIA/STCK
PAS1
IFS1
SDIA
STCK
PAS1
IFS0
PAWU
PAPU
PAS1
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.
PA7
ST CMOS
SDI
PAS1
PAS1
ST
—
SPI (SIM) seꢁial data inpꢀt
PA7/SDI/SDA/PTCKꢅ
SDA
ST NMOS IꢅC (SIM) data line
PAS1
IFS0
PTCKꢅ
PB0
ST
—
PTMꢅ clock inpꢀt
PBPU
PBS0
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-high.
ST CMOS
PB0/SCK/SCL
SCK
SCL
PBS0
PBS0
ST CMOS SPI (SIM) seꢁial clock
ST NMOS IꢅC (SIM) clock line
PBPU
PBS0
Geneꢁal pꢀꢁpose I/O.
ST CMOS
PB1
Registeꢁ enabled pꢀll-high.
PBS0
INTEG ST
INTC0
PB1/INT1/STPB
INT1
—
Exteꢁnal inteꢁꢁꢀpt 1
STPB
PBꢅ
PBS0
—
CMOS STM inveꢁting oꢀtpꢀt
Geneꢁal pꢀꢁpose I/O.
PBPU
PBS0
ST CMOS
Registeꢁ enabled pꢀll-high.
PBꢅ/SCS/SCKA
SCS
PBS0
ST CMOS SPI (SIM) slave chip select
PBS0
IFS1
SCKA
ST CMOS SPIA seꢁial clock inpꢀt
PBPU
PBS0
Geneꢁal pꢀꢁpose I/O.
ST CMOS
PB3
SDO
SDIA
Registeꢁ enabled pꢀll-high.
PBS0
—
CMOS SPI (SIM) seꢁial data oꢀtpꢀt
PB3/SDO/SDIA/RX
PBS0
IFS1
ST
—
—
SPIA seꢁial data inpꢀt
PBS0
IFS1
RX
ST
UART RX serial data input pin
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-high.
PBꢃ~PB7
PBn
PBPU
ST CMOS
ST CMOS
PCPU
PCS0
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-high.
PC0
PTP1
PTP1I
PC0/PTP1/PTP1I
PCS0
—
CMOS PTM1 oꢀtpꢀt
PCS0
IFS0
ST
—
PTM1 captꢀꢁe inpꢀt
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-high.
PC1
PTCK1
PCꢅ
PCPU
—
ST CMOS
PC1/PTCK1
ST
—
PTM1 clock inpꢀt
PCPU
PCS0
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-high.
ST CMOS
PCꢅ/PTPꢅ/PTPꢅI
PTPꢅ
PTPꢅI
PCS0
—
CMOS PTMꢅ oꢀtpꢀt
PCS0
IFS0
ST
—
PTMꢅ captꢀꢁe inpꢀt
Rev. 1.10
1ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Pin Name
PC3/PTCKꢅ
Function OPT
I/T
O/T
Descriptions
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-high.
PC3
PTCKꢅ
PCꢃ
PCPU
—
ST CMOS
ST
—
PTMꢅ clock inpꢀt
PCPU
PCS1
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-high.
ST CMOS
PCꢃ/SCSA
PCS1
IFS1
SCSA
PC5
ST CMOS SPIA slave select pin
PCPU
PCS1
Geneꢁal pꢀꢁpose I/O.
ST CMOS
Registeꢁ enabled pꢀll-high.
PC5/SDOA/TX
PAS0
PCS1
SDOA
TX
—
—
CMOS SPIA seꢁial data oꢀtpꢀt
PCS1
CMOS UART TX serial data output pin
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-high.
PC6~ PC7
PD0~ PD1
PCn
PCPU
ST CMOS
ST CMOS
ST CMOS
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-high.
PDn
PDꢅ
RX
PDPU
PDPU
PDS0
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-high.
PD2/RX
PDS0
IFS1
ST
—
UART RX serial data input pin
PDPU
PDS0
Geneꢁal pꢀꢁpose I/O.
Registeꢁ enabled pꢀll-high.
PD3
ST CMOS
PD3/TX
TX
PDS0
—
—
CMOS UART TX serial data output pin
A/D Converter
PWR
PWR
AN
—
—
—
—
LDO oꢀtpꢀt pin
VOREG
Positive poweꢁ sꢀpplꢂ foꢁ VCMꢄ
A/D conveꢁteꢁꢄ PGA
VOREG/VREFP
VREFP
AVSS
—
—
Exteꢁnal positive ꢁefeꢁence inpꢀt of A/D conveꢁteꢁ
Negative poweꢁ sꢀpplꢂ foꢁ VCMꢄ
A/D conveꢁteꢁꢄ PGA
PWR
AVSS/VREFN
VREFN
ANn
—
—
AN
AN
AN
—
—
—
Exteꢁnal negative ꢁefeꢁence inpꢀt of A/D conveꢁteꢁ
A/D inpꢀt pin
AN0 ~ AN3
VCM
—
Exteꢁnal inpꢀt voltage foꢁ A/D conveꢁteꢁ common mode
A/D conveꢁteꢁ Common mode voltage oꢀtpꢀt
VCM
—
AN
Body Fat Circuit
RFC
CP0N
TO
RFC
CP0N
TO
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AN
AN
—
—
A/D conveꢁteꢁ analog inpꢀt
Peak detectoꢁ inpꢀt
—
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
Operational amplifier output
Right hand channel 1
Right hand channel ꢅ
Right foot channel 1
HVR
HIR
FVR
FIR
HVR
HIR
FVR
FIR
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
—
Right foot channel ꢅ
RFꢅ
RF1
FIL
RFꢅ
RF1
FIL
Refeꢁence ꢅ impedance channel
Refeꢁence 1 impedance channel
Left foot channel ꢅ
FVL
HVL
HIL
FVL
HVL
HIL
Left foot channel 1
Left hand channel 1
Left hand channel ꢅ
RF
RF
Refeꢁence 1/ꢅ impedance channel
Sine wave oꢀtpꢀt
SIN
SIN
Rev. 1.10
13
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
OperatingꢀTemperature
StorageꢀTemperature
..................................................................................................... -50°Cꢀtoꢀ125°C
................................................................................................... -40°Cꢀtoꢀ85°C
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Pin Name
Power
Function OPT
I/T
O/T
Descriptions
VDD
VIN
—
—
—
PWR
PWR
PWR
—
—
—
Positive poweꢁ sꢀpplꢂ
LDO inpꢀt pin
VDD/VIN
VSS
VSS
Negative poweꢁ sꢀpplꢂ.
Legend: I/T: Inpꢀt tꢂpe;
O/T: Oꢀtpꢀt tꢂpe
PWR: Poweꢁ
OPT: Optional bꢂ ꢁegisteꢁ option;
ST: Schmitt Tꢁiggeꢁ inpꢀt;
NMOS: NMOS oꢀtpꢀt;
CMOS: CMOS oꢀtpꢀt
AN: Analog signal
HXT: High frequency crystal oscillator;
LXT: Low frequency crystal oscillator
Absolute Maximum Ratings
SupplyꢀVoltageꢀ......................................................................................................VSS-0.3V~VSS+6.0V
InputꢀVoltageꢀ.....................................................................................................VSS-0.3VꢀtoꢀVDD+0.3V
IOHꢀTotalꢀ...................................................................................................................................... -80mA
IOLꢀTotalꢀ....................................................................................................................................... 80mA
TotalꢀPowerꢀDissipationꢀ........................................................................................................... 500mW
Note:ꢀTheseꢀareꢀstressꢀratingsꢀonly.ꢀStressesꢀexceedingꢀtheꢀrangeꢀspecifiedꢀunderꢀ“Absoluteꢀ
MaximumꢀRatings”ꢀmayꢀcauseꢀsubstantialꢀdamageꢀtoꢀtheꢀdevices.ꢀFunctionalꢀoperationꢀofꢀ
theseꢀdevicesꢀatꢀotherꢀconditionsꢀbeyondꢀthoseꢀlistedꢀinꢀtheꢀspecificationꢀisꢀnotꢀimpliedꢀandꢀ
prolongedꢀexposureꢀtoꢀextremeꢀconditionsꢀmayꢀaffectꢀdeviceꢀreliability.
D.C. Characteristics
Forꢀdataꢀinꢀtheꢀfollowingꢀtables,ꢀnoteꢀthatꢀfactorsꢀsuchꢀasꢀoscillatorꢀtype,ꢀoperatingꢀvoltage,ꢀoperatingꢀ
frequency,ꢀpinꢀloadꢀconditions,ꢀtemperatureꢀandꢀprogramꢀinstructionꢀtype,ꢀetc.,ꢀcanꢀallꢀexertꢀanꢀ
influenceꢀonꢀtheꢀmeasuredꢀvalues.
Operating Voltage Characteristics
Ta=-ꢃ0°C ~ ꢆ5°C
Symbol
Parameter
Test Conditions
fSYS=ꢃMHz
Min.
ꢅ.ꢅ
ꢅ.ꢅ
ꢅ.7
3.3
ꢅ.ꢅ
ꢅ.ꢅ
ꢅ.7
ꢅ.ꢅ
ꢅ.ꢅ
Typ.
—
—
—
—
—
—
—
—
—
Max.
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
Unit
fSYS=ꢆMHz
Opeꢁating Voltage – HXT
V
fSYS=1ꢅMHz
fSYS=16MHz
fSYS=ꢃMHz
VDD
Opeꢁating Voltage – HIRC
fSYS=ꢆMHz
V
fSYS=1ꢅMHz
fSYS=3ꢅ.76ꢆkHz
fSYS=3ꢅkHz
Opeꢁating Voltage – LXT
V
V
Opeꢁating Voltage – LIRC
Rev. 1.10
1ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Standby Current Characteristics
Ta=ꢅ5°C
Test Conditions
Conditions
Max.
85°C
0.7
Symbol
Standby Mode
Min.
Typ.
Max.
Unit
VDD
ꢅ.ꢅV
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.ꢅ
0.ꢅ
0.6
0.ꢆ
3V WDT off
1.0
μA
μA
5V
0.5
1.0
1.ꢅ
SLEEP Mode
ꢅ.ꢅV
1.ꢅ
ꢅ.ꢃ
ꢅ.9
3V WDT on
1.5
3.0
3.6
5V
3.0
5.0
6.0
ꢅ.ꢅV
ꢅ.ꢃ
ꢃ.0
ꢃ.ꢆ
IDLE0 Mode – LIRC
3V fSUB on
3.0
5.0
6.0
μA
5V
5.0
10
1ꢅ
ꢅ.ꢅV
ꢅ.ꢃ
ꢃ.0
ꢃ.ꢆ
IDLE0 Mode – LXT
3V fSUB on
3.0
5.0
6.0
μA
5V
5.0
10
1ꢅ
ꢅ.ꢅV
0.17
0.ꢅ5
0.ꢃꢆ
0.3ꢅ
0.ꢃ7
0.91
0.60
0.6ꢆ
1.33
0.17
0.ꢅ5
0.ꢃꢆ
0.3ꢅ
0.ꢃ7
0.91
0.60
0.6ꢆ
1.33
1.10
1.ꢆ0
0.ꢅꢃ
0.35
0.67
0.ꢃ5
0.66
1.ꢅ7
0.ꢆꢃ
0.95
1.ꢆ6
0.ꢅꢃ
0.35
0.67
0.ꢃ5
0.66
1.ꢅ7
0.ꢆꢃ
0.95
1.ꢆ6
1.60
ꢅ.50
0.ꢅ6
0.3ꢆ5
0.70
0.ꢃꢆ
0.70
1.30
0.ꢆ7
1.00
1.90
0.ꢅ6
0.3ꢆ5
0.70
0.ꢃꢆ
0.70
1.30
0.ꢆ7
1.00
1.90
1.90
ꢅ.60
3V fSUB onꢄ fSYS=ꢃMHz
mA
mA
mA
mA
mA
5V
ꢅ.ꢅV
ISTB
IDLE1 Mode – HIRC
3V fSUB onꢄ fSYS =ꢆMHz
5V
ꢅ.7V
3V fSUB onꢄ fSYS=1ꢅMHz
5V
ꢅ.ꢅV
3V fSUB onꢄ fSYS =ꢃMHz
5V
ꢅ.ꢅV
3V fSUB onꢄ fSYS=ꢆMHz
IDLE1 Mode – HXT
5V
ꢅ.7V
3V fSUB onꢄ fSYS=1ꢅMHz
5V
mA
mA
3.3V
fSUB onꢄ fSYS=16MHz
5V
Notes:ꢀWhenꢀusingꢀtheꢀcharacteristicꢀtableꢀdata,ꢀtheꢀfollowingꢀnotesꢀshouldꢀbeꢀtakenꢀintoꢀconsideration:
1.ꢀAnyꢀdigitalꢀinputsꢀareꢀsetupꢀinꢀaꢀnon-floatingꢀcondition.
2.ꢀAllꢀmeasurementsꢀareꢀtakenꢀunderꢀconditionsꢀofꢀnoꢀloadꢀandꢀwithꢀallꢀperipheralsꢀinꢀanꢀoffꢀstate.
3.ꢀThereꢀareꢀnoꢀDCꢀcurrentꢀpaths.
4.ꢀAllꢀStandbyꢀCurrentꢀvaluesꢀareꢀtakenꢀafterꢀaꢀHALTꢀinstructionꢀexecutionꢀthusꢀstoppingꢀallꢀinstructionꢀ
execution.
Rev. 1.10
15
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Operating Current Characteristics
Ta=ꢅ5°C
Test Conditions
Conditions
Symbol
Operating Mode
Min. Typ. Max. Unit
VDD
ꢅ.ꢅV
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ꢆ
16
ꢅ0
SLOW Mode – LIRC
3V fSYS = 3ꢅkHz
10
μA
μA
5V
30
50
ꢅ.ꢅV
ꢆ
16
SLOW Mode – LXT
3V fSYS = 3ꢅ76ꢆHz
10
ꢅ0
5V
30
50
ꢅ.ꢅV
0.3
0.ꢃ
0.ꢆ
0.6
0.ꢆ
1.6
1.0
1.ꢅ
ꢅ.ꢃ
0.ꢃ
0.5
1.0
0.ꢆ
1.0
ꢅ.0
1.ꢅ
1.5
3.0
3.ꢅ
ꢃ.0
0.5
0.6
1.ꢅ
1.0
1.ꢅ
ꢅ.ꢃ
1.ꢃ
1.ꢆ
3.6
0.6
0.75
1.5
1.ꢅ
1.5
3.0
ꢅ.ꢅ
ꢅ.75
ꢃ.5
ꢃ.ꢆ
6.0
3V fSYS = ꢃMHz
mA
mA
mA
mA
mA
5V
ꢅ.ꢅV
FAST Mode – HIRC
3V fSYS = ꢆMHz
5V
ꢅ.7V
IDD
3V fSYS = 1ꢅMHz
5V
ꢅ.ꢅV
3V fSYS = ꢃMHz
5V
ꢅ.ꢅV
3V fSYS = ꢆMHz
FAST Mode – HXT
5V
ꢅ.7V
3V fSYS = 1ꢅMHz
5V
mA
mA
3.3V
fSYS = 16MHz
5V
Notes:ꢀWhenꢀusingꢀtheꢀcharacteristicꢀtableꢀdata,ꢀtheꢀfollowingꢀnotesꢀshouldꢀbeꢀtakenꢀintoꢀconsideration:
1.ꢀAnyꢀdigitalꢀinputsꢀareꢀsetupꢀinꢀaꢀnon-floatingꢀcondition.
2.ꢀAllꢀmeasurementsꢀareꢀtakenꢀunderꢀconditionsꢀofꢀnoꢀloadꢀandꢀwithꢀallꢀperipheralsꢀinꢀanꢀoffꢀstate.
3.ꢀThereꢀareꢀnoꢀDCꢀcurrentꢀpaths.
4.ꢀAllꢀOperatingꢀCurrentꢀvaluesꢀareꢀmeasuredꢀusingꢀaꢀcontinuousꢀNOPꢀinstructionꢀprogramꢀloop.
Rev. 1.10
16
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
A.C. Characteristics
Forꢀdataꢀinꢀtheꢀfollowingꢀtables,ꢀnoteꢀthatꢀfactorsꢀsuchꢀasꢀoscillatorꢀtype,ꢀoperatingꢀvoltage,ꢀoperatingꢀ
frequencyꢀandꢀtemperatureꢀetc.,ꢀcanꢀallꢀexertꢀanꢀinfluenceꢀonꢀtheꢀmeasuredꢀvalues.
High Speed Internal Oscillator – HIRC – Frequency Accuracy
DuringꢀtheꢀprogramꢀwritingꢀoperationꢀtheꢀwriterꢀwillꢀtrimꢀtheꢀHIRCꢀoscillatorꢀatꢀaꢀuserꢀselectedꢀ
HIRCꢀfrequencyꢀandꢀuserꢀselectedꢀvoltageꢀofꢀeitherꢀ3Vꢀorꢀ5V.ꢀ
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDD
Temp.
ꢅ5°C
-1%
-ꢅ%
ꢃ
ꢃ
+1%
+ꢅ%
3V/5V
-ꢃ0°C ~ ꢆ5°C
ꢅ5°C
ꢃMHz Wꢁiteꢁ Tꢁimmed HIRC
Fꢁeqꢀencꢂ
MHz
-ꢅ.5%
-3%
ꢃ
+ꢅ.5%
+3%
ꢅ.ꢅV~5.5V
3V/5V
-ꢃ0°C ~ ꢆ5°C
ꢅ5°C
ꢃ
-1%
ꢆ
+1%
-ꢃ0°C ~ ꢆ5°C
ꢅ5°C
-ꢅ%
ꢆ
+ꢅ%
ꢆMHz Wꢁiteꢁ Tꢁimmed HIRC
Fꢁeqꢀencꢂ
fHIRC
MHz
MHz
-ꢅ.5%
-3%
ꢆ
+ꢅ.5%
-3%
ꢅ.ꢅV~5.5V
5V
-ꢃ0°C ~ ꢆ5°C
ꢅ5°C
ꢆ
-1%
1ꢅ
1ꢅ
1ꢅ
1ꢅ
+1%
-ꢃ0°C ~ ꢆ5°C
ꢅ5°C
-ꢅ%
+ꢅ%
1ꢅMHz Wꢁiteꢁ Tꢁimmed HIRC
Fꢁeqꢀencꢂ
-ꢅ.5%
-3%
+ꢅ.5%
+3%
ꢅ.7V~5.5V
-ꢃ0°C ~ ꢆ5°C
Notes:ꢀ1.ꢀTheꢀ3V/5VꢀvaluesꢀforꢀVDDꢀareꢀprovidedꢀasꢀtheseꢀareꢀtheꢀtwoꢀselectableꢀfixedꢀvoltagesꢀatꢀwhichꢀtheꢀHIRCꢀ
frequencyꢀisꢀtrimmedꢀbyꢀtheꢀwriter.
2.ꢀTheꢀrowꢀbelowꢀtheꢀ3V/5VꢀtrimꢀvoltageꢀrowꢀisꢀprovidedꢀtoꢀshowꢀtheꢀvaluesꢀforꢀtheꢀfullꢀVDDꢀrangeꢀoperatingꢀ
voltage.ꢀItꢀisꢀrecommendedꢀthatꢀtheꢀtrimꢀvoltageꢀisꢀfixedꢀatꢀ3Vꢀforꢀapplicationꢀvoltageꢀrangesꢀfromꢀ2.2Vꢀ
toꢀ3.6Vꢀandꢀfixedꢀatꢀ5Vꢀforꢀapplicationꢀvoltageꢀrangesꢀfromꢀ3.3Vꢀtoꢀ5.5V.
3.ꢀTheꢀminimumꢀandꢀmaximumꢀtoleranceꢀvaluesꢀprovidedꢀinꢀtheꢀtableꢀareꢀonlyꢀforꢀtheꢀfrequencyꢀatꢀwhichꢀ
theꢀwriterꢀtrimsꢀtheꢀHIRCꢀoscillator.ꢀAfterꢀtrimmingꢀatꢀthisꢀchosenꢀspecificꢀfrequencyꢀanyꢀchangeꢀinꢀ
HIRCꢀoscillatorꢀfrequencyꢀusingꢀtheꢀoscillatorꢀregisterꢀcontrolꢀbitsꢀbyꢀtheꢀapplicationꢀprogramꢀwillꢀgiveꢀaꢀ
frequencyꢀtoleranceꢀtoꢀwithinꢀ±20%.
Low Speed Internal Oscillator Characteristics – LIRC
Ta=25°C, unless otherwise specified
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Temp.
ꢅ5°C
-5%
3ꢅ
3ꢅ
+5%
fLIRC
LIRC Fꢁeqꢀencꢂ
ꢅ.ꢅV~5.5V
kHz
-ꢃ0°C~ꢆ5°C
-10%
+10%
Rev. 1.10
17
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Operating Frequency Characteristic Curves
System Operating Frequency
16MHz
1ꢅMHz
ꢆMHz
ꢃMHz
ꢅ.ꢅV
ꢅ.7V
3.3V
5.5V
Operating Voltage
System Start Up Time Characteristics
Ta=-ꢃ0°C~ꢆ5°C
Min. Typ. Max. Unit
Test Conditions
Symbol
Parameter
VDD
—
Conditions
fSYS = fH ~ fH/6ꢃꢄ fH = fHXT
fSYS = fH ~ fH/6ꢃꢄ fH = fHIRC
fSYS = fSUB = fLXT
—
—
—
—
1ꢅꢆ
16
—
—
—
—
tHXT
tHIRC
tLXT
Sꢂstem Staꢁt-ꢀp Time
Wake-ꢀp fꢁom condition
wheꢁe fSYS is off
—
—
10ꢅꢃ
ꢅ
—
fSYS = fSUB = fLIRC
tLIRC
fSYS = fH ~ fH/6ꢃꢄ
fH = fHXT oꢁ fHIRC
Sꢂstem Staꢁt-ꢀp Time
Wake-ꢀp fꢁom condition
wheꢁe fSYS is on
tSST
—
—
ꢅ
—
tH
—
—
—
—
fSYS = fSUB = fLXT oꢁ fLIRC
—
—
—
—
ꢅ
—
—
—
—
tSUB
tHXT
tHIRC
tLXT
fHXT switches from off → on
fHIRC switches fꢁom off → on
fLXT switches from off → on
10ꢅꢃ
16
Sꢂstem Speed Switch Time
FAST to SLOW Mode oꢁ
SLOW to FAST Mode
10ꢅꢃ
Sꢂstem Reset Delaꢂ Time
Reset soꢀꢁce fꢁom Poweꢁ-on ꢁeset oꢁ
LVR haꢁdwaꢁe ꢁeset
—
—
RRPOR=5V/ms
—
ꢃꢅ
ꢃꢆ
5ꢃ
ms
tRSTD
Sꢂstem Reset Delaꢂ Time
LVRC/WDTC/RSTC softwaꢁe ꢁeset
Sꢂstem Reset Delaꢂ Time
Reset source from WDT overflow
—
—
—
—
1ꢃ
ꢃ5
16
90
1ꢆ
ms
tSRESET
Minimꢀm Softwaꢁe Reset Width to Reset
1ꢅ0
μs
Notes:ꢀ1.ForꢀtheꢀSystemꢀStart-upꢀtimeꢀvalues,ꢀwhetherꢀfSYSꢀisꢀonꢀorꢀoffꢀdependsꢀuponꢀtheꢀmodeꢀtypeꢀandꢀtheꢀchosenꢀ
fSYSꢀsystemꢀoscillator.ꢀDetailsꢀareꢀprovidedꢀinꢀtheꢀSystemꢀOperatingꢀModesꢀsection.
2.ꢀTheꢀtimeꢀunits,ꢀshownꢀbyꢀtheꢀsymbolsꢀtHXT,ꢀtHIRCꢀetc.ꢀareꢀtheꢀinverseꢀofꢀtheꢀcorrespondingꢀfrequencyꢀvaluesꢀ
asꢀprovidedꢀinꢀtheꢀfrequencyꢀtables.ꢀForꢀexampleꢀtHIRCꢀ=ꢀ1/fHIRC,ꢀtSYSꢀ=ꢀ1/fSYSꢀetc.
3.ꢀIfꢀtheꢀLIRCꢀisꢀusedꢀasꢀtheꢀsystemꢀclockꢀandꢀifꢀitꢀisꢀoffꢀwhenꢀinꢀtheꢀSLEEPꢀMode,ꢀthenꢀanꢀadditionalꢀLIRCꢀ
startꢀupꢀtime,ꢀtSTART,ꢀasꢀprovidedꢀinꢀtheꢀLIRCꢀfrequencyꢀtable,ꢀmustꢀbeꢀaddedꢀtoꢀtheꢀtSSTꢀtimeꢀinꢀtheꢀtableꢀ
above.
4.ꢀTheꢀSystemꢀSpeedꢀSwitchꢀTimeꢀisꢀeffectivelyꢀtheꢀtimeꢀtakenꢀforꢀtheꢀnewlyꢀactivatedꢀoscillatorꢀtoꢀstartꢀup.
Rev. 1.10
1ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Input/Output Characteristics
Ta=ꢅ5°C
Test Conditions
Conditions
Symbol
VIL
Parameter
Min. Typ. Max. Unit
VDD
5V
—
0
0
—
—
—
—
3ꢅ
65
1.5
0.ꢅVDD
5.0
Inpꢀt Low Voltage foꢁ I/O Poꢁts
Inpꢀt High Voltage foꢁ I/O Poꢁts
Sink Cꢀꢁꢁent foꢁ I/O Poꢁts
—
—
V
V
5V
—
3.5
0.ꢆVDD
16
VIH
VDD
—
3V
5V
IOL
VOL=0.1VDD
mA
3ꢅ
—
VOH = 0.9VDD
ꢄ
3V
5V
3V
5V
3V
5V
3V
5V
SLEDCn[m+1ꢄ m] = 00B
(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
-0.7 -1.5
-1.5 -ꢅ.9
-1.3 -ꢅ.5
-ꢅ.5 -5.1
-1.ꢆ -3.6
-3.6 -7.3
—
—
—
—
—
—
—
—
VOH = 0.9VDD
ꢄ
SLEDCn[m+1ꢄ m] = 00B
(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
VOH = 0.9VDD
ꢄ
SLEDCn[m+1ꢄ m] = 01B
(n = 0ꢄ1;m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
VOH = 0.9VDD
ꢄ
SLEDCn[m+1ꢄ m] = 01B
(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
IOH
Soꢀꢁce Cꢀꢁꢁent foꢁ I/O Poꢁts
mA
VOH = 0.9VDD
ꢄ
SLEDCn[m+1ꢄ m] = 10B
(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
VOH = 0.9VDD
ꢄ
SLEDCn[m+1ꢄ m] = 10B
(n = 0ꢄ1;m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
VOH = 0.9VDD
ꢄ
SLEDCn[m+1ꢄ m] = 11B
(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
-ꢃ
-ꢆ
-ꢆ
VOH = 0.9VDD
ꢄ
SLEDCn[m+1ꢄ m] = 11B
-16
(n = 0ꢄ1;m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
3V
5V
IOL = 16mA
IOL = 3ꢅmA
—
—
—
—
0.3
0.5
VOL
Oꢀtpꢀt Low Voltage foꢁ I/O Poꢁts
V
Rev. 1.10
19
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Test Conditions
Min. Typ. Max. Unit
Conditions
Symbol
Parameter
VDD
IOH = -0.7mAꢄ
3V
SLEDCn[m+1ꢄ m] = 00B
(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
ꢅ.7
ꢃ.5
ꢅ.7
ꢃ.5
ꢅ.7
ꢃ.5
ꢅ.7
ꢃ.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOH = -1.5mAꢄ
SLEDCn[m+1ꢄ m] = 00B
(n = 0ꢄ1;m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
5V
3V
5V
3V
5V
3V
5V
IOH = -1.3mAꢄ
SLEDCn[m+1ꢄ m] = 01B
(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
IOH = -ꢅ.5mAꢄ
SLEDCn[m+1ꢄ m] = 01B
(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
VOH
Oꢀtpꢀt High Voltage foꢁ I/O Poꢁts
V
IOH = -1.ꢆmAꢄ
SLEDCn[m+1ꢄ m] = 10B
(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
IOH = -3.6mAꢄ
SLEDCn[m+1ꢄ m] = 10B
(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
IOH = -ꢃmAꢄ
SLEDCn[m+1ꢄ m] = 11B
(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
IOH = -ꢆmAꢄ
SLEDCn[m+1ꢄ m] = 11B
(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)
3V
5V
ꢅ0
10
—
60
30
—
100
50
RPH
Pꢀll-High Resistance foꢁ I/O Poꢁts (Note)
Inpꢀt Leakage Cꢀꢁꢁent
—
kΩ
ILEAK
tTPI
tTCK
tINT
3V/5V VIN = VDD oꢁ VIN = VSS
±1
μA
μs
STPIꢄ PTPnI Inpꢀt Pin Minimꢀm Pꢀlse
Width
—
—
—
—
—
—
0.3
0.3
10
—
—
—
—
—
—
STCKꢄ PTCKn Inpꢀt Pin Minimꢀm
Pꢀlse Width
μs
μs
Exteꢁnal Inteꢁꢁꢀpt Minimꢀm Pꢀlse
Width
Note:ꢀTheꢀRPHꢀinternalꢀpullꢀhighꢀresistanceꢀvalueꢀisꢀcalculatedꢀbyꢀconnectingꢀtoꢀgroundꢀandꢀenablingꢀtheꢀinputꢀpinꢀ
withꢀaꢀpull-highꢀresistorꢀandꢀthenꢀmeasuringꢀtheꢀinputꢀsinkꢀcurrentꢀatꢀtheꢀspecifiedꢀsupplyꢀvoltageꢀlevel.ꢀ
DividingꢀtheꢀvoltageꢀbyꢀthisꢀmeasuredꢀcurrentꢀprovidesꢀtheꢀRPHꢀvalue.
Memory Characteristics
Ta=-ꢃ0°C~ꢆ5°C
Test Conditions
Symbol
Parameter
VDD foꢁ Read / Wꢁite
Min. Typ. Max. Unit
VDD
Conditions
VRW
—
—
VDDmin
—
VDDmax
V
Program Flash / Data EEPROM Memory
tDEW
IDDPGM
EP
Eꢁase / Wꢁite Cꢂcle Time
Pꢁogꢁamming / Eꢁase Cꢀꢁꢁent on VDD
Cell Endꢀꢁance
—
—
—
—
—
—
—
ꢅ.ꢅ
—
ꢅ.5
—
ꢅ.ꢆ
5.0
—
ms
mA
100K
—
—
E/W
Yeaꢁ
tRETD
ROM Data Retention Time
Ta = ꢅ5°C
ꢃ0
—
RAM Data Memory
VDR
RAM Data Retention Voltage
—
—
1.0
—
—
V
Rev. 1.10
ꢅ0
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
LVD/LVR Electrical Characteristics
Ta=ꢅ5°C
Test Conditions
Symbol
Parameter
Opeꢁating Voltage
Min. Typ. Max. Unit
VDD
—
—
—
—
—
—
—
—
—
—
—
—
—
Conditions
VDD
—
ꢅ.ꢅ
—
5.5
V
LVR enableꢄ voltage select ꢅ.10V
LVR enableꢄ voltage select ꢅ.55V
LVR enableꢄ voltage select 3.15V
LVR enableꢄ voltage select 3.ꢆ0V
LVD enableꢄ voltage select 1.0ꢃV
LVD enableꢄ voltage select ꢅ.ꢅ0V
LVD enableꢄ voltage select ꢅ.ꢃ0V
LVD enableꢄ voltage select ꢅ.70V
LVD enableꢄ voltage select 3.00V
LVD enableꢄ voltage select 3.30V
LVD enableꢄ voltage select 3.60V
LVD enableꢄ voltage select ꢃ.00V
-5%
ꢅ.1
+5%
-5% ꢅ.55 +5%
-5% 3.15 +5%
VLVR
Low Voltage Reset Voltage
V
-5%
3.ꢆ
+5%
-10% 1.0ꢃ +10%
-5%
-5%
-5%
-5%
-5%
-5%
-5%
—
ꢅ.ꢅ
ꢅ.ꢃ
ꢅ.7
3.0
3.3
3.6
ꢃ.0
—
+5%
+5%
+5%
+5%
+5%
+5%
+5%
1ꢆ
VLVD
Low Voltage Detection Voltage
V
3V LVD enableꢄ LVR enableꢄ VBGEN=0
5V LVD enableꢄ LVR enableꢄ VBGEN=0
3V LVD enableꢄ LVR enableꢄ VBGEN=1
5V LVD enableꢄ LVR enableꢄ VBGEN=1
—
ꢅ0
ꢅ5
ILVRLVDBG Opeꢁating Cꢀꢁꢁent
μA
μs
—
—
150
30
—
ꢅ5
Foꢁ LVR enableꢄ VBGEN=0ꢄ
LVD off → on
—
—
—
—
—
15
tLVDS
LVDO Stable Time
Foꢁ LVR disableꢄ VBGEN=0ꢄ
LVD off → on
—
150
ꢃꢆ0
ꢅꢃ0
Minimꢀm Low Voltage Width to
Reset
tLVR
tLVD
—
—
—
—
1ꢅ0
60
ꢅꢃ0
1ꢅ0
μs
μs
Minimꢀm Low Voltage Width to
Inteꢁꢁꢀpt
ILVR
ILVD
Additional Cꢀꢁꢁent foꢁ LVR Enable
Additional Cꢀꢁꢁent foꢁ LVD Enable
—
—
LVD disableꢄ VBGEN=0
LVR disableꢄ VBGEN=0
—
—
—
—
ꢅꢃ
ꢅꢃ
μA
μA
24-bit A/D Converter Electrical Characteristics
LDO + VCM Test conditions: MCU HALTꢄ otheꢁ fꢀnction disable;
VDD=VINꢄ Ta=ꢅ5°C
Test Conditions
Symbol
VIN
IQ
Parameter
Min.
Typ.
Max.
Unit
VDD
Conditions
LDO Inpꢀt Voltage
—
—
ꢅ.6
—
—
5.5
V
LDOVS[1:0]=00Bꢄ VIN =3.6Vꢄ
No load
LDO Qꢀiescent Cꢀꢁꢁent
—
—
—
—
—
—
ꢃ00
5ꢅ0
μA
LDOVS[1:0]=00Bꢄ VIN=3.6Vꢄ
ILOAD=0.1mA
ꢅ.ꢃ
ꢅ.6
ꢅ.9
3.3
LDOVS[1:0]=01Bꢄ VIN=3.6Vꢄ
ILOAD=0.1mA
VOUT_LDO LDO Oꢀtpꢀt Voltage
-5%
—
+ 5%
V
LDOVS[1:0]=10Bꢄ VIN=3.6Vꢄ
ILOAD=0.1mA
LDOVS[1:0]=11Bꢄ VIN=3.6Vꢄ
ILOAD=0.1mA
LDOVS[1:0]=00Bꢄ VIN=VOUT_LDO+0.ꢅVꢄ
0mA ≤ ILOAD ≤ 10mA
ΔVLOAD
LDO Load Regꢀlation(Note 1)
0.105 0.ꢅ1 %/mA
Rev. 1.10
ꢅ1
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
LDOVS[1:0]=00Bꢄ VIN=3.6Vꢄ
ILOAD=10mA, ∆VOUT_LDO=ꢅ%
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ꢅꢅ0
ꢅ00
1ꢆ0
160
LDOVS[1:0]=01Bꢄ VIN=3.6Vꢄ
ILOAD=10mA, ∆VOUT_LDO=ꢅ%
—
—
—
—
VDROP_LDO LDO Dꢁopoꢀt Voltage(Noteꢅ)
mV
LDOVS[1:0]=10Bꢄ VIN=3.6Vꢄ
ILOAD=10mA, ∆VOUT_LDO=ꢅ%
LDOVS[1:0]=11Bꢄ VIN=3.6Vꢄ
ILOAD=10mA, ∆VOUT_LDO=ꢅ%
LDO Tempeꢁatꢀꢁe
Coefficient
Ta=-ꢃ0°C~ꢆ5°Cꢄ LDOVS[1:0]=00Bꢄ
VIN=3.6Vꢄ ILOAD=100μA
TCLDO
0.ꢃꢆ mV/°C
LDOVS[1:0]=00B, 2.6V ≤ VIN ≤ 5.5V,
ILOAD=100μA
0.7
0.ꢅ
%/V
ΔVLINE_LDO LDO Line Regꢀlation
—
LDOVS[1:0]=00B, 2.6V ≤ VIN ≤ 3.6V,
ILOAD=100μA
—
-5%
—
%/V
V
VOUT_VCM VCM Oꢀtpꢀt Voltage
—
—
VOREG=3.3Vꢄ No load
1.ꢅ5 + 5%
VCM Tempeꢁatꢀꢁe
Coefficient
Ta=-ꢃ0°C~ꢆ5°Cꢄ VOREG=3.3Vꢄ
ILOAD=10μA
TCVCM
—
0.ꢅꢃ mV/°C
ΔVLINE_VCM VCM Line Regꢀlation
—
—
2.4V ≤ VOREG ≤ 3.3V, No load
—
—
—
—
0.3
10
%/V
ms
tVCMS
VCM Tꢀꢁn on Stable Time
VOREG=3.3Vꢄ No load
Soꢀꢁce Cꢀꢁꢁent foꢁ VCM
Oꢀtpꢀt Pin
IOH
—
—
VOREG=3.3V, ∆VOUT_VCM=-ꢅ%
VOREG=3.3V, ∆VOUT_VCM=+ꢅ%
1
1
—
—
—
—
mA
mA
Sink Cꢀꢁꢁent foꢁ VCM
Oꢀtpꢀt Pin
IOL
A/D Converter & A/D Converter Internal Reference Voltage (Delta Sigma A/D Converter)
—
—
LDOEN=0
LDOEN=1
ꢅ.ꢃ
ꢅ.ꢃ
—
—
3.3
3.3
Sꢀpplꢂ Voltage foꢁ VCMꢄ
A/D conveꢁteꢁꢄ PGAꢄ OPA
VOREG
V
VCM enableꢄ VRBUFP=1 and
VRBUFN=1
—
—
—
—
750
600
900
750
Additional Cꢀꢁꢁent foꢁ A/D
Conveꢁteꢁ Enable
IADC
μA
VCM enableꢄ VRBUFP=0 and
VRBUFN=0
IADSTB
NR
Standbꢂ Cꢀꢁꢁent
Resolꢀtion
—
—
MCU enteꢁs SLEEP modeꢄ No Load
—
—
—
—
—
1
μA
ꢅꢃ
Bit
VOREG=3.3Vꢄ VREF=1.ꢅ5Vꢄ
∆SI=±450mV, PGA gain=1
INL
Integꢁal Non-lineaꢁitꢂ
—
—
±50
±ꢅ00
ppm
NFB
Noise Fꢁee Bits
—
—
PGA gain=1ꢅꢆꢄ Data ꢁate=10Hz
PGA gain=1ꢅꢆꢄ Data ꢁate=10Hz
—
—
15.ꢃ
1ꢆ.1
—
—
Bit
Bit
ENOB
Effective Nꢀmbeꢁ of Bits
A/D Conveꢁteꢁ
Clock Fꢁeqꢀencꢂ
fADCK
fADO
VREFP
VREFN
—
—
ꢃ0
ꢃ09.6
ꢃꢃ0
kHz
Hz
V
—
—
fMCLK=ꢃMHzꢄ FLMS[ꢅ:0]=000B
fMCLK=ꢃMHzꢄ FLMS[ꢅ:0]=010B
ꢃ
—
—
5ꢅ1
A/D Conveꢁteꢁ
Oꢀtpꢀt Data Rate
10
130ꢅ
VREFN
+ 0.ꢆ
—
—
VOREG
VREFS=1ꢄ VRBUFP=0ꢄ VRBUFN=0
Exteꢁnal Refeꢁence Inpꢀt
Voltage
VREFP
- 0.ꢆ
—
—
0
—
—
V
V
VREF
VGS[1:0]=00Bꢄ VREF=VREFP−VREFN
0.ꢆ0
1.75
PGA
Common Mode Voltage
Range
VOREG
- 0.95
VCM_PGA
—
—
—
0.ꢃ
—
—
V
V
Diffeꢁential Inpꢀt Voltage
Range
-VREF
/Gain
+VREF
/Gain
ΔDI
Gain=PGS × AGS
Rev. 1.10
ꢅꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Temperature Sensor
Ta=-ꢃ0°C~ꢆ5°Cꢄ VREF=1.ꢅ5Vꢄ
VGS[1:0]=00B (Gain=1)ꢄ VRBUFP=0ꢄ
VRBUFN=0
Tempeꢁatꢀꢁe Sensoꢁ
Temperature Coefficient
TCTS
—
—
175
—
μV/°C
Note:ꢀ1.ꢀLoadꢀregulationꢀisꢀmeasuredꢀatꢀaꢀconstantꢀjunctionꢀtemperature,ꢀusingꢀpulseꢀtestingꢀwithꢀaꢀlowꢀONꢀtimeꢀ
andꢀisꢀguaranteedꢀupꢀtoꢀtheꢀmaximumꢀpowerꢀdissipation.ꢀPowerꢀdissipationꢀisꢀdeterminedꢀbyꢀtheꢀinput/
outputꢀdifferentialꢀvoltageꢀandꢀtheꢀoutputꢀcurrent.ꢀGuaranteedꢀmaximumꢀpowerꢀdissipationꢀwillꢀnotꢀbeꢀ
availableꢀoverꢀtheꢀfullꢀinput/outputꢀrange.ꢀTheꢀmaximumꢀallowableꢀpowerꢀdissipationꢀatꢀanyꢀambientꢀ
temperatureꢀisꢀPD=(TJ(MAX)-Ta)/θJA.
2.ꢀDropoutꢀvoltageꢀisꢀdefinedꢀasꢀtheꢀinputꢀvoltageꢀminusꢀtheꢀoutputꢀvoltageꢀthatꢀproducesꢀaꢀ2%ꢀchangeꢀinꢀtheꢀ
outputꢀvoltageꢀfromꢀtheꢀvalueꢀatꢀappointedꢀVIN.
12-bit D/A Converter Electrical Characteristics
Ta=ꢅ5°C
Test Conditions
Symbol
Parameter
Min.
Typ. Max. Unit
VDD
—
Conditions
VDACO
VREF
Oꢀtpꢀt Voltage Range
Refeꢁence Voltage
—
—
VSS
—
—
VREF
VDD
V
V
—
1.05
Additional Cꢀꢁꢁent foꢁ D/A
Conveꢁteꢁ Enable
IDAC
—
VREF=5V
—
—
ꢃ50
μA
DNL
INL
Diffeꢁential Non-lineaꢁitꢂ
Integꢁal Non-lineaꢁitꢂ
—
—
2.4V ≤ VDD ≤ 5.5V
2.4V ≤ VDD ≤ 5.5V
—
—
—
—
±ꢃ
±ꢆ
LSB
LSB
Operational Amplifier Electrical Characteristics (Body Fat Circuit)
Ta=ꢅ5°C
Test Conditions
Symbol
Parameter
Min.
Typ. Max. Unit
VDD
Conditions
VDD
ICC
Sꢀpplꢂ Voltage
Supply Current Per Signal Amplifier
—
—
ꢅ.ꢃ
—
5.5
V
5V Io=0A
150
360
500
μA
OP0, OP1, OP2
SR
Slew Rate at Unitꢂ Gain
Gain Bandwidth Pꢁodꢀct
3V RL=100kΩ, CL=100pF
3V RL=100kΩ, CL=100pF
7.5
—
—
—
—
ꢅ
V/μs
GBW
MHz
Rev. 1.10
ꢅ3
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Power-on Reset Characteristics
Ta=ꢅ5°C
Test Conditions
Symbol
Parameter
Min.
Typ. Max. Unit
VDD
Conditions
VPOR
VDD Staꢁt Voltage to Ensꢀꢁe Poweꢁ-on Reset
VDD Rising Rate to Ensꢀꢁe Poweꢁ-on Reset
—
—
—
—
—
100
—
mV
RRPOR
—
—
—
—
0.035
V/ms
Minimꢀm Time foꢁ VDD Staꢂs at VPOR to
Ensꢀꢁe Poweꢁ-on Reset
tPOR
1
—
—
ms
VDD
tPOR
RRPOR
VPOR
Time
System Architecture
Aꢀkeyꢀfactorꢀinꢀtheꢀhigh-performanceꢀfeaturesꢀofꢀtheꢀrangeꢀofꢀmicrocontrollersꢀisꢀattributedꢀtoꢀtheirꢀ
internalꢀsystemꢀarchitecture.ꢀThisꢀseriesꢀofꢀdevicesꢀtakeꢀadvantageꢀofꢀtheꢀusualꢀfeaturesꢀfoundꢀwithinꢀ
RISCꢀmicrocontrollersꢀprovidingꢀincreasedꢀspeedꢀofꢀoperationꢀandꢀenhancedꢀperformance.ꢀTheꢀ
pipeliningꢀschemeꢀisꢀimplementedꢀinꢀsuchꢀaꢀwayꢀthatꢀinstructionꢀfetchingꢀandꢀinstructionꢀexecutionꢀ
areꢀoverlapped,ꢀhenceꢀinstructionsꢀareꢀeffectivelyꢀexecutedꢀinꢀoneꢀorꢀtwoꢀcyclesꢀforꢀmostꢀofꢀtheꢀ
standardꢀorꢀextendedꢀinstructionsꢀrespectively.ꢀTheꢀexceptionsꢀtoꢀthisꢀareꢀbranchꢀorꢀcallꢀinstructionsꢀ
whichꢀneedꢀoneꢀmoreꢀcycle.ꢀAnꢀ8-bitꢀwideꢀALUꢀisꢀusedꢀinꢀpracticallyꢀallꢀinstructionꢀsetꢀoperations,ꢀ
whichꢀcarriesꢀoutꢀarithmeticꢀoperations,ꢀlogicꢀoperations,ꢀrotation,ꢀincrement,ꢀdecrement,ꢀbranchꢀ
decisions,ꢀetc.ꢀTheꢀinternalꢀdataꢀpathꢀisꢀsimplifiedꢀbyꢀmovingꢀdataꢀthroughꢀtheꢀAccumulatorꢀandꢀ
theꢀALU.ꢀCertainꢀinternalꢀregistersꢀareꢀimplementedꢀinꢀtheꢀDataꢀMemoryꢀandꢀcanꢀbeꢀdirectlyꢀ
orꢀindirectlyꢀaddressed.ꢀTheꢀsimpleꢀaddressingꢀmethodsꢀofꢀtheseꢀregistersꢀalongꢀwithꢀadditionalꢀ
architecturalꢀfeaturesꢀensureꢀthatꢀaꢀminimumꢀofꢀexternalꢀcomponentsꢀisꢀrequiredꢀtoꢀprovideꢀaꢀ
functionalꢀI/OꢀorꢀA/Dꢀcontrolꢀsystemꢀwithꢀmaximumꢀreliabilityꢀandꢀflexibility.ꢀThisꢀmakesꢀtheꢀ
devicesꢀsuitableꢀforꢀlow-cost,ꢀhigh-volumeꢀproductionꢀforꢀcontrollerꢀapplications.
Clocking and Pipelining
Theꢀmainꢀsystemꢀclock,ꢀderivedꢀfromꢀeitherꢀaꢀHXT,ꢀLXT,ꢀHIRCꢀorꢀLIRCꢀoscillatorꢀisꢀsubdividedꢀ
intoꢀfourꢀinternallyꢀgeneratedꢀnon-overlappingꢀclocks,ꢀT1~T4.ꢀTheꢀProgramꢀCounterꢀisꢀincrementedꢀ
atꢀtheꢀbeginningꢀofꢀtheꢀT1ꢀclockꢀduringꢀwhichꢀtimeꢀaꢀnewꢀinstructionꢀisꢀfetched.ꢀTheꢀremainingꢀ
T2~T4ꢀclocksꢀcarryꢀoutꢀtheꢀdecodingꢀandꢀexecutionꢀfunctions.ꢀInꢀthisꢀway,ꢀoneꢀT1~T4ꢀclockꢀ
cycleꢀformsꢀoneꢀinstructionꢀcycle.ꢀAlthoughꢀtheꢀfetchingꢀandꢀexecutionꢀofꢀinstructionsꢀtakesꢀplaceꢀ
inꢀconsecutiveꢀinstructionꢀcycles,ꢀtheꢀpipeliningꢀstructureꢀofꢀtheꢀmicrocontrollerꢀensuresꢀthatꢀ
instructionsꢀareꢀeffectivelyꢀexecutedꢀinꢀoneꢀinstructionꢀcycle.ꢀTheꢀexceptionꢀtoꢀthisꢀareꢀinstructionsꢀ
whereꢀtheꢀcontentsꢀofꢀtheꢀProgramꢀCounterꢀareꢀchanged,ꢀsuchꢀasꢀsubroutineꢀcallsꢀorꢀjumps,ꢀinꢀwhichꢀ
caseꢀtheꢀinstructionꢀwillꢀtakeꢀoneꢀmoreꢀinstructionꢀcycleꢀtoꢀexecute.
Rev. 1.10
ꢅꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
fSYS
(Sꢂstem Clock)
Phase Clock T1
Phase Clock Tꢅ
Phase Clock T3
Phase Clock Tꢃ
Pꢁogꢁam Coꢀnteꢁ
Pipelining
PC
PC+1
PC+ꢅ
Fetch Inst. (PC)
Execꢀte Inst. (PC-1)
Fetch Inst. (PC+1)
Execꢀte Inst. (PC)
Fetch Inst. (PC+ꢅ)
Execꢀte Inst. (PC+1)
System Clocking and Pipelining
Forꢀinstructionsꢀinvolvingꢀbranches,ꢀsuchꢀasꢀjumpꢀorꢀcallꢀinstructions,ꢀtwoꢀmachineꢀcyclesꢀareꢀ
requiredꢀtoꢀcompleteꢀinstructionꢀexecution.ꢀAnꢀextraꢀcycleꢀisꢀrequiredꢀasꢀtheꢀprogramꢀtakesꢀoneꢀ
cycleꢀtoꢀfirstꢀobtainꢀtheꢀactualꢀjumpꢀorꢀcallꢀaddressꢀandꢀthenꢀanotherꢀcycleꢀtoꢀactuallyꢀexecuteꢀtheꢀ
branch.ꢀTheꢀrequirementꢀforꢀthisꢀextraꢀcycleꢀshouldꢀbeꢀtakenꢀintoꢀaccountꢀbyꢀprogrammersꢀinꢀtimingꢀ
sensitiveꢀapplications.
Fetch Inst. 1
Execꢀte Inst. 1
Fetch Inst. ꢅ
1
ꢅ
3
ꢃ
5
MOV Aꢄ[1ꢅH]
CALL DELAY
CPL [1ꢅH]
:
:
Execꢀte Inst. ꢅ
Fetch Inst. 3
Flꢀsh Pipeline
Fetch Inst. 6
Execꢀte Inst. 6
Fetch Inst. 7
6 DELAY: NOP
Instruction Fetching
Program Counter
Duringꢀprogramꢀexecution,ꢀtheꢀProgramꢀCounterꢀisꢀusedꢀtoꢀkeepꢀtrackꢀofꢀtheꢀaddressꢀofꢀtheꢀnextꢀ
instructionꢀtoꢀbeꢀexecuted.ꢀItꢀisꢀautomaticallyꢀincrementedꢀbyꢀoneꢀeachꢀtimeꢀanꢀinstructionꢀisꢀex-
ecutedꢀexceptꢀforꢀinstructions,ꢀsuchꢀasꢀ“JMP”ꢀorꢀ“CALL”ꢀthatꢀdemandsꢀaꢀjumpꢀtoꢀaꢀnon-consecutiveꢀ
ProgramꢀMemoryꢀaddress.ꢀOnlyꢀtheꢀlowerꢀ8ꢀbits,ꢀknownꢀasꢀtheꢀProgramꢀCounterꢀLowꢀRegister,ꢀareꢀ
directlyꢀaddressableꢀbyꢀtheꢀapplicationꢀprogram.ꢀ
Whenꢀexecutingꢀinstructionsꢀrequiringꢀjumpsꢀtoꢀnon-consecutiveꢀaddressesꢀsuchꢀasꢀaꢀjumpꢀ
instruction,ꢀaꢀsubroutineꢀcall,ꢀinterruptꢀorꢀreset,ꢀetc.,ꢀtheꢀmicrocontrollerꢀmanagesꢀprogramꢀcontrolꢀ
byꢀloadingꢀtheꢀrequiredꢀaddressꢀintoꢀtheꢀProgramꢀCounter.ꢀForꢀconditionalꢀskipꢀinstructions,ꢀonceꢀ
theꢀconditionꢀhasꢀbeenꢀmet,ꢀtheꢀnextꢀinstruction,ꢀwhichꢀhasꢀalreadyꢀbeenꢀfetchedꢀduringꢀtheꢀpresentꢀ
instructionꢀexecution,ꢀisꢀdiscardedꢀandꢀaꢀdummyꢀcycleꢀtakesꢀitsꢀplaceꢀwhileꢀtheꢀcorrectꢀinstructionꢀisꢀ
obtained.
Program Counter
Device
Program Counter High Byte
PCL Register
PCL7~PCL0
PCL7~PCL0
BH66Fꢅ650
BH66Fꢅ660
PC1ꢅ~PCꢆ
PBP0ꢄ PC1ꢅ~PCꢆ
Program Counter
Rev. 1.10
ꢅ5
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
TheꢀlowerꢀbyteꢀofꢀtheꢀProgramꢀCounter,ꢀknownꢀasꢀtheꢀProgramꢀCounterꢀLowꢀregisterꢀorꢀPCL,ꢀisꢀ
availableꢀforꢀprogramꢀcontrolꢀandꢀisꢀaꢀreadableꢀandꢀwriteableꢀregister.ꢀByꢀtransferringꢀdataꢀdirectlyꢀ
intoꢀthisꢀregister,ꢀaꢀshortꢀprogramꢀjumpꢀcanꢀbeꢀexecutedꢀdirectly.ꢀHowever,ꢀasꢀonlyꢀthisꢀlowꢀbyteꢀ
isꢀavailableꢀforꢀmanipulation,ꢀtheꢀjumpsꢀareꢀlimitedꢀtoꢀtheꢀpresentꢀpageꢀofꢀmemory,ꢀthatꢀisꢀ256ꢀ
locations.ꢀWhenꢀsuchꢀprogramꢀjumpsꢀareꢀexecutedꢀitꢀshouldꢀalsoꢀbeꢀnotedꢀthatꢀaꢀdummyꢀcycleꢀ
willꢀbeꢀinserted.ꢀManipulatingꢀtheꢀPCLꢀregisterꢀmayꢀcauseꢀprogramꢀbranching,ꢀsoꢀanꢀextraꢀcycleꢀisꢀ
neededꢀtoꢀpre-fetch.
Stack
ThisꢀisꢀaꢀspecialꢀpartꢀofꢀtheꢀmemoryꢀwhichꢀisꢀusedꢀtoꢀsaveꢀtheꢀcontentsꢀofꢀtheꢀProgramꢀCounterꢀonly.ꢀ
Theꢀstackꢀisꢀorganizedꢀintoꢀ8ꢀlevelsꢀandꢀisꢀneitherꢀpartꢀofꢀtheꢀdataꢀnorꢀpartꢀofꢀtheꢀprogramꢀspace,ꢀ
andꢀisꢀneitherꢀreadableꢀnorꢀwriteable.ꢀTheꢀactivatedꢀlevelꢀisꢀindexedꢀbyꢀtheꢀStackꢀPointer,ꢀandꢀisꢀ
neitherꢀreadableꢀnorꢀwriteable.ꢀAtꢀaꢀsubroutineꢀcallꢀorꢀinterruptꢀacknowledgeꢀsignal,ꢀtheꢀcontentsꢀofꢀ
theꢀProgramꢀCounterꢀareꢀpushedꢀontoꢀtheꢀstack.ꢀAtꢀtheꢀendꢀofꢀaꢀsubroutineꢀorꢀanꢀinterruptꢀroutine,ꢀ
signaledꢀbyꢀaꢀreturnꢀinstruction,ꢀRETꢀorꢀRETI,ꢀtheꢀProgramꢀCounterꢀisꢀrestoredꢀtoꢀitsꢀpreviousꢀvalueꢀ
fromꢀtheꢀstack.ꢀAfterꢀaꢀdeviceꢀreset,ꢀtheꢀStackꢀPointerꢀwillꢀpointꢀtoꢀtheꢀtopꢀofꢀtheꢀstack.
Pꢁogꢁam Coꢀnteꢁ
Top of Stack
Stack Level 1
Stack Level ꢅ
Stack Level 3
Stack
Pointeꢁ
Pꢁogꢁam Memoꢁꢂ
:
:
:
Bottom of Stack
Stack Level ꢆ
Ifꢀtheꢀstackꢀisꢀfullꢀandꢀanꢀenabledꢀinterruptꢀtakesꢀplace,ꢀtheꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀrecordedꢀ
butꢀtheꢀacknowledgeꢀsignalꢀwillꢀbeꢀinhibited.ꢀWhenꢀtheꢀStackꢀPointerꢀisꢀdecremented,ꢀbyꢀRETꢀorꢀ
RETI,ꢀtheꢀinterruptꢀwillꢀbeꢀserviced.ꢀThisꢀfeatureꢀpreventsꢀstackꢀoverflowꢀallowingꢀtheꢀprogrammerꢀ
toꢀuseꢀtheꢀstructureꢀmoreꢀeasily.ꢀHowever,ꢀwhenꢀtheꢀstackꢀisꢀfull,ꢀaꢀCALLꢀsubroutineꢀinstructionꢀcanꢀ
stillꢀbeꢀexecutedꢀwhichꢀwillꢀresultꢀinꢀaꢀstackꢀoverflow.ꢀPrecautionsꢀshouldꢀbeꢀtakenꢀtoꢀavoidꢀsuchꢀ
casesꢀwhichꢀmightꢀcauseꢀunpredictableꢀprogramꢀbranching.ꢀIfꢀtheꢀstackꢀisꢀoverflow,ꢀtheꢀfirstꢀProgramꢀ
Counterꢀsaveꢀinꢀtheꢀstackꢀwillꢀbeꢀlost.
Arithmetic and Logic Unit – ALU
Theꢀarithmetic-logicꢀunitꢀorꢀALUꢀisꢀaꢀcriticalꢀareaꢀofꢀtheꢀmicrocontrollerꢀthatꢀcarriesꢀoutꢀarithmeticꢀ
andꢀlogicꢀoperationsꢀofꢀtheꢀinstructionꢀset.ꢀConnectedꢀtoꢀtheꢀmainꢀmicrocontrollerꢀdataꢀbus,ꢀtheꢀALUꢀ
receivesꢀrelatedꢀinstructionꢀcodesꢀandꢀperformsꢀtheꢀrequiredꢀarithmeticꢀorꢀlogicalꢀoperationsꢀafterꢀ
whichꢀtheꢀresultꢀwillꢀbeꢀplacedꢀinꢀtheꢀspecifiedꢀregister.ꢀAsꢀtheseꢀALUꢀcalculationꢀorꢀoperationsꢀmayꢀ
resultꢀinꢀcarry,ꢀborrowꢀorꢀotherꢀstatusꢀchanges,ꢀtheꢀstatusꢀregisterꢀwillꢀbeꢀcorrespondinglyꢀupdatedꢀtoꢀ
reflectꢀtheseꢀchanges.ꢀTheꢀALUꢀsupportsꢀtheꢀfollowingꢀfunctions:
•ꢀ Arithmeticꢀoperations:ꢀ
ADD,ꢀADDM,ꢀADC,ꢀADCM,ꢀSUB,ꢀSUBM,ꢀSBC,ꢀSBCM,ꢀDAAꢀ
LADD,ꢀLADDM,ꢀLADC,ꢀLADCM,ꢀLSUB,ꢀLSUBM,ꢀLSBC,ꢀLSBCM,ꢀLDAAꢀ
•ꢀ Logicꢀoperations:ꢀ
AND,ꢀOR,ꢀXOR,ꢀANDM,ꢀORM,ꢀXORM,ꢀCPL,ꢀCPLAꢀ
LAND,ꢀLANDM,ꢀLOR,ꢀLORM,ꢀLXOR,ꢀLXORM,ꢀLCPL,ꢀLCPLAꢀ
Rev. 1.10
ꢅ6
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
•ꢀ Rotation:ꢀ
RRA,ꢀRR,ꢀRRCA,ꢀRRC,ꢀRLA,ꢀRL,ꢀRLCA,ꢀRLC,ꢀꢀ
LRRA,ꢀLRR,ꢀLRRCA,ꢀLRRC,ꢀLRLA,ꢀLRL,ꢀLRLCA,ꢀLRLC
•ꢀ IncrementꢀandꢀDecrement:ꢀ
INCA,ꢀINC,ꢀDECA,ꢀDEC,ꢀLINCA,ꢀLINC,ꢀLDECA,ꢀLDEC
•ꢀ Branchꢀdecision:ꢀ
JMP,ꢀSZ,ꢀSZA,ꢀSNZ,ꢀSIZ,ꢀSDZ,ꢀSIZA,ꢀSDZA,ꢀCALL,ꢀRET,ꢀRETI,ꢀꢀ
LSNZ,ꢀLSZ,ꢀLSZA,ꢀLSIZ,ꢀLSIZA,ꢀLSDZ,ꢀLSDZA
Flash Program Memory
TheꢀProgramꢀMemoryꢀisꢀtheꢀlocationꢀwhereꢀtheꢀuserꢀcodeꢀorꢀprogramꢀisꢀstored.ꢀForꢀtheꢀBH66F2650/
BH66F2660ꢀdevicesꢀtheꢀProgramꢀMemoryꢀisꢀFlashꢀtype,ꢀwhichꢀmeansꢀitꢀcanꢀbeꢀprogrammedꢀandꢀ
re-programmedꢀaꢀlargeꢀnumberꢀofꢀtimes,ꢀallowingꢀtheꢀuserꢀtheꢀconvenienceꢀofꢀcodeꢀmodificationꢀ
onꢀtheꢀsameꢀdevice.ꢀByꢀusingꢀtheꢀappropriateꢀprogrammingꢀtools,ꢀtheꢀFlashꢀdevicesꢀofferꢀusersꢀtheꢀ
flexibilityꢀtoꢀconvenientlyꢀdebugꢀandꢀdevelopꢀtheirꢀapplicationsꢀwhileꢀalsoꢀofferingꢀaꢀmeansꢀofꢀfieldꢀ
programmingꢀandꢀupdating.
Structure
TheꢀProgramꢀMemoryꢀhasꢀaꢀcapacityꢀofꢀ8K×16ꢀ~ꢀ16K×16ꢀbits.ꢀTheꢀProgramꢀMemoryꢀisꢀaddressedꢀ
byꢀtheꢀProgramꢀCounterꢀandꢀalsoꢀcontainsꢀdata,ꢀtableꢀinformationꢀandꢀinterruptꢀentries.ꢀTableꢀdata,ꢀ
whichꢀcanꢀbeꢀsetupꢀinꢀanyꢀlocationꢀwithinꢀtheꢀProgramꢀMemory,ꢀisꢀaddressedꢀbyꢀaꢀseparateꢀtableꢀ
pointerꢀregister.
Device
Capacity
ꢆK×16
Banks
—
BH66Fꢅ650
BH66Fꢅ660
16K×16
0~1
BH66F2650 BH66F2660
0000H
Reset
Reset
000ꢃH
0030H
Inteꢁꢁꢀpt
Vectoꢁ
Inteꢁꢁꢀpt
Vectoꢁ
16 bits
16 bits
Bank 1
1FFFH
ꢅ000H
3FFFH
Program Memory Structure
Special Vectors
WithinꢀtheꢀProgramꢀMemory,ꢀcertainꢀlocationsꢀareꢀreservedꢀforꢀtheꢀresetꢀandꢀinterrupts.ꢀTheꢀlocationꢀ
000Hꢀisꢀreservedꢀforꢀuseꢀbyꢀtheꢀdeviceꢀresetꢀforꢀprogramꢀinitialisation.ꢀAfterꢀaꢀdeviceꢀresetꢀisꢀ
initiated,ꢀtheꢀprogramꢀwillꢀjumpꢀtoꢀthisꢀlocationꢀandꢀbeginꢀexecution.
Rev. 1.10
ꢅ7
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Look-up Table
AnyꢀlocationꢀwithinꢀtheꢀProgramꢀMemoryꢀcanꢀbeꢀdefinedꢀasꢀaꢀlook-upꢀtableꢀwhereꢀprogrammersꢀcanꢀ
storeꢀfixedꢀdata.ꢀToꢀuseꢀtheꢀlook-upꢀtable,ꢀtheꢀtableꢀpointerꢀmustꢀfirstꢀbeꢀsetupꢀbyꢀplacingꢀtheꢀaddressꢀ
ofꢀtheꢀlookꢀupꢀdataꢀtoꢀbeꢀretrievedꢀinꢀtheꢀtableꢀpointerꢀregister,ꢀTBLPꢀandꢀTBHP.ꢀTheseꢀregistersꢀ
defineꢀtheꢀtotalꢀaddressꢀofꢀtheꢀlook-upꢀtable.
Afterꢀsettingꢀupꢀtheꢀtableꢀpointer,ꢀtheꢀtableꢀdataꢀcanꢀbeꢀretrievedꢀfromꢀtheꢀProgramꢀMemoryꢀusingꢀtheꢀ
correspondingꢀtableꢀreadꢀinstructionꢀsuchꢀasꢀ“TABRDꢀ[m]”ꢀorꢀ“TABRDLꢀ[m]”ꢀrespectivelyꢀwhenꢀ
theꢀmemoryꢀ[m]ꢀisꢀlocatedꢀinꢀsectorꢀ0.ꢀIfꢀtheꢀmemoryꢀ[m]ꢀisꢀlocatedꢀinꢀotherꢀsectors,ꢀtheꢀdataꢀcanꢀbeꢀ
retrievedꢀfromꢀtheꢀprogramꢀmemoryꢀusingꢀtheꢀcorrespondingꢀextendedꢀtableꢀreadꢀinstructionꢀsuchꢀasꢀ
“LTABRDꢀ[m]”ꢀorꢀ“LTABRDLꢀ[m]”ꢀrespectively.ꢀWhenꢀtheꢀinstructionꢀisꢀexecuted,ꢀtheꢀlowerꢀorderꢀ
tableꢀbyteꢀfromꢀtheꢀProgramꢀMemoryꢀwillꢀbeꢀtransferredꢀtoꢀtheꢀuserꢀdefinedꢀDataꢀMemoryꢀregisterꢀ[m]ꢀ
asꢀspecifiedꢀinꢀtheꢀinstruction.ꢀTheꢀhigherꢀorderꢀtableꢀdataꢀbyteꢀfromꢀtheꢀProgramꢀMemoryꢀwillꢀbeꢀ
transferredꢀtoꢀtheꢀTBLHꢀspecialꢀregister.ꢀ
Theꢀaccompanyingꢀdiagramꢀillustratesꢀtheꢀaddressingꢀdataꢀflowꢀofꢀtheꢀlook-upꢀtable.
Pꢁogꢁam Memoꢁꢂ
Last Page oꢁ
TBHP Registeꢁ
Data
16 bits
TBLP Registeꢁ
Useꢁ Selected
Registeꢁ TBLH
Registeꢁ
High Bꢂte
Low Bꢂte
Table Program Example
Theꢀfollowingꢀexampleꢀshowsꢀhowꢀtheꢀtableꢀpointerꢀandꢀtableꢀdataꢀisꢀdefinedꢀandꢀretrievedꢀfromꢀtheꢀ
microcontroller.ꢀThisꢀexampleꢀusesꢀrawꢀtableꢀdataꢀlocatedꢀinꢀtheꢀProgramꢀMemoryꢀwhichꢀisꢀstoredꢀ
thereꢀusingꢀtheꢀORGꢀstatement.ꢀTheꢀvalueꢀatꢀthisꢀORGꢀstatementꢀisꢀ“1F00H”ꢀwhichꢀrefersꢀtoꢀtheꢀ
startꢀaddressꢀofꢀtheꢀlastꢀpageꢀwithinꢀtheꢀ8KꢀProgramꢀMemoryꢀofꢀtheꢀBH66F2650ꢀdevice.ꢀTheꢀtableꢀ
pointerꢀlowꢀbyteꢀregisterꢀisꢀsetupꢀhereꢀtoꢀhaveꢀanꢀinitialꢀvalueꢀofꢀ“06H”.ꢀThisꢀwillꢀensureꢀthatꢀtheꢀ
firstꢀdataꢀreadꢀfromꢀtheꢀdataꢀtableꢀwillꢀbeꢀatꢀtheꢀProgramꢀMemoryꢀaddressꢀ“1F06H”ꢀorꢀ6ꢀlocationsꢀ
afterꢀtheꢀstartꢀofꢀtheꢀlastꢀpage.ꢀNoteꢀthatꢀtheꢀvalueꢀforꢀtheꢀtableꢀpointerꢀisꢀreferencedꢀtoꢀtheꢀaddressꢀ
specifiedꢀbyꢀTBLPꢀandꢀTBHPꢀifꢀtheꢀ“TABRDꢀ[m]”ꢀorꢀ“LTABRDꢀ[m]”ꢀinstructionꢀisꢀbeingꢀused.ꢀTheꢀ
highꢀbyteꢀofꢀtheꢀtableꢀdataꢀwhichꢀinꢀthisꢀcaseꢀisꢀequalꢀtoꢀ“0”ꢀwillꢀbeꢀtransferredꢀtoꢀtheꢀTBLHꢀregisterꢀ
automaticallyꢀwhenꢀtheꢀ“TABRDꢀ[m]”ꢀorꢀ“LTABRDꢀ[m]”ꢀinstructionꢀisꢀexecuted.ꢀ
BecauseꢀtheꢀTBLHꢀregisterꢀisꢀaꢀread/writeꢀregisterꢀandꢀcanꢀbeꢀrestored,ꢀcareꢀshouldꢀbeꢀtakenꢀ
toꢀensureꢀitsꢀprotectionꢀifꢀbothꢀtheꢀmainꢀroutineꢀandꢀInterruptꢀServiceꢀRoutineꢀuseꢀtableꢀreadꢀ
instructions.ꢀIfꢀusingꢀtheꢀtableꢀreadꢀinstructions,ꢀtheꢀInterruptꢀServiceꢀRoutinesꢀmayꢀchangeꢀtheꢀ
valueꢀofꢀtheꢀTBLHꢀandꢀsubsequentlyꢀcauseꢀerrorsꢀifꢀusedꢀagainꢀbyꢀtheꢀmainꢀroutine.ꢀAsꢀaꢀruleꢀitꢀisꢀ
recommendedꢀthatꢀsimultaneousꢀuseꢀofꢀtheꢀtableꢀreadꢀinstructionsꢀshouldꢀbeꢀavoided.ꢀHowever,ꢀinꢀ
situationsꢀwhereꢀsimultaneousꢀuseꢀcannotꢀbeꢀavoided,ꢀtheꢀinterruptsꢀshouldꢀbeꢀdisabledꢀpriorꢀtoꢀtheꢀ
executionꢀofꢀanyꢀmainꢀroutineꢀtable-readꢀinstructions.ꢀNoteꢀthatꢀallꢀtableꢀrelatedꢀinstructionsꢀrequireꢀ
twoꢀinstructionꢀcyclesꢀtoꢀcompleteꢀtheirꢀoperation.
Rev. 1.10
ꢅꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Table Read Program Example
tempreg1 db ? ; temporary register #1
tempreg2 db ? ; temporary register #2
:
:
mov a,06h
mov tblp,a
mov a,1Fh
mov tbhp,a
:
; initialise low table pointer - note that this address is referenced
; to the last page or the page that tbhp pointed
; initialise high table pointer
:
tabrd tempreg1 ; transfers value in table referenced by table pointer data at program
; memory address “1F06H” transferred to tempreg1 and TBLH
dec tblp
; reduce value of table pointer by one
tabrd tempreg2 ; transfers value in table referenced by table pointer
; data at program memory address “1F05H” transferred to
; tempreg2 and TBLH in this example the data “1AH” is
; transferred to tempreg1 and data “0FH” to register tempreg2
:
:
org 1F00h
; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
In Circuit Programming – ICP
TheꢀprovisionꢀofꢀFlashꢀtypeꢀProgramꢀMemoryꢀprovidesꢀtheꢀuserꢀwithꢀaꢀmeansꢀofꢀconvenientꢀandꢀeasyꢀ
upgradesꢀandꢀmodificationsꢀtoꢀtheirꢀprogramsꢀonꢀtheꢀsameꢀdevice.ꢀAsꢀanꢀadditionalꢀconvenience,ꢀ
aꢀmeansꢀofꢀprogrammingꢀtheꢀmicrocontrollerꢀin-circuitꢀhasꢀprovidedꢀusingꢀaꢀ4-pinꢀinterface.ꢀThisꢀ
providesꢀmanufacturersꢀwithꢀtheꢀpossibilityꢀofꢀmanufacturingꢀtheirꢀcircuitꢀboardsꢀcompleteꢀwithꢀaꢀ
programmedꢀorꢀun-programmedꢀmicrocontroller,ꢀandꢀthenꢀprogrammingꢀorꢀupgradingꢀtheꢀprogramꢀ
atꢀaꢀlaterꢀstage.ꢀThisꢀenablesꢀproductꢀmanufacturersꢀtoꢀeasilyꢀkeepꢀtheirꢀmanufacturedꢀproductsꢀ
suppliedꢀwithꢀtheꢀlatestꢀprogramꢀreleasesꢀwithoutꢀremovalꢀandꢀre-insertionꢀofꢀtheꢀdevice.
TheꢀFlashꢀMCUꢀtoꢀWriterꢀProgrammingꢀPinꢀcorrespondenceꢀtableꢀisꢀasꢀfollows:
Writer Pins
ICPDA
ICPCK
VDD
MCU Programming Pins
Pin Description
Pꢁogꢁamming Seꢁial Data/Addꢁess
Pꢁogꢁamming Clock
Poweꢁ Sꢀpplꢂ
PA0
PAꢅ
VDD
VSS
VSS
Gꢁoꢀnd
TheꢀProgramꢀMemoryꢀandꢀEEPROMꢀdataꢀMemoryꢀcanꢀbothꢀbeꢀprogrammedꢀseriallyꢀin-circuitꢀusingꢀ
thisꢀ4-wireꢀinterface.ꢀDataꢀisꢀdownloadedꢀandꢀuploadedꢀseriallyꢀonꢀaꢀsingleꢀpinꢀwithꢀanꢀadditionalꢀ
lineꢀforꢀtheꢀclock.ꢀTwoꢀadditionalꢀlinesꢀareꢀrequiredꢀforꢀtheꢀpowerꢀsupply.ꢀTheꢀtechnicalꢀdetailsꢀ
regardingꢀtheꢀin-circuitꢀprogrammingꢀofꢀtheꢀdeviceꢀareꢀbeyondꢀtheꢀscopeꢀofꢀthisꢀdocumentꢀandꢀwillꢀ
beꢀsuppliedꢀinꢀsupplementaryꢀliterature.
Duringꢀtheꢀprogrammingꢀprocess,ꢀtakingꢀcontrolꢀofꢀtheꢀICPDAꢀandꢀICPCKꢀpinsꢀforꢀdataꢀandꢀclockꢀ
programmingꢀpurposes.ꢀTheꢀuserꢀmustꢀthereꢀtakeꢀcareꢀtoꢀensureꢀthatꢀnoꢀotherꢀoutputsꢀareꢀconnectedꢀ
toꢀtheseꢀtwoꢀpins.
Rev. 1.10
ꢅ9
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Wꢁiteꢁ Connectoꢁ
Signals
MCU Pꢁogꢁamming
Pins
Wꢁiteꢁ_VDD
VDD
ICPDA
ICPCK
PA0
PAꢅ
Wꢁiteꢁ_VSS
VSS
*
*
To otheꢁ Ciꢁcꢀit
Note:ꢀ*ꢀmayꢀbeꢀresistorꢀorꢀcapacitor.ꢀTheꢀresistanceꢀofꢀ*ꢀmustꢀbeꢀgreaterꢀthanꢀ1kΩꢀorꢀtheꢀcapacitanceꢀ
ofꢀ*ꢀmustꢀbeꢀlessꢀthanꢀ1nF.
On-Chip Debug Support – OCDS
ThereꢀisꢀanꢀEVꢀchipꢀnamedꢀBH66V2650/BH66V2660ꢀwhichꢀisꢀusedꢀtoꢀemulateꢀtheꢀrealꢀMCUꢀdeviceꢀ
namedꢀBH66F2650/BH66F2660.ꢀThisꢀEVꢀchipꢀdeviceꢀalsoꢀprovidesꢀanꢀ“On-ChipꢀDebug”ꢀfunctionꢀ
toꢀdebugꢀtheꢀdeviceꢀduringꢀtheꢀdevelopmentꢀprocess.ꢀTheꢀEVꢀchipꢀandꢀtheꢀactualꢀMCUꢀdeviceꢀareꢀ
almostꢀfunctionallyꢀcompatibleꢀexceptꢀforꢀtheꢀ“On-ChipꢀDebug”ꢀfunction.ꢀUsersꢀcanꢀuseꢀtheꢀEVꢀchipꢀ
deviceꢀtoꢀemulateꢀtheꢀrealꢀchipꢀdeviceꢀbehaviorꢀbyꢀconnectingꢀtheꢀOCDSDAꢀandꢀOCDSCKꢀpinsꢀ
toꢀtheꢀHT-IDEꢀdevelopmentꢀtools.ꢀTheꢀOCDSDAꢀpinꢀisꢀtheꢀOCDSꢀData/Addressꢀinput/outputꢀpinꢀ
whileꢀtheꢀOCDSCKꢀpinꢀisꢀtheꢀOCDSꢀclockꢀinputꢀpin.ꢀWhenꢀusersꢀuseꢀtheꢀEVꢀchipꢀforꢀdebugging,ꢀ
otherꢀfunctionsꢀwhichꢀareꢀsharedꢀwithꢀtheꢀOCDSDAꢀandꢀOCDSCKꢀpinsꢀinꢀtheꢀactualꢀMCUꢀdeviceꢀ
willꢀhaveꢀnoꢀeffectꢀinꢀtheꢀEVꢀchip.ꢀHowever,ꢀtheꢀtwoꢀOCDSꢀpinsꢀwhichꢀareꢀpin-sharedꢀwithꢀtheꢀICPꢀ
programmingꢀpinsꢀareꢀstillꢀusedꢀasꢀtheꢀFlashꢀMemoryꢀprogrammingꢀpinsꢀforꢀICP.ꢀForꢀaꢀmoreꢀdetailedꢀ
OCDSꢀdescription,ꢀreferꢀtoꢀtheꢀcorrespondingꢀdocument.
e-Link Pins
OCDSDA
OCDSCK
VDD
EV Chip Pins
OCDSDA
OCDSCK
VDD
Pin Description
On-chip Debꢀg Sꢀppoꢁt Data/Addꢁess inpꢀt/oꢀtpꢀt
On-chip Debꢀg Sꢀppoꢁt Clock inpꢀt
Poweꢁ Sꢀpplꢂ
VSS
VSS
Gꢁoꢀnd
In Application Programming – IAP
TheꢀdevicesꢀofferꢀIAPꢀfunctionꢀtoꢀupdateꢀdataꢀorꢀapplicationꢀprogramꢀtoꢀFashꢀROM.ꢀUsersꢀcanꢀdefineꢀ
anyꢀROMꢀlocationꢀforꢀIAP,ꢀbutꢀthereꢀareꢀsomeꢀfeaturesꢀwhichꢀuserꢀmustꢀnoticeꢀinꢀusingꢀIAPꢀfunction.
IAP Features BH66F2650 Configurations BH66F2660 Configurations
Eꢁase Page
3ꢅ woꢁds / page
3ꢅ woꢁds / time
1 woꢁd / time
6ꢃ woꢁds / page
6ꢃ woꢁds / time
1 woꢁd / time
Wꢁiting Woꢁd
Reading Woꢁd
Rev. 1.10
30
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
In Application Programming Control Registers
TheꢀAddressꢀregisters,ꢀFARLꢀandꢀFARH,ꢀtheꢀDataꢀregisters,ꢀFD0L/FD0H,ꢀFD1L/FD1H,ꢀFD2L/FD2Hꢀ
andꢀFD3L/FD3H,ꢀandꢀtheꢀControlꢀregisters,ꢀFC0,ꢀFC1ꢀandꢀFC2,ꢀareꢀtheꢀcorrespondingꢀFlashꢀaccessꢀ
registersꢀlocatedꢀinꢀDataꢀMemoryꢀsectorꢀ1ꢀforꢀIAP.ꢀIfꢀusingꢀtheꢀindirectꢀaddressingꢀmethodꢀtoꢀaccessꢀ
theꢀFC0,ꢀFC1ꢀandꢀFC2ꢀregisters,ꢀallꢀreadꢀandꢀwriteꢀoperationsꢀtoꢀtheꢀregistersꢀmustꢀbeꢀperformedꢀ
usingꢀtheꢀIndirectꢀAddressingꢀRegister,ꢀIAR1ꢀorꢀIAR2,ꢀandꢀtheꢀMemoryꢀPointerꢀpair,ꢀMP1L/MP1Hꢀ
orꢀMP2L/MP2H.ꢀBecauseꢀtheꢀFC0,ꢀFC1ꢀandꢀFC2ꢀcontrolꢀregistersꢀareꢀlocatedꢀatꢀtheꢀaddressꢀofꢀ
43H~45HꢀinꢀDataꢀMemoryꢀsectorꢀ1,ꢀtheꢀdesiredꢀvalueꢀrangedꢀfromꢀ43Hꢀtoꢀ45Hꢀmustꢀfirstꢀbeꢀwrittenꢀ
intoꢀtheꢀMP1LꢀorꢀMP2LꢀMemoryꢀPointerꢀlowꢀbyteꢀandꢀtheꢀvalueꢀ“01H”ꢀmustꢀalsoꢀbeꢀwrittenꢀintoꢀtheꢀ
MP1HꢀorꢀMP2HꢀMemoryꢀPointerꢀhighꢀbyte.
Bit
Register Name
7
6
5
4
3
2
1
FRDEN
D1
0
FRD
D0
FC0
CFWEN FMODꢅ FMOD1 FMOD0 FWPEN
FWT
Dꢅ
FC1
D7
—
D6
—
D5
—
Dꢃ
—
D3
—
FCꢅ
—
—
CLWB
A0
FARL
A7
A6
A5
Aꢃ
A3
Aꢅ
A1
FARH (BH66Fꢅ650)
—
—
—
A1ꢅ
A1ꢅ
Dꢃ
A11
A11
D3
A10
A10
Dꢅ
A9
Aꢆ
FARH (BH66Fꢅ660)
FD0L
—
—
A13
D5
A9
Aꢆ
D7
D15
D7
D15
D7
D15
D7
D15
D6
D1ꢃ
D6
D1ꢃ
D6
D1ꢃ
D6
D1ꢃ
D1
D0
FD0H
D13
D5
D1ꢅ
Dꢃ
D11
D3
D10
Dꢅ
D9
Dꢆ
FD1L
D1
D0
FD1H
D13
D5
D1ꢅ
Dꢃ
D11
D3
D10
Dꢅ
D9
Dꢆ
FDꢅL
D1
D0
FDꢅH
D13
D5
D1ꢅ
Dꢃ
D11
D3
D10
Dꢅ
D9
Dꢆ
FD3L
D1
D0
FD3H
D13
D1ꢅ
D11
D10
D9
Dꢆ
IAP Registers List
• FC0 Register
Bit
Name
R/W
7
CFWEN
R/W
0
6
FMODꢅ
R/W
0
5
4
3
2
1
0
FMOD1
R/W
0
FMOD0
R/W
0
FWPEN
R/W
0
FWT
R/W
0
FRDEN
FRD
R/W
0
R/W
0
POR
Bitꢀ7
CFWEN:ꢀFlashꢀMemoryꢀWriteꢀEnableꢀControl
0:ꢀFlashꢀmemoryꢀwriteꢀfunctionꢀisꢀdisabled
1:ꢀFlashꢀmemoryꢀwriteꢀfunctionꢀhasꢀbeenꢀsuccessfullyꢀenabled
Whenꢀthisꢀbitꢀisꢀclearedꢀtoꢀ“0”ꢀbyꢀapplicationꢀprogram,ꢀtheꢀFlashꢀmemoryꢀwriteꢀ
functionꢀisꢀdisabled.ꢀNoteꢀthatꢀwritingꢀaꢀ“1”ꢀintoꢀthisꢀbitꢀresultsꢀinꢀnoꢀaction.ꢀThisꢀbitꢀisꢀ
usedꢀtoꢀindicateꢀthatꢀtheꢀFlashꢀmemoryꢀwriteꢀfunctionꢀstatus.ꢀWhenꢀthisꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀ
byꢀhardware,ꢀitꢀmeansꢀthatꢀtheꢀFlashꢀmemoryꢀwriteꢀfunctionꢀisꢀenabledꢀsuccessfully.ꢀ
Otherwise,ꢀtheꢀFlashꢀmemoryꢀwriteꢀfunctionꢀisꢀdisabledꢀasꢀtheꢀbitꢀcontentꢀisꢀ“0”.
Bitꢀ6~4
FMOD2~FMOD0:ꢀModeꢀSelection
000:ꢀWriteꢀprogramꢀmemory
001:ꢀPageꢀeraseꢀprogramꢀmemory
010:ꢀReserved
011:ꢀReadꢀprogramꢀmemory
100:ꢀReserved
101:ꢀReserved
110:ꢀFWENꢀmodeꢀ–ꢀFlashꢀmemoryꢀWriteꢀfunctionꢀEnableꢀmode
111:ꢀReserved
Rev. 1.10
31
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ3
Bitꢀ2
FWPEN:ꢀFlashꢀMemoryꢀWriteꢀProcedureꢀEnableꢀControl
0:ꢀDisable
1:ꢀEnable
Whenꢀthisꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀandꢀtheꢀFMODꢀfieldꢀisꢀsetꢀtoꢀ“110”,ꢀtheꢀIAPꢀcontrollerꢀwillꢀ
executeꢀtheꢀ“Flashꢀmemoryꢀwriteꢀfunctionꢀenable”ꢀprocedure.ꢀOnceꢀtheꢀFlashꢀmemoryꢀ
writeꢀfunctionꢀisꢀsuccessfullyꢀenabled,ꢀitꢀisꢀnotꢀnecessaryꢀtoꢀsetꢀtheꢀFWPENꢀbitꢀanyꢀ
more.
FWT:ꢀFlashꢀMemoryꢀWriteꢀInitiateꢀControl
0:ꢀDoꢀnotꢀinitiateꢀFlashꢀmemoryꢀwriteꢀorꢀFlashꢀmemoryꢀwriteꢀprocessꢀisꢀcompleted
1:ꢀInitiateꢀFlashꢀmemoryꢀwriteꢀprocess
ThisꢀbitꢀisꢀsetꢀbyꢀsoftwareꢀandꢀclearedꢀbyꢀhardwareꢀwhenꢀtheꢀFlashꢀmemoryꢀwriteꢀ
processꢀisꢀcompleted.
Bitꢀ1
Bitꢀ0
FRDEN:ꢀFlashꢀMemoryꢀReadꢀEnableꢀControl
0:ꢀFlashꢀmemoryꢀreadꢀdisable
1:ꢀFlashꢀmemoryꢀreadꢀenable
FRD:ꢀFlashꢀMemoryꢀReadꢀInitiateꢀControl
0:ꢀDoꢀnotꢀinitiateꢀFlashꢀmemoryꢀreadꢀorꢀFlashꢀmemoryꢀreadꢀprocessꢀisꢀcompleted
1:ꢀInitiateꢀFlashꢀmemoryꢀreadꢀprocess
ThisꢀbitꢀisꢀsetꢀbyꢀsoftwareꢀandꢀclearedꢀbyꢀhardwareꢀwhenꢀtheꢀFlashꢀmemoryꢀreadꢀ
processꢀisꢀcompleted.
• FC1 Register
Bit
Name
R/W
7
6
D6
R/W
0
5
D5
R/W
0
4
Dꢃ
R/W
0
3
D3
R/W
0
2
Dꢅ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
D7
R/W
0
POR
Bitꢀ7~0
D7~D0:ꢀWholeꢀChipꢀResetꢀPattern
Whenꢀuserꢀwritesꢀaꢀspecificꢀvalueꢀofꢀ“55H”ꢀtoꢀthisꢀregister,ꢀitꢀwillꢀgenerateꢀaꢀresetꢀ
signalꢀtoꢀresetꢀwholeꢀchip.
• FC2 Register
Bit
7
6
5
4
3
2
1
0
CLWB
R/W
0
Name
R/W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~1ꢀ
Bitꢀ0
Unimplemented,ꢀreadꢀasꢀ"0".
CLWB:ꢀFlashꢀMemoryꢀWriteꢀBufferꢀClearꢀControl
0:ꢀDoꢀnotꢀinitiateꢀWriteꢀBufferꢀClearꢀprocessꢀorꢀWriteꢀBufferꢀClearꢀprocessꢀisꢀ
completed
1:ꢀInitiateꢀWriteꢀBufferꢀClearꢀprocess
ThisꢀbitꢀisꢀsetꢀbyꢀsoftwareꢀandꢀclearedꢀbyꢀhardwareꢀwhenꢀtheꢀWriteꢀBufferꢀClearꢀ
processꢀisꢀcompleted.
• FARL Register
Bit
Name
R/W
7
A7
R/W
0
6
A6
R/W
0
5
A5
R/W
0
4
Aꢃ
R/W
0
3
A3
R/W
0
2
Aꢅ
R/W
0
1
A1
R/W
0
0
A0
R/W
0
POR
Bitꢀ7~0ꢀ
FlashꢀMemoryꢀAddressꢀbitꢀ7~bitꢀ0
Rev. 1.10
3ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
• FARH Register – BH66F2650
Bit
Name
R/W
7
6
5
4
3
A11
R/W
0
2
1
A9
R/W
0
0
Aꢆ
R/W
0
—
—
—
—
—
—
—
—
—
A1ꢅ
R/W
0
A10
R/W
0
POR
Bitꢀ7~5ꢀ
Bitꢀ4~0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
FlashꢀMemoryꢀAddressꢀbitꢀ12~bitꢀ8
• FARH Register – BH66F2660
Bit
Name
R/W
7
6
5
4
3
A11
R/W
0
2
1
A9
R/W
0
0
Aꢆ
R/W
0
—
—
—
—
—
—
A13
R/W
0
A1ꢅ
R/W
0
A10
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
FlashꢀMemoryꢀAddressꢀbitꢀ13~bitꢀ8
• FD0L Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
Dꢃ
R/W
0
3
D3
R/W
0
2
Dꢅ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀfirstꢀFlashꢀMemoryꢀDataꢀbitꢀ7~bitꢀ0
• FD0H Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
Dꢆ
R/W
0
D15
R/W
0
D1ꢃ
R/W
0
D13
R/W
0
D1ꢅ
R/W
0
D11
R/W
0
D10
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀfirstꢀFlashꢀMemoryꢀDataꢀbitꢀ15~bitꢀ8
• FD1L Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
Dꢃ
R/W
0
3
D3
R/W
0
2
Dꢅ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀsecondꢀFlashꢀMemoryꢀDataꢀbitꢀ7~bitꢀ0
• FD1H Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
Dꢆ
R/W
0
D15
R/W
0
D1ꢃ
R/W
0
D13
R/W
0
D1ꢅ
R/W
0
D11
R/W
0
D10
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀsecondꢀFlashꢀMemoryꢀDataꢀbitꢀ15~bitꢀ8
Rev. 1.10
33
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
• FD2L Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
Dꢃ
R/W
0
3
D3
R/W
0
2
Dꢅ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀthirdꢀFlashꢀMemoryꢀDataꢀbitꢀ7~bitꢀ0
• FD2H Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
Dꢆ
R/W
0
D15
R/W
0
D1ꢃ
R/W
0
D13
R/W
0
D1ꢅ
R/W
0
D11
R/W
0
D10
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀthirdꢀFlashꢀMemoryꢀDataꢀbitꢀ15~bitꢀ8
• FD3L Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
Dꢃ
R/W
0
3
D3
R/W
0
2
Dꢅ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀfourthꢀFlashꢀMemoryꢀDataꢀbitꢀ7~bitꢀ0
• FD3H Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
Dꢆ
R/W
0
D15
R/W
0
D1ꢃ
R/W
0
D13
R/W
0
D1ꢅ
R/W
0
D11
R/W
0
D10
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀfourthꢀFlashꢀMemoryꢀDataꢀbitꢀ15~bitꢀ8
Flash Memory Write Function Enable Procedure
InꢀorderꢀtoꢀallowꢀusersꢀtoꢀchangeꢀtheꢀFlashꢀmemoryꢀdataꢀthroughꢀtheꢀIAPꢀcontrolꢀregisters,ꢀusersꢀ
mustꢀfirstꢀenableꢀtheꢀFlashꢀmemoryꢀwriteꢀoperationꢀbyꢀtheꢀfollowingꢀprocedure:
1.ꢀWriteꢀ“110”ꢀintoꢀtheꢀFMOD2~FMOD0ꢀbitsꢀtoꢀselectꢀtheꢀFWENꢀmode.
2.ꢀSetꢀtheꢀFWPENꢀbitꢀtoꢀ“1”.ꢀTheꢀstepꢀ1ꢀandꢀstepꢀ2ꢀcanꢀbeꢀexecutedꢀsimultaneously.
3.ꢀTheꢀpatternꢀdataꢀwithꢀaꢀsequenceꢀofꢀ00H,ꢀ04H,ꢀ0DH,ꢀ09H,ꢀC3Hꢀandꢀ40Hꢀmustꢀbeꢀwrittenꢀintoꢀtheꢀ
FD1L,ꢀFD1H,ꢀFD2L,ꢀFD2H,ꢀFD3LꢀandꢀFD3Hꢀregistersꢀrespectively.
4.ꢀAꢀcounterꢀwithꢀaꢀtime-outꢀperiodꢀofꢀ300μsꢀwillꢀbeꢀactivatedꢀtoꢀallowꢀusersꢀwritingꢀtheꢀcorrectꢀ
patternꢀdataꢀintoꢀtheꢀFD1L/FD1H~FD3L/FD3Hꢀregisterꢀpairs.ꢀTheꢀcounterꢀclockꢀisꢀderivedꢀfromꢀ
LIRCꢀoscillator.
5.ꢀIfꢀtheꢀcounterꢀoverflowsꢀorꢀtheꢀpatternꢀdataꢀisꢀincorrect,ꢀtheꢀFlashꢀmemoryꢀwriteꢀoperationꢀwillꢀ
notꢀbeꢀenabledꢀandꢀusersꢀmustꢀagainꢀrepeatꢀtheꢀaboveꢀprocedure.ꢀThenꢀtheꢀFWPENꢀbitꢀwillꢀ
automaticallyꢀbeꢀclearedꢀtoꢀ“0”ꢀbyꢀhardware.
6.ꢀIfꢀtheꢀpatternꢀdataꢀisꢀcorrectꢀbeforeꢀtheꢀcounterꢀoverflows,ꢀtheꢀFlashꢀmemoryꢀwriteꢀoperationꢀwillꢀ
beꢀenabledꢀandꢀtheꢀFWPENꢀbitꢀwillꢀautomaticallyꢀbeꢀclearedꢀtoꢀ“0”ꢀbyꢀhardware.ꢀTheꢀCFWENꢀ
bitꢀwillꢀalsoꢀbeꢀsetꢀtoꢀ“1”ꢀbyꢀhardwareꢀtoꢀindicateꢀthatꢀtheꢀFlashꢀmemoryꢀwriteꢀoperationꢀisꢀ
successfullyꢀenabled.
7.ꢀOnceꢀtheꢀFlashꢀmemoryꢀwriteꢀoperationꢀisꢀenabled,ꢀtheꢀuserꢀcanꢀchangeꢀtheꢀFlashꢀROMꢀdataꢀ
throughꢀtheꢀFlashꢀcontrolꢀregister.
8.ꢀToꢀdisableꢀtheꢀFlashꢀmemoryꢀwriteꢀoperation,ꢀtheꢀuserꢀcanꢀclearꢀtheꢀCFWENꢀbitꢀtoꢀ“0”.
Rev. 1.10
3ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
No
Is coꢀnteꢁ
oveꢁflow ?
Flash Memoꢁꢂ
Wꢁite Fꢀnction
Yes
Enable Pꢁocedꢀꢁe
FWPEN=0
Set FMOD [ꢅ:0] =110 & FWPEN=1
Select FWEN mode & Staꢁt Flash wꢁite
Haꢁdwaꢁe activate a coꢀnteꢁ
No
Is patteꢁn
coꢁꢁect ?
Wꢁtie the following patteꢁn to Flash Data ꢁegisteꢁs
FD1L= 00h ꢄ FD1H = 0ꢃh
Yes
FDꢅL= 0Dh ꢄ FDꢅH = 09h
FD3L= C3h ꢄ FD3H = ꢃ0h
CFWEN=0
Failed
CFWEN = 1
Sꢀccess
END
Flash Memory Write Function Enable Procedure
Rev. 1.10
35
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Flash Memory Read/Write Procedure
AfterꢀtheꢀFlashꢀmemoryꢀwriteꢀfunctionꢀisꢀsuccessfullyꢀenabledꢀthroughꢀtheꢀprecedingꢀIAPꢀprocedure,ꢀ
usersꢀmustꢀfirstꢀeraseꢀtheꢀcorrespondingꢀFlashꢀmemoryꢀpageꢀandꢀthenꢀinitiateꢀtheꢀFlashꢀmemoryꢀwriteꢀ
operation.ꢀForꢀtheꢀBH66F2650/BH66F2660ꢀdevicesꢀtheꢀnumberꢀofꢀtheꢀpageꢀeraseꢀoperationꢀareꢀ32ꢀ
wordsꢀandꢀ64ꢀwordsꢀperꢀpageꢀrespectively,ꢀtheꢀavailableꢀpageꢀeraseꢀaddressꢀisꢀspecifiedꢀbyꢀFARHꢀ
registerꢀandꢀtheꢀcontentꢀofꢀFARLꢀ[7:5]ꢀandꢀFARL[7:6]bitꢀfieldꢀrespectively.
Erase Page
FARH
FARL [7:5]
000
FARL [4:0]
x xxxx
x xxxx
x xxxx
x xxxx
x xxxx
x xxxx
x xxxx
x xxxx
x xxxx
x xxxx
0
1
ꢅ
3
ꢃ
5
6
7
ꢆ
9
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0001
0000 0001
001
010
011
100
101
110
111
000
001
:
:
:
:
:
:
:
:
1ꢅ6
1ꢅ7
1ꢅꢆ
1ꢅ9
0000 1111
0000 1111
0001 0000
0001 0000
110
111
000
001
x xxxx
x xxxx
x xxxx
x xxxx
:
:
:
:
:
:
:
:
ꢅ5ꢃ
ꢅ55
0001 1111
0001 1111
110
111
x xxxx
x xxxx
“x”: don’t caꢁe
BH66F2650 Erase Page Number and Selection
Erase Page
FARH
FARL [7:6]
FARL [5:0]
xx xxxx
xx xxxx
xx xxxx
xx xxxx
xx xxxx
xx xxxx
0
1
ꢅ
3
ꢃ
5
0000 0000
0000 0000
0000 0000
0000 0000
0000 0001
0000 0001
00
01
10
11
00
01
:
:
:
:
:
:
:
:
1ꢅ6
1ꢅ7
1ꢅꢆ
1ꢅ9
0001 1111
0001 1111
0010 0000
0010 0000
10
11
00
01
xx xxxx
xx xxxx
xx xxxx
xx xxxx
:
:
:
:
:
:
:
:
ꢅ5ꢃ
ꢅ55
0011 1111
0011 1111
10
11
xx xxxx
xx xxxx
“x”: don’t caꢁe
BH66F2660 Erase Page Number and Selection
Rev. 1.10
36
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Read
Flash Memoꢁꢂ
Set FMOD [ꢅ:0]=011
& FRDEN=1
Set Flash Addꢁess ꢁegisteꢁs
FARH=xxhꢄ FARL=xxh
Set FRD=1
No
FRD=0 ?
Yes
Read data valꢀe:
FD0L=xxhꢄ FD0H=xxh
No
Read Finish ?
Yes
Cleaꢁ FRDEN bit
END
Read Flash Memory Procedure
Rev. 1.10
37
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Wꢁite
Flash Memoꢁꢂ
Flash Memoꢁꢂ Wꢁite Fꢀnction Enable
Pꢁocedꢀꢁe
Set Page Eꢁase addꢁess: FARH/FARL
Set FMOD [ꢅ:0]=001 & FWT=1
Select “Page Eꢁase mode”
& Initiate wꢁite opeꢁation
No
FWT=0 ?
Yes
Set FMOD [ꢅ:0]=000
Select “Wꢁite Flash Mode”
Set Wꢁite staꢁting addꢁess: FARH/FARL
Wꢁite data to data ꢁegisteꢁ: FD0L/FD0H
Yes
No
Page data
Wꢁite finish
Set FWT=1
Yes
No
FWT=0 ?
No
Wꢁite Finish ?
Yes
Cleaꢁ CFWEN=0
END
Write Flash Memory Procedure
Note:ꢀWhenꢀtheꢀFWTꢀorꢀFRDꢀbitꢀisꢀsetꢀtoꢀ“1”,ꢀtheꢀMCUꢀisꢀstopped.
Rev. 1.10
3ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
RAM Data Memory
TheꢀDataꢀMemoryꢀisꢀaꢀvolatileꢀareaꢀofꢀ8-bitꢀwideꢀRAMꢀinternalꢀmemoryꢀandꢀisꢀtheꢀlocationꢀwhereꢀ
temporaryꢀinformationꢀisꢀstored.
Categorisedꢀintoꢀthreeꢀtypes,ꢀtheꢀfirstꢀofꢀtheseꢀisꢀanꢀareaꢀofꢀRAMꢀwhereꢀspecialꢀfunctionꢀregistersꢀareꢀ
located.ꢀTheseꢀregistersꢀhaveꢀfixedꢀlocationsꢀandꢀareꢀnecessaryꢀforꢀcorrectꢀoperationꢀofꢀtheꢀdevices.ꢀ
Manyꢀofꢀtheseꢀregistersꢀcanꢀbeꢀreadꢀfromꢀandꢀwrittenꢀtoꢀdirectlyꢀunderꢀprogramꢀcontrol,ꢀhowever,ꢀ
someꢀremainꢀprotectedꢀfromꢀuserꢀmanipulation.ꢀTheꢀsecondꢀareaꢀofꢀDataꢀMemoryꢀisꢀreservedꢀforꢀ
generalꢀpurposeꢀuse.ꢀAllꢀlocationsꢀwithinꢀthisꢀareaꢀareꢀreadꢀandꢀwriteꢀaccessibleꢀunderꢀprogramꢀ
control.ꢀTheꢀthirdꢀareaꢀisꢀusedꢀforꢀtheꢀSineꢀPatternꢀfunction.ꢀTheꢀaddressesꢀofꢀtheꢀSineꢀPatternꢀ
MemoryꢀareaꢀoverlopꢀthoseꢀinꢀtheꢀSpecialꢀPurposeꢀDataꢀMemoryꢀarea.
Structure
TheꢀDataꢀMemoryꢀisꢀsubdividedꢀintoꢀseveralꢀsectors,ꢀallꢀofꢀwhichꢀareꢀimplementedꢀinꢀ8-bitꢀwideꢀ
RAM.ꢀEachꢀofꢀtheꢀDataꢀMemoryꢀSectorꢀisꢀcategorizedꢀintoꢀthreeꢀtypes,ꢀtheꢀspecialꢀPurposeꢀDataꢀ
MemoryꢀandꢀtheꢀGeneralꢀPurposeꢀDataꢀMemory.ꢀWhileꢀtheꢀ00H~3FHꢀofꢀSectorꢀ3ꢀisꢀSineꢀPatternꢀ
Memory.
TheꢀstartꢀaddressꢀofꢀtheꢀDataꢀMemoryꢀforꢀtheꢀdevicesꢀisꢀtheꢀaddressꢀ00H.ꢀSwitchingꢀbetweenꢀtheꢀ
differentꢀDataꢀMemoryꢀsectorsꢀisꢀachievedꢀbyꢀsettingꢀtheꢀMemoryꢀPointersꢀtoꢀtheꢀcorrectꢀvalue.
Special Purpose
Data Memory
Sine Pattern
Data Memory
General Purpose
Data Memory
Device
Available Sectors
Capacity
Address
Capacity
Address
0: 00H~7FH
1: ꢅ0H~5AH
0: ꢆ0H~FFH
1: ꢆ0H~FFH
BH66Fꢅ650
6ꢃ×ꢆ
6ꢃ×ꢆ
3: 00H~3FH
ꢅ56×ꢆ
0: ꢆ0H~FFH
1: ꢆ0H~FFH
:
6: ꢆ0H~FFH
7: ꢆ0H~FFH
0: 00H~7FH
1: ꢅ0H~5AH
BH66Fꢅ660
3: 00H~3FH
10ꢅꢃ×ꢆ
00H
00H
ꢅ0H
5AH
Special Pꢀꢁpose
Data Memoꢁꢂ
Sectoꢁ 3
Sine Patteꢁn Memoꢁꢂ
3FH
Sectoꢁ 1
7FH
ꢆ0H
Geneꢁal Pꢀꢁpose
Data Memoꢁꢂ
Sectoꢁ 0
Sectoꢁ N
FFH
Note:ꢀForꢀtheꢀBH66F2650,ꢀN=1;ꢀForꢀtheꢀBH66F2660,ꢀN=7
Data Memory Structure
Rev. 1.10
39
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Data Memory Addressing
Forꢀtheseꢀdevicesꢀthatꢀsupportꢀtheꢀextendedꢀinstructions,ꢀthereꢀisꢀnoꢀBankꢀPointerꢀforꢀDataꢀMemoryꢀ
addressing.ꢀForꢀDataꢀMemoryꢀtheꢀdesiredꢀSectorꢀisꢀpointedꢀbyꢀtheꢀMP1HꢀorꢀMP2Hꢀregisterꢀandꢀtheꢀ
certainꢀDataꢀMemoryꢀaddressꢀinꢀtheꢀselectedꢀsectorꢀisꢀspecifiedꢀbyꢀtheꢀMP1LꢀorꢀMP2Lꢀregisterꢀwhenꢀ
usingꢀindirectꢀaddressingꢀaccess.
DirectꢀAddressingꢀcanꢀbeꢀusedꢀinꢀallꢀsectorsꢀusingꢀtheꢀcorrespondingꢀinstructionꢀwhichꢀcanꢀaddressꢀ
allꢀavailableꢀdataꢀmemoryꢀspace.ꢀForꢀtheꢀaccessedꢀdataꢀmemoryꢀwhichꢀisꢀlocatedꢀinꢀanyꢀdataꢀ
memoryꢀsectorsꢀexceptꢀsectorꢀ0,ꢀtheꢀextendedꢀinstructionsꢀcanꢀbeꢀusedꢀtoꢀaccessꢀtheꢀdataꢀmemoryꢀ
insteadꢀofꢀusingꢀtheꢀindirectꢀaddressingꢀaccess.ꢀTheꢀmainꢀdifferenceꢀbetweenꢀstandardꢀinstructionsꢀ
andꢀextendedꢀinstructionsꢀisꢀthatꢀtheꢀdataꢀmemoryꢀaddressꢀ“m”ꢀinꢀtheꢀextendedꢀinstructionsꢀhasꢀ9ꢀorꢀ
11ꢀvalidꢀbitsꢀdependingꢀonꢀwhichꢀdeviceꢀisꢀselected,ꢀtheꢀhighꢀbyteꢀindicatesꢀaꢀsectorꢀandꢀtheꢀlowꢀbyteꢀ
indicatesꢀaꢀspecificꢀaddress.
General Purpose Data Memory
Allꢀmicrocontrollerꢀprogramsꢀrequireꢀanꢀareaꢀofꢀread/writeꢀmemoryꢀwhereꢀtemporaryꢀdataꢀcanꢀbeꢀ
storedꢀandꢀretrievedꢀforꢀuseꢀlater.ꢀItꢀisꢀthisꢀareaꢀofꢀRAMꢀmemoryꢀthatꢀisꢀknownꢀasꢀGeneralꢀPurposeꢀ
DataꢀMemory.ꢀThisꢀareaꢀofꢀDataꢀMemoryꢀisꢀfullyꢀaccessibleꢀbyꢀtheꢀuserꢀprogramingꢀforꢀbothꢀreadingꢀ
andꢀwritingꢀoperations.ꢀByꢀusingꢀtheꢀbitꢀoperationꢀinstructionsꢀindividualꢀbitsꢀcanꢀbeꢀsetꢀorꢀresetꢀ
underꢀprogramꢀcontrolꢀgivingꢀtheꢀuserꢀaꢀlargeꢀrangeꢀofꢀflexibilityꢀforꢀbitꢀmanipulationꢀinꢀtheꢀDataꢀ
Memory.
Special Purpose Data Memory
ThisꢀareaꢀofꢀDataꢀMemoryꢀisꢀwhereꢀregisters,ꢀnecessaryꢀforꢀtheꢀcorrectꢀoperationꢀofꢀtheꢀ
microcontroller,ꢀareꢀstored.ꢀMostꢀofꢀtheꢀregistersꢀareꢀbothꢀreadableꢀandꢀwriteableꢀbutꢀsomeꢀareꢀ
protectedꢀandꢀareꢀreadableꢀonly,ꢀtheꢀdetailsꢀofꢀwhichꢀareꢀlocatedꢀunderꢀtheꢀrelevantꢀSpecialꢀFunctionꢀ
Registerꢀsection.ꢀNoteꢀthatꢀforꢀlocationsꢀthatꢀareꢀunused,ꢀanyꢀreadꢀinstructionꢀtoꢀtheseꢀaddressesꢀwillꢀ
returnꢀtheꢀvalueꢀ“00H”.
Rev. 1.10
ꢃ0
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Sectoꢁ 0
Sectoꢁ 1
Sectoꢁ 0
Sectoꢁ 1
EEC
00H
01H
0ꢅH
03H
0ꢃH
05H
06H
07H
0ꢆH
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
1ꢅH
13H
1ꢃH
15H
16H
17H
1ꢆH
19H
1AH
1BH
1CH
1DH
1EH
1FH
ꢅ0H
ꢅ1H
ꢅꢅH
ꢅ3H
ꢅꢃH
ꢅ5H
ꢅ6H
ꢅ7H
ꢅꢆH
ꢅ9H
ꢅAH
ꢅBH
ꢅCH
ꢅDH
ꢅEH
ꢅFH
30H
31H
3ꢅH
33H
3ꢃH
35H
36H
37H
3ꢆH
39H
3AH
3BH
3CH
3DH
3EH
3FH
IAR0
MP0
IAR1
ꢃ0H
ꢃ1H
ꢃꢅH
ꢃ3H
ꢃꢃH
ꢃ5H
ꢃ6H
ꢃ7H
ꢃꢆH
ꢃ9H
ꢃAH
ꢃBH
ꢃCH
ꢃDH
ꢃEH
ꢃFH
50H
51H
5ꢅH
53H
5ꢃH
55H
56H
57H
5ꢆH
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
6ꢅH
63H
6ꢃH
65H
66H
67H
6ꢆH
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
7ꢅH
73H
7ꢃH
75H
76H
77H
7ꢆH
79H
7AH
7BH
7CH
7DH
7EH
7FH
EEA
EED
MP1L
MP1H
ACC
FC0
FC1
FCꢅ
PCL
FARL
FARH
FD0L
FD0H
FD1L
FD1H
FDꢅL
FDꢅH
FD3L
FD3H
IFS0
TBLP
TBLH
TBHP
STATUS
STMC0
STMC1
STMDL
STMDH
STMAL
STMAH
IARꢅ
MPꢅL
MPꢅH
RSTFC
SCC
HIRCC
HXTC
LXTC
PA
STMRP
PTM0C0
PTM0C1
PTM0DL
PTM0DH
PTM0AL
PTM0AH
PTM0RPL
PTM0RPH
IFS1
PAS0
PAS1
PBS0
PDS0
PCS0
PCS1
SLEDC0
SLEDC1
PAC
PAPU
PAWU
RSTC
LVRC
LVDC
MFI0
MDUWR0
MDUWR1
MDUWRꢅ
MDUWR3
MDUWRꢃ
MDUWR5
MDUWCTRL
MFI1
MFIꢅ
WDTC
INTEG
INTC0
INTC1
INTCꢅ
INTC3
PB
PBC
PBPU
PC
PTM1C0
PTM1C1
PTM1DL
PTM1DH
PTM1AL
PTM1AH
PTM1RPL
PTM1RPH
PTMꢅC0
PTMꢅC1
PTMꢅDL
PTMꢅDH
PTMꢅAL
PTMꢅAH
PTMꢅRPL
PTMꢅRPH
ADCS
ADCR0
ADCR1
PWRC
PGAC0
PGAC1
PGACS
ADRL
PCC
PCPU
PSCR
TB0C
TB1C
USR
UCR1
ADRM
ADRH
DSDAH
DSDAL
DSDACC
SGC
UCRꢅ
TXR_RXR
BRG
SIMC0
SIMC1
SIMD
SIMA/SIMCꢅ
SIMTOC
SGN
SGDNR
OPAC
SWC0
SWC1
SWCꢅ
DACO
FTRC
PD
SPIAC0
SPIAC1
SPIAD
PDC
PDPU
: Unꢀsedꢄ ꢁead as 00H
: Reseꢁvedꢄ cannot be changed
Special Purpose Data Memory Structure – BH66F2650
Rev. 1.10
ꢃ1
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Sectoꢁ 0
Sectoꢁ 1
Sectoꢁ 0
Sectoꢁ 1
EEC
00H
01H
0ꢅH
03H
0ꢃH
05H
06H
07H
0ꢆH
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
1ꢅH
13H
1ꢃH
15H
16H
17H
1ꢆH
19H
1AH
1BH
1CH
1DH
1EH
1FH
ꢅ0H
ꢅ1H
ꢅꢅH
ꢅ3H
ꢅꢃH
ꢅ5H
ꢅ6H
ꢅ7H
ꢅꢆH
ꢅ9H
ꢅAH
ꢅBH
ꢅCH
ꢅDH
ꢅEH
ꢅFH
30H
31H
3ꢅH
33H
3ꢃH
35H
36H
37H
3ꢆH
39H
3AH
3BH
3CH
3DH
3EH
3FH
IAR0
MP0
IAR1
ꢃ0H
ꢃ1H
ꢃꢅH
ꢃ3H
ꢃꢃH
ꢃ5H
ꢃ6H
ꢃ7H
ꢃꢆH
ꢃ9H
ꢃAH
ꢃBH
ꢃCH
ꢃDH
ꢃEH
ꢃFH
50H
51H
5ꢅH
53H
5ꢃH
55H
56H
57H
5ꢆH
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
6ꢅH
63H
6ꢃH
65H
66H
67H
6ꢆH
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
7ꢅH
73H
7ꢃH
75H
76H
77H
7ꢆH
79H
7AH
7BH
7CH
7DH
7EH
7FH
EEA
EED
MP1L
MP1H
ACC
FC0
FC1
FCꢅ
PCL
FARL
FARH
FD0L
FD0H
FD1L
FD1H
FDꢅL
FDꢅH
FD3L
FD3H
IFS0
TBLP
TBLH
TBHP
STATUS
PBP
STMC0
STMC1
STMDL
STMDH
STMAL
STMAH
IARꢅ
MPꢅL
MPꢅH
RSTFC
SCC
HIRCC
HXTC
LXTC
PA
STMRP
PTM0C0
PTM0C1
PTM0DL
PTM0DH
PTM0AL
PTM0AH
PTM0RPL
PTM0RPH
IFS1
PAS0
PAS1
PBS0
PDS0
PCS0
PCS1
SLEDC0
SLEDC1
PAC
PAPU
PAWU
RSTC
LVRC
LVDC
MFI0
MDUWR0
MDUWR1
MDUWRꢅ
MDUWR3
MDUWRꢃ
MDUWR5
MDUWCTRL
MFI1
MFIꢅ
WDTC
INTEG
INTC0
INTC1
INTCꢅ
INTC3
PB
PBC
PBPU
PC
PTM1C0
PTM1C1
PTM1DL
PTM1DH
PTM1AL
PTM1AH
PTM1RPL
PTM1RPH
PTMꢅC0
PTMꢅC1
PTMꢅDL
PTMꢅDH
PTMꢅAL
PTMꢅAH
PTMꢅRPL
PTMꢅRPH
ADCS
ADCR0
ADCR1
PWRC
PGAC0
PGAC1
PGACS
ADRL
PCC
PCPU
PSCR
TB0C
TB1C
USR
UCR1
ADRM
ADRH
DSDAH
DSDAL
DSDACC
SGC
UCRꢅ
TXR_RXR
BRG
SIMC0
SIMC1
SIMD
SIMA/SIMCꢅ
SIMTOC
SGN
SGDNR
OPAC
SWC0
SWC1
SWCꢅ
DACO
FTRC
PD
SPIAC0
SPIAC1
SPIAD
PDC
PDPU
: Unꢀsedꢄ ꢁead as 00H
: Reseꢁvedꢄ cannot be changed
Special Purpose Data Memory Structure – BH66F2660
Rev. 1.10
ꢃꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Special Function Register Description
MostꢀofꢀtheꢀSpecialꢀFunctionꢀRegisterꢀdetailsꢀwillꢀbeꢀdescribedꢀinꢀtheꢀrelevantꢀfunctionalꢀsections,ꢀ
howeverꢀseveralꢀregistersꢀrequireꢀaꢀseparateꢀdescriptionꢀinꢀthisꢀsection.
Indirect Addressing Registers – IAR0, IAR1, IAR2
TheꢀIndirectꢀAddressingꢀRegisters,ꢀIAR0,ꢀIAR1ꢀandꢀIAR2,ꢀalthoughꢀhavingꢀtheirꢀlocationsꢀinꢀnormalꢀ
RAMꢀregisterꢀspace,ꢀdoꢀnotꢀactuallyꢀphysicallyꢀexistꢀasꢀnormalꢀregisters.ꢀTheꢀmethodꢀofꢀindirectꢀ
addressingꢀforꢀRAMꢀdataꢀmanipulationꢀusesꢀtheseꢀIndirectꢀAddressingꢀRegistersꢀandꢀMemoryꢀ
Pointers,ꢀinꢀcontrastꢀtoꢀdirectꢀmemoryꢀaddressing,ꢀwhereꢀtheꢀactualꢀmemoryꢀaddressꢀisꢀspecified.ꢀ
ActionsꢀonꢀtheꢀIAR0,ꢀIAR1ꢀandꢀIAR2ꢀregistersꢀwillꢀresultꢀinꢀnoꢀactualꢀreadꢀorꢀwriteꢀoperationꢀtoꢀ
theseꢀregistersꢀbutꢀratherꢀtoꢀtheꢀmemoryꢀlocationꢀspecifiedꢀbyꢀtheirꢀcorrespondingꢀMemoryꢀPointers,ꢀ
MP0,ꢀMP1L/MP1HꢀorꢀMP2L/MP2H.ꢀActingꢀasꢀaꢀpair,ꢀIAR0ꢀandꢀMP0ꢀcanꢀtogetherꢀaccessꢀdataꢀonlyꢀ
fromꢀSectorꢀ0ꢀwhileꢀtheꢀIAR1ꢀregisterꢀtogetherꢀwithꢀtheꢀMP1L/MP1HꢀregisterꢀpairꢀandꢀIAR2ꢀregisterꢀ
togetherꢀwithꢀtheꢀMP2L/MP2HꢀregisterꢀpairꢀcanꢀaccessꢀdataꢀfromꢀanyꢀDataꢀMemoryꢀSector.ꢀAsꢀ
theꢀIndirectꢀAddressingꢀRegistersꢀareꢀnotꢀphysicallyꢀimplemented,ꢀreadingꢀtheꢀIndirectꢀAddressingꢀ
Registersꢀwillꢀreturnꢀaꢀresultꢀofꢀ“00H”ꢀandꢀwritingꢀtoꢀtheꢀregistersꢀwillꢀresultꢀinꢀnoꢀoperation.
Memory Pointers – MP0, MP1L, MP1H, MP2L, MP2H
FiveꢀMemoryꢀPointers,ꢀknownꢀasꢀMP0,ꢀMP1L,ꢀMP1H,ꢀMP2L,ꢀMP2H,ꢀareꢀprovided.ꢀTheseꢀMemoryꢀ
PointersꢀareꢀphysicallyꢀimplementedꢀinꢀtheꢀDataꢀMemoryꢀandꢀcanꢀbeꢀmanipulatedꢀinꢀtheꢀsameꢀwayꢀ
asꢀnormalꢀregistersꢀprovidingꢀaꢀconvenientꢀwayꢀwithꢀwhichꢀtoꢀaddressꢀandꢀtrackꢀdata.ꢀWhenꢀanyꢀ
operationꢀtoꢀtheꢀrelevantꢀIndirectꢀAddressingꢀRegistersꢀisꢀcarriedꢀout,ꢀtheꢀactualꢀaddressꢀthatꢀtheꢀ
microcontrollerꢀisꢀdirectedꢀtoꢀisꢀtheꢀaddressꢀspecifiedꢀbyꢀtheꢀrelatedꢀMemoryꢀPointer.ꢀMP0,ꢀtogetherꢀ
withꢀIndirectꢀAddressingꢀRegister,ꢀIAR0,ꢀareꢀusedꢀtoꢀaccessꢀdataꢀfromꢀSectorꢀ0,ꢀwhileꢀMP1L/MP1Hꢀ
togetherꢀwithꢀIAR1ꢀandꢀMP2L/MP2HꢀtogetherꢀwithꢀIAR2ꢀareꢀusedꢀtoꢀaccessꢀdataꢀfromꢀallꢀsectorsꢀ
accordingꢀtoꢀtheꢀcorrespondingꢀMP1HꢀorꢀMP2Hꢀregister.ꢀDirectꢀAddressingꢀcanꢀbeꢀusedꢀinꢀallꢀ
sectorsꢀusingꢀtheꢀcorrespondingꢀinstructionꢀwhichꢀcanꢀaddressꢀallꢀavailableꢀdataꢀmemoryꢀspace.
TheꢀfollowingꢀexampleꢀshowsꢀhowꢀtoꢀclearꢀaꢀsectionꢀofꢀfourꢀDataꢀMemoryꢀlocationsꢀalreadyꢀdefinedꢀ
asꢀlocationsꢀadres1ꢀtoꢀadres4.
Indirect Addressing Program Example 1
data .section ´data´
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block
db ?
code .section at 0 ´code´
org 00h
start:
mov a, 04h
; setup size of block
mov block, a
ꢀ
ꢀ
movꢀa,ꢀoffsetꢀadres1ꢀ ꢀ
ꢀ
ꢀ
;ꢀAccumulatorꢀloadedꢀwithꢀfirstꢀRAMꢀaddress
;ꢀsetupꢀmemoryꢀpointerꢀwithꢀfirstꢀRAMꢀaddress
movꢀmp0,ꢀaꢀꢀ ꢀꢀꢀꢀꢀ
ꢀ
loop:
ꢀ
clrꢀIAR0ꢀ
inc mp0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀclearꢀtheꢀdataꢀatꢀaddressꢀdefinedꢀbyꢀMP0
; increment memory pointer
sdz block
jmp loop
; check if last memory location has been cleared
continue:
Rev. 1.10
ꢃ3
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Indirect Addressing Program Example 2
data .section ´data´
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block
db ?
code .section at 0 ´code´
org 00h
start:
mov a, 04h
mov block, a
mov a, 01h
; setup size of block
; setup the memory sector
mov mp1h, a
ꢀ
movꢀa,ꢀoffsetꢀadres1ꢀ ꢀ ;ꢀAccumulatorꢀloadedꢀwithꢀfirstꢀRAMꢀaddress
ꢀ
movꢀmp1l,ꢀaꢀ
ꢀ
ꢀ
ꢀ
;ꢀsetupꢀmemoryꢀpointerꢀwithꢀfirstꢀRAMꢀaddress
loop:
ꢀ
ꢀ
clrꢀIAR1ꢀ
incꢀmp1lꢀ
sdz block
jmp loop
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀclearꢀtheꢀdataꢀatꢀaddressꢀdefinedꢀbyꢀMP1L
;ꢀincrementꢀmemoryꢀpointerꢀMP1L
; check if last memory location has been cleared
continue:
Theꢀimportantꢀpointꢀtoꢀnoteꢀhereꢀisꢀthatꢀinꢀtheꢀexampleꢀshownꢀabove,ꢀnoꢀreferenceꢀisꢀmadeꢀtoꢀspecificꢀ
DataꢀMemoryꢀaddresses.
Direct Addressing Program Example using extended instructions
data .section ´data´
temp db ?
code .section at 0 ´code´
org 00h
start:
lmov a, [m]
lsub a, [m+1]
snz c
; move [m] data to acc
; compare [m] and [m+1] data
; [m]>[m+1]?
jmp continue
lmov a, [m]
mov temp, a
lmov a, [m+1]
lmov [m], a
mov a, temp
lmov [m+1], a
; no
; yes, exchange [m] and [m+1] data
continue:
Note:ꢀhereꢀ“m”ꢀisꢀaꢀdataꢀmemoryꢀaddressꢀlocatedꢀinꢀanyꢀdataꢀmemoryꢀsectors.ꢀForꢀexample,ꢀ
m=1F0H,ꢀitꢀindicatesꢀaddressꢀ0F0HꢀinꢀSectorꢀ1.
Rev. 1.10
ꢃꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Program Memory Bank Pointer – PBP
ForꢀtheꢀBH66F2660ꢀdeviceꢀtheꢀProgramꢀMemoryꢀisꢀdividedꢀintoꢀseveralꢀbanks.ꢀSelectingꢀtheꢀ
requiredꢀProgramꢀMemoryꢀareaꢀisꢀachievedꢀusingꢀtheꢀProgramꢀMemoryꢀBankꢀPointer,ꢀPBP.ꢀTheꢀPBPꢀ
registerꢀshouldꢀbeꢀproperlyꢀconfiguredꢀbeforeꢀtheꢀdeviceꢀexecutesꢀtheꢀ“Branch”ꢀoperationꢀusingꢀtheꢀ
“JMP”ꢀorꢀ“CALL”ꢀinstruction.ꢀAfterꢀthatꢀaꢀjumpꢀtoꢀaꢀnon-consecutiveꢀProgramꢀMemoryꢀaddressꢀ
whichꢀisꢀlocatedꢀinꢀaꢀcertainꢀbankꢀselectedꢀbyꢀtheꢀprogramꢀmemoryꢀbankꢀpointerꢀbitsꢀwillꢀoccur.
PBP Register – BH66F2660
Bit
Name
R/W
7
6
5
4
3
2
1
0
PBP0
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~1ꢀ
Bitꢀ0
Unimplemented,ꢀreadꢀasꢀ“0”
PBP0:ꢀSelectꢀProgramꢀMemoryꢀBanks
0:ꢀBankꢀ0
1:ꢀBankꢀ1
Accumulator – ACC
TheꢀAccumulatorꢀisꢀcentralꢀtoꢀtheꢀoperationꢀofꢀanyꢀmicrocontrollerꢀandꢀisꢀcloselyꢀrelatedꢀwithꢀ
operationsꢀcarriedꢀoutꢀbyꢀtheꢀALU.ꢀTheꢀAccumulatorꢀisꢀtheꢀplaceꢀwhereꢀallꢀintermediateꢀresultsꢀ
fromꢀtheꢀALUꢀareꢀstored.ꢀWithoutꢀtheꢀAccumulatorꢀitꢀwouldꢀbeꢀnecessaryꢀtoꢀwriteꢀtheꢀresultꢀofꢀ
eachꢀcalculationꢀorꢀlogicalꢀoperationꢀsuchꢀasꢀaddition,ꢀsubtraction,ꢀshift,ꢀetc.,ꢀtoꢀtheꢀDataꢀMemoryꢀ
resultingꢀinꢀhigherꢀprogrammingꢀandꢀtimingꢀoverheads.ꢀDataꢀtransferꢀoperationsꢀusuallyꢀinvolveꢀ
theꢀtemporaryꢀstorageꢀfunctionꢀofꢀtheꢀAccumulator;ꢀforꢀexample,ꢀwhenꢀtransferringꢀdataꢀbetweenꢀ
oneꢀuser-definedꢀregisterꢀandꢀanother,ꢀitꢀisꢀnecessaryꢀtoꢀdoꢀthisꢀbyꢀpassingꢀtheꢀdataꢀthroughꢀtheꢀ
Accumulatorꢀasꢀnoꢀdirectꢀtransferꢀbetweenꢀtwoꢀregistersꢀisꢀpermitted.
Program Counter Low Register – PCL
Toꢀprovideꢀadditionalꢀprogramꢀcontrolꢀfunctions,ꢀtheꢀlowꢀbyteꢀofꢀtheꢀProgramꢀCounterꢀisꢀmadeꢀ
accessibleꢀtoꢀprogrammersꢀbyꢀlocatingꢀitꢀwithinꢀtheꢀSpecialꢀPurposeꢀareaꢀofꢀtheꢀDataꢀMemory.ꢀByꢀ
manipulatingꢀthisꢀregister,ꢀdirectꢀjumpsꢀtoꢀotherꢀprogramꢀlocationsꢀareꢀeasilyꢀimplemented.ꢀLoadingꢀ
aꢀvalueꢀdirectlyꢀintoꢀthisꢀPCLꢀregisterꢀwillꢀcauseꢀaꢀjumpꢀtoꢀtheꢀspecifiedꢀProgramꢀMemoryꢀlocation,ꢀ
however,ꢀasꢀtheꢀregisterꢀisꢀonlyꢀ8-bitꢀwide,ꢀonlyꢀjumpsꢀwithinꢀtheꢀcurrentꢀProgramꢀMemoryꢀpageꢀareꢀ
permitted.ꢀWhenꢀsuchꢀoperationsꢀareꢀused,ꢀnoteꢀthatꢀaꢀdummyꢀcycleꢀwillꢀbeꢀinserted.
Look-up Table Registers – TBLP, TBHP, TBLH
Theseꢀthreeꢀspecialꢀfunctionꢀregistersꢀareꢀusedꢀtoꢀcontrolꢀoperationꢀofꢀtheꢀlook-upꢀtableꢀwhichꢀisꢀ
storedꢀinꢀtheꢀProgramꢀMemory.ꢀTBLPꢀandꢀTBHPꢀareꢀtheꢀtableꢀpointersꢀandꢀindicateꢀtheꢀlocationꢀ
whereꢀtheꢀtableꢀdataꢀisꢀlocated.ꢀTheirꢀvalueꢀmustꢀbeꢀsetupꢀbeforeꢀanyꢀtableꢀreadꢀcommandsꢀareꢀ
executed.ꢀTheirꢀvalueꢀcanꢀbeꢀchanged,ꢀforꢀexampleꢀusingꢀtheꢀ“INC”ꢀorꢀ“DEC”ꢀinstructions,ꢀallowingꢀ
forꢀeasyꢀtableꢀdataꢀpointingꢀandꢀreading.ꢀTBLHꢀisꢀtheꢀlocationꢀwhereꢀtheꢀhighꢀorderꢀbyteꢀofꢀtheꢀtableꢀ
dataꢀisꢀstoredꢀafterꢀaꢀtableꢀreadꢀdataꢀinstructionꢀhasꢀbeenꢀexecuted.ꢀNoteꢀthatꢀtheꢀlowerꢀorderꢀtableꢀ
dataꢀbyteꢀisꢀtransferredꢀtoꢀaꢀuserꢀdefinedꢀlocation.ꢀ
Rev. 1.10
ꢃ5
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Status Register – STATUS
Thisꢀ8-bitꢀregisterꢀcontainsꢀtheꢀSCꢀflag,ꢀCZꢀflag,ꢀzeroꢀflagꢀ(Z),ꢀcarryꢀflagꢀ(C),ꢀauxiliaryꢀcarryꢀflagꢀ(AC),ꢀ
overflowꢀflagꢀ(OV),ꢀpowerꢀdownꢀflagꢀ(PDF),ꢀandꢀwatchdogꢀtime-outꢀflagꢀ(TO).ꢀTheseꢀarithmetic/
logicalꢀoperationꢀandꢀsystemꢀmanagementꢀflagsꢀareꢀusedꢀtoꢀrecordꢀtheꢀstatusꢀandꢀoperationꢀofꢀtheꢀ
microcontroller.ꢀ
WithꢀtheꢀexceptionꢀofꢀtheꢀTOꢀandꢀPDFꢀflags,ꢀbitsꢀinꢀtheꢀstatusꢀregisterꢀcanꢀbeꢀalteredꢀbyꢀinstructionsꢀ
likeꢀmostꢀotherꢀregisters.ꢀAnyꢀdataꢀwrittenꢀintoꢀtheꢀstatusꢀregisterꢀwillꢀnotꢀchangeꢀtheꢀTOꢀorꢀPDFꢀflag.ꢀ
Inꢀaddition,ꢀoperationsꢀrelatedꢀtoꢀtheꢀstatusꢀregisterꢀmayꢀgiveꢀdifferentꢀresultsꢀdueꢀtoꢀtheꢀdifferentꢀ
instructionꢀoperations.ꢀTheꢀTOꢀflagꢀcanꢀbeꢀaffectedꢀonlyꢀbyꢀaꢀsystemꢀpower-up,ꢀaꢀWDTꢀtime-outꢀorꢀ
byꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀorꢀ“HALT”ꢀinstruction.ꢀTheꢀPDFꢀflagꢀisꢀaffectedꢀonlyꢀbyꢀexecutingꢀ
theꢀ“HALT”ꢀorꢀ“CLRꢀWDT”ꢀinstructionꢀorꢀduringꢀaꢀsystemꢀpower-up.ꢀ
TheꢀZ,ꢀOV,ꢀAC,ꢀC,ꢀSCꢀandꢀCZꢀflagsꢀgenerallyꢀreflectꢀtheꢀstatusꢀofꢀtheꢀlatestꢀoperations.ꢀ
•ꢀ Cꢀisꢀsetꢀifꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀduringꢀanꢀadditionꢀoperationꢀorꢀifꢀaꢀborrowꢀdoesꢀnotꢀtakeꢀ
placeꢀduringꢀaꢀsubtractionꢀoperation;ꢀotherwiseꢀCꢀisꢀcleared.ꢀCꢀisꢀalsoꢀaffectedꢀbyꢀaꢀrotateꢀthroughꢀ
carryꢀinstruction.ꢀ
•ꢀ ACꢀisꢀsetꢀifꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀoutꢀofꢀtheꢀlowꢀnibblesꢀinꢀaddition,ꢀorꢀnoꢀborrowꢀfromꢀ
theꢀhighꢀnibbleꢀintoꢀtheꢀlowꢀnibbleꢀinꢀsubtraction;ꢀotherwiseꢀACꢀisꢀcleared.ꢀ
•ꢀ Zꢀisꢀsetꢀifꢀtheꢀresultꢀofꢀanꢀarithmeticꢀorꢀlogicalꢀoperationꢀisꢀzero;ꢀotherwiseꢀZꢀisꢀcleared.ꢀ
•ꢀ OVꢀisꢀsetꢀifꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀintoꢀtheꢀhighest-orderꢀbitꢀbutꢀnotꢀaꢀcarryꢀoutꢀofꢀtheꢀ
highest-orderꢀbit,ꢀorꢀviceꢀversa;ꢀotherwiseꢀOVꢀisꢀcleared.ꢀ
•ꢀ PDFꢀisꢀclearedꢀbyꢀaꢀsystemꢀpower-upꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀinstruction.ꢀPDFꢀisꢀsetꢀbyꢀ
executingꢀtheꢀ“HALT”ꢀinstruction.ꢀ
•ꢀ TOꢀisꢀclearedꢀbyꢀaꢀsystemꢀpower-upꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀorꢀ“HALT”ꢀinstruction.ꢀTOꢀisꢀ
setꢀbyꢀaꢀWDTꢀtime-out.ꢀ
•ꢀ CZꢀisꢀtheꢀoperationalꢀresultꢀofꢀdifferentꢀflagsꢀforꢀdifferentꢀinstructions.ꢀReferꢀtoꢀregisterꢀ
definitionsꢀforꢀmoreꢀdetails.
•ꢀ SCꢀisꢀtheꢀresultꢀofꢀtheꢀ“XOR”ꢀoperationꢀwhichꢀisꢀperformedꢀbyꢀtheꢀOVꢀflagꢀandꢀtheꢀMSBꢀofꢀtheꢀ
currentꢀinstructionꢀoperationꢀresult.ꢀ
Inꢀaddition,ꢀonꢀenteringꢀanꢀinterruptꢀsequenceꢀorꢀexecutingꢀaꢀsubroutineꢀcall,ꢀtheꢀstatusꢀregisterꢀwillꢀ
notꢀbeꢀpushedꢀontoꢀtheꢀstackꢀautomatically.ꢀIfꢀtheꢀcontentsꢀofꢀtheꢀstatusꢀregistersꢀareꢀimportantꢀandꢀifꢀ
theꢀsubroutineꢀcanꢀcorruptꢀtheꢀstatusꢀregister,ꢀprecautionsꢀmustꢀbeꢀtakenꢀtoꢀcorrectlyꢀsaveꢀit.
Rev. 1.10
ꢃ6
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
STATUS Register
Bit
Name
R/W
7
SC
R/W
x
6
CZ
R/W
x
5
TO
R
4
PDF
R
3
OV
R/W
x
2
Z
1
AC
R/W
x
0
C
R/W
x
R/W
x
POR
0
0
“x” ꢀnknown
Bitꢀ7
SC:ꢀXORꢀOperationꢀResultꢀ-ꢀperformedꢀbyꢀtheꢀOVꢀflagꢀandꢀtheꢀMSBꢀofꢀtheꢀinstructionꢀ
operationꢀresult.ꢀ
Bitꢀ6
CZ:ꢀOperationalꢀResultꢀofꢀDifferentꢀFlagsꢀforꢀDifferentꢀInstructions.ꢀ
ForꢀSUB/SUBM/LSUB/LSUBMꢀinstructions,ꢀtheꢀCZꢀflagꢀisꢀequalꢀtoꢀtheꢀZꢀflag.ꢀ
ForꢀSBC/SBCM/LSBC/LSBCMꢀinstructions,ꢀtheꢀCZꢀflagꢀisꢀtheꢀ“AND”ꢀoperationꢀ
resultꢀwhichꢀisꢀperformedꢀbyꢀtheꢀpreviousꢀoperationꢀCZꢀflagꢀandꢀcurrentꢀoperationꢀzeroꢀ
flag.ꢀ
Forꢀotherꢀinstructions,ꢀtheꢀCZꢀflagꢀwillꢀnotꢀbeꢀaffected.
Bitꢀ5
Bitꢀ4
Bitꢀ3
TO:ꢀWatchdogꢀTime-OutꢀFlag
0:ꢀAfterꢀpowerꢀupꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀorꢀ“HALT”ꢀinstruction
1:ꢀAꢀwatchdogꢀtime-outꢀoccurred.
PDF:ꢀPowerꢀDownꢀFlag
0:ꢀAfterꢀpowerꢀupꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀinstruction
1:ꢀByꢀexecutingꢀtheꢀ“HALT”ꢀinstruction
OV:ꢀOverflowꢀFlag
0:ꢀNoꢀoverflow
1:ꢀAnꢀoperationꢀresultsꢀinꢀaꢀcarryꢀintoꢀtheꢀhighest-orderꢀbitꢀbutꢀnotꢀaꢀcarryꢀoutꢀofꢀtheꢀ
highest-orderꢀbitꢀorꢀviceꢀversa.
Bitꢀ2
Bitꢀ1
Z:ꢀZeroꢀFlag
0:ꢀTheꢀresultꢀofꢀanꢀarithmeticꢀorꢀlogicalꢀoperationꢀisꢀnotꢀzero
1:ꢀTheꢀresultꢀofꢀanꢀarithmeticꢀorꢀlogicalꢀoperationꢀisꢀzero
AC:ꢀAuxiliaryꢀflag
0:ꢀNoꢀauxiliaryꢀcarry
1:ꢀAnꢀoperationꢀresultsꢀinꢀaꢀcarryꢀoutꢀofꢀtheꢀlowꢀnibblesꢀinꢀaddition,ꢀorꢀnoꢀborrowꢀ
fromꢀtheꢀhighꢀnibbleꢀintoꢀtheꢀlowꢀnibbleꢀinꢀsubtraction
Bitꢀ0
C:ꢀCarryꢀFlag
0:ꢀNoꢀcarry-out
1:ꢀAnꢀoperationꢀresultsꢀinꢀaꢀcarryꢀduringꢀanꢀadditionꢀoperationꢀorꢀifꢀaꢀborrowꢀdoesꢀ
notꢀtakeꢀplaceꢀduringꢀaꢀsubtractionꢀoperationꢀ
Cꢀisꢀalsoꢀaffectedꢀbyꢀaꢀrotateꢀthroughꢀcarryꢀinstruction.
Rev. 1.10
ꢃ7
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
EEPROM Data Memory
TheseꢀdevicesꢀcontainꢀanꢀareaꢀofꢀinternalꢀEEPROMꢀDataꢀMemory.ꢀEEPROM,ꢀwhichꢀstandsꢀforꢀ
ElectricallyꢀErasableꢀProgrammableꢀReadꢀOnlyꢀMemory,ꢀisꢀbyꢀitsꢀnatureꢀaꢀnon-volatileꢀformꢀ
ofꢀre-programmableꢀmemory,ꢀwithꢀdataꢀretentionꢀevenꢀwhenꢀitsꢀpowerꢀsupplyꢀisꢀremoved.ꢀByꢀ
incorporatingꢀthisꢀkindꢀofꢀdataꢀmemory,ꢀaꢀwholeꢀnewꢀhostꢀofꢀapplicationꢀpossibilitiesꢀareꢀmadeꢀ
availableꢀtoꢀtheꢀdesigner.ꢀTheꢀavailabilityꢀofꢀEEPROMꢀstorageꢀallowsꢀinformationꢀsuchꢀasꢀproductꢀ
identificationꢀnumbers,ꢀcalibrationꢀvalues,ꢀspecificꢀuserꢀdata,ꢀsystemꢀsetupꢀdataꢀorꢀotherꢀproductꢀ
informationꢀtoꢀbeꢀstoredꢀdirectlyꢀwithinꢀtheꢀproductꢀmicrocontroller.ꢀTheꢀprocessꢀofꢀreadingꢀandꢀ
writingꢀdataꢀtoꢀtheꢀEEPROMꢀmemoryꢀhasꢀbeenꢀreducedꢀtoꢀaꢀveryꢀtrivialꢀaffair.
EEPROM Data Memory Structure
TheꢀEEPROMꢀDataꢀMemoryꢀcapacityꢀisꢀ64×8ꢀ~ꢀ256×8ꢀbitsꢀforꢀtheseꢀdevices.ꢀUnlikeꢀtheꢀProgramꢀ
MemoryꢀandꢀRAMꢀDataꢀMemory,ꢀtheꢀEEPROMꢀDataꢀMemoryꢀisꢀnotꢀdirectlyꢀmappedꢀintoꢀmemoryꢀ
spaceꢀandꢀisꢀthereforeꢀnotꢀdirectlyꢀaddressableꢀinꢀtheꢀsameꢀwayꢀasꢀtheꢀotherꢀtypesꢀofꢀmemory.ꢀReadꢀ
andꢀWriteꢀoperationsꢀtoꢀtheꢀEEPROMꢀareꢀcarriedꢀoutꢀinꢀsingleꢀbyteꢀoperationsꢀusingꢀanꢀaddressꢀandꢀ
aꢀdataꢀregisterꢀinꢀSectorꢀ0ꢀandꢀaꢀsingleꢀcontrolꢀregisterꢀinꢀSectorꢀ1.
EEPROM Registers
ThreeꢀregistersꢀcontrolꢀtheꢀoverallꢀoperationꢀofꢀtheꢀinternalꢀEEPROMꢀDataꢀMemory.ꢀTheseꢀareꢀtheꢀ
addressꢀregister,ꢀEEA,ꢀtheꢀdataꢀregister,ꢀEEDꢀandꢀaꢀsingleꢀcontrolꢀregister,ꢀEEC.ꢀAsꢀbothꢀtheꢀEEAꢀ
andꢀEEDꢀregistersꢀareꢀlocatedꢀinꢀSectorꢀ0,ꢀtheyꢀcanꢀbeꢀdirectlyꢀaccessedꢀinꢀtheꢀsameꢀwasꢀasꢀanyꢀ
otherꢀSpecialꢀFunctionꢀRegister.ꢀTheꢀEECꢀregisterꢀhowever,ꢀbeingꢀlocatedꢀinꢀSectorꢀ1,ꢀcanꢀbeꢀreadꢀ
fromꢀorꢀwrittenꢀtoꢀindirectlyꢀusingꢀtheꢀMP1L/MP1HꢀorꢀMP2L/MP2HꢀMemoryꢀPointerꢀandꢀIndirectꢀ
AddressingꢀRegister,ꢀIAR1/IAR2.ꢀBecauseꢀtheꢀEECꢀcontrolꢀregisterꢀisꢀlocatedꢀatꢀaddressꢀ40Hꢀinꢀ
Sectorꢀ1,ꢀtheꢀMP1LꢀorꢀMP2LꢀMemoryꢀPointerꢀmustꢀfirstꢀbeꢀsetꢀtoꢀtheꢀvalueꢀ40HꢀandꢀtheꢀMP1Hꢀorꢀ
MP2HꢀMemoryꢀPointerꢀhighꢀbyteꢀsetꢀtoꢀtheꢀvalue,ꢀ01H,ꢀbeforeꢀanyꢀoperationsꢀonꢀtheꢀEECꢀregisterꢀ
areꢀexecuted.
Bit
Register Name
7
6
5
4
3
2
1
0
EEA (BH66Fꢅ650)
EEA (BH66Fꢅ660)
EED
—
—
EEA5
EEA5
EED5
—
EEAꢃ
EEAꢃ
EEDꢃ
—
EEA3
EEA3
EED3
WREN
EEAꢅ
EEAꢅ
EEDꢅ
WR
EEA1
EEA1
EED1
RDEN
EEA0
EEA0
EED0
RD
EEA7
EED7
—
EEA6
EED6
—
EEC
EEPROM Register List
• EEA Register – BH66F2650
Bit
Name
R/W
7
6
5
4
EEAꢃ
R/W
0
3
2
1
0
EEA0
R/W
0
—
—
—
—
—
—
EEA5
R/W
0
EEA3
R/W
0
EEAꢅ
R/W
0
EEA1
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~0
Unimplemented,ꢀreadꢀasꢀ“0”
EEA5~EEA0:ꢀDataꢀEEPROMꢀAddress
DataꢀEEPROMꢀaddressꢀbitꢀ5~bitꢀ0
Rev. 1.10
ꢃꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
• EEA Register – BH66F2660
Bit
Name
R/W
7
EEA7
R/W
0
6
EEA6
R/W
0
5
EEA5
R/W
0
4
EEAꢃ
R/W
0
3
EEA3
R/W
0
2
EEAꢅ
R/W
0
1
EEA1
R/W
0
0
EEA0
R/W
0
POR
Bitꢀ7~0
EEA7~EEA0:ꢀDataꢀEEPROMꢀAddress
DataꢀEEPROMꢀaddressꢀbitꢀ7~bitꢀ0
• EED Register
Bit
7
6
EED6
R/W
0
5
EED5
R/W
0
4
EEDꢃ
R/W
0
3
EED3
R/W
0
2
EEDꢅ
R/W
0
1
EED1
R/W
0
0
EED0
R/W
0
Name
R/W
EED7
R/W
0
POR
Bitꢀ7~0ꢀ
EED7~EED0:ꢀDataꢀEEPROMꢀData
DataꢀEEPROMꢀdataꢀbitꢀ7~bitꢀ0
• EEC Register
Bit
7
6
5
4
3
WREN
R/W
0
2
WR
R/W
0
1
RDEN
R/W
0
0
RD
R/W
0
Name
R/W
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~4ꢀꢀꢀꢀꢀꢀ Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ3ꢀꢀꢀꢀꢀꢀꢀ
WREN:ꢀDataꢀEEPROMꢀWriteꢀEnable
0:ꢀDisable
1:ꢀEnable
ThisꢀisꢀtheꢀDataꢀEEPROMꢀWriteꢀEnableꢀBitꢀwhichꢀmustꢀbeꢀsetꢀhighꢀbeforeꢀDataꢀ
EEPROMꢀwriteꢀoperationsꢀareꢀcarriedꢀout.ꢀClearingꢀthisꢀbitꢀtoꢀ“0”ꢀwillꢀinhibitꢀDataꢀ
EEPROMꢀwriteꢀoperations.
Bitꢀ2ꢀꢀꢀꢀꢀꢀꢀ
WR:ꢀEEPROMꢀWriteꢀControl
0:ꢀWriteꢀcycleꢀhasꢀfinished
1:ꢀActivateꢀaꢀwriteꢀcycle
ThisꢀisꢀtheꢀDataꢀEEPROMꢀWriteꢀControlꢀBitꢀandꢀwhenꢀsetꢀhighꢀbyꢀtheꢀapplicationꢀ
programꢀwillꢀactivateꢀaꢀwriteꢀcycle.ꢀThisꢀbitꢀwillꢀbeꢀautomaticallyꢀresetꢀtoꢀ“0”ꢀbyꢀtheꢀ
hardwareꢀafterꢀtheꢀwriteꢀcycleꢀhasꢀfinished.ꢀSettingꢀthisꢀbitꢀhighꢀwillꢀhaveꢀnoꢀeffectꢀifꢀ
theꢀWRENꢀhasꢀnotꢀfirstꢀbeenꢀsetꢀhigh.
Bitꢀ1ꢀꢀꢀꢀꢀꢀꢀ
Bitꢀ0ꢀꢀꢀꢀꢀꢀꢀ
RDEN:ꢀDataꢀEEPROMꢀReadꢀEnable
0:ꢀDisable
1:ꢀEnable
ThisꢀisꢀtheꢀDataꢀEEPROMꢀReadꢀEnableꢀBitꢀwhichꢀmustꢀbeꢀsetꢀhighꢀbeforeꢀDataꢀ
EEPROMꢀreadꢀoperationsꢀareꢀcarriedꢀout.ꢀClearingꢀthisꢀbitꢀtoꢀ“0”ꢀwillꢀinhibitꢀDataꢀ
EEPROMꢀreadꢀoperations.
RD:ꢀEEPROMꢀReadꢀControl
0:ꢀReadꢀcycleꢀhasꢀfinished
1:ꢀActivateꢀaꢀreadꢀcycle
ThisꢀisꢀtheꢀDataꢀEEPROMꢀReadꢀControlꢀBitꢀandꢀwhenꢀsetꢀhighꢀbyꢀtheꢀapplicationꢀ
programꢀwillꢀactivateꢀaꢀreadꢀcycle.ꢀThisꢀbitꢀwillꢀbeꢀautomaticallyꢀresetꢀtoꢀ“0”ꢀbyꢀtheꢀ
hardwareꢀafterꢀtheꢀreadꢀcycleꢀhasꢀfinished.ꢀSettingꢀthisꢀbitꢀhighꢀwillꢀhaveꢀnoꢀeffectꢀifꢀ
theꢀRDENꢀhasꢀnotꢀfirstꢀbeenꢀsetꢀhigh.
Note:ꢀTheꢀWREN,ꢀWR,ꢀRDENꢀandꢀRDꢀcannotꢀbeꢀsetꢀhighꢀatꢀtheꢀsameꢀtimeꢀinꢀoneꢀinstruction.ꢀTheꢀ
WRꢀandꢀRDꢀcannotꢀbeꢀsetꢀhighꢀatꢀtheꢀsameꢀtime.
Rev. 1.10
ꢃ9
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Reading Data from the EEPROM
ToꢀreadꢀdataꢀfromꢀtheꢀEEPROM,ꢀtheꢀreadꢀenableꢀbit,ꢀRDEN,ꢀinꢀtheꢀEECꢀregisterꢀmustꢀfirstꢀbeꢀsetꢀ
highꢀtoꢀenableꢀtheꢀreadꢀfunction.ꢀTheꢀEEPROMꢀaddressꢀofꢀtheꢀdataꢀtoꢀbeꢀreadꢀmustꢀthenꢀbeꢀplacedꢀ
inꢀtheꢀEEAꢀregister.ꢀIfꢀtheꢀRDꢀbitꢀinꢀtheꢀEECꢀregisterꢀisꢀnowꢀsetꢀhigh,ꢀaꢀreadꢀcycleꢀwillꢀbeꢀinitiated.ꢀ
SettingꢀtheꢀRDꢀbitꢀhighꢀwillꢀnotꢀinitiateꢀaꢀreadꢀoperationꢀifꢀtheꢀRDENꢀbitꢀhasꢀnotꢀbeenꢀset.ꢀWhenꢀ
theꢀreadꢀcycleꢀterminates,ꢀtheꢀRDꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀ“0”,ꢀafterꢀwhichꢀtheꢀdataꢀcanꢀ
beꢀreadꢀfromꢀtheꢀEEDꢀregister.ꢀTheꢀdataꢀwillꢀremainꢀinꢀtheꢀEEDꢀregisterꢀuntilꢀanotherꢀreadꢀorꢀwriteꢀ
operationꢀisꢀexecuted.ꢀTheꢀapplicationꢀprogramꢀcanꢀpollꢀtheꢀRDꢀbitꢀtoꢀdetermineꢀwhenꢀtheꢀdataꢀisꢀ
validꢀforꢀreading.
Writing Data to the EEPROM
TheꢀEEPROMꢀaddressꢀofꢀtheꢀdataꢀtoꢀbeꢀwrittenꢀmustꢀfirstꢀbeꢀplacedꢀinꢀtheꢀEEAꢀregisterꢀandꢀtheꢀdataꢀ
placedꢀinꢀtheꢀEEDꢀregister.ꢀToꢀwriteꢀdataꢀtoꢀtheꢀEEPROM,ꢀtheꢀwriteꢀenableꢀbit,ꢀWREN,ꢀinꢀtheꢀEECꢀ
registerꢀmustꢀfirstꢀbeꢀsetꢀhighꢀtoꢀenableꢀtheꢀwriteꢀfunction.ꢀAfterꢀthis,ꢀtheꢀWRꢀbitꢀinꢀtheꢀEECꢀregisterꢀ
mustꢀbeꢀimmediatelyꢀsetꢀhighꢀtoꢀinitiateꢀaꢀwriteꢀcycle.ꢀTheseꢀtwoꢀinstructionsꢀmustꢀbeꢀexecutedꢀ
consecutively.ꢀTheꢀglobalꢀinterruptꢀbitꢀEMIꢀshouldꢀalsoꢀfirstꢀbeꢀclearedꢀbeforeꢀimplementingꢀanyꢀ
writeꢀoperations,ꢀandꢀthenꢀsetꢀagainꢀafterꢀtheꢀwriteꢀcycleꢀhasꢀstarted.ꢀNoteꢀthatꢀsettingꢀtheꢀWRꢀbitꢀ
highꢀwillꢀnotꢀinitiateꢀaꢀwriteꢀcycleꢀifꢀtheꢀWRENꢀbitꢀhasꢀnotꢀbeenꢀset.ꢀAsꢀtheꢀEEPROMꢀwriteꢀcycleꢀisꢀ
controlledꢀusingꢀanꢀinternalꢀtimerꢀwhoseꢀoperationꢀisꢀasynchronousꢀtoꢀmicrocontrollerꢀsystemꢀclock,ꢀ
aꢀcertainꢀtimeꢀwillꢀelapseꢀbeforeꢀtheꢀdataꢀwillꢀhaveꢀbeenꢀwrittenꢀintoꢀtheꢀEEPROM.ꢀDetectingꢀwhenꢀ
theꢀwriteꢀcycleꢀhasꢀfinishedꢀcanꢀbeꢀimplementedꢀeitherꢀbyꢀpollingꢀtheꢀWRꢀbitꢀinꢀtheꢀEECꢀregisterꢀorꢀ
byꢀusingꢀtheꢀEEPROMꢀinterrupt.ꢀWhenꢀtheꢀwriteꢀcycleꢀterminates,ꢀtheꢀWRꢀbitꢀwillꢀbeꢀautomaticallyꢀ
clearedꢀtoꢀ“0”ꢀbyꢀtheꢀmicrocontroller,ꢀinformingꢀtheꢀuserꢀthatꢀtheꢀdataꢀhasꢀbeenꢀwrittenꢀtoꢀtheꢀ
EEPROM.ꢀTheꢀapplicationꢀprogramꢀcanꢀthereforeꢀpollꢀtheꢀWRꢀbitꢀtoꢀdetermineꢀwhenꢀtheꢀwriteꢀcycleꢀ
hasꢀended.
Write Protection
Protectionꢀagainstꢀinadvertentꢀwriteꢀoperationꢀisꢀprovidedꢀinꢀseveralꢀways.ꢀAfterꢀtheꢀdeviceꢀisꢀ
powered-onꢀtheꢀWriteꢀEnableꢀbitꢀinꢀtheꢀcontrolꢀregisterꢀwillꢀbeꢀclearedꢀpreventingꢀanyꢀwriteꢀ
operations.ꢀAlsoꢀatꢀpower-onꢀtheꢀMemoryꢀPointerꢀhighꢀbyteꢀregister,ꢀMP1HꢀorꢀMP2H,ꢀwillꢀbeꢀresetꢀ
toꢀ“0”,ꢀwhichꢀmeansꢀthatꢀDataꢀMemoryꢀSectorꢀ0ꢀwillꢀbeꢀselected.ꢀAsꢀtheꢀEEPROMꢀcontrolꢀregisterꢀ
isꢀlocatedꢀinꢀSectorꢀ1,ꢀthisꢀaddsꢀaꢀfurtherꢀmeasureꢀofꢀprotectionꢀagainstꢀspuriousꢀwriteꢀoperations.ꢀ
Duringꢀnormalꢀprogramꢀoperation,ꢀensuringꢀthatꢀtheꢀWriteꢀEnableꢀbitꢀinꢀtheꢀcontrolꢀregisterꢀisꢀ
clearedꢀwillꢀsafeguardꢀagainstꢀincorrectꢀwriteꢀoperations.
EEPROM Interrupt
TheꢀEEPROMꢀwriteꢀinterruptꢀisꢀgeneratedꢀwhenꢀanꢀEEPROMꢀwriteꢀcycleꢀhasꢀended.ꢀTheꢀEEPROMꢀ
interruptꢀmustꢀfirstꢀbeꢀenabledꢀbyꢀsettingꢀtheꢀDEEꢀbitꢀinꢀtheꢀrelevantꢀinterruptꢀregister.ꢀHoweverꢀasꢀ
theꢀEEPROMꢀisꢀcontainedꢀwithinꢀaꢀMulti-functionꢀInterrupt,ꢀtheꢀassociatedꢀmulti-functionꢀinterruptꢀ
enableꢀbitꢀmustꢀalsoꢀbeꢀset.ꢀWhenꢀanꢀEEPROMꢀwriteꢀcycleꢀends,ꢀtheꢀDEFꢀrequestꢀflagꢀandꢀitsꢀ
associatedꢀmulti-functionꢀinterruptꢀrequestꢀflagꢀwillꢀbothꢀbeꢀset.ꢀIfꢀtheꢀglobal,ꢀEEPROMꢀandꢀMulti-
functionꢀinterruptsꢀareꢀenabledꢀandꢀtheꢀstackꢀisꢀnotꢀfull,ꢀaꢀjumpꢀtoꢀtheꢀassociatedꢀMulti-functionꢀ
Interruptꢀvectorꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀservicedꢀonlyꢀtheꢀMulti-functionꢀinterruptꢀflagꢀ
willꢀbeꢀautomaticallyꢀreset,ꢀtheꢀEEPROMꢀinterruptꢀflagꢀmustꢀbeꢀmanuallyꢀresetꢀbyꢀtheꢀapplicationꢀ
program.ꢀMoreꢀdetailsꢀcanꢀbeꢀobtainedꢀinꢀtheꢀInterruptꢀsection.
Rev. 1.10
50
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Programming Considerations
CareꢀmustꢀbeꢀtakenꢀthatꢀdataꢀisꢀnotꢀinadvertentlyꢀwrittenꢀtoꢀtheꢀEEPROM.ꢀProtectionꢀcanꢀbeꢀ
enhancedꢀbyꢀensuringꢀthatꢀtheꢀWriteꢀEnableꢀbitꢀisꢀnormallyꢀclearedꢀtoꢀ“0”ꢀwhenꢀnotꢀwriting.ꢀAlsoꢀ
theꢀMemoryꢀPointerꢀhighꢀbyteꢀregister,ꢀMP1HꢀorꢀMP2H,ꢀcouldꢀbeꢀnormallyꢀclearedꢀtoꢀ“0”ꢀasꢀthisꢀ
wouldꢀinhibitꢀaccessꢀtoꢀSectorꢀ1ꢀwhereꢀtheꢀEEPROMꢀcontrolꢀregisterꢀexist.ꢀAlthoughꢀcertainlyꢀnotꢀ
necessary,ꢀconsiderationꢀmightꢀbeꢀgivenꢀinꢀtheꢀapplicationꢀprogramꢀtoꢀtheꢀcheckingꢀofꢀtheꢀvalidityꢀofꢀ
newꢀwriteꢀdataꢀbyꢀaꢀsimpleꢀreadꢀbackꢀprocess.
WhenꢀwritingꢀdataꢀtheꢀWRꢀbitꢀmustꢀbeꢀsetꢀhighꢀimmediatelyꢀafterꢀtheꢀWRENꢀbitꢀhasꢀbeenꢀsetꢀhigh,ꢀ
toꢀensureꢀtheꢀwriteꢀcycleꢀexecutesꢀcorrectly.ꢀTheꢀglobalꢀinterruptꢀbitꢀEMIꢀshouldꢀalsoꢀbeꢀclearedꢀ
beforeꢀaꢀwriteꢀcycleꢀisꢀexecutedꢀandꢀthenꢀre-enabledꢀafterꢀtheꢀwriteꢀcycleꢀstarts.ꢀNoteꢀthatꢀtheꢀdeviceꢀ
shouldꢀnotꢀenterꢀtheꢀIDLEꢀorꢀSLEEPꢀmodeꢀuntilꢀtheꢀEEPROMꢀreadꢀorꢀwriteꢀoperationꢀisꢀtotallyꢀ
complete.ꢀOtherwise,ꢀtheꢀEEPROMꢀreadꢀorꢀwriteꢀoperationꢀwillꢀfail.
Programming Examples
• Reading Data from the EEPROM − Polling Method
MOVꢀ A,ꢀEEPROM_ADRESꢀ
MOVꢀ EEA,ꢀA
ꢀ
;ꢀuserꢀdefinedꢀaddress
MOVꢀ A,ꢀ40Hꢀꢀ
MOVꢀ MP1L,ꢀAꢀ
MOVꢀ A,ꢀ01Hꢀꢀ
MOVꢀ MP1H,ꢀA
SETꢀ IAR1.1ꢀ ꢀ
SETꢀ IAR1.0ꢀ ꢀ
BACK:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀsetupꢀmemoryꢀpointerꢀMP1L
;ꢀMP1LꢀpointsꢀtoꢀEECꢀregister
;ꢀsetupꢀmemoryꢀpointerꢀMP1H
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀsetꢀRDENꢀbit,ꢀenableꢀreadꢀoperations
;ꢀstartꢀReadꢀCycleꢀ-ꢀsetꢀRDꢀbit
SZꢀ IAR1.0ꢀ ꢀ
JMPꢀ BACK
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀcheckꢀforꢀreadꢀcycleꢀend
;ꢀdisableꢀEEPROMꢀread/write
;ꢀmoveꢀreadꢀdataꢀtoꢀregister
CLRꢀ IAR1ꢀ
CLRꢀ MP1H
ꢀ
MOVꢀ A,ꢀEEDꢀꢀ
MOVꢀ READ_DATA,ꢀA
• Writing Data to the EEPROM − Polling Method
MOVꢀ A,ꢀEEPROM_ADRESꢀ
MOVꢀ EEA,ꢀA
ꢀ
;ꢀuserꢀdefinedꢀaddress
MOVꢀ A,ꢀEEPROM_DATAꢀ
MOVꢀ EED,ꢀA
ꢀ
;ꢀuserꢀdefinedꢀdata
MOVꢀ A,ꢀ040Hꢀꢀ
MOVꢀ MP1L,ꢀAꢀ
MOVꢀ A,ꢀ01Hꢀꢀ
MOVꢀ MP1H,ꢀA
CLRꢀ EMI
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀsetupꢀmemoryꢀpointerꢀMP1L
;ꢀMP1LꢀpointsꢀtoꢀEECꢀregister
;ꢀsetupꢀmemoryꢀpointerꢀMP1H
SETꢀ IAR1.3ꢀ ꢀ
SETꢀ IAR1.2ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀsetꢀWRENꢀbit,ꢀenableꢀwriteꢀoperations
;ꢀstartꢀWriteꢀCycleꢀ-ꢀsetꢀWRꢀbitꢀ–ꢀexecutedꢀimmediately
;ꢀafterꢀsetꢀWRENꢀbit
ꢀ
ꢀ
ꢀ
ꢀ
SETꢀꢀEMI
BACK:
SZꢀ IAR1.2ꢀ ꢀ
JMPꢀ BACK
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀcheckꢀforꢀwriteꢀcycleꢀend
;ꢀdisableꢀEEPROMꢀread/write
CLRꢀ IAR1ꢀ
CLRꢀ MP1H
ꢀ
Rev. 1.10
51
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Oscillators
Variousꢀoscillatorꢀoptionsꢀofferꢀtheꢀuserꢀaꢀwideꢀrangeꢀofꢀfunctionsꢀaccordingꢀtoꢀtheirꢀvariousꢀ
applicationꢀrequirements.ꢀTheꢀflexibleꢀfeaturesꢀofꢀtheꢀoscillatorꢀfunctionsꢀensureꢀthatꢀtheꢀbestꢀ
optimisationꢀcanꢀbeꢀachievedꢀinꢀtermsꢀofꢀspeedꢀandꢀpowerꢀsaving.ꢀOscillatorꢀselectionsꢀandꢀoperationꢀ
areꢀselectedꢀthroughꢀrelevantꢀcontrolꢀregisters.
Oscillator Overview
Inꢀadditionꢀtoꢀbeingꢀtheꢀsourceꢀofꢀtheꢀmainꢀsystemꢀclockꢀtheꢀoscillatorsꢀalsoꢀprovideꢀclockꢀsourcesꢀ
forꢀtheꢀWatchdogꢀTimerꢀandꢀTimeꢀBaseꢀInterrupts.ꢀExternalꢀoscillatorsꢀrequiringꢀsomeꢀexternalꢀ
componentsꢀasꢀwellꢀasꢀfullyꢀintegratedꢀinternalꢀoscillators,ꢀrequiringꢀnoꢀexternalꢀcomponents,ꢀareꢀ
providedꢀtoꢀformꢀaꢀwideꢀrangeꢀofꢀbothꢀfastꢀandꢀslowꢀsystemꢀoscillators.ꢀAllꢀoscillatorꢀoptionsꢀareꢀ
selectedꢀthroughꢀtheꢀregisters.ꢀTheꢀhigherꢀfrequencyꢀoscillatorsꢀprovideꢀhigherꢀperformanceꢀbutꢀ
carryꢀwithꢀitꢀtheꢀdisadvantageꢀofꢀhigherꢀpowerꢀrequirements,ꢀwhileꢀtheꢀoppositeꢀisꢀofꢀcourseꢀtrueꢀforꢀ
theꢀlowerꢀfrequencyꢀoscillators.ꢀWithꢀtheꢀcapabilityꢀofꢀdynamicallyꢀswitchingꢀbetweenꢀfastꢀandꢀslowꢀ
systemꢀclock,ꢀtheseꢀdevicesꢀhaveꢀtheꢀflexibilityꢀtoꢀoptimizeꢀtheꢀperformance/powerꢀratio,ꢀaꢀfeatureꢀ
especiallyꢀimportantꢀinꢀpowerꢀsensitiveꢀportableꢀapplications.
Type
Exteꢁnal Cꢁꢂstal
Name
HXT
Freq.
ꢃꢄ ꢆꢄ 1ꢅꢄ 16MHz
ꢃꢄ ꢆꢄ 1ꢅMHz
3ꢅ.76ꢆkHz
3ꢅkHz
Pins
OSC1/OSCꢅ
—
Inteꢁnal High Speed RC
Exteꢁnal Low Speed Cꢁꢂstal
Inteꢁnal Low Speed RC
HIRC
LXT
XT1/XT2
—
LIRC
System Clock Configurations
Thereꢀareꢀfourꢀmethodsꢀofꢀgeneratingꢀtheꢀsystemꢀclock,ꢀtwoꢀhighꢀspeedꢀoscillatorsꢀandꢀtwoꢀlowꢀspeedꢀ
oscillators.ꢀTheꢀhighꢀspeedꢀoscillatorsꢀareꢀtheꢀexternalꢀcrystal/ceramicꢀoscillatorꢀandꢀtheꢀinternalꢀ
4/8/12MHzꢀRCꢀoscillator.ꢀTheꢀtwoꢀlowꢀspeedꢀoscillatorsꢀareꢀtheꢀinternalꢀ32kHzꢀRCꢀoscillatorꢀandꢀ
theꢀexternalꢀ32.768kHzꢀcrystalꢀoscillator.ꢀSelectingꢀwhetherꢀtheꢀlowꢀorꢀhighꢀspeedꢀoscillatorꢀisꢀusedꢀ
asꢀtheꢀsystemꢀoscillatorꢀisꢀimplementedꢀusingꢀtheꢀCKS2~CKS0ꢀbitsꢀinꢀtheꢀSCCꢀregisterꢀandꢀasꢀtheꢀ
systemꢀclockꢀcanꢀbeꢀdynamicallyꢀselected.
TheꢀactualꢀsourceꢀclockꢀusedꢀforꢀtheꢀlowꢀspeedꢀoscillatorsꢀisꢀchosenꢀviaꢀtheꢀFSSꢀbitꢀinꢀtheꢀSCCꢀ
registerꢀwhileꢀforꢀtheꢀhighꢀspeedꢀoscillatorꢀtheꢀsourceꢀclockꢀisꢀselectedꢀbyꢀtheꢀFHSꢀbitꢀinꢀtheꢀSCCꢀ
register.ꢀTheꢀfrequencyꢀofꢀtheꢀslowꢀspeedꢀorꢀhighꢀspeedꢀsystemꢀclockꢀisꢀdeterminedꢀusingꢀtheꢀ
CKS2~CKS0ꢀbitsꢀinꢀtheꢀSCCꢀregister.ꢀNoteꢀthatꢀtwoꢀoscillatorꢀselectionsꢀmustꢀbeꢀmadeꢀnamelyꢀoneꢀ
highꢀspeedꢀandꢀoneꢀlowꢀspeedꢀsystemꢀoscillators.ꢀItꢀisꢀnotꢀpossibleꢀtoꢀchooseꢀaꢀno-oscillatorꢀselectionꢀ
forꢀeitherꢀtheꢀhighꢀorꢀlowꢀspeedꢀoscillator.
Rev. 1.10
5ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
fH
FHS
High Speed
fH/ꢅ
fH/ꢃ
fH/ꢆ
fH/16
Oscillatoꢁs
HXTEN
HXT
IDLE0
SLEEP
Pꢁescaleꢁ
fSYS
HIRCEN
HIRC
fH/3ꢅ
fH/6ꢃ
FSS
Low Speed
Oscillatoꢁs
CKSꢅ~CKS0
LXTEN
LXT
fSUB
fSUB
IDLEꢅ
SLEEP
fLIRC
LIRC
fLIRC
System Clock Configurations
External High Speed Crystal Oscillator − HXT
TheꢀsimpleꢀconnectionꢀofꢀaꢀcrystalꢀacrossꢀOSC1ꢀandꢀOSC2ꢀwillꢀcreateꢀtheꢀnecessaryꢀphaseꢀshiftꢀandꢀ
feedbackꢀforꢀoscillation.ꢀHowever,ꢀforꢀsomeꢀcrystalsꢀandꢀmostꢀresonatorꢀtypes,ꢀtoꢀensureꢀoscillationꢀ
andꢀaccurateꢀfrequencyꢀgeneration,ꢀitꢀisꢀnecessaryꢀtoꢀaddꢀtwoꢀsmallꢀvalueꢀexternalꢀcapacitors,ꢀC1ꢀandꢀ
C2.ꢀTheꢀexactꢀvaluesꢀofꢀC1ꢀandꢀC2ꢀshouldꢀbeꢀselectedꢀinꢀconsultationꢀwithꢀtheꢀcrystalꢀorꢀresonatorꢀ
manufacturer’sꢀspecification.
Forꢀoscillatorꢀstabilityꢀandꢀtoꢀminimiseꢀtheꢀeffectsꢀofꢀnoiseꢀandꢀcrosstalk,ꢀitꢀisꢀimportantꢀtoꢀensureꢀ
thatꢀtheꢀcrystalꢀandꢀanyꢀassociatedꢀresistorsꢀandꢀcapacitorsꢀalongꢀwithꢀinterconnectingꢀlinesꢀareꢀallꢀ
locatedꢀasꢀcloseꢀtoꢀtheꢀMCUꢀasꢀpossible.
Internal
Oscillator
Circuit
C1
OSC1
OSCꢅ
RP
RF
To inteꢁnal
ciꢁcꢀits
Cꢅ
Note: 1. RP is noꢁmallꢂ not ꢁeqꢀiꢁed. C1 and Cꢅ aꢁe ꢁeqꢀiꢁed.
ꢅ. Althoꢀgh not shown OSC1/OSCꢅ pins have a paꢁasitic
capacitance of aꢁoꢀnd 7pF.
Crystal/Resonator Oscillator – HXT
HXT Oscillator C1 and C2 Values
Crystal Frequency
1ꢅMHz
C1
0pF
C2
0pF
ꢆMHz
0pF
0pF
ꢃMHz
0pF
0pF
1MHz
100pF
100pF
Note: C1 and Cꢅ valꢀes aꢁe foꢁ gꢀidance onlꢂ.
Crystal Recommended Capacitor Values
Rev. 1.10
53
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Internal RC Oscillator − HIRC
TheꢀinternalꢀRCꢀoscillatorꢀisꢀaꢀfullyꢀintegratedꢀsystemꢀoscillatorꢀrequiringꢀnoꢀexternalꢀcomponents.ꢀ
TheꢀinternalꢀRCꢀoscillatorꢀhasꢀaꢀfixedꢀfrequencyꢀofꢀ4/8/12MHz.ꢀDeviceꢀtrimmingꢀduringꢀtheꢀ
manufacturingꢀprocessꢀandꢀtheꢀinclusionꢀofꢀinternalꢀfrequencyꢀcompensationꢀcircuitsꢀareꢀusedꢀtoꢀ
ensureꢀthatꢀtheꢀinfluenceꢀofꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀtemperatureꢀandꢀprocessꢀvariationsꢀonꢀtheꢀ
oscillationꢀfrequencyꢀareꢀminimised.ꢀNoteꢀthatꢀifꢀthisꢀinternalꢀsystemꢀclockꢀoptionꢀisꢀselected,ꢀasꢀitꢀ
requiresꢀnoꢀexternalꢀpinsꢀforꢀitsꢀoperation,ꢀI/OꢀpinsꢀareꢀfreeꢀforꢀuseꢀasꢀnormalꢀI/Oꢀpins.
External 32.768kHz Crystal Oscillator − LXT
Theꢀexternalꢀ32.768kHzꢀcrystalꢀsystemꢀoscillatorꢀisꢀoneꢀofꢀtheꢀlowꢀfrequencyꢀoscillatorꢀchoices,ꢀwhichꢀ
isꢀselectedꢀviaꢀaꢀsoftwareꢀcontrolꢀbit,ꢀFSS.ꢀThisꢀclockꢀsourceꢀhasꢀaꢀfixedꢀfrequencyꢀofꢀ32.768kHzꢀandꢀ
requiresꢀaꢀ32.768kHzꢀcrystalꢀtoꢀbeꢀconnectedꢀbetweenꢀpinsꢀXT1ꢀandꢀXT2.ꢀTheꢀexternalꢀresistorꢀandꢀ
capacitorꢀcomponentsꢀconnectedꢀtoꢀtheꢀ32.768kHzꢀcrystalꢀareꢀnecessaryꢀtoꢀprovideꢀoscillation.ꢀForꢀ
applicationsꢀwhereꢀpreciseꢀfrequenciesꢀareꢀessential,ꢀtheseꢀcomponentsꢀmayꢀbeꢀrequiredꢀtoꢀprovideꢀ
frequencyꢀcompensationꢀdueꢀtoꢀdifferentꢀcrystalꢀmanufacturingꢀtolerances.ꢀAfterꢀtheꢀLXTꢀoscillatorꢀ
isꢀenabledꢀbyꢀsettingꢀtheꢀLXTENꢀbitꢀtoꢀ“1”,ꢀthereꢀisꢀaꢀtimeꢀdelayꢀassociatedꢀwithꢀtheꢀLXTꢀoscillatorꢀ
waitingꢀforꢀitꢀtoꢀstart-up.
WhenꢀtheꢀmicrocontrollerꢀentersꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀtheꢀsystemꢀclockꢀisꢀswitchedꢀoffꢀtoꢀstopꢀ
microcontrollerꢀactivityꢀandꢀtoꢀconserveꢀpower.ꢀHowever,ꢀinꢀmanyꢀmicrocontrollerꢀapplicationsꢀ
itꢀmayꢀbeꢀnecessaryꢀtoꢀkeepꢀtheꢀinternalꢀtimersꢀoperationalꢀevenꢀwhenꢀtheꢀmicrocontrollerꢀisꢀinꢀ
theꢀSLEEPꢀorꢀIDLEꢀMode.ꢀToꢀdoꢀthis,ꢀanotherꢀclock,ꢀindependentꢀofꢀtheꢀsystemꢀclock,ꢀmustꢀbeꢀ
provided.ꢀ
However,ꢀforꢀsomeꢀcrystals,ꢀtoꢀensureꢀoscillationꢀandꢀaccurateꢀfrequencyꢀgeneration,ꢀitꢀisꢀnecessaryꢀ
toꢀaddꢀtwoꢀsmallꢀvalueꢀexternalꢀcapacitors,ꢀC1ꢀandꢀC2.ꢀTheꢀexactꢀvaluesꢀofꢀC1ꢀandꢀC2ꢀshouldꢀbeꢀ
selectedꢀinꢀconsultationꢀwithꢀtheꢀcrystalꢀorꢀresonatorꢀmanufacturer’sꢀspecification.ꢀTheꢀexternalꢀ
parallelꢀfeedbackꢀresistor,ꢀRP,ꢀandꢀtheꢀpullꢀhighꢀresistor,ꢀRU,ꢀareꢀrequired.
Theꢀpin-sharedꢀsoftwareꢀcontrolꢀbitsꢀdetermineꢀifꢀtheꢀXT1/XT2ꢀpinsꢀareꢀusedꢀforꢀtheꢀLXTꢀoscillatorꢀ
orꢀasꢀI/Oꢀorꢀotherꢀpin-sharedꢀfunctionalꢀpins.
•ꢀ IfꢀtheꢀLXTꢀoscillatorꢀisꢀnotꢀusedꢀforꢀanyꢀclockꢀsource,ꢀtheꢀXT1/XT2ꢀpinsꢀcanꢀbeꢀusedꢀasꢀnormalꢀ
I/Oꢀorꢀotherꢀpin-sharedꢀfunctionalꢀpins.
•ꢀ IfꢀtheꢀLXTꢀoscillatorꢀisꢀusedꢀforꢀanyꢀclockꢀsource,ꢀtheꢀ32.768kHzꢀcrystalꢀshouldꢀbeꢀconnectedꢀtoꢀ
theꢀXT1/XT2ꢀpins.
Forꢀoscillatorꢀstabilityꢀandꢀtoꢀminimiseꢀtheꢀeffectsꢀofꢀnoiseꢀandꢀcrosstalk,ꢀitꢀisꢀimportantꢀtoꢀensureꢀ
thatꢀtheꢀcrystalꢀandꢀanyꢀassociatedꢀresistorsꢀandꢀcapacitorsꢀalongꢀwithꢀinterconnectingꢀlinesꢀareꢀallꢀ
locatedꢀasꢀcloseꢀtoꢀtheꢀMCUꢀasꢀpossible.
VDD
Internal
Oscillator
Circuit
C1
XT1
XT2
3ꢅ.76ꢆ
kHz
Inteꢁnal RC
Oscillatoꢁ
RP
RU
To inteꢁnal
ciꢁcꢀits
Cꢅ
Note: 1. RPꢄ RUꢄ C1 and Cꢅ aꢁe ꢁeqꢀiꢁed.
2. Although not shown XT1/XTꢅ pins have a paꢁasitic
capacitance of aꢁoꢀnd 7pF.
External LXT Oscillator
Rev. 1.10
5ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
LXT Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
3ꢅ.76ꢆkHz
10pF
10pF
Note: 1. C1 and Cꢅ valꢀes aꢁe foꢁ gꢀidance onlꢂ.
ꢅ. RP=5M~10MΩ is recommended.
3. RU=10MΩ is recommended.
32.768kHz Crystal Recommended Capacitor Values
Internal 32kHz Oscillator − LIRC
Theꢀinternalꢀ32kHzꢀsystemꢀoscillatorꢀisꢀoneꢀofꢀtheꢀlowꢀfrequencyꢀoscillatorꢀchoices,ꢀwhichꢀisꢀ
selectedꢀviaꢀaꢀsoftwareꢀcontrolꢀbit,ꢀFSS.ꢀItꢀisꢀaꢀfullyꢀintegratedꢀRCꢀoscillatorꢀwithꢀaꢀtypicalꢀfrequencyꢀ
ofꢀ32kHzꢀatꢀ5V,ꢀrequiringꢀnoꢀexternalꢀcomponentsꢀforꢀitsꢀimplementation.ꢀDeviceꢀtrimmingꢀduringꢀ
theꢀmanufacturingꢀprocessꢀandꢀtheꢀinclusionꢀofꢀinternalꢀfrequencyꢀcompensationꢀcircuitsꢀareꢀusedꢀ
toꢀensureꢀthatꢀtheꢀinfluenceꢀofꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀtemperatureꢀandꢀprocessꢀvariationsꢀonꢀtheꢀ
oscillationꢀfrequencyꢀareꢀminimised.ꢀ
Operating Modes and System Clocks
Presentꢀdayꢀapplicationsꢀrequireꢀthatꢀtheirꢀmicrocontrollersꢀhaveꢀhighꢀperformanceꢀbutꢀoftenꢀstillꢀ
demandꢀthatꢀtheyꢀconsumeꢀasꢀlittleꢀpowerꢀasꢀpossible,ꢀconflictingꢀrequirementsꢀthatꢀareꢀespeciallyꢀ
trueꢀinꢀbatteryꢀpoweredꢀportableꢀapplications.ꢀTheꢀfastꢀclocksꢀrequiredꢀforꢀhighꢀperformanceꢀwillꢀ
byꢀtheirꢀnatureꢀincreaseꢀcurrentꢀconsumptionꢀandꢀofꢀcourseꢀviceꢀversa,ꢀlowerꢀspeedꢀclocksꢀreduceꢀ
currentꢀconsumption.ꢀAsꢀbothꢀhighꢀandꢀlowꢀspeedꢀclockꢀsourcesꢀareꢀprovidedꢀtheꢀmeansꢀtoꢀswitchꢀ
betweenꢀthemꢀdynamically,ꢀtheꢀuserꢀcanꢀoptimiseꢀtheꢀoperationꢀofꢀtheirꢀmicrocontrollerꢀtoꢀachieveꢀ
theꢀbestꢀperformance/powerꢀratio.
System Clocks
TheseꢀdevicesꢀhaveꢀdifferentꢀclockꢀsourcesꢀforꢀbothꢀtheꢀCPUꢀandꢀperipheralꢀfunctionꢀoperation.ꢀByꢀ
providingꢀtheꢀuserꢀwithꢀaꢀwideꢀrangeꢀofꢀclockꢀselectionsꢀusingꢀregisterꢀprogramming,ꢀaꢀclockꢀsystemꢀ
canꢀbeꢀconfiguredꢀtoꢀobtainꢀmaximumꢀapplicationꢀperformance.
Theꢀmainꢀsystemꢀclock,ꢀcanꢀcomeꢀfromꢀeitherꢀaꢀhighꢀfrequency,ꢀfH,ꢀorꢀlowꢀfrequency,ꢀfSUB,ꢀsource,ꢀ
andꢀisꢀselectedꢀusingꢀtheꢀCKS2~CKS0ꢀbitsꢀinꢀtheꢀSCCꢀregister.ꢀTheꢀhighꢀspeedꢀsystemꢀclockꢀisꢀ
sourcedꢀfromꢀanꢀHXTꢀorꢀHIRCꢀoscillator.ꢀTheꢀlowꢀspeedꢀsystemꢀclockꢀsourceꢀcanꢀbeꢀsourcedꢀ
fromꢀtheꢀinternalꢀclockꢀfSUB.ꢀIfꢀfSUBꢀisꢀselectedꢀthenꢀitꢀcanꢀbeꢀsourcedꢀbyꢀeitherꢀtheꢀLXTꢀorꢀLIRCꢀ
oscillators,ꢀselectedꢀviaꢀconfiguringꢀtheꢀFSSꢀbitꢀinꢀtheꢀSCCꢀregister.ꢀTheꢀotherꢀchoice,ꢀwhichꢀisꢀaꢀ
dividedꢀversionꢀofꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀhasꢀaꢀrangeꢀofꢀfH/2~fH/64.
Rev. 1.10
55
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
fH
High Speed
Oscillatoꢁs
FHS
fH/ꢅ
fH/ꢃ
HXTEN
HXT
fH/ꢆ
IDLE0
SLEEP
Pꢁescaleꢁ
fH/16
fH/3ꢅ
fH/6ꢃ
fSYS
HIRCEN
HIRC
FSS
Low Speed
Oscillatoꢁs
LXTEN
LXT
CKSꢅ~CKS0
fSUB
fSUB
fSYS
IDLEꢅ
SLEEP
fLIRC
LIRC
fLIRC
fPSC
fSYS/ꢃ
fSUB
WDT
LVR
Pꢁescaleꢁ
Time Bases
fLIRC
TB1[ꢅ:0] TB0[ꢅ:0]
CLKSEL[1:0]
Device Clock Configurations
Note:ꢀWhenꢀtheꢀsystemꢀclockꢀsourceꢀfSYSꢀisꢀswitchedꢀtoꢀfSUBꢀfromꢀfH,ꢀtheꢀhighꢀspeedꢀoscillatorꢀcanꢀbeꢀ
stoppedꢀtoꢀconserveꢀtheꢀpowerꢀorꢀcontinueꢀtoꢀoscillateꢀtoꢀprovideꢀtheꢀclockꢀsource,ꢀfH~fH/64,ꢀ
forꢀperipheralꢀcircuitꢀtoꢀuse,ꢀwhichꢀisꢀdeterminedꢀbyꢀconfiguringꢀtheꢀcorrespondingꢀhighꢀspeedꢀ
oscillatorꢀenableꢀcontrolꢀbit.
System Operation Modes
Thereꢀareꢀsixꢀdifferentꢀmodesꢀofꢀoperationꢀforꢀtheꢀmicrocontroller,ꢀeachꢀoneꢀwithꢀitsꢀownꢀ
specialꢀcharacteristicsꢀandꢀwhichꢀcanꢀbeꢀchosenꢀaccordingꢀtoꢀtheꢀspecificꢀperformanceꢀandꢀ
powerꢀrequirementsꢀofꢀtheꢀapplication.ꢀThereꢀareꢀtwoꢀmodesꢀallowingꢀnormalꢀoperationꢀofꢀtheꢀ
microcontroller,ꢀtheꢀFASTꢀModeꢀandꢀSLOWꢀMode.ꢀTheꢀremainingꢀfourꢀmodes,ꢀtheꢀSLEEP,ꢀIDLE0,ꢀ
IDLE1ꢀandꢀIDLE2ꢀModeꢀareꢀusedꢀwhenꢀtheꢀmicrocontrollerꢀCPUꢀisꢀswitchedꢀoffꢀtoꢀconserveꢀpower.
Register Setting
FHIDEN FSIDEN CKS2~CKS0
Operation
Mode
CPU
fSYS
fH
fSUB
fLIRC
FAST
On
On
x
x
x
x
000~110
fH~fH/6ꢃ
On
On/Off (1)
On
On
On
On
SLOW
111
000~110
111
fSUB
Off
On
IDLE0
IDLE1
IDLEꢅ
SLEEP
Off
Off
Off
Off
0
1
1
0
1
1
0
0
Off
On
On
Off
On
On
Off
Off
On
On
On
xxx
On
000~110
111
On
Off
Off
xxx
On/Off (ꢅ)
“x” don’t caꢁe
Note:ꢀ1.ꢀTheꢀfHꢀclockꢀwillꢀbeꢀswitchedꢀonꢀorꢀoffꢀbyꢀconfiguringꢀtheꢀcorrespondingꢀoscillatorꢀenableꢀ
bitꢀinꢀtheꢀSLOWꢀmode.
2.ꢀTheꢀfLIRCꢀclockꢀcanꢀbeꢀswitchedꢀonꢀorꢀoffꢀwhichꢀisꢀcontrolledꢀbyꢀtheꢀWDTꢀfunctionꢀbeingꢀ
enabledꢀorꢀdisabled.
Rev. 1.10
56
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
FAST Mode
Asꢀtheꢀnameꢀsuggestsꢀthisꢀisꢀoneꢀofꢀtheꢀmainꢀoperatingꢀmodesꢀwhereꢀtheꢀmicrocontrollerꢀhasꢀallꢀofꢀ
itsꢀfunctionsꢀoperationalꢀandꢀwhereꢀtheꢀsystemꢀclockꢀisꢀprovidedꢀbyꢀoneꢀofꢀtheꢀhighꢀspeedꢀoscillators.ꢀ
Thisꢀmodeꢀoperatesꢀallowingꢀtheꢀmicrocontrollerꢀtoꢀoperateꢀnormallyꢀwithꢀaꢀclockꢀsourceꢀwillꢀcomeꢀ
fromꢀoneꢀofꢀtheꢀhighꢀspeedꢀoscillators,ꢀeitherꢀtheꢀHXTꢀorꢀHIRCꢀoscillators.ꢀTheꢀhighꢀspeedꢀoscillatorꢀ
willꢀhoweverꢀfirstꢀbeꢀdividedꢀbyꢀaꢀratioꢀrangingꢀfromꢀ1ꢀtoꢀ64,ꢀtheꢀactualꢀratioꢀbeingꢀselectedꢀbyꢀ
theꢀCKS2~CKS0ꢀbitsꢀinꢀtheꢀSCCꢀregister.ꢀAlthoughꢀaꢀhighꢀspeedꢀoscillatorꢀisꢀused,ꢀrunningꢀtheꢀ
microcontrollerꢀatꢀaꢀdividedꢀclockꢀratioꢀreducesꢀtheꢀoperatingꢀcurrent.
SLOW Mode
Thisꢀisꢀalsoꢀaꢀmodeꢀwhereꢀtheꢀmicrocontrollerꢀoperatesꢀnormallyꢀalthoughꢀnowꢀwithꢀaꢀslowerꢀspeedꢀ
clockꢀsource.ꢀTheꢀclockꢀsourceꢀusedꢀwillꢀbeꢀfromꢀfSUB.ꢀTheꢀfSUBꢀclockꢀisꢀderivedꢀfromꢀeitherꢀtheꢀ
LIRCꢀorꢀLXTꢀoscillator.ꢀ
SLEEP Mode
TheꢀSLEEPꢀModeꢀisꢀenteredꢀwhenꢀanꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀFHIDENꢀandꢀ
FSIDENꢀbitꢀareꢀlow.ꢀInꢀtheꢀSLEEPꢀmodeꢀtheꢀCPUꢀwillꢀbeꢀstopped.ꢀHoweverꢀtheꢀfLIRCꢀclockꢀcanꢀstillꢀ
continueꢀtoꢀoperateꢀifꢀtheꢀWDTꢀfunctionꢀisꢀenabled.
IDLE0 Mode
TheꢀIDLE0ꢀModeꢀisꢀenteredꢀwhenꢀanꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀFHIDENꢀbitꢀinꢀ
theꢀSCCꢀregisterꢀisꢀlowꢀandꢀtheꢀFSIDENꢀbitꢀinꢀtheꢀSCCꢀregisterꢀisꢀhigh.ꢀInꢀtheꢀIDLE0ꢀModeꢀtheꢀ
CPUꢀwillꢀbeꢀswitchedꢀoffꢀbutꢀtheꢀlowꢀspeedꢀoscillatorꢀwillꢀbeꢀturnedꢀonꢀtoꢀdriveꢀsomeꢀperipheralꢀ
functions.
IDLE1 Mode
TheꢀIDLE1ꢀModeꢀisꢀenteredꢀwhenꢀanꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀFHIDENꢀbitꢀinꢀtheꢀ
SCCꢀregisterꢀisꢀhighꢀandꢀtheꢀFSIDENꢀbitꢀinꢀtheꢀSCCꢀregisterꢀisꢀhigh.ꢀInꢀtheꢀIDLE1ꢀModeꢀtheꢀCPUꢀ
willꢀbeꢀswitchedꢀoffꢀbutꢀbothꢀtheꢀhighꢀandꢀlowꢀspeedꢀoscillatorsꢀwillꢀbeꢀturnedꢀonꢀtoꢀprovideꢀaꢀclockꢀ
sourceꢀtoꢀkeepꢀsomeꢀperipheralꢀfunctionsꢀoperational.
IDLE2 Mode
TheꢀIDLE2ꢀModeꢀisꢀenteredꢀwhenꢀanꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀFHIDENꢀbitꢀinꢀtheꢀ
SCCꢀregisterꢀisꢀhighꢀandꢀtheꢀFSIDENꢀbitꢀinꢀtheꢀSCCꢀregisterꢀisꢀlow.ꢀInꢀtheꢀIDLE2ꢀModeꢀtheꢀCPUꢀ
willꢀbeꢀswitchedꢀoffꢀbutꢀtheꢀhighꢀspeedꢀoscillatorꢀwillꢀbeꢀturnedꢀonꢀtoꢀprovideꢀaꢀclockꢀsourceꢀtoꢀkeepꢀ
someꢀperipheralꢀfunctionsꢀoperational.
Control Registers
Theꢀregisters,ꢀSCC,ꢀHIRCC,ꢀHXTCꢀandꢀLXTC,ꢀareꢀusedꢀforꢀtheꢀoverallꢀcontrolꢀofꢀtheꢀsystemꢀclockꢀ
withinꢀtheseꢀdevices.
Bit
Register
Name
7
CKSꢅ
—
6
CKS1
—
5
CKS0
—
4
3
FHS
HIRC1
—
2
1
0
SCC
HIRCC
HXTC
LXTC
—
—
—
—
FSS
HIRC0
HXTM
—
FHIDEN FSIDEN
HIRCF
HXTF
LXTF
HIRCEN
HXTEN
LXTEN
—
—
—
—
—
—
—
System Operating Mode Control Registers List
Rev. 1.10
57
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
SCC Register
Bit
Name
R/W
7
CKSꢅ
R/W
0
6
CKS1
R/W
0
5
CKS0
R/W
0
4
3
2
1
0
—
—
—
FHS
R/W
0
FSS
R/W
0
FHIDEN FSIDEN
R/W
0
R/W
0
POR
Bitꢀ7~5
CKS2~CKS0:ꢀSystemꢀClockꢀSelection
000:ꢀfH
001:ꢀfH/2
010:ꢀfH/4
011:ꢀfH/8
100:ꢀfH/16
101:ꢀfH/32
110:ꢀfH/64
111:ꢀfSUB
Theseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀwhichꢀclockꢀisꢀusedꢀasꢀtheꢀsystemꢀclockꢀsource.ꢀInꢀ
additionꢀtoꢀtheꢀsystemꢀclockꢀsourceꢀdirectlyꢀderivedꢀfromꢀfHꢀorꢀfSUB,ꢀaꢀdividedꢀversionꢀ
ofꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀcanꢀalsoꢀbeꢀchosenꢀasꢀtheꢀsystemꢀclockꢀsource.
Bitꢀ4ꢀ
Bitꢀ3
Unimplemented,ꢀreadꢀasꢀ“0”
FHS:ꢀHighꢀFrequencyꢀClockꢀSelection
0:ꢀHIRC
1:ꢀHXT
Bitꢀ2
Bitꢀ1
FSS:ꢀLowꢀFrequencyꢀClockꢀSelection
0:ꢀLIRC
1:ꢀLXT
FHIDEN:ꢀHighꢀFrequencyꢀOscillatorꢀControlꢀwhenꢀCPUꢀisꢀSwitchedꢀOff
0:ꢀDisable
1:ꢀEnable
Thisꢀbitꢀisꢀusedꢀtoꢀcontrolꢀwhetherꢀtheꢀhighꢀspeedꢀoscillatorꢀisꢀactivatedꢀorꢀstoppedꢀ
whenꢀtheꢀCPUꢀisꢀswitchedꢀoffꢀbyꢀexecutingꢀanꢀ“HALT”ꢀinstruction.
Bitꢀ0
FSIDEN:ꢀLowꢀFrequencyꢀOscillatorꢀControlꢀwhenꢀCPUꢀisꢀSwitchedꢀOff
0:ꢀDisable
1:ꢀEnable
Thisꢀbitꢀisꢀusedꢀtoꢀcontrolꢀwhetherꢀtheꢀlowꢀspeedꢀoscillatorꢀisꢀactivatedꢀorꢀstoppedꢀ
whenꢀtheꢀCPUꢀisꢀswitchedꢀoffꢀbyꢀexecutingꢀanꢀ“HALT”ꢀinstruction.ꢀTheꢀLIRCꢀ
oscillatorꢀisꢀcontrolledꢀbyꢀthisꢀbitꢀtogetherꢀwithꢀtheꢀWDTꢀfunctionꢀenableꢀcontrolꢀwhenꢀ
theꢀLIRCꢀisꢀselectedꢀtoꢀbeꢀtheꢀlowꢀspeedꢀoscillatorꢀclockꢀsourceꢀorꢀtheꢀWDTꢀfunctionꢀ
isꢀenabledꢀrespectively.ꢀIfꢀthisꢀbitꢀisꢀclearedꢀtoꢀ“0”ꢀbutꢀtheꢀWDTꢀfunctionꢀisꢀenabled,ꢀ
theꢀLIRCꢀoscillatorꢀwillꢀalsoꢀbeꢀenabled.
Rev. 1.10
5ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
HIRCC Register
Bit
Name
R/W
7
6
5
4
3
HIRC1
R/W
0
2
HIRC0
R/W
0
1
0
HIRCEN
R/W
1
—
—
—
—
—
—
—
—
—
—
—
—
HIRCF
R
0
POR
Bitꢀ7~4ꢀ
Bitꢀ3~2
Unimplemented,ꢀreadꢀasꢀ“0”
HIRC1~HIRC0:ꢀHIRCꢀFrequencyꢀSelection
00:ꢀ4MHz
01:ꢀ8MHz
10:ꢀ12MHz
11:ꢀ4MHz
WhenꢀtheꢀHIRCꢀoscillatorꢀisꢀenabledꢀorꢀtheꢀHIRCꢀfrequencyꢀselectionꢀisꢀchangedꢀ
byꢀapplicationꢀprogram,ꢀtheꢀclockꢀfrequencyꢀwillꢀautomaticallyꢀbeꢀchangedꢀafterꢀtheꢀ
HIRCFꢀflagꢀisꢀsetꢀtoꢀ“1”.
Bitꢀ1
HIRCF:ꢀHIRCꢀOscillatorꢀStableꢀFlag
0:ꢀHIRCꢀunstable
1:ꢀHIRCꢀstable
ThisꢀbitꢀisꢀusedꢀtoꢀindicateꢀwhetherꢀtheꢀHIRCꢀoscillatorꢀisꢀstableꢀorꢀnot.ꢀWhenꢀtheꢀ
HIRCENꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀtoꢀenableꢀtheꢀHIRCꢀoscillatorꢀorꢀtheꢀHIRCꢀfrequencyꢀ
selectionꢀisꢀchangedꢀbyꢀapplicationꢀprogram,ꢀtheꢀHIRCFꢀbitꢀwillꢀfirstꢀbeꢀclearedꢀtoꢀ“0”ꢀ
andꢀthenꢀsetꢀtoꢀ“1”ꢀafterꢀtheꢀHIRCꢀoscillatorꢀisꢀstable.
Bitꢀ0
HIRCEN:ꢀHIRCꢀOscillatorꢀEnableꢀControl
0:ꢀDisable
1:ꢀEnable
HXTC Register
Bit
Name
R/W
7
6
5
4
3
2
HXTM
R/W
0
1
HXTF
R
0
HXTEN
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
0
Bitꢀ7~3ꢀ
Bitꢀ2
Unimplemented,ꢀreadꢀasꢀ“0”
HXTM:ꢀHXTꢀModeꢀSelection
0:ꢀHXTꢀfrequencyꢀ ꢀ10MHz
≤
1:ꢀHXTꢀfrequencyꢀ 10MHz
>
ThisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀHXTꢀoscillatorꢀoperatingꢀmode.ꢀNoteꢀthatꢀthisꢀbitꢀmustꢀbeꢀ
properlyꢀconfiguredꢀbeforeꢀtheꢀHXTꢀisꢀenabled.ꢀWhenꢀtheꢀHXTENꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀtoꢀ
enableꢀtheꢀHXTꢀoscillator,ꢀitꢀisꢀinvalidꢀtoꢀchangeꢀtheꢀvalueꢀofꢀthisꢀbit.
Bitꢀ1
Bitꢀ0
HXTF:ꢀHXTꢀOscillatorꢀStableꢀFlag
0:ꢀHXTꢀunstable
1:ꢀHXTꢀstable
ThisꢀbitꢀisꢀusedꢀtoꢀindicateꢀwhetherꢀtheꢀHXTꢀoscillatorꢀisꢀstableꢀorꢀnot.ꢀWhenꢀtheꢀ
HXTENꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀtoꢀenableꢀtheꢀHXTꢀoscillator,ꢀtheꢀHXTFꢀbitꢀwillꢀfirstꢀbeꢀ
clearedꢀtoꢀ“0”ꢀandꢀthenꢀsetꢀtoꢀ“1”ꢀafterꢀtheꢀHXTꢀoscillatorꢀisꢀstable.
HXTEN:ꢀHXTꢀOscillatorꢀEnableꢀControl
0:ꢀDisable
1:ꢀEnable
Rev. 1.10
59
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
LXTC Register
Bit
Name
R/W
7
6
5
4
3
2
1
LXTF
R
0
LXTEN
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
0
Bitꢀ7~2ꢀ
Bitꢀ1
Unimplemented,ꢀreadꢀasꢀ“0”
LXTF:ꢀLXTꢀOscillatorꢀStableꢀFlag
0:ꢀLXTꢀunstable
1:ꢀLXTꢀstable
ThisꢀbitꢀisꢀusedꢀtoꢀindicateꢀwhetherꢀtheꢀLXTꢀoscillatorꢀisꢀstableꢀorꢀnot.ꢀWhenꢀtheꢀ
LXTENꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀtoꢀenableꢀtheꢀLXTꢀoscillator,ꢀtheꢀLXTFꢀbitꢀwillꢀfirstꢀbeꢀclearedꢀ
toꢀ“0”ꢀandꢀthenꢀsetꢀtoꢀ“1”ꢀafterꢀtheꢀLXTꢀoscillatorꢀisꢀstable.
Bitꢀ0
LXTEN:ꢀLXTꢀOscillatorꢀEnableꢀControl
0:ꢀDisable
1:ꢀEnable
Operating Mode Switching
Theꢀdeviceꢀcanꢀswitchꢀbetweenꢀoperatingꢀmodesꢀdynamicallyꢀallowingꢀtheꢀuserꢀtoꢀselectꢀtheꢀbestꢀ
performance/powerꢀratioꢀforꢀtheꢀpresentꢀtaskꢀinꢀhand.ꢀInꢀthisꢀwayꢀmicrocontrollerꢀoperationsꢀthatꢀ
doꢀnotꢀrequireꢀhighꢀperformanceꢀcanꢀbeꢀexecutedꢀusingꢀslowerꢀclocksꢀthusꢀrequiringꢀlessꢀoperatingꢀ
currentꢀandꢀprolongingꢀbatteryꢀlifeꢀinꢀportableꢀapplications.
Inꢀsimpleꢀterms,ꢀModeꢀSwitchingꢀbetweenꢀtheꢀFASTꢀModeꢀandꢀSLOWꢀModeꢀisꢀexecutedꢀusingꢀtheꢀ
CKS2~CKS0ꢀbitsꢀinꢀtheꢀSCCꢀregisterꢀwhileꢀModeꢀSwitchingꢀfromꢀtheꢀFAST/SLOWꢀModesꢀtoꢀtheꢀ
SLEEP/IDLEꢀModesꢀisꢀexecutedꢀviaꢀtheꢀHALTꢀinstruction.ꢀWhenꢀanꢀHALTꢀinstructionꢀisꢀexecuted,ꢀ
whetherꢀtheꢀdeviceꢀentersꢀtheꢀIDLEꢀModeꢀorꢀtheꢀSLEEPꢀModeꢀisꢀdeterminedꢀbyꢀtheꢀconditionꢀofꢀtheꢀ
FHIDENꢀandꢀFSIDENꢀbitsꢀinꢀtheꢀSCCꢀregister.
FAST
fSYS=fH~fH/6ꢃ
fH on
SLOW
fSYS=fSUB
fSUB on
CPU ꢁꢀn
fSYS on
CPU ꢁꢀn
fSYS on
fSUB on
fH on/off
SLEEP
HALT instꢁꢀction execꢀted
CPU stop
IDLE0
HALT instꢁꢀction execꢀted
CPU stop
FHIDEN=0
FHIDEN=0
FSIDEN=0
FSIDEN=1
fH off
fH off
fSUB off
fSUB on
IDLE2
IDLE1
HALT instꢁꢀction execꢀted
CPU stop
HALT instꢁꢀction execꢀted
CPU stop
FHIDEN=1
FSIDEN=0
fH on
FHIDEN=1
FSIDEN=1
fH on
fSUB off
fSUB on
Rev. 1.10
60
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
FAST Mode to SLOW Mode Switching
WhenꢀrunningꢀinꢀtheꢀFASTꢀMode,ꢀwhichꢀusesꢀtheꢀhighꢀspeedꢀsystemꢀoscillator,ꢀandꢀthereforeꢀ
consumesꢀmoreꢀpower,ꢀtheꢀsystemꢀclockꢀcanꢀswitchꢀtoꢀrunꢀinꢀtheꢀSLOWꢀModeꢀbyꢀsetꢀtheꢀ
CKS2~CKS0ꢀbitsꢀtoꢀ“111”ꢀinꢀtheꢀSCCꢀregister.ꢀThisꢀwillꢀthenꢀuseꢀtheꢀlowꢀspeedꢀsystemꢀoscillatorꢀ
whichꢀwillꢀconsumeꢀlessꢀpower.ꢀUsersꢀmayꢀdecideꢀtoꢀdoꢀthisꢀforꢀcertainꢀoperationsꢀwhichꢀdoꢀnotꢀ
requireꢀhighꢀperformanceꢀandꢀcanꢀsubsequentlyꢀreduceꢀpowerꢀconsumption.
TheꢀSLOWꢀModeꢀisꢀsourcedꢀfromꢀtheꢀLXTꢀorꢀLIRCꢀoscillatorꢀdeterminedꢀbyꢀtheꢀFSSꢀbitꢀinꢀtheꢀSCCꢀ
registerꢀandꢀthereforeꢀrequiresꢀthisꢀoscillatorꢀtoꢀbeꢀstableꢀbeforeꢀfullꢀmodeꢀswitchingꢀoccurs.
FAST Mode
CKSꢅ~CKS0 = 111
SLOW Mode
FHIDEN=0ꢄ FSIDEN=0
HALT instꢁꢀction is execꢀted
SLEEP Mode
FHIDEN=0ꢄ FSIDEN=1
HALT instꢁꢀction is execꢀted
IDLE0 Mode
FHIDEN=1ꢄ FSIDEN=1
HALT instꢁꢀction is execꢀted
IDLE1 Mode
FHIDEN=1ꢄ FSIDEN=0
HALT instꢁꢀction is execꢀted
IDLE2 Mode
Rev. 1.10
61
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
SLOW Mode to FAST Mode Switching
InꢀSLOWꢀmodeꢀtheꢀsystemꢀclockꢀisꢀderivedꢀfromꢀfSUB.ꢀWhenꢀsystemꢀclockꢀisꢀswitchedꢀbackꢀtoꢀtheꢀ
FASTꢀmodeꢀfromꢀfSUB,ꢀtheꢀCKS2ꢀ~ꢀCKS0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ“000”ꢀ~ꢀ“110”ꢀandꢀthenꢀtheꢀsystemꢀ
clockꢀwillꢀrespectivelyꢀbeꢀswitchedꢀtoꢀfHꢀ~ꢀfH/64.
However,ꢀifꢀfHꢀisꢀnotꢀusedꢀinꢀSLOWꢀmodeꢀandꢀthusꢀswitchedꢀoff,ꢀitꢀwillꢀtakeꢀsomeꢀtimeꢀtoꢀre-
oscillateꢀandꢀstabiliseꢀwhenꢀswitchingꢀtoꢀtheꢀFASTꢀmodeꢀfromꢀtheꢀSLOWꢀMode.ꢀThisꢀisꢀmonitoredꢀ
usingꢀtheꢀHXTFꢀbitꢀinꢀtheꢀHXTCꢀregisterꢀorꢀtheꢀHIRCFꢀbitꢀinꢀtheꢀHIRCCꢀregister.ꢀTheꢀtimeꢀdurationꢀ
requiredꢀforꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀstabilizationꢀisꢀspecifiedꢀinꢀtheꢀtheꢀSystemꢀStartꢀUpꢀTimeꢀ
Characteristics.
SLOW Mode
CKSꢅ~CKS0 = 000~110
FAST Mode
FHIDEN=0ꢄ FSIDEN=0
HALT instꢁꢀction is execꢀted
SLEEP Mode
FHIDEN=0ꢄ FSIDEN=1
HALT instꢁꢀction is execꢀted
IDLE0 Mode
FHIDEN=1ꢄ FSIDEN=1
HALT instꢁꢀction is execꢀted
IDLE1 Mode
FHIDEN=1ꢄ FSIDEN=0
HALT instꢁꢀction is execꢀted
IDLE2 Mode
Entering the SLEEP Mode
ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheseꢀdevicesꢀtoꢀenterꢀtheꢀSLEEPꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ“HALT”ꢀ
instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀbothꢀtheꢀFHIDENꢀandꢀFSIDENꢀbitsꢀinꢀtheꢀSCCꢀregisterꢀ
equalꢀtoꢀ“0”.ꢀInꢀthisꢀmodeꢀallꢀtheꢀclocksꢀandꢀfunctionsꢀwillꢀbeꢀswitchedꢀoffꢀexceptꢀtheꢀWDTꢀfunction.ꢀ
Whenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀdescribedꢀabove,ꢀtheꢀfollowingꢀwillꢀoccur:
•ꢀ Theꢀsystemꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ“HALT”ꢀ
instruction.
•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.
•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.
•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀflagꢀPDFꢀwillꢀbeꢀset,ꢀandꢀWDTꢀtimeoutꢀflagꢀTOꢀwillꢀbeꢀ
cleared.
•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀifꢀtheꢀWDTꢀfunctionꢀisꢀenabled.ꢀIfꢀtheꢀWDTꢀ
functionꢀisꢀdisabled,ꢀtheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀstopped.
Rev. 1.10
6ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Entering the IDLE0 Mode
ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheseꢀdevicesꢀtoꢀenterꢀtheꢀIDLE0ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ“HALT”ꢀ
instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀFHIDENꢀbitꢀinꢀtheꢀSCCꢀregisterꢀequalꢀtoꢀ“0”ꢀandꢀtheꢀ
FSIDENꢀbitꢀinꢀtheꢀSCCꢀregisterꢀequalꢀtoꢀ“1”.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀ
describedꢀabove,ꢀtheꢀfollowingꢀwillꢀoccur:ꢀ
•ꢀ TheꢀfHꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ“HALT”ꢀinstruction,ꢀbutꢀ
theꢀfSUBꢀclockꢀwillꢀbeꢀon.
•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.
•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.
•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀflagꢀPDFꢀwillꢀbeꢀset,ꢀandꢀWDTꢀtimeoutꢀflagꢀTOꢀwillꢀbeꢀ
cleared.
•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀifꢀtheꢀWDTꢀfunctionꢀisꢀenabled.ꢀIfꢀtheꢀWDTꢀ
functionꢀisꢀdisabled,ꢀtheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀstopped.
Entering the IDLE1 Mode
ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheseꢀdevicesꢀtoꢀenterꢀtheꢀIDLE0ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ“HALT”ꢀ
instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀbothꢀtheꢀFHIDENꢀandꢀFSIDENꢀbitsꢀinꢀtheꢀSCCꢀregisterꢀ
equalꢀtoꢀ“1”.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀdescribedꢀabove,ꢀtheꢀfollowingꢀ
willꢀoccur:ꢀ
•ꢀ TheꢀfHꢀandꢀfSUBꢀclocksꢀwillꢀbeꢀonꢀbutꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ“HALT”ꢀinstruction.
•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.
•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.
•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀflagꢀPDFꢀwillꢀbeꢀset,ꢀandꢀWDTꢀtimeoutꢀflagꢀTOꢀwillꢀbeꢀ
cleared.
•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀifꢀtheꢀWDTꢀfunctionꢀisꢀenabled.ꢀIfꢀtheꢀWDTꢀ
functionꢀisꢀdisabled,ꢀtheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀstopped.
Entering the IDLE2 Mode
ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheseꢀdevicesꢀtoꢀenterꢀtheꢀIDLE2ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ“HALT”ꢀ
instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀFHIDENꢀbitꢀinꢀtheꢀSCCꢀregisterꢀequalꢀtoꢀ“1”ꢀandꢀtheꢀ
FSIDENꢀbitꢀinꢀtheꢀSCCꢀregisterꢀequalꢀtoꢀ“0”.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀ
describedꢀabove,ꢀtheꢀfollowingꢀwillꢀoccur:ꢀ
•ꢀ TheꢀfHꢀclockꢀwillꢀbeꢀonꢀbutꢀtheꢀfSUBꢀclockꢀwillꢀbeꢀoffꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ
“HALT”ꢀinstruction.
•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.
•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.
•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀflagꢀPDFꢀwillꢀbeꢀset,ꢀandꢀWDTꢀtimeoutꢀflagꢀTOꢀwillꢀbeꢀ
cleared.
•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀifꢀtheꢀWDTꢀfunctionꢀisꢀenabled.ꢀIfꢀtheꢀWDTꢀ
functionꢀisꢀdisabled,ꢀtheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀstopped.
Rev. 1.10
63
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Standby Current Considerations
AsꢀtheꢀmainꢀreasonꢀforꢀenteringꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀisꢀtoꢀkeepꢀtheꢀcurrentꢀconsumptionꢀofꢀ
theseꢀdevicesꢀtoꢀasꢀlowꢀaꢀvalueꢀasꢀpossible,ꢀperhapsꢀonlyꢀinꢀtheꢀorderꢀofꢀseveralꢀmicro-ampsꢀexceptꢀ
inꢀtheꢀIDLE1ꢀandꢀIDLE2ꢀMode,ꢀthereꢀareꢀotherꢀconsiderationsꢀwhichꢀmustꢀalsoꢀbeꢀtakenꢀintoꢀaccountꢀ
byꢀtheꢀcircuitꢀdesignerꢀifꢀtheꢀpowerꢀconsumptionꢀisꢀtoꢀbeꢀminimised.ꢀSpecialꢀattentionꢀmustꢀbeꢀmadeꢀ
toꢀtheꢀI/Oꢀpinsꢀonꢀtheseꢀdevices.ꢀAllꢀhigh-impedanceꢀinputꢀpinsꢀmustꢀbeꢀconnectedꢀtoꢀeitherꢀaꢀfixedꢀ
highꢀorꢀlowꢀlevelꢀasꢀanyꢀfloatingꢀinputꢀpinsꢀcouldꢀcreateꢀinternalꢀoscillationsꢀandꢀresultꢀinꢀincreasedꢀ
currentꢀconsumption.ꢀThisꢀalsoꢀappliesꢀtoꢀtheꢀdevicesꢀwhichꢀhaveꢀdifferentꢀpackageꢀtypes,ꢀasꢀthereꢀ
mayꢀbeꢀunbonbedꢀpins.ꢀTheseꢀmustꢀeitherꢀbeꢀsetupꢀasꢀoutputsꢀorꢀifꢀsetupꢀasꢀinputsꢀmustꢀhaveꢀpull-
highꢀresistorsꢀconnected.
Careꢀmustꢀalsoꢀbeꢀtakenꢀwithꢀtheꢀloads,ꢀwhichꢀareꢀconnectedꢀtoꢀI/Oꢀpins,ꢀwhichꢀareꢀsetupꢀasꢀoutputs.ꢀ
Theseꢀshouldꢀbeꢀplacedꢀinꢀaꢀconditionꢀinꢀwhichꢀminimumꢀcurrentꢀisꢀdrawnꢀorꢀconnectedꢀonlyꢀtoꢀ
externalꢀcircuitsꢀthatꢀdoꢀnotꢀdrawꢀcurrent,ꢀsuchꢀasꢀotherꢀCMOSꢀinputs.ꢀAlsoꢀnoteꢀthatꢀadditionalꢀ
standbyꢀcurrentꢀwillꢀalsoꢀbeꢀrequiredꢀifꢀtheꢀLXTꢀorꢀLIRCꢀoscillatorꢀhasꢀenabled.
InꢀtheꢀIDLE1ꢀandꢀIDLEꢀ2ꢀModeꢀtheꢀhighꢀspeedꢀoscillatorꢀisꢀon,ꢀifꢀtheꢀperipheralꢀfunctionꢀclockꢀ
sourceꢀisꢀderivedꢀfromꢀtheꢀhighꢀspeedꢀoscillator,ꢀtheꢀadditionalꢀstandbyꢀcurrentꢀwillꢀalsoꢀbeꢀperhapsꢀ
inꢀtheꢀorderꢀofꢀseveralꢀhundredꢀmicro-amps.
Wake-up
ToꢀminimiseꢀpowerꢀconsumptionꢀtheꢀdeviceꢀcanꢀenterꢀtheꢀSLEEPꢀorꢀanyꢀIDLEꢀMode,ꢀwhereꢀtheꢀ
CPUꢀwillꢀbeꢀswitchedꢀoff.ꢀHowever,ꢀwhenꢀtheꢀdeviceꢀisꢀwokenꢀupꢀagain,ꢀitꢀwillꢀtakeꢀaꢀconsiderableꢀ
timeꢀforꢀtheꢀoriginalꢀsystemꢀoscillatorꢀtoꢀrestart,ꢀstabliseꢀandꢀallowꢀnormalꢀoperationꢀtoꢀresume.
AfterꢀtheꢀsystemꢀentersꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀitꢀcanꢀbeꢀwokenꢀupꢀfromꢀoneꢀofꢀvariousꢀsourcesꢀ
listedꢀasꢀfollows:
•ꢀ AnꢀexternalꢀfallingꢀedgeꢀonꢀPortꢀA
•ꢀ Aꢀsystemꢀinterrupt
•ꢀ AꢀWDTꢀoverflow
Whenꢀtheꢀdeviceꢀexecutesꢀtheꢀ“HALT”ꢀinstruction,ꢀtheꢀPDFꢀflagꢀwillꢀbeꢀsetꢀtoꢀ“1”.ꢀTheꢀPDFꢀflagꢀwillꢀ
beꢀclearedꢀtoꢀ“0ꢀifꢀtheꢀdeviceꢀexperiencesꢀaꢀsystemꢀpower-upꢀorꢀexecutesꢀtheꢀclearꢀWatchdogꢀTimerꢀ
instruction.ꢀIfꢀtheꢀsystemꢀisꢀwokenꢀupꢀbyꢀaꢀWDTꢀoverflow,ꢀaꢀWatchdogꢀTimerꢀresetꢀwillꢀbeꢀinitiatedꢀ
andꢀtheꢀTOꢀflagꢀwillꢀbeꢀsetꢀtoꢀ“1”.ꢀTheꢀTOꢀflagꢀisꢀsetꢀifꢀaꢀWDTꢀtime-outꢀoccursꢀandꢀcausesꢀaꢀwake-
upꢀthatꢀonlyꢀresetsꢀtheꢀProgramꢀCounterꢀandꢀStackꢀPointer,ꢀotherꢀflagsꢀremainꢀinꢀtheirꢀoriginalꢀstatus.
EachꢀpinꢀonꢀPortꢀAꢀcanꢀbeꢀsetupꢀusingꢀtheꢀPAWUꢀregisterꢀtoꢀpermitꢀaꢀnegativeꢀtransitionꢀonꢀtheꢀpinꢀ
toꢀwakeꢀupꢀtheꢀsystem.ꢀWhenꢀaꢀPortꢀAꢀpinꢀwake-upꢀoccurs,ꢀtheꢀprogramꢀwillꢀresumeꢀexecutionꢀatꢀ
theꢀinstructionꢀfollowingꢀtheꢀ“HALT”ꢀinstruction.ꢀIfꢀtheꢀsystemꢀisꢀwokenꢀupꢀbyꢀanꢀinterrupt,ꢀthenꢀ
twoꢀpossibleꢀsituationsꢀmayꢀoccur.ꢀTheꢀfirstꢀisꢀwhereꢀtheꢀrelatedꢀinterruptꢀisꢀdisabledꢀorꢀtheꢀinterruptꢀ
isꢀenabledꢀbutꢀtheꢀstackꢀisꢀfull,ꢀinꢀwhichꢀcaseꢀtheꢀprogramꢀwillꢀresumeꢀexecutionꢀatꢀtheꢀinstructionꢀ
followingꢀtheꢀ“HALT”ꢀinstruction.ꢀInꢀthisꢀsituation,ꢀtheꢀinterruptꢀwhichꢀwokeꢀupꢀtheꢀdeviceꢀwillꢀnotꢀ
beꢀimmediatelyꢀserviced,ꢀbutꢀwillꢀratherꢀbeꢀservicedꢀlaterꢀwhenꢀtheꢀrelatedꢀinterruptꢀisꢀfinallyꢀenabledꢀ
orꢀwhenꢀaꢀstackꢀlevelꢀbecomesꢀfree.ꢀTheꢀotherꢀsituationꢀisꢀwhereꢀtheꢀrelatedꢀinterruptꢀisꢀenabledꢀandꢀ
theꢀstackꢀisꢀnotꢀfull,ꢀinꢀwhichꢀcaseꢀtheꢀregularꢀinterruptꢀresponseꢀtakesꢀplace.ꢀIfꢀanꢀinterruptꢀrequestꢀ
flagꢀisꢀsetꢀhighꢀbeforeꢀenteringꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀtheꢀwake-upꢀfunctionꢀofꢀtheꢀrelatedꢀ
interruptꢀwillꢀbeꢀdisabled.
Rev. 1.10
6ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Watchdog Timer
TheꢀWatchdogꢀTimerꢀisꢀprovidedꢀtoꢀpreventꢀprogramꢀmalfunctionsꢀorꢀsequencesꢀfromꢀjumpingꢀtoꢀ
unknownꢀlocations,ꢀdueꢀtoꢀcertainꢀuncontrollableꢀexternalꢀeventsꢀsuchꢀasꢀelectricalꢀnoise.
Watchdog Timer Clock Source
TheꢀWatchdogꢀTimerꢀclockꢀsourceꢀisꢀprovidedꢀbyꢀtheꢀinternalꢀclock,ꢀfLIRC,ꢀwhichꢀisꢀinꢀturnꢀsuppliedꢀ
byꢀtheꢀLIRCꢀoscillator.ꢀTheꢀWatchdogꢀTimerꢀsourceꢀclockꢀisꢀthenꢀsubdividedꢀbyꢀaꢀratioꢀofꢀ28ꢀtoꢀ218ꢀtoꢀ
giveꢀlongerꢀtimeouts,ꢀtheꢀactualꢀvalueꢀbeingꢀchosenꢀusingꢀtheꢀWS2~WS0ꢀbitsꢀinꢀtheꢀWDTCꢀregister.ꢀ
TheꢀLIRCꢀinternalꢀoscillatorꢀhasꢀanꢀapproximateꢀfrequencyꢀofꢀ32kHzꢀandꢀthisꢀspecifiedꢀinternalꢀ
clockꢀperiodꢀcanꢀvaryꢀwithꢀVDD,ꢀtemperatureꢀandꢀprocessꢀvariations.ꢀ
Watchdog Timer Control Register
Aꢀsingleꢀregister,ꢀWDTC,ꢀcontrolsꢀtheꢀrequiredꢀtimeoutꢀperiodꢀasꢀwellꢀasꢀtheꢀenable/disableꢀandꢀresetꢀ
MCUꢀoperation.
WDTC Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
WEꢃ
R/W
0
WE3
R/W
1
WEꢅ
R/W
0
WE1
R/W
1
WE0
R/W
0
WSꢅ
R/W
0
WS1
R/W
1
WS0
R/W
1
POR
Bitꢀ7~3ꢀ
WE4~WE0:ꢀWDTꢀFunctionꢀSoftwareꢀControl
10101:ꢀDisable
01010:ꢀEnable
Others:ꢀResetꢀMCU
Whenꢀtheseꢀbitsꢀareꢀchangedꢀbyꢀtheꢀenvironmentalꢀnoiseꢀorꢀsoftwareꢀsettingꢀtoꢀresetꢀ
theꢀmicrocontroller,ꢀtheꢀresetꢀoperationꢀwillꢀbeꢀactivatedꢀafterꢀꢀaꢀdelayꢀtime,ꢀtSRESET,ꢀandꢀ
theꢀWRFꢀbitꢀinꢀtheꢀRSTFCꢀregisterꢀwillꢀbeꢀsetꢀhigh.
Bitꢀ2~0
WS2~WS0:ꢀWDTꢀTime-outꢀPeriodꢀSelection
000:ꢀ28/fLIRC
001:ꢀ210/fLIRC
010:ꢀ212/fLIRC
011:ꢀ214/fLIRC
100:ꢀ215/fLIRC
101:ꢀ216/fLIRC
110:ꢀ217/fLIRC
111:ꢀ218/fLIRC
Theseꢀthreeꢀbitsꢀdetermineꢀtheꢀdivisionꢀratioꢀofꢀtheꢀwatchdogꢀtimerꢀsourceꢀclock,ꢀ
whichꢀinꢀturnꢀdeterminesꢀtheꢀtime-outꢀperiod.
Rev. 1.10
65
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
RSTFC Register
Bit
Name
R/W
7
6
5
4
3
RSTF
R/W
0
2
LVRF
R/W
x
1
0
WRF
—
—
—
—
—
—
—
—
—
—
—
—
LRF
R/W
0
R/W
POR
0
“x” ꢀnknown
Bitꢀ7~4ꢀ
Bitꢀ3
Unimplemented,ꢀreadꢀasꢀ“0”
RSTF:ꢀResetꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag
0:ꢀNotꢀoccurred
1:ꢀOccurred
Thisꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀbyꢀtheꢀRSTCꢀcontrolꢀregisterꢀsoftwareꢀresetꢀandꢀclearedꢀbyꢀtheꢀ
applicationꢀprogram.ꢀNoteꢀthatꢀthisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ“0”ꢀbyꢀtheꢀapplicationꢀ
program.
Bitꢀ2
Bitꢀ1
Bitꢀ0
LVRF:ꢀLVRꢀFunctionꢀResetꢀFlag
Describedꢀelsewhere.
LRF:ꢀLVRꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag
Describedꢀelsewhere.
WRF:ꢀWDTꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag
0:ꢀNotꢀoccur
1:ꢀOccurred
ThisꢀbitꢀisꢀsetꢀhighꢀbyꢀtheꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀandꢀclearedꢀbyꢀtheꢀ
applicationꢀprogram.ꢀNoteꢀthatꢀthisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀzeroꢀbyꢀtheꢀapplicationꢀ
program.
Watchdog Timer Operation
TheꢀWatchdogꢀTimerꢀoperatesꢀbyꢀprovidingꢀaꢀdeviceꢀresetꢀwhenꢀitsꢀtimerꢀoverflows.ꢀThisꢀmeansꢀ
thatꢀinꢀtheꢀapplicationꢀprogramꢀandꢀduringꢀnormalꢀoperationꢀtheꢀuserꢀhasꢀtoꢀstrategicallyꢀclearꢀtheꢀ
WatchdogꢀTimerꢀbeforeꢀitꢀoverflowsꢀtoꢀpreventꢀtheꢀWatchdogꢀTimerꢀfromꢀexecutingꢀaꢀreset.ꢀThisꢀisꢀ
doneꢀusingꢀtheꢀclearꢀwatchdogꢀinstructions.ꢀIfꢀtheꢀprogramꢀmalfunctionsꢀforꢀwhateverꢀreason,ꢀjumpsꢀ
toꢀanꢀunknownꢀlocation,ꢀorꢀentersꢀanꢀendlessꢀloop,ꢀtheseꢀclearꢀinstructionsꢀwillꢀnotꢀbeꢀexecutedꢀinꢀtheꢀ
correctꢀmanner,ꢀinꢀwhichꢀcaseꢀtheꢀWatchdogꢀTimerꢀwillꢀoverflowꢀandꢀresetꢀtheꢀdevice.ꢀThereꢀareꢀfiveꢀ
bits,ꢀWE4~WE0,ꢀinꢀtheꢀWDTCꢀregisterꢀtoꢀofferꢀtheꢀenable/disableꢀcontrolꢀandꢀresetꢀcontrolꢀofꢀtheꢀ
WatchdogꢀTimer.ꢀTheꢀWDTꢀfunctionꢀwillꢀbeꢀdisabledꢀwhenꢀtheꢀWE4~WE0ꢀbitsꢀareꢀsetꢀtoꢀaꢀvalueꢀofꢀ
10101BꢀwhileꢀtheꢀWDTꢀfunctionꢀwillꢀbeꢀenabledꢀifꢀtheꢀWE4~WE0ꢀbitsꢀareꢀequalꢀtoꢀ01010B.ꢀIfꢀtheꢀ
WE4~WE0ꢀbitsꢀareꢀsetꢀtoꢀanyꢀotherꢀvalues,ꢀotherꢀthanꢀ01010Bꢀandꢀ10101B,ꢀitꢀwillꢀresetꢀtheꢀdeviceꢀ
afterꢀaꢀdelayꢀtime,ꢀtSRESET.ꢀAfterꢀpowerꢀonꢀtheseꢀbitsꢀwillꢀhaveꢀaꢀvalueꢀofꢀ01010B.
WE4~WE0 Bits
10101B
WDT Function
Disable
01010B
Enable
Anꢂ otheꢁ valꢀes
Reset MCU
Watchdog Timer Enable/Disable Control
Underꢀnormalꢀprogramꢀoperation,ꢀaꢀWatchdogꢀTimerꢀtime-outꢀwillꢀinitialiseꢀaꢀdeviceꢀresetꢀandꢀsetꢀ
theꢀstatusꢀbitꢀTO.ꢀHowever,ꢀifꢀtheꢀsystemꢀisꢀinꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀwhenꢀaꢀWatchdogꢀTimerꢀ
time-outꢀoccurs,ꢀtheꢀTOꢀbitꢀinꢀtheꢀstatusꢀregisterꢀwillꢀbeꢀsetꢀandꢀonlyꢀtheꢀProgramꢀCounterꢀandꢀStackꢀ
Pointerꢀwillꢀbeꢀreset.ꢀThreeꢀmethodsꢀcanꢀbeꢀadoptedꢀtoꢀclearꢀtheꢀcontentsꢀofꢀtheꢀWatchdogꢀTimer.ꢀ
TheꢀfirstꢀisꢀaꢀWDTꢀreset,ꢀwhichꢀmeansꢀaꢀcertainꢀvalueꢀexceptꢀ01010Bꢀandꢀ10101Bꢀwrittenꢀintoꢀtheꢀ
WE4~WE0ꢀbitꢀfiled,ꢀtheꢀsecondꢀisꢀusingꢀtheꢀWatchdogꢀTimerꢀsoftwareꢀclearꢀinstructionꢀandꢀtheꢀthirdꢀ
isꢀviaꢀaꢀHALTꢀinstruction.ꢀ
Rev. 1.10
66
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
ThereꢀisꢀonlyꢀoneꢀmethodꢀofꢀusingꢀsoftwareꢀinstructionꢀtoꢀclearꢀtheꢀWatchdogꢀTimer.ꢀThatꢀisꢀtoꢀuseꢀ
theꢀsingleꢀ“CLRꢀWDT”ꢀinstructionꢀtoꢀclearꢀtheꢀWDT.
Theꢀmaximumꢀtimeꢀoutꢀperiodꢀisꢀwhenꢀtheꢀ218ꢀdivisionꢀratioꢀisꢀselected.ꢀAsꢀanꢀexample,ꢀwithꢀaꢀ
32kHzꢀLIRCꢀoscillatorꢀasꢀitsꢀsourceꢀclock,ꢀthisꢀwillꢀgiveꢀaꢀmaximumꢀwatchdogꢀperiodꢀofꢀaroundꢀ8ꢀ
secondsꢀforꢀtheꢀ218ꢀdivisionꢀratio,ꢀandꢀaꢀminimumꢀtimeoutꢀofꢀ8msꢀforꢀtheꢀ28ꢀdivisionꢀration.
WDTC Registeꢁ
WEꢃ~WE0 bits
Reset MCU
CLR
“CLR WDT” Instꢁꢀction
“HALT” Instꢁꢀction
fLIRC
fLIRC/ꢅꢆ
LIRC
ꢆ-stage Divideꢁ
WSꢅ~WS0
WDT Pꢁescaleꢁ
8-to-1 MUX
WDT Time-oꢀt
Watchdog Timer
Reset and Initialisation
Aꢀresetꢀfunctionꢀisꢀaꢀfundamentalꢀpartꢀofꢀanyꢀmicrocontrollerꢀensuringꢀthatꢀtheꢀdeviceꢀcanꢀbeꢀsetꢀtoꢀ
someꢀpredeterminedꢀconditionꢀirrespectiveꢀofꢀoutsideꢀparameters.ꢀTheꢀmostꢀimportantꢀresetꢀconditionꢀ
isꢀafterꢀpowerꢀisꢀfirstꢀappliedꢀtoꢀtheꢀmicrocontroller.ꢀInꢀthisꢀcase,ꢀinternalꢀcircuitryꢀwillꢀensureꢀthatꢀ
theꢀmicrocontroller,ꢀafterꢀaꢀshortꢀdelay,ꢀwillꢀbeꢀinꢀaꢀwell-definedꢀstateꢀandꢀreadyꢀtoꢀexecuteꢀtheꢀfirstꢀ
programꢀinstruction.ꢀAfterꢀthisꢀpower-onꢀreset,ꢀcertainꢀimportantꢀinternalꢀregistersꢀwillꢀbeꢀsetꢀtoꢀ
definedꢀstatesꢀbeforeꢀtheꢀprogramꢀcommences.ꢀOneꢀofꢀtheseꢀregistersꢀisꢀtheꢀProgramꢀCounter,ꢀwhichꢀ
willꢀbeꢀresetꢀtoꢀ“0”ꢀforcingꢀtheꢀmicrocontrollerꢀtoꢀbeginꢀprogramꢀexecutionꢀfromꢀtheꢀlowestꢀProgramꢀ
Memoryꢀaddress.ꢀ
AnotherꢀtypeꢀofꢀresetꢀisꢀwhenꢀtheꢀWatchdogꢀTimerꢀoverflowsꢀandꢀresets.ꢀAllꢀtypesꢀofꢀresetꢀoperationsꢀ
resultꢀinꢀdifferentꢀregisterꢀconditionsꢀbeingꢀsetup.ꢀAnotherꢀresetꢀexistsꢀinꢀtheꢀformꢀofꢀaꢀLowꢀVoltageꢀ
Reset,ꢀLVR,ꢀwhereꢀaꢀfullꢀreset,ꢀisꢀimplementedꢀinꢀsituationsꢀwhereꢀtheꢀpowerꢀsupplyꢀvoltageꢀfallsꢀ
belowꢀaꢀcertainꢀthreshold.ꢀ
Reset Functions
Thereꢀareꢀseveralꢀwaysꢀinꢀwhichꢀaꢀmicrocontrollerꢀresetꢀcanꢀoccur,ꢀthroughꢀeventsꢀoccurringꢀ
internally.
Power-on Reset
Theꢀmostꢀfundamentalꢀandꢀunavoidableꢀresetꢀisꢀtheꢀoneꢀthatꢀoccursꢀafterꢀpowerꢀisꢀfirstꢀappliedꢀtoꢀ
theꢀmicrocontroller.ꢀAsꢀwellꢀasꢀensuringꢀthatꢀtheꢀProgramꢀMemoryꢀbeginsꢀexecutionꢀfromꢀtheꢀfirstꢀ
memoryꢀaddress,ꢀaꢀpower-onꢀresetꢀalsoꢀensuresꢀthatꢀcertainꢀotherꢀregistersꢀareꢀpresetꢀtoꢀknownꢀ
conditions.ꢀAllꢀtheꢀI/Oꢀportꢀandꢀportꢀcontrolꢀregistersꢀwillꢀpowerꢀupꢀinꢀaꢀhighꢀconditionꢀensuringꢀthatꢀ
allꢀI/Oꢀportsꢀwillꢀbeꢀfirstꢀsetꢀtoꢀinputs.
VDD
Poweꢁ-on Reset
tRSTD
SST Time-oꢀt
Power-On Reset Timing Chart
Rev. 1.10
67
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Internal Reset Control
Thereꢀisꢀanꢀinternalꢀresetꢀcontrolꢀregister,ꢀRSTC,ꢀwhichꢀisꢀusedꢀtoꢀprovideꢀaꢀresetꢀwhenꢀtheꢀdeviceꢀ
operatesꢀabnormallyꢀdueꢀtoꢀtheꢀenvironmentalꢀnoiseꢀinterference.ꢀIfꢀtheꢀcontentꢀofꢀtheꢀRSTCꢀregisterꢀ
isꢀsetꢀtoꢀanyꢀvalueꢀotherꢀthanꢀ01010101Bꢀorꢀ10101010B,ꢀitꢀwillꢀresetꢀtheꢀdeviceꢀafterꢀaꢀdelayꢀtime,ꢀ
tSRESET.ꢀAfterꢀpowerꢀonꢀtheꢀregisterꢀwillꢀhaveꢀaꢀvalueꢀofꢀ01010101B.
RSTC7~RSTC0 Bits
01010101B
Reset Function
No opeꢁation
No opeꢁation
Reset MCU
10101010B
Anꢂ otheꢁ valꢀe
Internal Reset Function Control
• RSTC Register
Bit
Name
R/W
7
6
RSTC6
R/W
1
5
RSTC5
R/W
0
4
RSTCꢃ
R/W
1
3
RSTC3
R/W
0
2
RSTCꢅ
R/W
1
1
RSTC1
R/W
0
0
RSTC0
R/W
1
RSTC7
R/W
0
POR
Bitꢀ7~0
RSTC7~RSTC0:ꢀResetꢀFunctionꢀControl
01010101:ꢀNoꢀoperation
10101010:ꢀNoꢀoperation
Otherꢀvalues:ꢀResetꢀMCU
Ifꢀtheseꢀbitsꢀareꢀchangedꢀdueꢀtoꢀadverseꢀenvironmentalꢀconditions,ꢀtheꢀmicrocontrollerꢀ
willꢀbeꢀreset.ꢀTheꢀresetꢀoperationꢀwillꢀbeꢀactivatedꢀafterꢀaꢀdelayꢀtime,ꢀtSRESETꢀandꢀtheꢀ
RSTFꢀbitꢀinꢀtheꢀRSTFCꢀregisterꢀwillꢀbeꢀsetꢀtoꢀ“1”.
• RSTFC Register
Bit
Name
R/W
7
6
5
4
3
RSTF
R/W
0
2
LVRF
R/W
x
1
0
WRF
—
—
—
—
—
—
—
—
—
—
—
—
LRF
R/W
0
R/W
POR
0
“x” ꢀnknown
Bitꢀ7~4ꢀ
Bitꢀ3
Unimplemented,ꢀreadꢀasꢀ“0”
RSTF:ꢀResetꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag
0:ꢀNotꢀoccurred
1:ꢀOccurred
Thisꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀbyꢀtheꢀRSTCꢀcontrolꢀregisterꢀsoftwareꢀresetꢀandꢀclearedꢀbyꢀtheꢀ
applicationꢀprogram.ꢀNoteꢀthatꢀthisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ“0”ꢀbyꢀtheꢀapplicationꢀ
program.
Bitꢀ2
Bitꢀ1
Bitꢀ0
LVRF:ꢀLVRꢀFunctionꢀResetꢀFlag
Describedꢀelsewhere.
LRF:ꢀLVRꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag
Describedꢀelsewhere.
WRF:ꢀWDTꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag
Describedꢀelsewhere.
Rev. 1.10
6ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
In Application Programing Reset
TheꢀdevicesꢀcontainꢀtheꢀIAPꢀfunction.ꢀSoꢀthereꢀexistsꢀanꢀIAPꢀreset,ꢀwhichꢀisꢀcausedꢀbyꢀwritingꢀdataꢀ
55HꢀtoꢀFC1ꢀregister.
Low Voltage Reset – LVR
Theꢀmicrocontrollersꢀcontainꢀaꢀlowꢀvoltageꢀresetꢀcircuitꢀinꢀorderꢀtoꢀmonitorꢀtheꢀsupplyꢀvoltageꢀofꢀtheꢀ
device.ꢀTheꢀLVRꢀfunctionꢀisꢀalwaysꢀenabledꢀwithꢀaꢀspecificꢀLVRꢀvoltageꢀVLVR.ꢀIfꢀtheꢀsupplyꢀvoltageꢀ
ofꢀtheꢀdeviceꢀdropsꢀtoꢀwithinꢀaꢀrangeꢀofꢀ0.9V~VLVRꢀsuchꢀasꢀmightꢀoccurꢀwhenꢀchangingꢀtheꢀbattery,ꢀ
theꢀLVRꢀwillꢀautomaticallyꢀresetꢀtheꢀdeviceꢀinternallyꢀandꢀtheꢀLVRFꢀbitꢀinꢀtheꢀRSTFCꢀregisterꢀwillꢀ
alsoꢀbeꢀsetꢀhigh.ꢀForꢀaꢀvalidꢀLVRꢀsignal,ꢀaꢀlowꢀsupplyꢀvoltage,ꢀi.e.,ꢀaꢀvoltageꢀinꢀtheꢀrangeꢀbetweenꢀ
0.9V~VLVRꢀmustꢀexistꢀforꢀaꢀtimeꢀgreaterꢀthanꢀthatꢀspecifiedꢀbyꢀtLVRꢀinꢀtheꢀLVD/LVRꢀcharacteristics.ꢀIfꢀ
theꢀlowꢀsupplyꢀvoltageꢀstateꢀdoesꢀnotꢀexceedꢀthisꢀvalue,ꢀtheꢀLVRꢀwillꢀignoreꢀtheꢀlowꢀsupplyꢀvoltageꢀ
andꢀwillꢀnotꢀperformꢀaꢀresetꢀfunction.ꢀTheꢀactualꢀVLVRꢀvalueꢀcanꢀbeꢀselectedꢀbyꢀtheꢀLVS7~LVS0ꢀ
bitsꢀinꢀtheꢀLVRCꢀregister.ꢀIfꢀtheꢀLVS7~LVS0ꢀbitsꢀareꢀchangedꢀtoꢀsomeꢀcertainꢀvaluesꢀbyꢀtheꢀ
environmentalꢀnoiseꢀorꢀsoftwareꢀsetting,ꢀtheꢀLVRꢀwillꢀresetꢀtheꢀdeviceꢀafterꢀaꢀdelayꢀtime,ꢀtSRESET.ꢀ
Whenꢀthisꢀhappens,ꢀtheꢀLRFꢀbitꢀinꢀtheꢀRSTFCꢀregisterꢀwillꢀbeꢀsetꢀhigh.ꢀAfterꢀpowerꢀonꢀtheꢀregisterꢀ
willꢀhaveꢀtheꢀvalueꢀofꢀ01010101B.ꢀNoteꢀthatꢀtheꢀLVRꢀfunctionꢀwillꢀbeꢀautomaticallyꢀdisabledꢀwhenꢀ
theꢀdeviceꢀentersꢀtheꢀpowerꢀdownꢀmode.
LVR
tRSTD + tSST
Inteꢁnal Reset
Low Voltage Reset Timing Chart
• LVRC Register
Bit
Name
R/W
7
LVS7
R/W
0
6
LVS6
R/W
1
5
LVS5
R/W
0
4
LVSꢃ
R/W
1
3
LVS3
R/W
0
2
LVSꢅ
R/W
1
1
LVS1
R/W
0
0
LVS0
R/W
1
POR
Bitꢀ7~0ꢀ
LVS7~LVS0:ꢀLVRꢀVoltageꢀSelect
01010101:ꢀ2.1V
00110011:ꢀ2.55V
10011001:ꢀ3.15V
10101010:ꢀ3.8V
Otherꢀvalues:ꢀMCUꢀresetꢀ(registerꢀisꢀresetꢀtoꢀPORꢀvalue)
Whenꢀanꢀactualꢀlowꢀvoltageꢀconditionꢀoccurs,ꢀasꢀspecifiedꢀbyꢀoneꢀofꢀtheꢀfourꢀdefinedꢀ
LVRꢀvoltageꢀvaluesꢀabove,ꢀanꢀMCUꢀresetꢀwillꢀbeꢀgenerated.ꢀTheꢀresetꢀoperationꢀ
willꢀbeꢀactivatedꢀafterꢀtheꢀlowꢀvoltageꢀconditionꢀkeepsꢀmoreꢀthanꢀaꢀtLVRꢀtime.ꢀInꢀthisꢀ
situationꢀtheꢀregisterꢀcontentsꢀwillꢀremainꢀtheꢀsameꢀafterꢀsuchꢀaꢀresetꢀoccurs.
Anyꢀregisterꢀvalue,ꢀotherꢀthanꢀtheꢀfourꢀdefinedꢀLVRꢀvaluesꢀabove,ꢀwillꢀalsoꢀresultꢀinꢀ
theꢀgenerationꢀofꢀanꢀMCUꢀreset.ꢀTheꢀresetꢀoperationꢀwillꢀbeꢀactivatedꢀafterꢀꢀaꢀdelayꢀ
time,ꢀtSRESET.ꢀHoweverꢀinꢀthisꢀsituationꢀtheꢀregisterꢀcontentsꢀwillꢀbeꢀresetꢀtoꢀtheꢀPORꢀ
value.
Rev. 1.10
69
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
• RSTFC Register
Bit
Name
R/W
7
6
5
4
3
RSTF
R/W
0
2
LVRF
R/W
x
1
0
WRF
—
—
—
—
—
—
—
—
—
—
—
—
LRF
R/W
0
R/W
POR
0
“x” ꢀnknown
Bitꢀ7~4ꢀ
Bitꢀ3ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
RSTF:ꢀResetꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag
Describedꢀelsewhere.
Bitꢀ2
LVRF:ꢀLVRꢀFunctionꢀResetꢀFlag
0:ꢀNotꢀoccur
1:ꢀOccurred
ThisꢀbitꢀisꢀsetꢀhighꢀwhenꢀaꢀspecificꢀLowꢀVoltageꢀResetꢀsituationꢀconditionꢀoccurs.ꢀThisꢀ
bitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ“0”ꢀbyꢀtheꢀapplicationꢀprogram.
Bitꢀ1
LRF:ꢀLVRꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag
0:ꢀNotꢀoccur
1:ꢀOccurred
ThisꢀbitꢀisꢀsetꢀhighꢀifꢀtheꢀLVRCꢀregisterꢀcontainsꢀanyꢀnon-definedꢀLVRꢀvoltageꢀregisterꢀ
values.ꢀThisꢀinꢀeffectꢀactsꢀlikeꢀaꢀsoftware-resetꢀfunction.ꢀThisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ
“0”ꢀbyꢀtheꢀapplicationꢀprogram.
Bitꢀ0
WRF:ꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀflag
Describedꢀelsewhere.
Watchdog Time-out Reset during Normal Operation
TheꢀWatchdogꢀtime-outꢀResetꢀduringꢀnormalꢀoperationꢀisꢀtheꢀsameꢀasꢀLVRꢀresetꢀexceptꢀthatꢀtheꢀ
Watchdogꢀtime-outꢀflagꢀTOꢀwillꢀbeꢀsetꢀhigh.
WDT Time-oꢀt
tRSTD + tSST
Inteꢁnal Reset
WDT Time-out Reset during Normal Operation Timing Chart
Watchdog Time-out Reset during SLEEP or IDLE Mode
TheꢀWatchdogꢀtime-outꢀResetꢀduringꢀSLEEPꢀorꢀIDLEꢀModeꢀisꢀaꢀlittleꢀdifferentꢀfromꢀotherꢀkindsꢀ
ofꢀreset.ꢀMostꢀofꢀtheꢀconditionsꢀremainꢀunchangedꢀexceptꢀthatꢀtheꢀProgramꢀCounterꢀandꢀtheꢀStackꢀ
Pointerꢀwillꢀbeꢀclearedꢀtoꢀ“0”ꢀandꢀtheꢀTOꢀflagꢀwillꢀbeꢀsetꢀhigh.ꢀReferꢀtoꢀtheꢀSystemꢀStartꢀUpꢀTimeꢀ
CharacteristicsꢀforꢀtSSTꢀdetails.
WDT Time-oꢀt
tSST
Inteꢁnal Reset
WDT Time-out Reset during SLEEP or IDLE Mode Timing Chart
Rev. 1.10
70
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Reset Initial Conditions
Theꢀdifferentꢀtypesꢀofꢀresetꢀdescribedꢀaffectꢀtheꢀresetꢀflagsꢀinꢀdifferentꢀways.ꢀTheseꢀflags,ꢀknownꢀ
asꢀPDFꢀandꢀTOꢀareꢀlocatedꢀinꢀtheꢀstatusꢀregisterꢀandꢀareꢀcontrolledꢀbyꢀvariousꢀmicrocontrollerꢀ
operations,ꢀsuchꢀasꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀfunctionꢀorꢀWatchdogꢀTimer.ꢀTheꢀresetꢀflagsꢀareꢀ
shownꢀinꢀtheꢀtable:
TO
0
PDF
Reset Conditions
0
ꢀ
ꢀ
1
Poweꢁ-on ꢁeset
ꢀ
LVR ꢁeset dꢀꢁing FAST oꢁ SLOW Mode opeꢁation
1
WDT time-oꢀt ꢁeset dꢀꢁing FAST oꢁ SLOW Mode opeꢁation
WDT time-oꢀt ꢁeset dꢀꢁing IDLE oꢁ SLEEP Mode opeꢁation
1
“ꢀ” stands foꢁ ꢀnchanged
Theꢀfollowingꢀtableꢀindicatesꢀtheꢀwayꢀinꢀwhichꢀtheꢀvariousꢀcomponentsꢀofꢀtheꢀmicrocontrollerꢀareꢀ
affectedꢀafterꢀaꢀpower-onꢀresetꢀoccurs.ꢀ
Item
Pꢁogꢁam Coꢀnteꢁ
Inteꢁꢁꢀpts
Condition after Reset
Reset to zeꢁo
All inteꢁꢁꢀpts will be disabled
WDTꢄ Time Bases
Timeꢁ Modꢀles
Inpꢀt/Oꢀtpꢀt Poꢁts
Stack Pointeꢁ
Cleaꢁ afteꢁ ꢁesetꢄ WDT begins coꢀnting
Timeꢁ Modꢀles will be tꢀꢁned off
I/O poꢁts will be setꢀp as inpꢀts
Stack Pointeꢁ will point to the top of the stack
Theꢀdifferentꢀkindsꢀofꢀresetsꢀallꢀaffectꢀtheꢀinternalꢀregistersꢀofꢀtheꢀmicrocontrollerꢀinꢀdifferentꢀways.ꢀ
Toꢀensureꢀreliableꢀcontinuationꢀofꢀnormalꢀprogramꢀexecutionꢀafterꢀaꢀresetꢀoccurs,ꢀitꢀisꢀimportantꢀtoꢀ
knowꢀwhatꢀconditionꢀtheꢀmicrocontrollerꢀisꢀinꢀafterꢀaꢀparticularꢀresetꢀoccurs.ꢀTheꢀfollowingꢀtableꢀ
describesꢀhowꢀeachꢀtypeꢀofꢀresetꢀaffectsꢀeachꢀofꢀtheꢀmicrocontrollerꢀinternalꢀregisters.
Register
Name
Reset
(Power On)
LVR Reset
(Normal Operation) (Normal Operation)
WDT Time-out
WDT Time-out
(IDLE/SLEEP)
IAR0
●
●
●
●
●
●
●
●
●
●
—
●
—
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
—
●
●
●
●
●
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
x x x x x x x x
0000 0000
x x x x x x x x
x x x x x x x x
- - - x x x x x
- - x x x x x x
x x 0 0 x x x x
- - - - - - - 0
0000 0000
0000 0000
0000 0000
- - - - 0 x 0 0
0 0 0 - 0 0 0 0
- - - - 0 0 0 1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
0000 0000
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - ꢀ ꢀ ꢀ ꢀ ꢀ
- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - - - - - 0
0000 0000
0000 0000
0000 0000
- - - - ꢀ 1 ꢀ ꢀ
0 0 0 - 0 0 0 0
- - - - 0 0 0 1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
0000 0000
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - ꢀ ꢀ ꢀ ꢀ ꢀ
- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
x x 1 ꢀ ꢀ ꢀ ꢀ ꢀ
- - - - - - - 0
0000 0000
0000 0000
0000 0000
- - - - ꢀ ꢀ ꢀ ꢀ
0 0 0 - 0 0 0 0
- - - - 0 0 0 1
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
0000 0000
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - ꢀ ꢀ ꢀ ꢀ ꢀ
- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
ꢀ ꢀ 11 ꢀ ꢀ ꢀ ꢀ
- - - - - - - ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - - ꢀ ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ - ꢀ ꢀ ꢀ ꢀ
- - - - ꢀ ꢀ ꢀ ꢀ
MP0
IAR1
MP1L
MP1H
ACC
PCL
TBLP
TBLH
TBHP
TBHP
STATUS
PBP
IARꢅ
MPꢅL
MPꢅH
RSTFC
SCC
HIRCC
Rev. 1.10
71
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Register
Name
Reset
(Power On)
LVR Reset
(Normal Operation) (Normal Operation)
WDT Time-out
WDT Time-out
(IDLE/SLEEP)
HXTC
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
—
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
—
●
●
●
●
- - - - - 0 0 0
- - - - - - 0 0
1111 1111
1111 1111
0000 0000
0000 0000
0101 0101
0101 0101
- - 0 0 0 0 0 0
0000 0000
0000 0000
- - 0 0 - - 0 0
0 1 0 1 0 0 11
- - - - 0 0 0 0
- 0 0 0 0 0 0 0
- 0 0 0 - 0 0 0
0000 0000
- - - 0 - - - 0
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
0000 0000
- - - - - - 0 0
0 - - - - 0 0 0
0 - - - - 0 0 0
0 0 0 0 1 0 11
0000 00x0
0000 0000
x x x x x x x x
x x x x x x x x
111 - 0 0 0 0
1000 0001
x x x x x x x x
0000 0000
0000 0000
0000 0000
1 1 1 - - - 0 0
- - 0 0 0 0 0 0
x x x x x x x x
- - 0 0 0 0 0 0
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
- - - - - 0 0 0
- - - - - - 0 0
1111 1111
1111 1111
0000 0000
0000 0000
0101 0101
0101 0101
- - 0 0 0 0 0 0
0000 0000
0000 0000
- - 0 0 - - 0 0
0 1 0 1 0 0 11
- - - - 0 0 0 0
- 0 0 0 0 0 0 0
- 0 0 0 - 0 0 0
0000 0000
- - - 0 - - - 0
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
0000 0000
- - - - - - 0 0
0 - - - - 0 0 0
0 - - - - 0 0 0
0 0 0 0 1 0 11
0000 00x0
0000 0000
x x x x x x x x
x x x x x x x x
111 - 0 0 0 0
1000 0001
x x x x x x x x
0000 0000
0000 0000
0000 0000
1 1 1 - - - 0 0
- - 0 0 0 0 0 0
x x x x x x x x
- - 0 0 0 0 0 0
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
- - - - - 0 0 0
- - - - - - 0 0
1111 1111
1111 1111
0000 0000
0000 0000
0101 0101
0101 0101
- - 0 0 0 0 0 0
0000 0000
0000 0000
- - 0 0 - - 0 0
0 1 0 1 0 0 11
- - - - 0 0 0 0
- 0 0 0 0 0 0 0
- 0 0 0 - 0 0 0
0000 0000
- - - 0 - - - 0
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
0000 0000
- - - - - - 0 0
0 - - - - 0 0 0
0 - - - - 0 0 0
0 0 0 0 1 0 11
0000 00x0
0000 0000
x x x x x x x x
x x x x x x x x
111 - 0 0 0 0
1000 0001
x x x x x x x x
0000 0000
0000 0000
0000 0000
1 1 1 - - - 0 0
- - 0 0 0 0 0 0
x x x x x x x x
- - 0 0 0 0 0 0
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
- - - - - ꢀ ꢀ ꢀ
- - - - - - ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - ꢀ ꢀ - - ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - - ꢀ ꢀ ꢀ ꢀ
- ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
- ꢀ ꢀ ꢀ - ꢀ ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - ꢀ - - - ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - - - - ꢀ ꢀ
ꢀ - - - - ꢀ ꢀ ꢀ
ꢀ - - - - ꢀ ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀ ꢀ ꢀ - ꢀ ꢀ ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀ ꢀ ꢀ - - - ꢀ ꢀ
- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀ ꢀ ꢀ ꢀ ꢀ - - -
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
LXTC
PA
PAC
PAPU
PAWU
RSTC
LVRC
LVDC
MFI0
MFI1
MFIꢅ
WDTC
INTEG
INTC0
INTC1
INTCꢅ
INTC3
PB
PBC
PBPU
PC
PCC
PCPU
PSCR
TB0C
TB1C
USR
UCR1
UCRꢅ
TXR_RXR
BRG
SIMC0
SIMC1
SIMD
SIMA
SIMCꢅ
SIMTOC
SPIC0
SPIC1
SPID
EEA
EEA
EED
STMC0
STMC1
Rev. 1.10
7ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Register
Name
Reset
(Power On)
LVR Reset
(Normal Operation) (Normal Operation)
WDT Time-out
WDT Time-out
(IDLE/SLEEP)
STMDL
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
0 0 - - - - - -
- - - 0 0 0 0 0
0 0 1 0 0 0 - 0
0 0 0 0 0 0 0 -
0 - - - - 0 0 0
- 0 0 0 0 0 0 0
- 0 0 0 0 0 0 -
0000 0000
x x x x x x x x
x x x x x x x x
x x x x x x x x
0000 0000
- - - - 0 0 0 0
0 0 0 - - - - -
0 0 0 0 - - - -
- - 0 0 0 0 0 0
- - - 0 0 0 0 0
0 - - - 0 0 0 0
0000 0000
- 0 0 0 0 0 0 0
- 0 0 0 0 0 0 -
- - 0 0 0 0 0 0
0 - - 0 - - 0 0
- - - - 1 1 1 1
- - - - 1 1 1 1
- - - - 0 0 0 0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 - - - - - -
- - - 0 0 0 0 0
0 0 1 0 0 0 - 0
0 0 0 0 0 0 0 -
0 - - - - 0 0 0
- 0 0 0 0 0 0 0
- 0 0 0 0 0 0 -
0000 0000
x x x x x x x x
x x x x x x x x
x x x x x x x x
0000 0000
- - - - 0 0 0 0
0 0 0 - - - - -
0 0 0 0 - - - -
- - 0 0 0 0 0 0
- - - 0 0 0 0 0
0 - - - 0 0 0 0
0000 0000
- 0 0 0 0 0 0 0
- 0 0 0 0 0 0 -
- - 0 0 0 0 0 0
0 - - 0 - - 0 0
- - - - 1 1 1 1
- - - - 1 1 1 1
- - - - 0 0 0 0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 - - - - - -
- - - 0 0 0 0 0
0 0 1 0 0 0 - 0
0 0 0 0 0 0 0 -
0 - - - - 0 0 0
- 0 0 0 0 0 0 0
- 0 0 0 0 0 0 -
0000 0000
x x x x x x x x
x x x x x x x x
x x x x x x x x
0000 0000
- - - - 0 0 0 0
0 0 0 - - - - -
0 0 0 0 - - - -
- - 0 0 0 0 0 0
- - - 0 0 0 0 0
0 - - - 0 0 0 0
0000 0000
- 0 0 0 0 0 0 0
- 0 0 0 0 0 0 -
- - 0 0 0 0 0 0
0 - - 0 - - 0 0
- - - - 1 1 1 1
- - - - 1 1 1 1
- - - - 0 0 0 0
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀ ꢀ ꢀ ꢀ ꢀ - - -
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - - - - ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - - - - ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - - - - ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀ ꢀ - - - - - -
- - - ꢀ ꢀ ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ - ꢀ
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ -
ꢀ - - - - ꢀ ꢀ ꢀ
- ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
- ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ -
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - - ꢀ ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ - - - - -
ꢀ ꢀ ꢀ ꢀ - - - -
- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
- - - ꢀ ꢀ ꢀ ꢀ ꢀ
ꢀ - - - ꢀ ꢀ ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
- ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ -
- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
ꢀ - - ꢀ - - ꢀ ꢀ
- - - - ꢀ ꢀ ꢀ ꢀ
- - - - ꢀ ꢀ ꢀ ꢀ
- - - - ꢀ ꢀ ꢀ ꢀ
STMDH
STMAL
STMAH
STMRP
PTM0C0
PTM0C1
PTM0DL
PTM0DH
PTM0AL
PTM0AH
PTM0RPL
PTM0RPH
MDUWR0
MDUWR1
MDUWRꢅ
MDUWR3
MDUWRꢃ
MDUWR5
MDUWCTRL
ADCS
ADCR0
ADCR1
PWRC
PGAC0
PGAC1
PGACS
ADRL
ADRM
ADRH
DSDAH
DSDAL
DSDACC
SGC
SGN
SGDNR
OPAC
SWC0
SWC1
SWCꢅ
DACO
FTRC
PD
PDC
PDPU
Rev. 1.10
73
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Register
Name
Reset
(Power On)
LVR Reset
(Normal Operation) (Normal Operation)
WDT Time-out
WDT Time-out
(IDLE/SLEEP)
PTM1C0
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
—
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
—
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
0 0 0 0 0 - - -
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0 0 0 0 0 - - -
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
- - - - 0 0 0 0
0000 0000
0000 0000
- - - - - - - 0
0000 0000
- - - 0 0 0 0 0
- - 0 0 0 0 0 0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 - - 0 - - 0
- 0 0 0 - - 0 0
0000 0000
0000 0000
0000 0000
0 0 0 0 - - - -
- - 0 0 - - 0 0
- - - - 0 0 0 0
0000 0000
- - 0 0 0 0 0 0
0 0 0 0 0 - - -
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0 0 0 0 0 - - -
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
- - - - 0 0 0 0
0000 0000
0000 0000
- - - - - - - 0
0000 0000
- - - 0 0 0 0 0
- - 0 0 0 0 0 0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 - - 0 - - 0
- 0 0 0 - - 0 0
0000 0000
0000 0000
0000 0000
0 0 0 0 - - - -
- - 0 0 - - 0 0
- - - - 0 0 0 0
0000 0000
- - 0 0 0 0 0 0
0 0 0 0 0 - - -
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0 0 0 0 0 - - -
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
- - - - 0 0 0 0
0000 0000
0000 0000
- - - - - - - 0
0000 0000
- - - 0 0 0 0 0
- - 0 0 0 0 0 0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 - - 0 - - 0
- 0 0 0 - - 0 0
0000 0000
0000 0000
0000 0000
0 0 0 0 - - - -
- - 0 0 - - 0 0
- - - - 0 0 0 0
0000 0000
- - 0 0 0 0 0 0
ꢀ ꢀ ꢀ ꢀ ꢀ - - -
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - - - - ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - - - - ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - - - - ꢀ ꢀ
ꢀ ꢀ ꢀ ꢀ ꢀ - - -
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - - - - ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - - - - ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - - - - ꢀ ꢀ
- - - - ꢀ ꢀ ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - - - - - ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - - ꢀ ꢀ ꢀ ꢀ ꢀ
- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀ ꢀ - - ꢀ - - ꢀ
- ꢀ ꢀ ꢀ - - ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀ ꢀ ꢀ ꢀ - - - -
- - ꢀ ꢀ - - ꢀ ꢀ
- - - - ꢀ ꢀ ꢀ ꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
PTM1C1
PTM1DL
PTM1DH
PTM1AL
PTM1AH
PTM1RPL
PTM1RPH
PTMꢅC0
PTMꢅC1
PTMꢅDL
PTMꢅDH
PTMꢅAL
PTMꢅAH
PTMꢅRPL
PTMꢅRPH
EEC
FC0
FC1
FCꢅ
FARL
FARH
FARH
FD0L
FD0H
FD1L
FD1H
FDꢅL
FDꢅH
FD3L
FD3H
IFS0
IFS1
PAS0
PAS1
PBS0
PDS0
PCS0
PCS1
SLEDC0
SLEDC1
Note:ꢀ“u”ꢀstandsꢀforꢀunchanged
“x”ꢀstandsꢀforꢀunknown
“-”ꢀstandsꢀforꢀunimplemented
Rev. 1.10
7ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Input/Output Ports
TheꢀmicrocontrollersꢀofferꢀconsiderableꢀflexibilityꢀonꢀtheirꢀI/Oꢀports.ꢀWithꢀtheꢀinputꢀorꢀoutputꢀ
designationꢀofꢀeveryꢀpinꢀfullyꢀunderꢀuserꢀprogramꢀcontrol,ꢀpull-highꢀselectionsꢀforꢀallꢀportsꢀandꢀ
wake-upꢀselectionsꢀonꢀcertainꢀpins,ꢀtheꢀuserꢀisꢀprovidedꢀwithꢀanꢀI/Oꢀstructureꢀtoꢀmeetꢀtheꢀneedsꢀofꢀaꢀ
wideꢀrangeꢀofꢀapplicationꢀpossibilities.ꢀ
Theseꢀdevicesꢀprovideꢀbidirectionalꢀinput/outputꢀlinesꢀlabeledꢀwithꢀportꢀnamesꢀPA~PD.ꢀTheseꢀI/Oꢀ
portsꢀareꢀmappedꢀtoꢀtheꢀRAMꢀDataꢀMemoryꢀwithꢀspecificꢀaddressesꢀasꢀshownꢀinꢀtheꢀSpecialꢀPurposeꢀ
DataꢀMemoryꢀtable.ꢀAllꢀofꢀtheseꢀI/Oꢀportsꢀcanꢀbeꢀusedꢀforꢀinputꢀandꢀoutputꢀoperations.ꢀForꢀinputꢀ
operation,ꢀtheseꢀportsꢀareꢀnon-latching,ꢀwhichꢀmeansꢀtheꢀinputsꢀmustꢀbeꢀreadyꢀatꢀtheꢀT2ꢀrisingꢀedgeꢀ
ofꢀinstructionꢀ“MOVꢀA,ꢀ[m]”,ꢀwhereꢀmꢀdenotesꢀtheꢀportꢀaddress.ꢀForꢀoutputꢀoperation,ꢀallꢀtheꢀdataꢀisꢀ
latchedꢀandꢀremainsꢀunchangedꢀuntilꢀtheꢀoutputꢀlatchꢀisꢀrewritten.
Bit
Register
Name
7
6
5
4
3
2
1
0
PA
PA7
PA6
PA5
PAꢃ
PA3
PAꢅ
PA1
PA0
PAC
PAC7
PAPU7
PAWU7
PB7
PAC5
PAPUꢃ
PAWU6
PB6
PAC5
PAPU5
PAWU5
PB5
PACꢃ
PAPUꢃ
PAWUꢃ
PBꢃ
PAC3
PAPU3
PAWU3
PB3
PACꢅ
PAPUꢅ
PAWUꢅ
PBꢅ
PAC1
PAPU1
PAWU1
PB1
PAC0
PAPU0
PAWU0
PB0
PAPU
PAWU
PB
PBC
PBPU
PC
PBC7
PBPU7
PC7
PBC6
PBPU6
PC6
PBC5
PBPU5
PC5
PBCꢃ
PBPUꢃ
PCꢃ
PBC3
PBPU3
PC3
PBCꢅ
PBPUꢅ
PCꢅ
PBC1
PBPU1
PC1
PBC0
PBPU0
PC0
PCC
PCPU
PD
PCC7
PCPU7
—
PCC6
PCPU6
—
PCC5
PCPU5
—
PCCꢃ
PCPUꢃ
—
PCC3
PCPU3
PD3
PCCꢅ
PCPUꢅ
PDꢅ
PCC1
PCPU1
PD1
PCC0
PCPU0
PD0
PDC
PDPU
—
—
—
—
PDC3
PDPU3
PDCꢅ
PDPUꢅ
PDC1
PDPU1
PDC0
PDPU0
—
—
—
—
“—” ꢀnimplemented
I/O Logic Function Registers List
Pull-high Resistors
Manyꢀproductꢀapplicationsꢀrequireꢀpull-highꢀresistorsꢀforꢀtheirꢀswitchꢀinputsꢀusuallyꢀrequiringꢀtheꢀ
useꢀofꢀanꢀexternalꢀresistor.ꢀToꢀeliminateꢀtheꢀneedꢀforꢀtheseꢀexternalꢀresistors,ꢀallꢀI/Oꢀpins,ꢀwhenꢀ
configuredꢀasꢀanꢀinputꢀhaveꢀtheꢀcapabilityꢀofꢀbeingꢀconnectedꢀtoꢀanꢀinternalꢀpull-highꢀresistor.ꢀTheseꢀ
pull-highꢀresistorsꢀareꢀselectedꢀusingꢀregistersꢀPAPU~PDPU,ꢀandꢀareꢀimplementedꢀusingꢀweakꢀ
PMOSꢀtransistors.
Noteꢀthatꢀtheꢀpull-highꢀresistorꢀcanꢀbeꢀcontrolledꢀbyꢀtheꢀrelevantꢀpull-highꢀcontrolꢀregisterꢀonlyꢀwhenꢀ
theꢀpin-sharedꢀfunctionalꢀpinꢀisꢀselectedꢀasꢀaꢀdigitalꢀinputꢀorꢀNMOSꢀoutput.ꢀOtherwise,ꢀtheꢀpull-highꢀ
resistorsꢀcannotꢀbeꢀenabled.
PxPU Register
Bit
7
PxPU7
R/W
0
6
PxPUꢃ
R/W
0
5
PxPU5
R/W
0
4
PxPUꢃ
R/W
0
3
PxPU3
R/W
0
2
PxPUꢅ
R/W
0
1
PxPU1
R/W
0
0
PxPU0
R/W
0
Name
R/W
POR
PxPUn: I/OꢀPortꢀxꢀPinꢀPull-highꢀFunctionꢀControl
0:ꢀDisable
1:ꢀEnable
TheꢀPxPUnꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀpinꢀpull-highꢀfunction.ꢀHereꢀtheꢀ“x”ꢀcanꢀbeꢀA,ꢀB,ꢀCꢀandꢀ
D.ꢀHowever,ꢀtheꢀactualꢀavailableꢀbitsꢀforꢀeachꢀI/Oꢀportꢀmayꢀbeꢀdifferent.
Rev. 1.10
75
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Port A Wake-up
TheꢀHALTꢀinstructionꢀforcesꢀtheꢀmicrocontrollerꢀintoꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀwhichꢀpreservesꢀ
power,ꢀaꢀfeatureꢀthatꢀisꢀimportantꢀforꢀbatteryꢀandꢀotherꢀlow-powerꢀapplications.ꢀVariousꢀmethodsꢀ
existꢀtoꢀwake-upꢀtheꢀmicrocontroller,ꢀoneꢀofꢀwhichꢀisꢀtoꢀchangeꢀtheꢀlogicꢀconditionꢀonꢀoneꢀofꢀtheꢀPortꢀ
Aꢀpinsꢀfromꢀhighꢀtoꢀlow.ꢀThisꢀfunctionꢀisꢀespeciallyꢀsuitableꢀforꢀapplicationsꢀthatꢀcanꢀbeꢀwokenꢀupꢀ
viaꢀexternalꢀswitches.ꢀEachꢀpinꢀonꢀPortꢀAꢀcanꢀbeꢀselectedꢀindividuallyꢀtoꢀhaveꢀthisꢀwake-upꢀfeatureꢀ
usingꢀtheꢀPAWUꢀregister.
Noteꢀthatꢀtheꢀwake-upꢀfunctionꢀcanꢀbeꢀcontrolledꢀbyꢀtheꢀwake-upꢀcontrolꢀregistersꢀonlyꢀwhenꢀtheꢀ
pin-sharedꢀfunctionalꢀpinꢀisꢀselectedꢀasꢀgeneralꢀpurposeꢀinput/outputꢀandꢀtheꢀMCUꢀentersꢀtheꢀPowerꢀ
downꢀmode.
PAWU Register
Bit
7
PAWU7
R/W
0
6
PAWU6
R/W
0
5
PAWU5
R/W
0
4
PAWUꢃ
R/W
0
3
PAWU3
R/W
0
2
PAWUꢅ
R/W
0
1
PAWU1
R/W
0
0
PAWU0
R/W
0
Name
R/W
POR
PAWUn:ꢀPortꢀAꢀPinꢀWake-upꢀControl
0:ꢀDisable
1:ꢀEnable
I/O Port Control Registers
EachꢀI/OꢀportꢀhasꢀitsꢀownꢀcontrolꢀregisterꢀknownꢀasꢀPAC~PDC,ꢀtoꢀcontrolꢀtheꢀinput/outputꢀ
configuration.ꢀWithꢀthisꢀcontrolꢀregister,ꢀeachꢀCMOSꢀoutputꢀorꢀinputꢀcanꢀbeꢀreconfiguredꢀ
dynamicallyꢀunderꢀsoftwareꢀcontrol.ꢀEachꢀpinꢀofꢀtheꢀI/Oꢀportsꢀisꢀdirectlyꢀmappedꢀtoꢀaꢀbitꢀinꢀitsꢀ
associatedꢀportꢀcontrolꢀregister.ꢀForꢀtheꢀI/Oꢀpinꢀtoꢀfunctionꢀasꢀanꢀinput,ꢀtheꢀcorrespondingꢀbitꢀofꢀtheꢀ
controlꢀregisterꢀmustꢀbeꢀwrittenꢀasꢀaꢀ“1”.ꢀThisꢀwillꢀthenꢀallowꢀtheꢀlogicꢀstateꢀofꢀtheꢀinputꢀpinꢀtoꢀbeꢀ
directlyꢀreadꢀbyꢀinstructions.ꢀWhenꢀtheꢀcorrespondingꢀbitꢀofꢀtheꢀcontrolꢀregisterꢀisꢀwrittenꢀasꢀaꢀ“0”,ꢀ
theꢀI/OꢀpinꢀwillꢀbeꢀsetupꢀasꢀaꢀCMOSꢀoutput.ꢀIfꢀtheꢀpinꢀisꢀcurrentlyꢀsetupꢀasꢀanꢀoutput,ꢀinstructionsꢀ
canꢀstillꢀbeꢀusedꢀtoꢀreadꢀtheꢀoutputꢀregister.ꢀHowever,ꢀitꢀshouldꢀbeꢀnotedꢀthatꢀtheꢀprogramꢀwillꢀinꢀfactꢀ
onlyꢀreadꢀtheꢀstatusꢀofꢀtheꢀoutputꢀdataꢀlatchꢀandꢀnotꢀtheꢀactualꢀlogicꢀstatusꢀofꢀtheꢀoutputꢀpin.
PxC Register
Bit
7
PxC7
R/W
1
6
PxC5
R/W
1
5
PxC5
R/W
1
4
PxCꢃ
R/W
1
3
PxC3
R/W
1
2
PxCꢅ
R/W
1
1
PxC1
R/W
1
0
PxC0
R/W
1
Name
R/W
POR
PxCn:ꢀI/OꢀPortꢀxꢀPinꢀTypeꢀSelection
0:ꢀOutput
1:ꢀInput
TheꢀPxCnꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀpinꢀtypeꢀselection.ꢀHereꢀtheꢀ“x”ꢀcanꢀbeꢀA,ꢀB,ꢀCꢀandꢀD.ꢀ
However,ꢀtheꢀactualꢀavailableꢀbitsꢀforꢀeachꢀI/Oꢀportꢀmayꢀbeꢀdifferent.
Rev. 1.10
76
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
I/O Port Source Current Control
TheꢀdevicesꢀsupportꢀdifferentꢀsourceꢀcurrentꢀdrivingꢀcapabilityꢀforꢀeachꢀI/Oꢀport.ꢀWithꢀtheꢀ
correspondingꢀselectionꢀregisters,ꢀSLEDC0ꢀandꢀSLEDC1,ꢀeachꢀI/Oꢀportꢀcanꢀsupportꢀfourꢀlevelsꢀofꢀ
theꢀsourceꢀcurrentꢀdrivingꢀcapability.ꢀUsersꢀshouldꢀreferꢀtoꢀtheꢀInput/OutputꢀCharacteristicsꢀsectionꢀ
toꢀselectꢀtheꢀdesiredꢀsourceꢀcurrentꢀforꢀdifferentꢀapplications.
SLEDC0 Register
Bit
7
6
5
4
3
2
1
0
Name SLEDC07 SLEDC06 SLEDC05 SLEDC0ꢃ SLEDC03 SLEDC0ꢅ SLEDC01 SLEDC00
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~6
Bitꢀ5~4
Bitꢀ3~2
Bitꢀ1~0
SLEDC07~SLEDC06:ꢀPB7~PB4ꢀSourceꢀCurrentꢀSelection
00:ꢀSourceꢀcurrent=Levelꢀ0ꢀ(min.)
01:ꢀSourceꢀcurrent=Levelꢀ1
10:ꢀSourceꢀcurrent=Levelꢀ2
11:ꢀSourceꢀcurrent=Levelꢀ3ꢀ(max.)
SLEDC05~SLEDC04:ꢀPB3~PB0ꢀSourceꢀCurrentꢀSelection
00:ꢀSourceꢀcurrent=Levelꢀ0ꢀ(min.)
01:ꢀSourceꢀcurrent=Levelꢀ1
10:ꢀSourceꢀcurrent=Levelꢀ2
11:ꢀSourceꢀcurrent=Levelꢀ3ꢀ(max.)
SLEDC03~SLEDC02:ꢀPA7~PA4ꢀSourceꢀCurrentꢀSelection
00:ꢀSourceꢀcurrent=Levelꢀ0ꢀ(min.)
01:ꢀSourceꢀcurrent=Levelꢀ1
10:ꢀSourceꢀcurrent=Levelꢀ2
11:ꢀSourceꢀcurrent=Levelꢀ3ꢀ(max.)
SLEDC01~SLEDC00:ꢀPA3~PA0ꢀSourceꢀCurrentꢀSelection
00:ꢀSourceꢀcurrent=Levelꢀ0ꢀ(min.)
01:ꢀSourceꢀcurrent=Levelꢀ1
10:ꢀSourceꢀcurrent=Levelꢀ2
11:ꢀSourceꢀcurrent=Levelꢀ3ꢀ(max.)
SLEDC1 Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
—
—
—
—
—
—
SLEDC15 SLEDC1ꢃ SLEDC13 SLEDC1ꢅ SLEDC11 SLEDC10
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~4
Unimplemented,ꢀreadꢀasꢀ“0”
SLEDC15~SLEDC14:ꢀPD3~PD0ꢀSourceꢀCurrentꢀSelection
00:ꢀSourceꢀcurrent=Levelꢀ0ꢀ(min.)
01:ꢀSourceꢀcurrent=Levelꢀ1
10:ꢀSourceꢀcurrent=Levelꢀ2
11:ꢀSourceꢀcurrent=Levelꢀ3ꢀ(max.)
Bitꢀ3~2
Bitꢀ1~0
SLEDC13~SLEDC12:ꢀPC7~PC4ꢀSourceꢀCurrentꢀSelection
00:ꢀSourceꢀcurrent=Levelꢀ0ꢀ(min.)
01:ꢀSourceꢀcurrent=Levelꢀ1
10:ꢀSourceꢀcurrent=Levelꢀ2
11:ꢀSourceꢀcurrent=Levelꢀ3ꢀ(max.)
SLEDC11~SLEDC10:ꢀPC3~PC0ꢀSourceꢀCurrentꢀSelection
00:ꢀSourceꢀcurrent=Levelꢀ0ꢀ(min.)
01:ꢀSourceꢀcurrent=Levelꢀ1
10:ꢀSourceꢀcurrent=Levelꢀ2
11:ꢀSourceꢀcurrent=Levelꢀ3ꢀ(max.)
Rev. 1.10
77
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Pin-shared Functions
Theꢀflexibilityꢀofꢀtheꢀmicrocontrollerꢀrangeꢀisꢀgreatlyꢀenhancedꢀbyꢀtheꢀuseꢀofꢀpinsꢀthatꢀhaveꢀmoreꢀ
thanꢀoneꢀfunction.ꢀLimitedꢀnumbersꢀofꢀpinsꢀcanꢀforceꢀseriousꢀdesignꢀconstraintsꢀonꢀdesignersꢀbutꢀbyꢀ
supplyingꢀpinsꢀwithꢀmulti-functions,ꢀmanyꢀofꢀtheseꢀdifficultiesꢀcanꢀbeꢀovercome.ꢀForꢀtheseꢀpins,ꢀtheꢀ
desiredꢀfunctionꢀofꢀtheꢀmulti-functionꢀI/Oꢀpinsꢀisꢀselectedꢀbyꢀaꢀseriesꢀofꢀregistersꢀviaꢀtheꢀapplicationꢀ
programꢀcontrol.
Pin-shared Function Selection Registers
Theꢀlimitedꢀnumberꢀofꢀsuppliedꢀpinsꢀinꢀaꢀpackageꢀcanꢀimposeꢀrestrictionsꢀonꢀtheꢀamountꢀofꢀfunctionsꢀ
aꢀcertainꢀdeviceꢀcanꢀcontain.ꢀHoweverꢀbyꢀallowingꢀtheꢀsameꢀpinsꢀtoꢀshareꢀseveralꢀdifferentꢀfunctionsꢀ
andꢀprovidingꢀaꢀmeansꢀofꢀfunctionꢀselection,ꢀaꢀwideꢀrangeꢀofꢀdifferentꢀfunctionsꢀcanꢀbeꢀincorporatedꢀ
intoꢀevenꢀrelativelyꢀsmallꢀpackageꢀsizes.ꢀTheꢀdevicesꢀincludeꢀPortꢀ“x”ꢀoutputꢀfunctionꢀSelectionꢀ
registerꢀ“n”,ꢀlabeledꢀasꢀPxSn,ꢀandꢀInputꢀFunctionꢀSelectionꢀregisterꢀ“n”,ꢀlabeledꢀasꢀIFSn,ꢀwhichꢀcanꢀ
selectꢀtheꢀdesiredꢀfunctionsꢀofꢀtheꢀmulti-functionꢀpin-sharedꢀpins.
Whenꢀtheꢀpin-sharedꢀinputꢀfunctionꢀisꢀselectedꢀtoꢀbeꢀused,ꢀtheꢀcorrespondingꢀinputꢀandꢀoutputꢀ
functionsꢀselectionꢀshouldꢀbeꢀproperlyꢀmanaged.ꢀForꢀexample,ꢀifꢀtheꢀI2CꢀSDAꢀlineꢀisꢀused,ꢀtheꢀ
correspondingꢀoutputꢀpin-sharedꢀfunctionꢀshouldꢀbeꢀconfiguredꢀasꢀtheꢀSDI/SDAꢀfunctionꢀbyꢀ
configuringꢀtheꢀPxSnꢀregisterꢀandꢀtheꢀSDAꢀsignalꢀintputꢀshouldꢀbeꢀproperlyꢀselectedꢀusingꢀtheꢀ
IFSnꢀregister.ꢀHowever,ꢀifꢀtheꢀexternalꢀinterruptꢀfunctionꢀisꢀselectedꢀtoꢀbeꢀused,ꢀtheꢀrelevantꢀoutputꢀ
pin-sharedꢀfunctionꢀshouldꢀbeꢀselectedꢀasꢀanꢀI/Oꢀfunctionꢀandꢀtheꢀinterruptꢀinputꢀsignalꢀshouldꢀbeꢀ
selected.
Theꢀmostꢀimportantꢀpointꢀtoꢀnoteꢀisꢀtoꢀmakeꢀsureꢀthatꢀtheꢀdesiredꢀpin-sharedꢀfunctionꢀisꢀproperlyꢀ
selectedꢀandꢀalsoꢀdeselected.ꢀForꢀmostꢀpin-sharedꢀfunctions,ꢀtoꢀselectꢀtheꢀdesiredꢀpin-sharedꢀfunction,ꢀ
theꢀpin-sharedꢀfunctionꢀshouldꢀfirstꢀbeꢀcorrectlyꢀselectedꢀusingꢀtheꢀcorrespondingꢀpin-sharedꢀcontrolꢀ
register.ꢀAfterꢀthatꢀtheꢀcorrespondingꢀperipheralꢀfunctionalꢀsettingꢀshouldꢀbeꢀconfiguredꢀandꢀthenꢀtheꢀ
peripheralꢀfunctionꢀcanꢀbeꢀenabled.ꢀHowever,ꢀaꢀspecialꢀpointꢀmustꢀbeꢀnotedꢀforꢀsomeꢀdigitalꢀinputꢀ
pins,ꢀsuchꢀasꢀINTn,ꢀxTCKn,ꢀxTPnI,ꢀetc,ꢀwhichꢀshareꢀtheꢀsameꢀpin-sharedꢀcontrolꢀconfigurationꢀwithꢀ
theirꢀcorrespondingꢀgeneralꢀpurposeꢀI/Oꢀfunctionsꢀwhenꢀsettingꢀtheꢀrelevantꢀpin-sharedꢀcontrolꢀbitꢀ
fields.ꢀToꢀselectꢀtheseꢀpinꢀfunctions,ꢀinꢀadditionꢀtoꢀtheꢀnecessaryꢀpin-sharedꢀcontrolꢀandꢀperipheralꢀ
functionalꢀsetupꢀaforementioned,ꢀtheyꢀmustꢀalsoꢀbeꢀsetupꢀasꢀanꢀinputꢀbyꢀsettingꢀtheꢀcorrespondingꢀbitꢀ
inꢀtheꢀI/Oꢀportꢀcontrolꢀregister.ꢀToꢀcorrectlyꢀdeselectꢀtheꢀpin-sharedꢀfunction,ꢀtheꢀperipheralꢀfunctionꢀ
shouldꢀfirstꢀbeꢀdisabledꢀandꢀthenꢀtheꢀcorrespondingꢀpin-sharedꢀfunctionꢀcontrolꢀregisterꢀcanꢀbeꢀ
modifiedꢀtoꢀselectꢀotherꢀpin-sharedꢀfunctions.
Bit
Register
Name
7
6
5
4
3
PTCKꢅPS
—
2
1
—
0
IFS0
IFS1
PTPꢅIPS PTP1IPS
—
—
—
—
STCKPS
RXPS0
—
SCSAPS SDIAPS SCKAPS
RXPS1
PAS0
PAS1
PBS0
PCS0
PCS1
PDS0
PAS07
PAS17
PBS07
—
PAS06
PAS16
PBS06
—
PAS05
PAS15
PBS05
PCS05
—
PAS0ꢃ
PAS1ꢃ
PBS0ꢃ
PCS0ꢃ
—
PAS03
PAS13
PBS03
—
PAS0ꢅ
PAS1ꢅ
PBS0ꢅ
—
PAS01
PAS11
PBS01
PCS01
PCS11
—
PAS00
PAS10
PBS00
PCS00
PCS10
—
—
—
PCS13
—
PCS1ꢅ
—
PDS07
PDS06
PDS05
PDS0ꢃ
Pin-shared Function Selection Registers List
Rev. 1.10
7ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
• PAS0 Register
Bit
Name
R/W
7
PAS07
R/W
0
6
PAS06
R/W
0
5
PAS05
R/W
0
4
PAS0ꢃ
R/W
0
3
PAS03
R/W
0
2
PAS0ꢅ
R/W
0
1
PAS01
R/W
0
0
PAS00
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~4
Bitꢀ3~2
Bitꢀ1~0
PAS07~PAS06:ꢀPA3ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPA3/PTP1I
01:ꢀPTP1
10:ꢀSDOA
11:ꢀOSC2
PAS05~PAS04:ꢀPA2ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPA2/PTCK0
01:ꢀPA2/PTCK0
10:ꢀPA2/PTCK0
11:ꢀXT2
PAS03~PAS02:ꢀPA1ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPA1/INT0/STCK
01:ꢀPA1/INT0/STCK
10:ꢀLVDIN
11:ꢀPTP0B
PAS01~PAS00:ꢀPA0ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPA0/PTP0I
01:ꢀPA0/PTP0I
10:ꢀPTP0
11:ꢀXT1
• PAS1 Register
Bit
Name
R/W
7
6
PAS16
R/W
0
5
PAS15
R/W
0
4
PAS1ꢃ
R/W
0
3
PAS13
R/W
0
2
PAS1ꢅ
R/W
0
1
PAS11
R/W
0
0
PAS10
R/W
0
PAS17
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~4
Bitꢀ3~2
Bitꢀ1~0
PAS17~PAS16:ꢀPA7ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPA7/PTCK2
01:ꢀPA7/PTCK2
10:ꢀPA7/PTCK2
11:ꢀSDI/SDA
PAS15~PAS14:ꢀPA6ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPA6/STCK
01:ꢀSDIA
10:ꢀPA6/STCK
11:ꢀRX
PAS13~PAS12:ꢀPA5ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPA5/STPI
01:ꢀSTP
10:ꢀSCKA
11:ꢀTX
PAS11~PAS10:ꢀPA4ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPA4/PTP2I
01:ꢀPTP2
10:ꢀSCSA
11:ꢀOSC1
Rev. 1.10
79
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
• PBS0 Register
Bit
Name
R/W
7
PBS07
R/W
0
6
PBS06
R/W
0
5
PBS05
R/W
0
4
PBS0ꢃ
R/W
0
3
PBS03
R/W
0
2
PBS0ꢅ
R/W
0
1
PBS01
R/W
0
0
PBS00
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~4
Bitꢀ3~2
Bitꢀ1~0
PBS07~PBS06:ꢀPB3ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPB3
01:ꢀRX
10:ꢀSDIA
11:ꢀSDO
PBS05~PBS04:ꢀPB2ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPB2
01:ꢀPB2
10:ꢀSCS
11:ꢀSCKA
PBS03~PBS02:ꢀPB1ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPB1/INT1
01:ꢀPB1/INT1
10:ꢀSTPB
11:ꢀPB1/INT1
PBS01~PBS00:ꢀPB0ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPB0
01:ꢀPB0
10:ꢀSCK/SCL
11:ꢀPB0
• PCS0 Register
Bit
Name
R/W
7
6
5
PCS05
R/W
0
4
PCS0ꢃ
R/W
0
3
2
1
PCS01
R/W
0
0
PCS00
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~6ꢀ
Bitꢀ5~4
Unimplemented,ꢀreadꢀasꢀ“0”
PCS05~PCS04:ꢀPC2ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPC2/PTP2I
01:ꢀPTP2
10:ꢀPC2/PTP2I
11:ꢀPC2/PTP2I
Bitꢀ3~2ꢀ
Bitꢀ1~0
Unimplemented,ꢀreadꢀasꢀ“0”
PCS01~PCS00:ꢀPC0ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPC0/PTP1I
01:ꢀPC0/PTP1I
10:ꢀPTP1
11:ꢀPC0/PTP1I
Rev. 1.10
ꢆ0
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
• PCS1 Register
Bit
Name
R/W
7
6
5
4
3
PCS13
R/W
0
2
PCS1ꢅ
R/W
0
1
PCS11
R/W
0
0
PCS10
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~4ꢀ
Bitꢀ3~2ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
PCS13~PCS12:ꢀPC5ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPC5
01:ꢀPC5
10:ꢀTX
11:ꢀSDOA
Bitꢀ1~0
PCS11~PCS10:ꢀPC4ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPC4
01:ꢀPC4
10:ꢀPC4
11:ꢀSCSA
• PDS0 Register
Bit
Name
R/W
7
PDS07
R/W
0
6
PDS06
R/W
0
5
PDS05
R/W
0
4
PDS0ꢃ
R/W
0
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~6ꢀ
PDS07~PDS06:ꢀPD3ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPD3
01:ꢀPD3
10:ꢀTX
11:ꢀPD3
Bitꢀ5~4
PDS05~PDS04:ꢀPD2ꢀPin-SharedꢀFunctionꢀSelection
00:ꢀPD2
01:ꢀPD2
10:ꢀRX
11:ꢀPD2
Bitꢀ3~0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
• IFS0 Register
Bit
7
6
5
4
3
PTCKꢅPS
R/W
2
1
0
STCKPS
R/W
Name
R/W
PTPꢅIPS PTP1IPS
—
—
—
—
—
—
—
—
—
—
—
—
R/W
0
R/W
0
POR
0
0
Bitꢀ7ꢀ
PTP2IPS:ꢀPTP2IꢀInputꢀSourceꢀPinꢀSelectionꢀ
0:ꢀPTP2IꢀonꢀPA4ꢀ
1:ꢀPTP2IꢀonꢀPC2
Bitꢀ6
PTP1IPS:ꢀPTP1IꢀInputꢀSourceꢀPinꢀSelection
0:ꢀPTP1IꢀonꢀPA3
1:ꢀPTP1IꢀonꢀPC0
Bitꢀ5~4ꢀ
Bitꢀ3
Unimplemented,ꢀreadꢀasꢀ“0”
PTCK2PS:ꢀPTCK2ꢀInputꢀSourceꢀPinꢀSelection
0:ꢀPTCK2ꢀonꢀPC3
1:ꢀPTCK2ꢀonꢀPA7
Bitꢀ2~1ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Rev. 1.10
ꢆ1
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ0
STCKPS:ꢀSTCKꢀInputꢀSourceꢀPinꢀSelection
0:ꢀSTCKꢀonꢀPA1
1:ꢀSTCKꢀonꢀPA6
• IFS1 Register
Bit
7
6
SCSAPS
R/W
5
SDIAPS
R/W
0
4
SCKAPS
R/W
3
2
1
RXPS1
R/W
0
0
RXPS0
R/W
0
Name
R/W
—
—
—
—
—
—
—
—
—
POR
0
0
Bitꢀ7ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ6
Bitꢀ5
Bitꢀ4
SCSAPS:ꢀSCSAꢀInputꢀSourceꢀPinꢀSelection
0:ꢀSCSAꢀonꢀPA4
1:ꢀSCSAꢀonꢀPC4
SDIAPS:ꢀSDIAꢀInputꢀSourceꢀPinꢀSelection
0:ꢀSDIAꢀonꢀPA6ꢀ
1:ꢀSDIAꢀonꢀPB3
SCKAPS:ꢀSCKAꢀInputꢀSourceꢀPinꢀSelection
0:ꢀSCKAꢀonꢀPA5ꢀ
1:ꢀSCKAꢀonꢀPB2
Bitꢀ3~2ꢀ
Bitꢀ1~0
Unimplemented,ꢀreadꢀasꢀ“0”
RXPS1~RXPS0:ꢀRXꢀInputꢀSourceꢀPinꢀSelection
00:ꢀRXꢀonꢀPA6
01:ꢀRXꢀonꢀPB3
10:ꢀRXꢀonꢀPD2
11:ꢀRXꢀonꢀPD2
I/O Pin Structures
TheꢀaccompanyingꢀdiagramꢀillustratesꢀtheꢀinternalꢀstructuresꢀofꢀtheꢀI/Oꢀlogicꢀfunction.ꢀAsꢀtheꢀexactꢀ
logicalꢀconstructionꢀofꢀtheꢀI/Oꢀpinꢀwillꢀdifferꢀfromꢀthisꢀdiagram,ꢀitꢀisꢀsuppliedꢀasꢀaꢀguideꢀonlyꢀtoꢀ
assistꢀwithꢀtheꢀfunctionalꢀunderstandingꢀofꢀtheꢀlogicꢀfunctionꢀI/Oꢀpins.ꢀTheꢀwideꢀrangeꢀofꢀpin-sharedꢀ
structuresꢀdoesꢀnotꢀpermitꢀallꢀtypesꢀtoꢀbeꢀshown.
VDD
Pꢀll-high
Registeꢁ
Select
Weak
Pꢀll-ꢀp
Contꢁol Bit
Data Bꢀs
D
Q
Wꢁite Contꢁol Registeꢁ
Chip Reset
CK
Q
S
I/O pin
Read Contꢁol Registeꢁ
Data Bit
D
Q
Wꢁite Data Registeꢁ
CK
Q
S
M
U
X
Read Data Registeꢁ
Sꢂstem Wake-ꢀp
PA onlꢂ
wake-ꢀp Select
Logic Function Input/Output Structure
Rev. 1.10
ꢆꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Programming Considerations
Withinꢀtheꢀuserꢀprogram,ꢀoneꢀofꢀtheꢀthingsꢀfirstꢀtoꢀconsiderꢀisꢀportꢀinitialisation.ꢀAfterꢀaꢀreset,ꢀallꢀ
ofꢀtheꢀI/Oꢀdataꢀandꢀportꢀcontrolꢀregistersꢀwillꢀbeꢀsetꢀtoꢀhigh.ꢀThisꢀmeansꢀthatꢀallꢀI/Oꢀpinsꢀwillꢀbeꢀ
defaultedꢀtoꢀanꢀinputꢀstate,ꢀtheꢀlevelꢀofꢀwhichꢀdependsꢀonꢀtheꢀotherꢀconnectedꢀcircuitryꢀandꢀwhetherꢀ
pull-highꢀselectionsꢀhaveꢀbeenꢀchosen.ꢀIfꢀtheꢀportꢀcontrolꢀregistersꢀareꢀthenꢀprogrammedꢀtoꢀsetupꢀ
someꢀpinsꢀasꢀoutputs,ꢀtheseꢀoutputꢀpinsꢀwillꢀhaveꢀanꢀinitialꢀhighꢀoutputꢀvalueꢀunlessꢀtheꢀassociatedꢀ
portꢀdataꢀregistersꢀareꢀfirstꢀprogrammed.ꢀSelectingꢀwhichꢀpinsꢀareꢀinputsꢀandꢀwhichꢀareꢀoutputsꢀcanꢀ
beꢀachievedꢀbyte-wideꢀbyꢀloadingꢀtheꢀcorrectꢀvaluesꢀintoꢀtheꢀappropriateꢀportꢀcontrolꢀregisterꢀorꢀ
byꢀprogrammingꢀindividualꢀbitsꢀinꢀtheꢀportꢀcontrolꢀregisterꢀusingꢀtheꢀ“SETꢀ[m].i”ꢀandꢀ“CLRꢀ[m].i”ꢀ
instructions.ꢀNoteꢀthatꢀwhenꢀusingꢀtheseꢀbitꢀcontrolꢀinstructions,ꢀaꢀread-modify-writeꢀoperationꢀtakesꢀ
place.ꢀTheꢀmicrocontrollerꢀmustꢀfirstꢀreadꢀinꢀtheꢀdataꢀonꢀtheꢀentireꢀport,ꢀmodifyꢀitꢀtoꢀtheꢀrequiredꢀnewꢀ
bitꢀvaluesꢀandꢀthenꢀrewriteꢀthisꢀdataꢀbackꢀtoꢀtheꢀoutputꢀports.ꢀ
PortꢀAꢀhasꢀtheꢀadditionalꢀcapabilityꢀofꢀprovidingꢀwake-upꢀfunctions.ꢀWhenꢀtheꢀdeviceꢀisꢀinꢀtheꢀ
SLEEPꢀorꢀIDLEꢀMode,ꢀvariousꢀmethodsꢀareꢀavailableꢀtoꢀwakeꢀtheꢀdeviceꢀup.ꢀOneꢀofꢀtheseꢀisꢀaꢀhighꢀ
toꢀlowꢀtransitionꢀofꢀanyꢀofꢀtheꢀPortꢀAꢀpins.ꢀSingleꢀorꢀmultipleꢀpinsꢀonꢀPortꢀAꢀcanꢀbeꢀsetupꢀtoꢀhaveꢀthisꢀ
function.
Timer Modules – TM
Oneꢀofꢀtheꢀmostꢀfundamentalꢀfunctionsꢀinꢀanyꢀmicrocontrollerꢀdevicesꢀisꢀtheꢀabilityꢀtoꢀcontrolꢀandꢀ
measureꢀtime.ꢀToꢀimplementꢀtimeꢀrelatedꢀfunctionsꢀeachꢀdeviceꢀincludesꢀseveralꢀTimerꢀModules,ꢀ
generallyꢀabbreviatedꢀtoꢀtheꢀnameꢀTM.ꢀTheꢀTMsꢀareꢀmulti-purposeꢀtimingꢀunitsꢀandꢀserveꢀtoꢀprovideꢀ
operationsꢀsuchꢀasꢀTimer/Counter,ꢀInputꢀCapture,ꢀCompareꢀMatchꢀOutputꢀandꢀSingleꢀPulseꢀOutputꢀ
asꢀwellꢀasꢀbeingꢀtheꢀfunctionalꢀunitꢀforꢀtheꢀgenerationꢀofꢀPWMꢀsignals.ꢀEachꢀofꢀtheꢀTMsꢀhasꢀtwoꢀ
interrupts.ꢀTheꢀadditionꢀofꢀinputꢀandꢀoutputꢀpinsꢀforꢀeachꢀTMꢀensuresꢀthatꢀusersꢀareꢀprovidedꢀwithꢀ
timingꢀunitsꢀwithꢀaꢀwideꢀandꢀflexibleꢀrangeꢀofꢀfeatures.
TheꢀcommonꢀfeaturesꢀofꢀtheꢀdifferentꢀTMꢀtypesꢀareꢀdescribedꢀhereꢀwithꢀmoreꢀdetailedꢀinformationꢀ
providedꢀinꢀtheꢀindividualꢀStandardꢀandꢀPeriodicꢀTMꢀsections.
Introduction
EachꢀdeviceꢀcontainsꢀfourꢀTMsꢀandꢀeachꢀindividualꢀTMꢀcanꢀbeꢀcategorisedꢀasꢀaꢀcertainꢀtype,ꢀnamelyꢀ
StandardꢀTypeꢀTMꢀorꢀPeriodicꢀTypeꢀTM.ꢀAlthoughꢀsimilarꢀinꢀnature,ꢀtheꢀdifferentꢀTMꢀtypesꢀvaryꢀ
inꢀtheirꢀfeatureꢀcomplexity.ꢀTheꢀcommonꢀfeaturesꢀtoꢀallꢀofꢀtheꢀStandardꢀandꢀPeriodicꢀTypeꢀTMsꢀ
willꢀbeꢀdescribedꢀinꢀthisꢀsectionꢀandꢀtheꢀdetailedꢀoperationꢀregardingꢀeachꢀofꢀtheꢀTMꢀtypesꢀwillꢀbeꢀ
describedꢀinꢀseparateꢀsections.ꢀTheꢀmainꢀfeaturesꢀandꢀdifferencesꢀbetweenꢀtheꢀthreeꢀtypesꢀofꢀTMsꢀareꢀ
summarisedꢀinꢀtheꢀaccompanyingꢀtable.
TM Function
Timeꢁ/Coꢀnteꢁ
STM
PTM
√
√
Inpꢀt Captꢀꢁe
√
√
Compaꢁe Match Oꢀtpꢀt
PWM Channels
√
√
1
1
Single Pꢀlse Oꢀtpꢀt
PWM Alignment
1
1
Edge
Edge
PWM Adjꢀstment Peꢁiod & Dꢀtꢂ
Dꢀtꢂ oꢁ Peꢁiod
Dꢀtꢂ oꢁ Peꢁiod
TM Function Summary
Rev. 1.10
ꢆ3
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Device
STM
PTM
10-bit PTM0
10-bit PTM1
10-bit PTMꢅ
BH66Fꢅ650
16-bit STM
BH66Fꢅ660
TM Name/Type Reference
TM Operation
TheꢀdifferentꢀtypesꢀofꢀTMꢀofferꢀaꢀdiverseꢀrangeꢀofꢀfunctions,ꢀfromꢀsimpleꢀtimingꢀoperationsꢀtoꢀPWMꢀ
signalꢀgeneration.ꢀTheꢀkeyꢀtoꢀunderstandingꢀhowꢀtheꢀTMꢀoperatesꢀisꢀtoꢀseeꢀitꢀinꢀtermsꢀofꢀaꢀfreeꢀ
runningꢀcount-upꢀcounterꢀwhoseꢀvalueꢀisꢀthenꢀcomparedꢀwithꢀtheꢀvalueꢀofꢀpre-programmedꢀinternalꢀ
comparators.ꢀWhenꢀtheꢀfreeꢀrunningꢀcount-upꢀcounterꢀhasꢀtheꢀsameꢀvalueꢀasꢀtheꢀpre-programmedꢀ
comparator,ꢀknownꢀasꢀaꢀcompareꢀmatchꢀsituation,ꢀaꢀTMꢀinterruptꢀsignalꢀwillꢀbeꢀgeneratedꢀwhichꢀ
canꢀclearꢀtheꢀcounterꢀandꢀperhapsꢀalsoꢀchangeꢀtheꢀconditionꢀofꢀtheꢀTMꢀoutputꢀpin.ꢀTheꢀinternalꢀTMꢀ
counterꢀisꢀdrivenꢀbyꢀaꢀuserꢀselectableꢀclockꢀsource,ꢀwhichꢀcanꢀbeꢀanꢀinternalꢀclockꢀorꢀanꢀexternalꢀpin.
TM Clock Source
TheꢀclockꢀsourceꢀwhichꢀdrivesꢀtheꢀmainꢀcounterꢀinꢀeachꢀTMꢀcanꢀoriginateꢀfromꢀvariousꢀsources.ꢀ
TheꢀselectionꢀofꢀtheꢀrequiredꢀclockꢀsourceꢀisꢀimplementedꢀusingꢀtheꢀSTCK2~STCK0ꢀandꢀ
PTnCK2~PTnCK0ꢀbitsꢀinꢀtheꢀSTMꢀandꢀPTMnꢀcontrolꢀregisters,ꢀwhereꢀ“n”ꢀstandsꢀforꢀtheꢀspecificꢀ
TMꢀserialꢀnumber.ꢀTheꢀclockꢀsourceꢀcanꢀbeꢀaꢀratioꢀofꢀtheꢀsystemꢀclock,ꢀfSYS,ꢀorꢀtheꢀinternalꢀhighꢀ
clock,ꢀfH,ꢀtheꢀfSUBꢀclockꢀsourceꢀorꢀtheꢀexternalꢀSTCKꢀandꢀPTCKnꢀpin.ꢀTheꢀSTCKꢀandꢀPTCKnꢀpinꢀ
clockꢀsourceꢀisꢀusedꢀtoꢀallowꢀanꢀexternalꢀsignalꢀtoꢀdriveꢀtheꢀTMꢀasꢀanꢀexternalꢀclockꢀsourceꢀforꢀeventꢀ
counting.
TM Interrupts
TheꢀStandardꢀorꢀPeriodicꢀtypeꢀTMꢀhasꢀtwoꢀinternalꢀinterrupt,ꢀoneꢀforꢀeachꢀofꢀtheꢀinternalꢀcomparatorꢀ
AꢀorꢀcomparatorꢀP,ꢀwhichꢀgenerateꢀaꢀTMꢀinterruptꢀwhenꢀaꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀWhenꢀaꢀ
TMꢀinterruptꢀisꢀgenerated,ꢀitꢀcanꢀbeꢀusedꢀtoꢀclearꢀtheꢀcounterꢀandꢀalsoꢀtoꢀchangeꢀtheꢀstateꢀofꢀtheꢀTMꢀ
outputꢀpin.
TM External Pins
EachꢀofꢀtheꢀTMs,ꢀirrespectiveꢀofꢀwhatꢀtype,ꢀhasꢀtwoꢀTMꢀinputꢀpins,ꢀwithꢀtheꢀlabelꢀSTCK,ꢀPTCKnꢀ
andꢀSTPI,ꢀPTPnIꢀrespectively.ꢀTheꢀSTM,ꢀPTMnꢀinputꢀpin,ꢀSTCK,ꢀPTCKn,ꢀisꢀessentiallyꢀaꢀclockꢀ
sourceꢀforꢀtheꢀSTM,ꢀPTMnꢀandꢀisꢀselectedꢀusingꢀtheꢀSTCK2~STCK0ꢀorꢀPTnCK2~PTnCK0ꢀbitsꢀ
inꢀtheꢀSTMC0ꢀorꢀPTMnC0ꢀregister.ꢀThisꢀexternalꢀTMꢀinputꢀpinꢀallowsꢀanꢀexternalꢀclockꢀsourceꢀtoꢀ
driveꢀtheꢀinternalꢀTM.ꢀTheꢀSTCK,ꢀPTCKnꢀinputꢀpinꢀcanꢀbeꢀchosenꢀtoꢀhaveꢀeitherꢀaꢀrisingꢀorꢀfallingꢀ
activeꢀedge.ꢀTheꢀSTCKꢀandꢀPTCKnꢀpinsꢀareꢀalsoꢀusedꢀasꢀtheꢀexternalꢀtriggerꢀinputꢀpinꢀinꢀsingleꢀ
pulseꢀoutputꢀmodeꢀforꢀtheꢀSTMꢀandꢀPTMnꢀrespectively.
TheꢀotherꢀSTM,ꢀPTMnꢀinputꢀpin,ꢀSTPI,ꢀPTPnI,ꢀisꢀtheꢀcaptureꢀinputꢀwhoseꢀactiveꢀedgeꢀcanꢀbeꢀaꢀrisingꢀ
edge,ꢀaꢀfallingꢀedgeꢀorꢀbothꢀrisingꢀandꢀfallingꢀedgesꢀandꢀtheꢀactiveꢀedgeꢀtransitionꢀtypeꢀisꢀselectedꢀ
usingꢀtheꢀSTIO1~STIO0,ꢀPTnIO1~PTnIO0ꢀbitsꢀinꢀtheꢀSTMC1,ꢀPTMnC1ꢀregisterꢀrespectively.ꢀThereꢀ
isꢀanotherꢀcaptureꢀinput,ꢀPTCKn,ꢀforꢀPTMnꢀcaptureꢀinputꢀmode,ꢀwhichꢀcanꢀbeꢀusedꢀasꢀtheꢀexternalꢀ
triggerꢀinputꢀsourceꢀexceptꢀtheꢀPTPnIꢀpin.
TheꢀTMsꢀeachꢀhaveꢀoneꢀorꢀmoreꢀoutputꢀpins.ꢀTheꢀSTPB,ꢀPTP0BꢀisꢀtheꢀinvertedꢀsignalꢀofꢀtheꢀSTP,ꢀ
PTP0ꢀoutput.ꢀTheꢀTMꢀoutputꢀpinsꢀcanꢀbeꢀselectedꢀusingꢀtheꢀcorrespondingꢀpin-sharedꢀfunctionꢀ
selectionꢀbitsꢀdescribedꢀinꢀtheꢀPin-sharedꢀFunctionꢀsection.ꢀWhenꢀtheꢀTMꢀisꢀinꢀtheꢀCompareꢀMatchꢀ
OutputꢀMode,ꢀtheseꢀpinsꢀcanꢀbeꢀcontrolledꢀbyꢀtheꢀTMꢀtoꢀswitchꢀtoꢀaꢀhighꢀorꢀlowꢀlevelꢀorꢀtoꢀtoggleꢀ
whenꢀaꢀcompareꢀmatchꢀsituationꢀoccurs.ꢀTheꢀexternalꢀSTP,ꢀPTPnꢀorꢀSTPB,ꢀPTP0Bꢀoutputꢀpinꢀisꢀalsoꢀ
Rev. 1.10
ꢆꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
theꢀpinꢀwhereꢀtheꢀTMꢀgeneratesꢀtheꢀPWMꢀoutputꢀwaveform.ꢀAsꢀtheꢀTMꢀoutputꢀpinsꢀareꢀpin-sharedꢀ
withꢀotherꢀfunctions,ꢀtheꢀTMꢀoutputꢀfunctionꢀmustꢀfirstꢀbeꢀsetupꢀusingꢀrelevantꢀpin-sharedꢀfunctionꢀ
selectionꢀregister.
STM
PTMn
Input
Output
Input
Output
PTCK0ꢄ PTP0Iꢄ
PTCK1ꢄ PTP1I
PTCKꢅꢄ PTPꢅI
PTP0Bꢄ PTP0ꢄ
PTP1ꢄ PTPꢅ
STCKꢄ STPI
STPꢄ STPB
TM External Pins
TM Input/Output Pin Selection
SelectingꢀtoꢀhaveꢀaꢀTMꢀinput/outputꢀorꢀwhetherꢀtoꢀretainꢀitsꢀotherꢀsharedꢀfunctionꢀisꢀimplementedꢀ
usingꢀtheꢀrelevantꢀpin-sharedꢀfunctionꢀselectionꢀregisters,ꢀwithꢀtheꢀcorrespondingꢀselectionꢀbitsꢀinꢀ
eachꢀpin-sharedꢀfunctionꢀregisterꢀcorrespondingꢀtoꢀaꢀTMꢀinput/outputꢀpin.ꢀConfiguringꢀtheꢀselectionꢀ
bitsꢀcorrectlyꢀwillꢀsetupꢀtheꢀcorrespondingꢀpinꢀasꢀaꢀTMꢀinput/output.ꢀTheꢀdetailsꢀofꢀtheꢀpin-sharedꢀ
functionꢀselectionꢀareꢀdescribedꢀinꢀtheꢀpin-sharedꢀfunctionꢀsection.
STCK
CCR captꢀꢁe inpꢀt
STPI
STM
CCR oꢀtpꢀt
STP
STPB
STM Function Pin Control Block Diagram
PTCKn
CCR captꢀꢁe inpꢀt
PTPnI
PTMn
CCR oꢀtpꢀt
PTPn
PTPnB
PTM Function Pin Control Block Diagram – n=0
PTCKn
CCR captꢀꢁe inpꢀt
PTPnI
PTMn
CCR oꢀtpꢀt
PTPn
PTM Function Pin Control Block Diagram – n=1 or 2
Rev. 1.10
ꢆ5
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Programming Considerations
TheꢀTMꢀCounterꢀRegistersꢀandꢀtheꢀCapture/CompareꢀCCRAꢀandꢀCCRPꢀregisters,ꢀallꢀhaveꢀaꢀlowꢀ
andꢀhighꢀbyteꢀstructure.ꢀTheꢀhighꢀbytesꢀcanꢀbeꢀdirectlyꢀaccessed,ꢀbutꢀasꢀtheꢀlowꢀbytesꢀcanꢀonlyꢀbeꢀ
accessedꢀviaꢀanꢀinternalꢀ8-bitꢀbuffer,ꢀreadingꢀorꢀwritingꢀtoꢀtheseꢀregisterꢀpairsꢀmustꢀbeꢀcarriedꢀoutꢀinꢀ
aꢀspecificꢀway.ꢀTheꢀimportantꢀpointꢀtoꢀnoteꢀisꢀthatꢀdataꢀtransferꢀtoꢀandꢀfromꢀtheꢀ8-bitꢀbufferꢀandꢀitsꢀ
relatedꢀlowꢀbyteꢀonlyꢀtakesꢀplaceꢀwhenꢀaꢀwriteꢀorꢀreadꢀoperationꢀtoꢀitsꢀcorrespondingꢀhighꢀbyteꢀisꢀ
executed.
AsꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀimplementedꢀinꢀtheꢀwayꢀshownꢀinꢀtheꢀfollowingꢀdiagramꢀandꢀ
accessingꢀtheseꢀregisterꢀpairsꢀisꢀcarriedꢀoutꢀinꢀaꢀspecificꢀwayꢀasꢀdescribedꢀabove,ꢀitꢀisꢀrecommendedꢀ
toꢀuseꢀtheꢀ“MOV”ꢀinstructionꢀtoꢀaccessꢀtheꢀCCRAꢀandꢀCCRPꢀlowꢀbyteꢀregisters,ꢀnamedꢀSTMAL,ꢀ
PTMnALꢀandꢀPTMnRPL,ꢀusingꢀtheꢀfollowingꢀaccessꢀprocedures.ꢀAccessingꢀtheꢀCCRAꢀorꢀCCRPꢀ
lowꢀbyteꢀregistersꢀwithoutꢀfollowingꢀtheseꢀaccessꢀproceduresꢀwillꢀresultꢀinꢀunpredictableꢀvalues.
PTMn Coꢀnteꢁ Registeꢁ (Read onlꢂ)
PTMnDL
ꢆ-bit Bꢀffeꢁ
PTMnAL
PTMnDH
STM Coꢀnteꢁ Registeꢁ (Read onlꢂ)
STMDL
STMDH
PTMnAH
ꢆ-bit Bꢀffeꢁ
PTMn CCRA Registeꢁ (Read/Wꢁite)
STMAL
STMAH
PTMnRPL
PTMnRPH
STM CCRA Registeꢁ (Read/Wꢁite)
PTMn CCRP Registeꢁ (Read/Wꢁite)
Data Bꢀs
Data Bꢀs
Theꢀfollowingꢀstepsꢀshowꢀtheꢀreadꢀandꢀwriteꢀprocedures:
•ꢀ WritingꢀDataꢀtoꢀCCRAꢀorꢀCCRPꢀ
ꢀ
♦
Stepꢀ1.ꢀWriteꢀdataꢀtoꢀLowꢀByteꢀSTMAL,ꢀPTMnALꢀorꢀPTMnRPL
–ꢀnoteꢀthatꢀhereꢀdataꢀisꢀonlyꢀwrittenꢀtoꢀtheꢀ8-bitꢀbuffer.
ꢀ
♦
Stepꢀ2.ꢀWriteꢀdataꢀtoꢀHighꢀByteꢀSTMAH,ꢀPTMnAHꢀorꢀPTMnRPH
–ꢀhereꢀdataꢀisꢀwrittenꢀdirectlyꢀtoꢀtheꢀhighꢀbyteꢀregistersꢀandꢀsimultaneouslyꢀdataꢀisꢀlatchedꢀ
fromꢀtheꢀ8-bitꢀbufferꢀtoꢀtheꢀLowꢀByteꢀregisters.
•ꢀ ReadingꢀDataꢀfromꢀtheꢀCounterꢀRegistersꢀandꢀCCRAꢀorꢀCCRP
ꢀ
♦
Stepꢀ1.ꢀReadꢀdataꢀfromꢀtheꢀHighꢀByteꢀSTMDH,ꢀPTMnDH,ꢀSTMAH,ꢀPTMnAHꢀorꢀPTMnRPH
–ꢀhereꢀdataꢀisꢀreadꢀdirectlyꢀfromꢀtheꢀHighꢀByteꢀregistersꢀandꢀsimultaneouslyꢀdataꢀisꢀlatchedꢀ
fromꢀtheꢀLowꢀByteꢀregisterꢀintoꢀtheꢀ8-bitꢀbuffer.
ꢀ
♦
Stepꢀ2.ꢀReadꢀdataꢀfromꢀtheꢀLowꢀByteꢀSTMDL,ꢀPTMnDL,ꢀSTMAL,ꢀPTMnALꢀorꢀPTMnRPL
–ꢀthisꢀstepꢀreadsꢀdataꢀfromꢀtheꢀ8-bitꢀbuffer.
Rev. 1.10
ꢆ6
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Standard Type TM – STM
TheꢀStandardꢀTypeꢀTMꢀcontainsꢀfiveꢀoperatingꢀmodes,ꢀwhichꢀareꢀCompareꢀMatchꢀOutput,ꢀTimer/
EventꢀCounter,ꢀCaptureꢀInput,ꢀSingleꢀPulseꢀOutputꢀandꢀPWMꢀOutputꢀmodes.ꢀTheꢀStandardꢀTMꢀcanꢀ
alsoꢀbeꢀcontrolledꢀwithꢀtwoꢀexternalꢀinputꢀpinsꢀandꢀcanꢀdriveꢀtwoꢀexternalꢀoutputꢀpins.
STM Core
STM Input Pin
STM Output Pin
16-bit STM
STCKꢄ STPI
STPꢄ STPB
CCRP
Compaꢁatoꢁ P Match
ꢆ-bit Compaꢁatoꢁ P
bꢆ~b15
STMPF Inteꢁꢁꢀpt
STOC
000
001
010
011
100
101
110
111
fSYS/ꢃ
fSYS
fH/16
fH/6ꢃ
fSUB
STP
Coꢀnteꢁ Cleaꢁ
0
1
Oꢀtpꢀt
Contꢁol
Polaꢁitꢂ
Contꢁol
Pin
Contꢁol
16-bit Coꢀnt-ꢀp Coꢀnteꢁ
STPB
fSUB
STON
STPAU
STCCLR
STM1ꢄ STM0
STIO1ꢄ STIO0
STPOL
PxSn
b0~b15
Pin Contꢁol
STCK
Compaꢁatoꢁ A Match
STIO1ꢄ STIO0
16-bit Compaꢁatoꢁ A
STMAF Inteꢁꢁꢀpt
STCKꢅ~STCK0
PxSn
IFSn
CCRA
Edge Detectoꢁ
Pin Contꢁol
STPI
PxSn
Standard Type TM Block Diagram
Standard TM Operation
TheꢀsizeꢀofꢀStandardꢀTMꢀisꢀ16-bitꢀwideꢀandꢀitsꢀcoreꢀisꢀaꢀ16-bitꢀcount-upꢀcounterꢀwhichꢀisꢀdrivenꢀbyꢀ
aꢀuserꢀselectableꢀinternalꢀorꢀexternalꢀclockꢀsource.ꢀThereꢀareꢀalsoꢀtwoꢀinternalꢀcomparatorsꢀwithꢀtheꢀ
names,ꢀComparatorꢀAꢀandꢀComparatorꢀP.ꢀTheseꢀcomparatorsꢀwillꢀcompareꢀtheꢀvalueꢀinꢀtheꢀcounterꢀ
withꢀCCRPꢀandꢀCCRAꢀregisters.ꢀTheꢀCCRPꢀcomparatorꢀisꢀ8-bitꢀwideꢀwhoseꢀvalueꢀisꢀcomparedꢀ
withꢀtheꢀhighestꢀ8ꢀbitsꢀinꢀtheꢀcounterꢀwhileꢀtheꢀCCRAꢀisꢀtheꢀsixteenꢀbitsꢀandꢀthereforeꢀcomparesꢀallꢀ
counterꢀbits.
Theꢀonlyꢀwayꢀofꢀchangingꢀtheꢀvalueꢀofꢀtheꢀ16-bitꢀcounterꢀusingꢀtheꢀapplicationꢀprogram,ꢀisꢀtoꢀ
clearꢀtheꢀcounterꢀbyꢀchangingꢀtheꢀSTONꢀbitꢀfromꢀlowꢀtoꢀhigh.ꢀTheꢀcounterꢀwillꢀalsoꢀbeꢀclearedꢀ
automaticallyꢀbyꢀaꢀcounterꢀoverflowꢀorꢀaꢀcompareꢀmatchꢀwithꢀoneꢀofꢀitsꢀassociatedꢀcomparators.ꢀ
Whenꢀtheseꢀconditionsꢀoccur,ꢀaꢀSTMꢀinterruptꢀsignalꢀwillꢀalsoꢀusuallyꢀbeꢀgenerated.ꢀTheꢀStandardꢀ
TypeꢀTMꢀcanꢀoperateꢀinꢀaꢀnumberꢀofꢀdifferentꢀoperationalꢀmodes,ꢀcanꢀbeꢀdrivenꢀbyꢀdifferentꢀclockꢀ
sourcesꢀincludingꢀanꢀinputꢀpinꢀandꢀcanꢀalsoꢀcontrolꢀanꢀoutputꢀpin.ꢀAllꢀoperatingꢀsetupꢀconditionsꢀareꢀ
selectedꢀusingꢀrelevantꢀinternalꢀregisters.
Rev. 1.10
ꢆ7
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Standard Type TM Register Description
OverallꢀoperationꢀofꢀtheꢀStandardꢀTMꢀisꢀcontrolledꢀusingꢀaꢀseriesꢀofꢀregisters.ꢀAꢀreadꢀonlyꢀregisterꢀ
pairꢀexistsꢀtoꢀstoreꢀtheꢀinternalꢀcounterꢀ16-bitꢀvalue,ꢀwhileꢀaꢀread/writeꢀregisterꢀpairꢀexistsꢀtoꢀstoreꢀ
theꢀinternalꢀ16-bitꢀCCRAꢀvalue.ꢀTheꢀSTMRPꢀregisterꢀisꢀusedꢀtoꢀstoreꢀtheꢀ8-bitꢀCCRPꢀbits.ꢀTheꢀ
remainingꢀtwoꢀregistersꢀareꢀcontrolꢀregistersꢀwhichꢀsetupꢀtheꢀdifferentꢀoperatingꢀandꢀcontrolꢀmodes.
Bit
Register
Name
7
STPAU
STM1
D7
6
STCKꢅ
STM0
D6
5
STCK1
STIO1
D5
4
STCK0
STIO0
Dꢃ
3
STON
STOC
D3
2
—
1
—
0
—
STMC0
STMC1
STMDL
STMDH
STMAL
STMAH
STMRP
STPOL
Dꢅ
STDPX
D1
STCCLR
D0
D15
D7
D1ꢃ
D6
D13
D5
D1ꢅ
Dꢃ
D11
D3
D10
Dꢅ
D9
Dꢆ
D1
D0
D15
D7
D1ꢃ
D6
D13
D5
D1ꢅ
Dꢃ
D11
D3
D10
Dꢅ
D9
Dꢆ
D1
D0
16-bit Standard TM Registers List
STMDL Register
Bit
Name
R/W
7
D7
R
6
D6
R
5
D5
R
4
Dꢃ
R
3
D3
R
2
1
D1
R
0
D0
R
Dꢅ
R
POR
0
0
0
0
0
0
0
0
Bitꢀ7~0
D7~D0:ꢀSTMꢀCounterꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
STMꢀ16-bitꢀCounterꢀbitꢀ7~bitꢀ0
STMDH Register
Bit
Name
R/W
7
D15
R
6
D1ꢃ
R
5
D13
R
4
D1ꢅ
R
3
D11
R
2
D10
R
1
D9
R
0
Dꢆ
R
POR
0
0
0
0
0
0
0
0
Bitꢀ7~0
D15~D8:ꢀSTMꢀCounterꢀHighꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
STMꢀ16-bitꢀCounterꢀbitꢀ15~bitꢀ8
STMAL Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
Dꢃ
R/W
0
3
D3
R/W
0
2
Dꢅ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0
D7~D0:ꢀSTMꢀCCRAꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
STMꢀ16-bitꢀCCRAꢀbitꢀ7~bitꢀ0
Rev. 1.10
ꢆꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
STMAH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
Dꢆ
R/W
0
D15
R/W
0
D1ꢃ
R/W
0
D13
R/W
0
D1ꢅ
R/W
0
D11
R/W
0
D10
R/W
0
POR
Bitꢀ7~0
D15~D8:ꢀSTMꢀCCRAꢀHighꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
STMꢀ16-bitꢀCCRAꢀbitꢀ15~bitꢀ8
STMC0 Register
Bit
7
6
STCKꢅ
R/W
0
5
STCK1
R/W
0
4
STCK0
R/W
0
3
STON
R/W
0
2
1
0
Name
R/W
STPAU
R/W
0
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7
STPAU:ꢀSTMꢀCounterꢀPauseꢀControl
0:ꢀRun
1:ꢀPause
Theꢀcounterꢀcanꢀbeꢀpausedꢀbyꢀsettingꢀthisꢀbitꢀhigh.ꢀClearingꢀtheꢀbitꢀtoꢀ“0”ꢀrestoresꢀ
normalꢀcounterꢀoperation.ꢀWhenꢀinꢀaꢀPauseꢀconditionꢀtheꢀSTMꢀwillꢀremainꢀpoweredꢀ
upꢀandꢀcontinueꢀtoꢀconsumeꢀpower.ꢀTheꢀcounterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀwhenꢀ
thisꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀandꢀresumeꢀcountingꢀfromꢀthisꢀvalueꢀwhenꢀtheꢀbitꢀ
changesꢀtoꢀaꢀlowꢀvalueꢀagain.
Bitꢀ6~4
STCK2~STCK0:ꢀSelectꢀSTMꢀCounterꢀClock
000:ꢀfSYS/4
001:ꢀfSYS
010:ꢀfH/16
011:ꢀfH/64
100:ꢀfSUB
101:ꢀfSUB
110:ꢀSTCKꢀrisingꢀedgeꢀclock
111:ꢀSTCKꢀfallingꢀedgeꢀclock
TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀclockꢀsourceꢀforꢀtheꢀSTM.ꢀTheꢀexternalꢀpinꢀclockꢀ
sourceꢀcanꢀbeꢀchosenꢀtoꢀbeꢀactiveꢀonꢀtheꢀrisingꢀorꢀfallingꢀedge.ꢀTheꢀclockꢀsourceꢀfSYSꢀisꢀ
theꢀsystemꢀclock,ꢀwhileꢀfHꢀandꢀfSUBꢀareꢀotherꢀinternalꢀclocks,ꢀtheꢀdetailsꢀofꢀwhichꢀcanꢀ
beꢀfoundꢀinꢀtheꢀoscillatorꢀsection.
Bitꢀ3
STON:ꢀSTMꢀCounterꢀOn/OffꢀControl
0:ꢀOff
1:ꢀOn
Thisꢀbitꢀcontrolsꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀSTM.ꢀSettingꢀtheꢀbitꢀhighꢀenablesꢀ
theꢀcounterꢀtoꢀrunꢀwhileꢀclearingꢀtheꢀbitꢀdisablesꢀtheꢀSTM.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀ
willꢀstopꢀtheꢀcounterꢀfromꢀcountingꢀandꢀturnꢀoffꢀtheꢀSTMꢀwhichꢀwillꢀreduceꢀitsꢀpowerꢀ
consumption.ꢀWhenꢀtheꢀbitꢀchangesꢀstateꢀfromꢀlowꢀtoꢀhighꢀtheꢀinternalꢀcounterꢀvalueꢀ
willꢀbeꢀresetꢀtoꢀzero,ꢀhoweverꢀwhenꢀtheꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow,ꢀtheꢀinternalꢀ
counterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀuntilꢀtheꢀbitꢀreturnsꢀhighꢀagain.ꢀIfꢀtheꢀSTMꢀisꢀinꢀ
theꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀtheꢀPWMꢀOutputꢀModeꢀorꢀSingleꢀPulseꢀOutputꢀ
ModeꢀthenꢀtheꢀSTMꢀoutputꢀpinꢀwillꢀbeꢀresetꢀtoꢀitsꢀinitialꢀcondition,ꢀasꢀspecifiedꢀbyꢀtheꢀ
STOCꢀbit,ꢀwhenꢀtheꢀSTONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh.
Bitꢀ2~0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Rev. 1.10
ꢆ9
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
STMC1 Register
Bit
Name
R/W
7
STM1
R/W
0
6
STM0
R/W
0
5
STIO1
R/W
0
4
STIO0
R/W
0
3
STOC
R/W
0
2
STPOL
R/W
0
1
STDPX
R/W
0
0
STCCLR
R/W
POR
0
Bitꢀ7~6
STM1~STM0:ꢀSelectꢀSTMꢀOperatingꢀMode
00:ꢀCompareꢀMatchꢀOutputꢀMode
01:ꢀCaptureꢀInputꢀMode
10:ꢀPWMꢀModeꢀorꢀSingleꢀPulseꢀOutputꢀMode
11:ꢀTimer/CounterꢀMode
TheseꢀbitsꢀsetupꢀtheꢀrequiredꢀoperatingꢀmodeꢀforꢀtheꢀSTM.ꢀToꢀensureꢀreliableꢀoperationꢀ
theꢀSTMꢀshouldꢀbeꢀswitchedꢀoffꢀbeforeꢀanyꢀchangesꢀareꢀmadeꢀtoꢀtheꢀSTM1ꢀandꢀSTM0ꢀ
bits.ꢀInꢀtheꢀTimer/CounterꢀMode,ꢀtheꢀSTMꢀoutputꢀpinꢀstateꢀisꢀundefined.
Bitꢀ5~4
STIO1~STIO0:ꢀSelectꢀSTMꢀExternalꢀPinꢀ(STPꢀorꢀSTPI)ꢀFunction
CompareꢀMatchꢀOutputꢀMode
00:ꢀNoꢀchange
01:ꢀOutputꢀlow
10:ꢀOutputꢀhigh
11:ꢀToggleꢀoutput
PWMꢀOutputꢀMode/SingleꢀPulseꢀOutputꢀMode
00:ꢀPWMꢀoutputꢀinactiveꢀstate
01:ꢀPWMꢀoutputꢀactiveꢀstate
10:ꢀPWMꢀoutput
11:ꢀSingleꢀPulseꢀOutput
CaptureꢀInputꢀMode
00:ꢀInputꢀcaptureꢀatꢀrisingꢀedgeꢀofꢀSTPI
01:ꢀInputꢀcaptureꢀatꢀfallingꢀedgeꢀofꢀSTPI
10:ꢀInputꢀcaptureꢀatꢀrising/fallingꢀedgeꢀofꢀSTPI
11:ꢀInputꢀcaptureꢀdisabled
Timer/CounterꢀMode
Unused
TheseꢀtwoꢀbitsꢀareꢀusedꢀtoꢀdetermineꢀhowꢀtheꢀSTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀ
certainꢀconditionꢀisꢀreached.ꢀTheꢀfunctionꢀthatꢀtheseꢀbitsꢀselectꢀdependsꢀuponꢀinꢀwhichꢀ
modeꢀtheꢀSTMꢀisꢀrunning.
InꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀ
STMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀ
A.ꢀTheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀsetupꢀtoꢀswitchꢀhigh,ꢀswitchꢀlowꢀorꢀtoꢀtoggleꢀitsꢀpresentꢀ
stateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀWhenꢀtheꢀbitsꢀareꢀbothꢀ
“0”,ꢀthenꢀnoꢀchangeꢀwillꢀtakeꢀplaceꢀonꢀtheꢀoutput.ꢀTheꢀinitialꢀvalueꢀofꢀtheꢀSTMꢀoutputꢀ
pinꢀshouldꢀbeꢀsetupꢀusingꢀtheꢀSTOCꢀbitꢀinꢀtheꢀSTMC1ꢀregister.ꢀNoteꢀthatꢀtheꢀoutputꢀ
levelꢀrequestedꢀbyꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀmustꢀbeꢀdifferentꢀfromꢀtheꢀinitialꢀvalueꢀ
setupꢀusingꢀtheꢀSTOCꢀbitꢀotherwiseꢀnoꢀchangeꢀwillꢀoccurꢀonꢀtheꢀSTMꢀoutputꢀpinꢀwhenꢀ
aꢀcompareꢀmatchꢀoccurs.ꢀAfterꢀtheꢀSTMꢀoutputꢀpinꢀchangesꢀstate,ꢀitꢀcanꢀbeꢀresetꢀtoꢀitsꢀ
initialꢀlevelꢀbyꢀchangingꢀtheꢀlevelꢀofꢀtheꢀSTONꢀbitꢀfromꢀlowꢀtoꢀhigh.
InꢀtheꢀPWMꢀMode,ꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀSTMꢀoutputꢀpinꢀ
changesꢀstateꢀwhenꢀaꢀcertainꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀTheꢀPWMꢀoutputꢀ
functionꢀisꢀmodifiedꢀbyꢀchangingꢀtheseꢀtwoꢀbits.ꢀItꢀisꢀnecessaryꢀtoꢀonlyꢀchangeꢀtheꢀ
valuesꢀofꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀonlyꢀafterꢀtheꢀSTMꢀhasꢀbeenꢀswitchedꢀoff.ꢀ
UnpredictableꢀPWMꢀoutputsꢀwillꢀoccurꢀifꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀareꢀchangedꢀ
whenꢀtheꢀSTMꢀisꢀrunning.
Rev. 1.10
90
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ3
STOC:ꢀSTMꢀSTPꢀOutputꢀControl
CompareꢀMatchꢀOutputꢀMode
0:ꢀInitialꢀlow
1:ꢀInitialꢀhigh
PWMꢀOutputꢀMode/SingleꢀPulseꢀOutputꢀMode
0:ꢀActiveꢀlow
1:ꢀActiveꢀhigh
ThisꢀisꢀtheꢀoutputꢀcontrolꢀbitꢀforꢀtheꢀSTMꢀoutputꢀpin.ꢀItsꢀoperationꢀdependsꢀuponꢀ
whetherꢀSTMꢀisꢀbeingꢀusedꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀinꢀtheꢀPWMꢀ
OutputꢀMode/SingleꢀPulseꢀOutputꢀMode.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀSTMꢀisꢀinꢀtheꢀTimer/
CounterꢀMode.ꢀInꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀitꢀdeterminesꢀtheꢀlogicꢀlevelꢀofꢀ
theꢀSTMꢀoutputꢀpinꢀbeforeꢀaꢀcompareꢀmatchꢀoccurs.ꢀInꢀtheꢀPWMꢀOutputꢀMode/Singleꢀ
PulseꢀOutputꢀModeꢀitꢀdeterminesꢀifꢀtheꢀPWMꢀsignalꢀisꢀactiveꢀhighꢀorꢀactiveꢀlow.
Bitꢀ2
STPOL:ꢀSTMꢀSTPꢀOutputꢀPolarityꢀControl
0:ꢀNon-inverted
1:ꢀInverted
ThisꢀbitꢀcontrolsꢀtheꢀpolarityꢀofꢀtheꢀSTPꢀoutputꢀpin.ꢀWhenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀSTMꢀ
outputꢀpinꢀwillꢀbeꢀinvertedꢀandꢀnotꢀinvertedꢀwhenꢀtheꢀbitꢀisꢀ“0”.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀ
STMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.
Bitꢀ1
Bitꢀ0
STDPX:ꢀSTMꢀPWMꢀDuty/PeriodꢀControl
0:ꢀCCRPꢀ–ꢀperiod;ꢀCCRAꢀ–ꢀduty
1:ꢀCCRPꢀ–ꢀduty;ꢀCCRAꢀ–ꢀperiod
ThisꢀbitꢀdeterminesꢀwhichꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀforꢀperiodꢀandꢀ
dutyꢀcontrolꢀofꢀtheꢀPWMꢀwaveform.
STCCLR:ꢀSTMꢀCounterꢀClearꢀConditionꢀSelection
0:ꢀComparatorꢀPꢀmatch
1:ꢀComparatorꢀAꢀmatch
Thisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀmethodꢀwhichꢀclearsꢀtheꢀcounter.ꢀRememberꢀthatꢀtheꢀ
StandardꢀTMꢀcontainsꢀtwoꢀcomparators,ꢀComparatorꢀAꢀandꢀComparatorꢀP,ꢀeitherꢀofꢀ
whichꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounter.ꢀWithꢀtheꢀSTCCLRꢀbitꢀsetꢀhigh,ꢀ
theꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ
Whenꢀtheꢀbitꢀisꢀlow,ꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀ
theꢀComparatorꢀPꢀorꢀwithꢀaꢀcounterꢀoverflow.ꢀAꢀcounterꢀoverflowꢀclearingꢀmethodꢀcanꢀ
onlyꢀbeꢀimplementedꢀifꢀtheꢀCCRPꢀbitsꢀareꢀallꢀclearedꢀtoꢀ“0”.ꢀTheꢀSTCCLRꢀbitꢀisꢀnotꢀ
usedꢀinꢀtheꢀPWMꢀOutput,ꢀSingleꢀPulseꢀOutputꢀorꢀCaptureꢀInputꢀMode.
STMRP Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
Dꢃ
R/W
0
3
D3
R/W
0
2
Dꢅ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0
D7~D0:ꢀSTMꢀCCRPꢀ8-bitꢀRegister,ꢀComparedꢀwithꢀtheꢀSTMꢀCounterꢀbitꢀ15~bitꢀ8
ComparatorꢀPꢀmatchꢀperiod
0:ꢀ65536ꢀSTMꢀclocks
1~255:ꢀ(1~255)ꢀ×ꢀ256ꢀSTMꢀclocks
TheseꢀeightꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀvalueꢀonꢀtheꢀinternalꢀCCRPꢀ8-bitꢀregister,ꢀwhichꢀ
areꢀthenꢀcomparedꢀwithꢀtheꢀinternalꢀcounter'sꢀhighestꢀeightꢀbits.ꢀTheꢀresultꢀofꢀthisꢀ
comparisonꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀifꢀtheꢀSTCCLRꢀbitꢀisꢀsetꢀtoꢀ“0”.ꢀ
SettingꢀtheꢀSTCCLRꢀbitꢀtoꢀ“0”ꢀensuresꢀthatꢀaꢀcompareꢀmatchꢀwithꢀtheꢀCCRPꢀvaluesꢀ
willꢀresetꢀtheꢀinternalꢀcounter.ꢀAsꢀtheꢀCCRPꢀbitsꢀareꢀonlyꢀcomparedꢀwithꢀtheꢀhighestꢀ
eightꢀcounterꢀbits,ꢀtheꢀcompareꢀvaluesꢀexistꢀinꢀ256ꢀclockꢀcycleꢀmultiples.ꢀClearingꢀallꢀ
eightꢀbitsꢀtoꢀ“0”ꢀisꢀinꢀeffectꢀallowingꢀtheꢀcounterꢀtoꢀoverflowꢀatꢀitsꢀmaximumꢀvalue.
Rev. 1.10
91
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Standard Type TM Operation Modes
TheꢀStandardꢀTypeꢀTMꢀcanꢀoperateꢀinꢀoneꢀofꢀfiveꢀoperatingꢀmodes,ꢀCompareꢀMatchꢀOutputꢀMode,ꢀ
PWMꢀOutputꢀMode,ꢀSingleꢀPulseꢀOutputꢀMode,ꢀCaptureꢀInputꢀModeꢀorꢀTimer/CounterꢀMode.ꢀTheꢀ
operatingꢀmodeꢀisꢀselectedꢀusingꢀtheꢀSTM1ꢀandꢀSTM0ꢀbitsꢀinꢀtheꢀSTMC1ꢀregister.
Compare Match Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀSTM1ꢀandꢀSTM0ꢀinꢀtheꢀSTMC1ꢀregister,ꢀshouldꢀbeꢀsetꢀtoꢀ“00”ꢀrespectively.ꢀ
Inꢀthisꢀmodeꢀonceꢀtheꢀcounterꢀisꢀenabledꢀandꢀrunningꢀitꢀcanꢀbeꢀclearedꢀbyꢀthreeꢀmethods.ꢀTheseꢀareꢀ
aꢀcounterꢀoverflow,ꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀandꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀP.ꢀ
WhenꢀtheꢀSTCCLRꢀbitꢀisꢀlow,ꢀthereꢀareꢀtwoꢀwaysꢀinꢀwhichꢀtheꢀcounterꢀcanꢀbeꢀcleared.ꢀOneꢀisꢀwhenꢀ
aꢀcompareꢀmatchꢀfromꢀComparatorꢀP,ꢀtheꢀotherꢀisꢀwhenꢀtheꢀCCRPꢀbitsꢀareꢀallꢀ“0”ꢀwhichꢀallowsꢀtheꢀ
counterꢀtoꢀoverflow.ꢀHereꢀbothꢀSTMAFꢀandꢀSTMPFꢀinterruptꢀrequestꢀflagsꢀforꢀComparatorꢀAꢀandꢀ
ComparatorꢀPꢀrespectively,ꢀwillꢀbothꢀbeꢀgenerated.
IfꢀtheꢀSTCCLRꢀbitꢀinꢀtheꢀSTMC1ꢀregisterꢀisꢀhighꢀthenꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀ
matchꢀoccursꢀfromꢀComparatorꢀA.ꢀHowever,ꢀhereꢀonlyꢀtheꢀSTMAFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀ
generatedꢀevenꢀifꢀtheꢀvalueꢀofꢀtheꢀCCRPꢀbitsꢀisꢀlessꢀthanꢀthatꢀofꢀtheꢀCCRAꢀregisters.ꢀThereforeꢀwhenꢀ
STCCLRꢀisꢀhighꢀnoꢀSTMPFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀgenerated.ꢀInꢀtheꢀCompareꢀMatchꢀOutputꢀ
Mode,ꢀtheꢀCCRAꢀcanꢀnotꢀbeꢀsetꢀtoꢀ“0”.
Asꢀtheꢀnameꢀofꢀtheꢀmodeꢀsuggests,ꢀafterꢀaꢀcomparisonꢀisꢀmade,ꢀtheꢀSTMꢀoutputꢀpin,ꢀwillꢀchangeꢀ
state.ꢀTheꢀSTMꢀoutputꢀpinꢀconditionꢀhoweverꢀonlyꢀchangesꢀstateꢀwhenꢀaꢀSTMAFꢀinterruptꢀrequestꢀ
flagꢀisꢀgeneratedꢀafterꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀSTMPFꢀinterruptꢀrequestꢀ
flag,ꢀgeneratedꢀfromꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀwillꢀhaveꢀnoꢀeffectꢀonꢀtheꢀSTMꢀ
outputꢀpin.ꢀTheꢀwayꢀinꢀwhichꢀtheꢀSTMꢀoutputꢀpinꢀchangesꢀstateꢀareꢀdeterminedꢀbyꢀtheꢀconditionꢀofꢀ
theꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀinꢀtheꢀSTMC1ꢀregister.ꢀTheꢀSTMꢀoutputꢀpinꢀcanꢀbeꢀselectedꢀusingꢀtheꢀ
STIO1ꢀandꢀSTIO0ꢀbitsꢀtoꢀgoꢀhigh,ꢀtoꢀgoꢀlowꢀorꢀtoꢀtoggleꢀfromꢀitsꢀpresentꢀconditionꢀwhenꢀaꢀcompareꢀ
matchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀinitialꢀconditionꢀofꢀtheꢀSTMꢀoutputꢀpin,ꢀwhichꢀisꢀsetupꢀafterꢀ
theꢀSTONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀisꢀsetupꢀusingꢀtheꢀSTOCꢀbit.ꢀNoteꢀthatꢀifꢀtheꢀSTIO1ꢀandꢀ
STIO0ꢀbitsꢀareꢀ“0”ꢀthenꢀnoꢀpinꢀchangeꢀwillꢀtakeꢀplace.
Rev. 1.10
9ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Coꢀnteꢁ oveꢁflow
CCRP=0
Coꢀnteꢁ Valꢀe
0xFFFF
STCCLR = 0; STM [1:0] = 00
CCRP > 0
Coꢀnteꢁ cleaꢁed bꢂ CCRP valꢀe
CCRP > 0
Coꢀnteꢁ
Restaꢁt
Resꢀme
Paꢀse
CCRP
CCRA
Stop
Time
STON
STPAU
STPOL
CCRP Int. flag
STMPF
CCRA Int. flag
STMAF
STM
O/P Pin
Oꢀtpꢀt not affected bꢂ
STMAF flag. Remains High
ꢀntil ꢁeset bꢂ STON bit
Oꢀtpꢀt pin set to
initial Level Low if
STOC=0
Oꢀtpꢀt Toggle
with STMAF flag
Oꢀtpꢀt Inveꢁts
when STPOL is high
Oꢀtpꢀt Pin
Note STIO [1:0] = 10
Active High Oꢀtpꢀt select
Reset to Initial valꢀe
Oꢀtpꢀt contꢁolled bꢂ
otheꢁ pin-shaꢁed fꢀnction
Heꢁe STIO [1:0] = 11
Toggle Oꢀtpꢀt select
Compare Match Output Mode – STCCLR=0
Note:ꢀ1.ꢀWithꢀSTCCLR=0ꢀaꢀComparatorꢀPꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀSTMꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀSTMAFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsinitialꢀstateꢀbyꢀaꢀSTONꢀbitꢀrisingꢀedge
Rev. 1.10
93
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Coꢀnteꢁ Valꢀe
STCCLR = 1; STM [1:0] = 00
CCRA = 0
Coꢀnteꢁ oveꢁflow
CCRA > 0 Coꢀnteꢁ cleaꢁed bꢂ CCRA valꢀe
0xFFFF
CCRA
CCRP
CCRA=0
Resꢀme
Paꢀse
Stop
Coꢀnteꢁ Restaꢁt
Time
STON
STPAU
STPOL
No STMAF flag
geneꢁated on
CCRA oveꢁflow
CCRA Int. flag
STMAF
CCRP Int. flag
STMPF
STMPF not
geneꢁated
Oꢀtpꢀt does
not change
STM
O/P Pin
Oꢀtpꢀt not affected bꢂ
STMAF flag. Remains High
ꢀntil ꢁeset bꢂ STON bit
Oꢀtpꢀt Inveꢁts
when STPOL is high
Oꢀtpꢀt Toggle
with STMAF flag
Oꢀtpꢀt pin set to
initial Level Low if
STOC=0
Oꢀtpꢀt Pin
Reset to Initial valꢀe
Oꢀtpꢀt contꢁolled bꢂ
otheꢁ pin-shaꢁed fꢀnction
Note STIO [1:0] = 10
Active High Oꢀtpꢀt select
Heꢁe STIO [1:0] = 11
Toggle Oꢀtpꢀt select
Compare Match Output Mode – STCCLR=1
Note:ꢀ1.ꢀWithꢀSTCCLR=1ꢀaꢀComparatorꢀAꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀSTMꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀSTMAFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀSTONꢀbitꢀrisingꢀedge
4.ꢀAꢀSTMPFꢀflagꢀisꢀnotꢀgeneratedꢀwhenꢀSTCCLR=1
Rev. 1.10
9ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Timer/Counter Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀSTM1ꢀandꢀSTM0ꢀinꢀtheꢀSTMC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“11”ꢀrespectively.ꢀ
TheꢀTimer/CounterꢀModeꢀoperatesꢀinꢀanꢀidenticalꢀwayꢀtoꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀ
generatingꢀtheꢀsameꢀinterruptꢀflags.ꢀTheꢀexceptionꢀisꢀthatꢀinꢀtheꢀTimer/CounterꢀModeꢀtheꢀSTMꢀ
outputꢀpinꢀisꢀnotꢀused.ꢀThereforeꢀtheꢀaboveꢀdescriptionꢀandꢀTimingꢀDiagramsꢀforꢀtheꢀCompareꢀ
MatchꢀOutputꢀModeꢀcanꢀbeꢀusedꢀtoꢀunderstandꢀitsꢀfunction.ꢀAsꢀtheꢀSTMꢀoutputꢀpinꢀisꢀnotꢀusedꢀinꢀ
thisꢀmode,ꢀtheꢀpinꢀcanꢀbeꢀusedꢀasꢀaꢀnormalꢀI/Oꢀpinꢀorꢀotherꢀpin-sharedꢀfunction.
PWM Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀSTM1ꢀandꢀSTM0ꢀinꢀtheꢀSTMC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“10”ꢀrespectivelyꢀ
andꢀalsoꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ“10”ꢀrespectively.ꢀTheꢀPWMꢀfunctionꢀwithinꢀ
theꢀSTMꢀisꢀusefulꢀforꢀapplicationsꢀwhichꢀrequireꢀfunctionsꢀsuchꢀasꢀmotorꢀcontrol,ꢀheatingꢀcontrol,ꢀ
illuminationꢀcontrolꢀetc.ꢀByꢀprovidingꢀaꢀsignalꢀofꢀfixedꢀfrequencyꢀbutꢀofꢀvaryingꢀdutyꢀcycleꢀonꢀtheꢀ
STMꢀoutputꢀpin,ꢀaꢀsquareꢀwaveꢀACꢀwaveformꢀcanꢀbeꢀgeneratedꢀwithꢀvaryingꢀequivalentꢀDCꢀRMSꢀ
values.
AsꢀbothꢀtheꢀperiodꢀandꢀdutyꢀcycleꢀofꢀtheꢀPWMꢀwaveformꢀcanꢀbeꢀcontrolled,ꢀtheꢀchoiceꢀofꢀgeneratedꢀ
waveformꢀisꢀextremelyꢀflexible.ꢀInꢀtheꢀPWMꢀmode,ꢀtheꢀSTCCLRꢀbitꢀhasꢀnoꢀeffectꢀasꢀtheꢀPWMꢀ
period.ꢀBothꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀtoꢀgenerateꢀtheꢀPWMꢀwaveform,ꢀoneꢀregisterꢀ
isꢀusedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀandꢀthusꢀcontrolꢀtheꢀPWMꢀwaveformꢀfrequency,ꢀwhileꢀtheꢀotherꢀ
oneꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdutyꢀcycle.ꢀWhichꢀregisterꢀisꢀusedꢀtoꢀcontrolꢀeitherꢀfrequencyꢀorꢀdutyꢀcycleꢀ
isꢀdeterminedꢀusingꢀtheꢀSTDPXꢀbitꢀinꢀtheꢀSTMC1ꢀregister.ꢀTheꢀPWMꢀwaveformꢀfrequencyꢀandꢀdutyꢀ
cycleꢀcanꢀthereforeꢀbeꢀcontrolledꢀbyꢀtheꢀvaluesꢀinꢀtheꢀCCRAꢀandꢀCCRPꢀregisters.
Anꢀinterruptꢀflag,ꢀoneꢀforꢀeachꢀofꢀtheꢀCCRAꢀandꢀCCRP,ꢀwillꢀbeꢀgeneratedꢀwhenꢀaꢀcompareꢀmatchꢀ
occursꢀfromꢀeitherꢀComparatorꢀAꢀorꢀComparatorꢀP.ꢀTheꢀSTOCꢀbitꢀinꢀtheꢀSTMC1ꢀregisterꢀisꢀusedꢀtoꢀ
selectꢀtheꢀrequiredꢀpolarityꢀofꢀtheꢀPWMꢀwaveformꢀwhileꢀtheꢀtwoꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀareꢀusedꢀtoꢀ
enableꢀtheꢀPWMꢀoutputꢀorꢀtoꢀforceꢀtheꢀSTMꢀoutputꢀpinꢀtoꢀaꢀfixedꢀhighꢀorꢀlowꢀlevel.ꢀTheꢀSTPOLꢀbitꢀ
isꢀusedꢀtoꢀreverseꢀtheꢀpolarityꢀofꢀtheꢀPWMꢀoutputꢀwaveform.
• 16-bit STM, PWM Output Mode, Edge-aligned Mode, STDPX=0
CCRP
Peꢁiod
Dꢀtꢂ
1~255
0
CCRP×ꢅ56
65536
CCRA
IfꢀfSYSꢀ=ꢀ16MHz,ꢀTMꢀclockꢀsourceꢀisꢀfSYS/4,ꢀCCRPꢀ=ꢀ2ꢀandꢀCCRAꢀ=ꢀ128,
TheꢀSTMꢀPWMꢀoutputꢀfrequencyꢀ=ꢀ(fSYS/4)ꢀ/ꢀ(2×256)ꢀ=ꢀfSYSꢀ/ꢀ2048ꢀ=ꢀ7.8125ꢀkHz,ꢀ
dutyꢀ=ꢀ128ꢀ/ꢀ(2×256)ꢀ=ꢀ25%.
IfꢀtheꢀDutyꢀvalueꢀdefinedꢀbyꢀtheꢀCCRAꢀregisterꢀisꢀequalꢀtoꢀorꢀgreaterꢀthanꢀtheꢀPeriodꢀvalue,ꢀthenꢀtheꢀ
PWMꢀoutputꢀdutyꢀisꢀ100%.
• 16-bit STM, PWM Output Mode, Edge-aligned Mode, STDPX=1
CCRP
Peꢁiod
Dꢀtꢂ
1~255
0
CCRA
CCRP×ꢅ56
65536
TheꢀPWMꢀoutputꢀperiodꢀisꢀdeterminedꢀbyꢀtheꢀCCRAꢀregisterꢀvalueꢀtogetherꢀwithꢀtheꢀTMꢀclockꢀ
whileꢀtheꢀPWMꢀdutyꢀcycleꢀisꢀdefinedꢀbyꢀtheꢀCCRPꢀregisterꢀvalueꢀexceptꢀwhenꢀtheꢀCCRPꢀvalueꢀisꢀ
equalꢀtoꢀ“0”.
Rev. 1.10
95
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Coꢀnteꢁ Valꢀe
STDPX = 0; STM [1:0] = 10
Coꢀnteꢁ cleaꢁed bꢂ
CCRP
Coꢀnteꢁ Reset when
STON ꢁetꢀꢁns high
CCRP
CCRA
Coꢀnteꢁ Stop if
STON bit low
Paꢀse
Resꢀme
Time
STON
STPAU
STPOL
CCRA Int. flag
STMAF
CCRP Int. flag
STMPF
STM O/P Pin
(STOC=1)
STM O/P Pin
(STOC=0)
PWM Dꢀtꢂ Cꢂcle
set bꢂ CCRA
PWM ꢁesꢀmes
opeꢁation
Oꢀtpꢀt contꢁolled bꢂ
otheꢁ pin-shaꢁed fꢀnction
Oꢀtpꢀt Inveꢁts
when STPOL = 1
PWM Peꢁiod
set bꢂ CCRP
PWM Output Mode – STDPX=0
Note:ꢀ1.ꢀHereꢀSTDPX=0ꢀ–ꢀCounterꢀclearedꢀbyꢀCCRP
2.ꢀAꢀcounterꢀclearꢀsetsꢀtheꢀPWMꢀPeriod
3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀSTIOꢀ[1:0]=00ꢀorꢀ01
4.ꢀTheꢀSTCCLRꢀbitꢀhasꢀnoꢀinfluenceꢀonꢀPWMꢀoperation
Rev. 1.10
96
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Coꢀnteꢁ Valꢀe
STDPX = 1; STM [1:0] = 10
Coꢀnteꢁ cleaꢁed bꢂ
CCRA
Coꢀnteꢁ Reset when
STON ꢁetꢀꢁns high
CCRA
CCRP
Coꢀnteꢁ Stop if
STON bit low
Paꢀse
Resꢀme
Time
STON
STPAU
STPOL
CCRP Int.
flag STMPF
CCRA Int.
flag STMAF
STM O/P Pin
(STOC=1)
STM O/P Pin
(STOC=0)
PWM ꢁesꢀmes
opeꢁation
PWM Dꢀtꢂ Cꢂcle
set bꢂ CCRP
Oꢀtpꢀt contꢁolled bꢂ
otheꢁ pin-shaꢁed fꢀnction
Oꢀtpꢀt Inveꢁts
when STPOL = 1
PWM Peꢁiod set bꢂ CCRA
PWM Output Mode – STDPX=1
Note:ꢀ1.ꢀHereꢀSTDPX=1ꢀ–ꢀCounterꢀclearedꢀbyꢀCCRA
2.ꢀAꢀcounterꢀclearꢀsetsꢀtheꢀPWMꢀPeriod
3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀevenꢀwhenꢀSTIOꢀ[1:0]=00ꢀorꢀ01
4.ꢀTheꢀSTCCLRꢀbitꢀhasꢀnoꢀinfluenceꢀonꢀPWMꢀoperation
Rev. 1.10
97
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Single Pulse Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀSTM1ꢀandꢀSTM0ꢀinꢀtheꢀSTMC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“10”ꢀrespectivelyꢀ
andꢀalsoꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ“11”ꢀrespectively.ꢀTheꢀSingleꢀPulseꢀOutputꢀ
Mode,ꢀasꢀtheꢀnameꢀsuggests,ꢀwillꢀgenerateꢀaꢀsingleꢀshotꢀpulseꢀonꢀtheꢀSTMꢀoutputꢀpin.ꢀ
TheꢀtriggerꢀforꢀtheꢀpulseꢀoutputꢀleadingꢀedgeꢀisꢀaꢀlowꢀtoꢀhighꢀtransitionꢀofꢀtheꢀSTONꢀbit,ꢀwhichꢀcanꢀ
beꢀimplementedꢀusingꢀtheꢀapplicationꢀprogram.ꢀHoweverꢀinꢀtheꢀSingleꢀPulseꢀMode,ꢀtheꢀSTONꢀbitꢀ
canꢀalsoꢀbeꢀmadeꢀtoꢀautomaticallyꢀchangeꢀfromꢀlowꢀtoꢀhighꢀusingꢀtheꢀexternalꢀSTCKꢀpin,ꢀwhichꢀwillꢀ
inꢀturnꢀinitiateꢀtheꢀSingleꢀPulseꢀoutput.ꢀWhenꢀtheꢀSTONꢀbitꢀtransitionsꢀtoꢀaꢀhighꢀlevel,ꢀtheꢀcounterꢀ
willꢀstartꢀrunningꢀandꢀtheꢀpulseꢀleadingꢀedgeꢀwillꢀbeꢀgenerated.ꢀTheꢀSTONꢀbitꢀshouldꢀremainꢀhighꢀ
whenꢀtheꢀpulseꢀisꢀinꢀitsꢀactiveꢀstate.ꢀTheꢀgeneratedꢀpulseꢀtrailingꢀedgeꢀwillꢀbeꢀgeneratedꢀwhenꢀtheꢀ
STONꢀbitꢀisꢀclearedꢀtoꢀ“0”,ꢀwhichꢀcanꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogramꢀorꢀwhenꢀaꢀ
compareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀ
HoweverꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀautomaticallyꢀclearꢀtheꢀSTONꢀbitꢀandꢀ
thusꢀgenerateꢀtheꢀSingleꢀPulseꢀoutputꢀtrailingꢀedge.ꢀInꢀthisꢀwayꢀtheꢀCCRAꢀvalueꢀcanꢀbeꢀusedꢀtoꢀ
controlꢀtheꢀpulseꢀwidth.ꢀAꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀgenerateꢀaꢀSTMꢀinterrupt.ꢀ
Theꢀcounterꢀcanꢀonlyꢀbeꢀresetꢀbackꢀtoꢀ“0”ꢀwhenꢀtheꢀSTONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhenꢀtheꢀ
counterꢀrestarts.ꢀInꢀtheꢀSingleꢀPulseꢀModeꢀCCRPꢀisꢀnotꢀused.ꢀTheꢀSTCCLRꢀandꢀSTDPXꢀbitsꢀareꢀnotꢀ
usedꢀinꢀthisꢀMode.
CCRA
CCRA
Leading Edge
Tꢁailing Edge
S/W Command SET "STON"
S/W Command CLR "STON"
oꢁ
CCRA Compaꢁe Match
STON bit
0 → 1
STON bit
1 → 0
oꢁ
STCK Pin Tꢁansition
STP Oꢀtpꢀt Pin
Pꢀlse Width = CCRA Valꢀe
Single Pulse Generation
Rev. 1.10
9ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Coꢀnteꢁ Valꢀe
STM [1:0] = 10 ; STIO [1:0] = 11
Coꢀnteꢁ stopped bꢂ
CCRA
Coꢀnteꢁ Reset when
STON ꢁetꢀꢁns high
CCRA
CCRP
Coꢀnteꢁ Stops
bꢂ softwaꢁe
Resꢀme
Paꢀse
Time
STON
Aꢀto. set bꢂ
STCK pin
Softwaꢁe Cleaꢁed bꢂ
Softwaꢁe
Tꢁiggeꢁ
Softwaꢁe
Cleaꢁ
Softwaꢁe
Tꢁiggeꢁ
Softwaꢁe
Tꢁiggeꢁ
Tꢁiggeꢁ
CCRA match
STCK pin
STPAU
STCK pin
Tꢁiggeꢁ
STPOL
No CCRP
Inteꢁꢁꢀpts
geneꢁated
CCRP Int.
Flag STMPF
CCRA Int.
Flag STMAF
STM O/P Pin
(STOC=1)
STM O/P Pin
(STOC=0)
Oꢀtpꢀt Inveꢁts
when STPOL = 1
Pꢀlse Width
set bꢂ CCRA
Single Pulse Mode
Note:ꢀ1.ꢀCounterꢀstoppedꢀbyꢀCCRA
2.ꢀCCRPꢀisꢀnotꢀused
3.ꢀTheꢀpulseꢀtriggeredꢀbyꢀtheꢀSTCKꢀpinꢀorꢀbyꢀsettingꢀtheꢀSTONꢀbitꢀhigh
4.ꢀAꢀSTCKꢀpinꢀactiveꢀedgeꢀwillꢀautomaticallyꢀsetꢀtheꢀSTONꢀbitꢀhigh.
5.ꢀInꢀtheꢀSingleꢀPulseꢀMode,ꢀSTIOꢀ[1:0]ꢀmustꢀbeꢀsetꢀtoꢀ“11”ꢀandꢀcanꢀnotꢀbeꢀchanged.
Rev. 1.10
99
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Capture Input Mode
ToꢀselectꢀthisꢀmodeꢀbitsꢀSTM1ꢀandꢀSTM0ꢀinꢀtheꢀSTMC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“01”ꢀrespectively.ꢀ
Thisꢀmodeꢀenablesꢀexternalꢀsignalsꢀtoꢀcaptureꢀandꢀstoreꢀtheꢀpresentꢀvalueꢀofꢀtheꢀinternalꢀcounterꢀ
andꢀcanꢀthereforeꢀbeꢀusedꢀforꢀapplicationsꢀsuchꢀasꢀpulseꢀwidthꢀmeasurements.ꢀTheꢀexternalꢀsignalꢀ
isꢀsuppliedꢀonꢀtheꢀSTPIꢀpin,ꢀwhoseꢀactiveꢀedgeꢀcanꢀbeꢀaꢀrisingꢀedge,ꢀaꢀfallingꢀedgeꢀorꢀbothꢀrisingꢀ
andꢀfallingꢀedges;ꢀtheꢀactiveꢀedgeꢀtransitionꢀtypeꢀisꢀselectedꢀusingꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀinꢀ
theꢀSTMC1ꢀregister.ꢀTheꢀcounterꢀisꢀstartedꢀwhenꢀtheꢀSTONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhichꢀisꢀ
initiatedꢀusingꢀtheꢀapplicationꢀprogram.
WhenꢀtheꢀrequiredꢀedgeꢀtransitionꢀappearsꢀonꢀtheꢀSTPIꢀpinꢀtheꢀpresentꢀvalueꢀinꢀtheꢀcounterꢀwillꢀbeꢀ
latchedꢀintoꢀtheꢀCCRAꢀregistersꢀandꢀaꢀSTMꢀinterruptꢀgenerated.ꢀIrrespectiveꢀofꢀwhatꢀeventsꢀoccurꢀ
onꢀtheꢀSTPIꢀpinꢀtheꢀcounterꢀwillꢀcontinueꢀtoꢀfreeꢀrunꢀuntilꢀtheꢀSTONꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow.ꢀ
WhenꢀaꢀCCRPꢀcompareꢀmatchꢀoccursꢀtheꢀcounterꢀwillꢀresetꢀbackꢀtoꢀzero;ꢀinꢀthisꢀwayꢀtheꢀCCRPꢀ
valueꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀmaximumꢀcounterꢀvalue.ꢀWhenꢀaꢀCCRPꢀcompareꢀmatchꢀoccursꢀ
fromꢀComparatorꢀP,ꢀaꢀSTMꢀinterruptꢀwillꢀalsoꢀbeꢀgenerated.ꢀCountingꢀtheꢀnumberꢀofꢀoverflowꢀ
interruptꢀsignalsꢀfromꢀtheꢀCCRPꢀcanꢀbeꢀaꢀusefulꢀmethodꢀinꢀmeasuringꢀlongꢀpulseꢀwidths.ꢀTheꢀSTIO1ꢀ
andꢀSTIO0ꢀbitsꢀcanꢀselectꢀtheꢀactiveꢀtriggerꢀedgeꢀonꢀtheꢀSTPIꢀpinꢀtoꢀbeꢀaꢀrisingꢀedge,ꢀfallingꢀedgeꢀorꢀ
bothꢀedgeꢀtypes.ꢀIfꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀareꢀbothꢀsetꢀhigh,ꢀthenꢀnoꢀcaptureꢀoperationꢀwillꢀtakeꢀ
placeꢀirrespectiveꢀofꢀwhatꢀhappensꢀonꢀtheꢀSTPIꢀpin,ꢀhoweverꢀitꢀmustꢀbeꢀnotedꢀthatꢀtheꢀcounterꢀwillꢀ
continueꢀtoꢀrun.ꢀTheꢀSTCCLRꢀandꢀSTDPXꢀbitsꢀareꢀnotꢀusedꢀinꢀthisꢀMode.
Rev. 1.10
100
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Coꢀnteꢁ Valꢀe
STM [1:0] = 01
Coꢀnteꢁ cleaꢁed bꢂ
CCRP
Coꢀnteꢁ Coꢀnteꢁ
Stop
Reset
CCRP
YY
Resꢀme
Paꢀse
XX
Time
STON
STPAU
Active
edge
Active
edge
Active
edge
STM captꢀꢁe
pin STPI
CCRA Int.
Flag STMAF
CCRP Int. Flag
STMPF
CCRA
Valꢀe
XX
YY
XX
YY
STIO [1:0]
Valꢀe
00 – Rising edge
01 – Falling edge 10 – Both edges
11 – Disable Captꢀꢁe
Capture Input Mode
Note:ꢀ1.ꢀSTMꢀ[1:0]=01ꢀandꢀactiveꢀedgeꢀsetꢀbyꢀtheꢀSTIOꢀ[1:0]ꢀbits
2.ꢀAꢀSTMꢀCaptureꢀinputꢀpinꢀactiveꢀedgeꢀtransfersꢀtheꢀcounterꢀvalueꢀtoꢀCCRA
3.ꢀSTCCLRꢀbitꢀnotꢀused
4.ꢀNoꢀoutputꢀfunctionꢀ−ꢀSTOCꢀandꢀSTPOLꢀbitsꢀareꢀnotꢀused
5.ꢀCCRPꢀdeterminesꢀtheꢀcounterꢀvalueꢀandꢀtheꢀcounterꢀhasꢀaꢀmaximumꢀcountꢀvalueꢀwhenꢀCCRPꢀisꢀequalꢀtoꢀ“0”.
Rev. 1.10
101
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Periodic Type TM – PTM
TheꢀPeriodicꢀTypeꢀTMꢀcontainsꢀfiveꢀoperatingꢀmodes,ꢀwhichꢀareꢀCompareꢀMatchꢀOutput,ꢀTimer/
EventꢀCounter,ꢀCaptureꢀInput,ꢀSingleꢀPulseꢀOutputꢀandꢀPWMꢀOutputꢀmodes.ꢀTheꢀPeriodicꢀTMꢀcanꢀ
beꢀcontrolledꢀwithꢀtwoꢀexternalꢀinputꢀpinsꢀandꢀcanꢀdriveꢀoneꢀorꢀtwoꢀexternalꢀoutputꢀpins.
CCRP
Compaꢁatoꢁ P Match
10-bit Compaꢁatoꢁ P
PTMnPF Inteꢁꢁꢀpt
000
001
010
011
100
101
110
111
fSYS/ꢃ
fSYS
PTnOC
b0~b9
fH/16
fH/6ꢃ
fSUB
PTPn
Coꢀnteꢁ Cleaꢁ
0
1
Oꢀtpꢀt
Contꢁol
Polaꢁitꢂ
Contꢁol
Pin
10-bit Coꢀnt-ꢀp Coꢀnteꢁ
Contꢁol
PTPnB
fSUB
PTnON
PTnPAU
PTnCCLR
PTnM1ꢄ PTnM0
PTnIO1ꢄ PTnIO0
PTnPOL
PxSn
b0~b9
Pin Contꢁol
PTCKn
Compaꢁatoꢁ A Match
PTnIO1ꢄ PTnIO0
Edge Detectoꢁ
10-bit Compaꢁatoꢁ A
PTMnAF Inteꢁꢁꢀpt
PxSn
PTnCKꢅ~PTnCK0
PxSn
IFSn
IFSn
PTnCAPTS
Pin Contꢁol
0
1
PTPnI
CCRA
Note:ꢀTheꢀPTPnBꢀpinꢀonlyꢀexistsꢀwhenꢀn=0.
Periodic Type TM Block Diagram (n=0, 1 or 2)
Periodic TM Operation
TheꢀPeriodicꢀTypeꢀTMꢀcoreꢀisꢀaꢀ10-bitꢀcount-upꢀcounterꢀwhichꢀisꢀdrivenꢀbyꢀaꢀuserꢀselectableꢀinternalꢀ
orꢀexternalꢀclockꢀsource.ꢀThereꢀareꢀalsoꢀtwoꢀinternalꢀcomparatorsꢀwithꢀtheꢀnames,ꢀComparatorꢀAꢀ
andꢀComparatorꢀP.ꢀTheseꢀcomparatorsꢀwillꢀcompareꢀtheꢀvalueꢀinꢀtheꢀcounterꢀwithꢀCCRPꢀandꢀCCRAꢀ
registers.ꢀTheꢀCCRPꢀcomparatorꢀisꢀ10-bitꢀwide.
Theꢀonlyꢀwayꢀofꢀchangingꢀtheꢀvalueꢀofꢀtheꢀ10-bitꢀcounterꢀusingꢀtheꢀapplicationꢀprogram,ꢀisꢀtoꢀ
clearꢀtheꢀcounterꢀbyꢀchangingꢀtheꢀPTnONꢀbitꢀfromꢀlowꢀtoꢀhigh.ꢀTheꢀcounterꢀwillꢀalsoꢀbeꢀclearedꢀ
automaticallyꢀbyꢀaꢀcounterꢀoverflowꢀorꢀaꢀcompareꢀmatchꢀwithꢀoneꢀofꢀitsꢀassociatedꢀcomparators.ꢀ
Whenꢀtheseꢀconditionsꢀoccur,ꢀaꢀPTMnꢀinterruptꢀsignalꢀwillꢀalsoꢀusuallyꢀbeꢀgenerated.ꢀTheꢀPeriodicꢀ
TypeꢀTMꢀcanꢀoperateꢀinꢀaꢀnumberꢀofꢀdifferentꢀoperationalꢀmodes,ꢀcanꢀbeꢀdrivenꢀbyꢀdifferentꢀclockꢀ
sourcesꢀincludingꢀanꢀinputꢀpinꢀandꢀcanꢀalsoꢀcontrolꢀmoreꢀthanꢀoneꢀoutputꢀpin.ꢀAllꢀoperatingꢀsetupꢀ
conditionsꢀareꢀselectedꢀusingꢀrelevantꢀinternalꢀregisters.
Periodic Type TM Register Description
OverallꢀoperationꢀofꢀtheꢀPeriodicꢀTypeꢀTMꢀisꢀcontrolledꢀusingꢀaꢀseriesꢀofꢀregisters.ꢀAꢀreadꢀonlyꢀ
registerꢀpairꢀexistsꢀtoꢀstoreꢀtheꢀinternalꢀcounterꢀ10-bitꢀvalue,ꢀwhileꢀtwoꢀread/writeꢀregisterꢀpairsꢀexistꢀ
toꢀstoreꢀtheꢀinternalꢀ10-bitꢀCCRAꢀvalueꢀandꢀCCRPꢀvalue.ꢀTheꢀremainingꢀtwoꢀregistersꢀareꢀcontrolꢀ
registersꢀwhichꢀsetupꢀtheꢀdifferentꢀoperatingꢀandꢀcontrolꢀmodes.
Bit
Register
Name
7
6
5
4
3
2
1
0
PTMnC0
PTMnC1
PTMnDL
PTMnDH
PTMnAL
PTMnAH
PTMnRPL
PTMnRPH
PTnPAU PTnCKꢅ PTnCK1 PTnCK0 PTnON
—
—
—
PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL PTnCAPTS PTnCCLR
D7
—
D6
—
D5
—
Dꢃ
—
D3
—
Dꢅ
—
D1
D9
D1
D9
D1
D9
D0
Dꢆ
D0
Dꢆ
D0
Dꢆ
D7
—
D6
—
D5
—
Dꢃ
—
D3
—
Dꢅ
—
D7
—
D6
—
D5
—
Dꢃ
—
D3
—
Dꢅ
—
10-bit Periodic TM Register List (n=0, 1 or 2)
Rev. 1.10
10ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
PTMnC0 Register
Bit
Name
R/W
7
6
5
4
3
PTnON
R/W
0
2
1
0
PTnPAU PTnCKꢅ PTnCK1 PTnCK0
—
—
—
—
—
—
—
—
—
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7ꢀ
PTnPAU:ꢀPTMnꢀCounterꢀPauseꢀControl
0:ꢀRun
1:ꢀPause
Theꢀcounterꢀcanꢀbeꢀpausedꢀbyꢀsettingꢀthisꢀbitꢀhigh.ꢀClearingꢀtheꢀbitꢀtoꢀzeroꢀrestoresꢀ
normalꢀcounterꢀoperation.ꢀWhenꢀinꢀaꢀPauseꢀconditionꢀtheꢀPTMnꢀwillꢀremainꢀpoweredꢀ
upꢀandꢀcontinueꢀtoꢀconsumeꢀpower.ꢀTheꢀcounterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀwhenꢀ
thisꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀandꢀresumeꢀcountingꢀfromꢀthisꢀvalueꢀwhenꢀtheꢀbitꢀ
changesꢀtoꢀaꢀlowꢀvalueꢀagain.
Bitꢀ6~4
PTnCK2~PTnCK0:ꢀSelectꢀPTMnꢀCounterꢀClock
000:ꢀfSYS/4
001:ꢀfSYS
010:ꢀfH/16
011:ꢀfH/64
100:ꢀfSUB
101:ꢀfSUB
110:ꢀPTCKnꢀrisingꢀedgeꢀclock
111:ꢀPTCKnꢀfallingꢀedgeꢀclock
TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀclockꢀsourceꢀforꢀtheꢀPTMn.ꢀTheꢀexternalꢀpinꢀ
clockꢀsourceꢀcanꢀbeꢀchosenꢀtoꢀbeꢀactiveꢀonꢀtheꢀrisingꢀorꢀfallingꢀedge.ꢀTheꢀclockꢀsourceꢀ
fSYSꢀisꢀtheꢀsystemꢀclock,ꢀwhileꢀfHꢀandꢀfSUBꢀareꢀotherꢀinternalꢀclocks,ꢀtheꢀdetailsꢀofꢀwhichꢀ
canꢀbeꢀfoundꢀinꢀtheꢀoscillatorꢀsection.
Bitꢀ3
PTnON:ꢀPTMnꢀCounterꢀOn/OffꢀControl
0:ꢀOff
1:ꢀOn
Thisꢀbitꢀcontrolsꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀPTMn.ꢀSettingꢀtheꢀbitꢀhighꢀenablesꢀ
theꢀcounterꢀtoꢀrun,ꢀclearingꢀtheꢀbitꢀdisablesꢀtheꢀPTMn.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀwillꢀ
stopꢀtheꢀcounterꢀfromꢀcountingꢀandꢀturnꢀoffꢀtheꢀPTMnꢀwhichꢀwillꢀreduceꢀitsꢀpowerꢀ
consumption.ꢀWhenꢀtheꢀbitꢀchangesꢀstateꢀfromꢀlowꢀtoꢀhighꢀtheꢀinternalꢀcounterꢀvalueꢀ
willꢀbeꢀresetꢀtoꢀzero,ꢀhoweverꢀwhenꢀtheꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow,ꢀtheꢀinternalꢀ
counterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀuntilꢀtheꢀbitꢀreturnsꢀhighꢀagain.ꢀ
IfꢀtheꢀPTMnꢀisꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀPWMꢀoutputꢀModeꢀorꢀSingleꢀ
PulseꢀOutputꢀModeꢀthenꢀtheꢀPTMnꢀoutputꢀpinꢀwillꢀbeꢀresetꢀtoꢀitsꢀinitialꢀcondition,ꢀasꢀ
specifiedꢀbyꢀtheꢀPTnOCꢀbit,ꢀwhenꢀtheꢀPTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh.
Bitꢀ2~0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Rev. 1.10
103
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
PTMnC1 Register
Bit
Name
R/W
7
PTnM1
R/W
0
6
PTnM0
R/W
0
5
4
3
2
1
0
PTnIO1 PTnIO0
PTnOC PTnPOL PTnCAPTS PTnCCLR
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~6ꢀ
PTnM1~PTnM0:ꢀSelectꢀPTMnꢀOperatingꢀMode
00:ꢀCompareꢀMatchꢀOutputꢀMode
01:ꢀCaptureꢀInputꢀMode
10:ꢀPWMꢀModeꢀorꢀSingleꢀPulseꢀOutputꢀMode
11:ꢀTimer/CounterꢀMode
TheseꢀbitsꢀsetupꢀtheꢀrequiredꢀoperatingꢀmodeꢀforꢀtheꢀPTMn.ꢀToꢀensureꢀreliableꢀ
operationꢀtheꢀPTMnꢀshouldꢀbeꢀswitchedꢀoffꢀbeforeꢀanyꢀchangesꢀareꢀmadeꢀtoꢀtheꢀ
PTnM1ꢀandꢀPTnM0ꢀbits.ꢀInꢀtheꢀTimer/CounterꢀMode,ꢀtheꢀPTMnꢀoutputꢀpinꢀstateꢀisꢀ
undefined.
Bitꢀ5~4
PTnIO1~PTnIO0:ꢀSelectꢀPTMnꢀExternalꢀPinꢀ(PTPnꢀorꢀPTPnI/PTCKn)ꢀFunction
CompareꢀMatchꢀOutputꢀMode
00:ꢀNoꢀchange
01:ꢀOutputꢀlow
10:ꢀOutputꢀhigh
11:ꢀToggleꢀoutput
PWMꢀOutputꢀMode/SingleꢀPulseꢀOutputꢀMode
00:ꢀPWMꢀOutputꢀinactiveꢀstate
01:ꢀPWMꢀOutputꢀactiveꢀstate
10:ꢀPWMꢀoutput
11:ꢀSingleꢀpulseꢀoutput
CaptureꢀInputꢀMode
00:ꢀInputꢀcaptureꢀatꢀrisingꢀedgeꢀofꢀPTPnIꢀorꢀPTCKn
01:ꢀInputꢀcaptureꢀatꢀfallingꢀedgeꢀofꢀPTPnIꢀorꢀPTCKn
10:ꢀInputꢀcaptureꢀatꢀfalling/risingꢀedgeꢀofꢀPTPnIꢀorꢀPTCKn
11:ꢀInputꢀcaptureꢀdisabled
Timer/CounterꢀModeꢀ
Unused
TheseꢀtwoꢀbitsꢀareꢀusedꢀtoꢀdetermineꢀhowꢀtheꢀPTMnꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀ
certainꢀconditionꢀisꢀreached.ꢀTheꢀfunctionꢀthatꢀtheseꢀbitsꢀselectꢀdependsꢀuponꢀinꢀwhichꢀ
modeꢀtheꢀPTMnꢀisꢀrunning.
InꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀ
PTMnꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ
TheꢀPTMnꢀoutputꢀpinꢀcanꢀbeꢀsetupꢀtoꢀswitchꢀhigh,ꢀswitchꢀlowꢀorꢀtoꢀtoggleꢀitsꢀpresentꢀ
stateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀWhenꢀtheꢀbitsꢀareꢀbothꢀ
zero,ꢀthenꢀnoꢀchangeꢀwillꢀtakeꢀplaceꢀonꢀtheꢀoutput.ꢀTheꢀinitialꢀvalueꢀofꢀtheꢀPTMnꢀ
outputꢀpinꢀshouldꢀbeꢀsetupꢀusingꢀtheꢀPTnOCꢀbitꢀinꢀtheꢀPTMnC1ꢀregister.ꢀNoteꢀthatꢀ
theꢀoutputꢀlevelꢀrequestedꢀbyꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀmustꢀbeꢀdifferentꢀfromꢀtheꢀ
initialꢀvalueꢀsetupꢀusingꢀtheꢀPTnOCꢀbitꢀotherwiseꢀnoꢀchangeꢀwillꢀoccurꢀonꢀtheꢀPTMnꢀ
outputꢀpinꢀwhenꢀaꢀcompareꢀmatchꢀoccurs.ꢀAfterꢀtheꢀPTMnꢀoutputꢀpinꢀchangesꢀstate,ꢀ
itꢀcanꢀbeꢀresetꢀtoꢀitsꢀinitialꢀlevelꢀbyꢀchangingꢀtheꢀlevelꢀofꢀtheꢀPTnONꢀbitꢀfromꢀlowꢀtoꢀ
high.
InꢀtheꢀPWMꢀOutputꢀMode,ꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀPTMnꢀ
outputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcertainꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀTheꢀPWMꢀ
outputꢀfunctionꢀisꢀmodifiedꢀbyꢀchangingꢀtheseꢀtwoꢀbits.ꢀItꢀisꢀnecessaryꢀtoꢀonlyꢀchangeꢀ
theꢀvaluesꢀofꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀonlyꢀafterꢀtheꢀTMꢀhasꢀbeenꢀswitchedꢀoff.ꢀ
UnpredictableꢀPWMꢀoutputsꢀwillꢀoccurꢀifꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀareꢀchangedꢀ
whenꢀtheꢀPTMnꢀisꢀrunning.
Rev. 1.10
10ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ3
PTnOC:ꢀPTMnꢀPTPnꢀOutputꢀControlꢀbit
CompareꢀMatchꢀOutputꢀMode
0:ꢀInitialꢀlow
1:ꢀInitialꢀhigh
PWMꢀOutputꢀMode/SingleꢀPulseꢀOutputꢀMode
0:ꢀActiveꢀlow
1:ꢀActiveꢀhigh
ThisꢀisꢀtheꢀoutputꢀcontrolꢀbitꢀforꢀtheꢀPTMnꢀoutputꢀpin.ꢀItsꢀoperationꢀdependsꢀuponꢀ
whetherꢀPTMnꢀisꢀbeingꢀusedꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀinꢀtheꢀPWMꢀ
Mode/SingleꢀPulseꢀOutputꢀMode.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀPTMnꢀisꢀinꢀtheꢀTimer/Counterꢀ
Mode.ꢀInꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀitꢀdeterminesꢀtheꢀlogicꢀlevelꢀofꢀtheꢀPTMnꢀ
outputꢀpinꢀbeforeꢀaꢀcompareꢀmatchꢀoccurs.ꢀInꢀtheꢀPWMꢀModeꢀitꢀdeterminesꢀifꢀtheꢀ
PWMꢀsignalꢀisꢀactiveꢀhighꢀorꢀactiveꢀlow.
Bitꢀ2
PTnPOL:ꢀPTMnꢀPTPnꢀOutputꢀPolarityꢀControl
0:ꢀNon-invert
1:ꢀInvert
ThisꢀbitꢀcontrolsꢀtheꢀpolarityꢀofꢀtheꢀPTPnꢀoutputꢀpin.ꢀWhenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀ
PTMnꢀoutputꢀpinꢀwillꢀbeꢀinvertedꢀandꢀnotꢀinvertedꢀwhenꢀtheꢀbitꢀisꢀzero.ꢀItꢀhasꢀnoꢀeffectꢀ
ifꢀtheꢀPTMnꢀisꢀinꢀtheꢀTimer/CounterꢀMode.
Bitꢀ1
Bitꢀ0
PTnCAPTS:ꢀPTMnꢀCaptureꢀTriggerꢀSourceꢀSelection
0:ꢀFromꢀPTPnIꢀpin
1:ꢀFromꢀPTCKnꢀpin
PTnCCLR:ꢀSelectꢀPTMnꢀCounterꢀClearꢀCondition
0:ꢀPTMnꢀComparatorꢀPꢀmatch
1:ꢀPTMnꢀComparatorꢀAꢀmatch
Thisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀmethodꢀwhichꢀclearsꢀtheꢀcounter.ꢀRememberꢀthatꢀtheꢀ
PeriodicꢀTMꢀcontainsꢀtwoꢀcomparators,ꢀComparatorꢀAꢀandꢀComparatorꢀP,ꢀeitherꢀofꢀ
whichꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounter.ꢀWithꢀtheꢀPTnCCLRꢀbitꢀsetꢀhigh,ꢀ
theꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ
Whenꢀtheꢀbitꢀisꢀlow,ꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀ
theꢀComparatorꢀPꢀorꢀwithꢀaꢀcounterꢀoverflow.ꢀAꢀcounterꢀoverflowꢀclearingꢀmethodꢀcanꢀ
onlyꢀbeꢀimplementedꢀifꢀtheꢀCCRPꢀbitsꢀareꢀallꢀclearedꢀtoꢀzero.ꢀTheꢀPTnCCLRꢀbitꢀisꢀnotꢀ
usedꢀinꢀtheꢀPWMꢀOutputꢀMode,ꢀSingleꢀPulseꢀOutputꢀorꢀCaptureꢀInputꢀMode.
PTMnDL Register
Bit
7
6
D6
R
5
D5
R
4
Dꢃ
R
3
D3
R
2
Dꢅ
R
1
D1
R
0
D0
R
Name
R/W
D7
R
POR
0
0
0
0
0
0
0
0
Bitꢀ7~0
D7~D0:ꢀPTMnꢀCounterꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
PTMnꢀ10-bitꢀCounterꢀbitꢀ7~bitꢀ0
PTMnDH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R
0
Dꢆ
R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
0
0
Bitꢀ7~2ꢀ
Bitꢀ1~0
Unimplemented,ꢀreadꢀasꢀ“0”
D9~D8:ꢀPTMnꢀCounterꢀHighꢀByteꢀRegisterꢀbitꢀ1~bitꢀ0
PTMnꢀ10-bitꢀCounterꢀbitꢀ9~bitꢀ8
Rev. 1.10
105
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
PTMnAL Register
Bit
7
6
D6
R/W
0
5
D5
R/W
0
4
Dꢃ
R/W
0
3
D3
R/W
0
2
Dꢅ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
Name
R/W
D7
R/W
0
POR
Bitꢀ7~0
D7~D0:ꢀPTMnꢀCCRAꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
PTMnꢀ10-bitꢀCCRAꢀbitꢀ7~bitꢀ0
PTMnAH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
Dꢆ
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~2ꢀ
Bitꢀ1~0
Unimplemented,ꢀreadꢀasꢀ“0”
D9~D8:ꢀPTMnꢀCCRAꢀHighꢀByteꢀRegisterꢀbitꢀ1~bitꢀ0
PTMnꢀ10-bitꢀCCRAꢀbitꢀ9~bitꢀ8
PTMnRPL Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
Dꢃ
R/W
0
3
D3
R/W
0
2
Dꢅ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0ꢀ
D7~D0:ꢀPTMnꢀCCRPꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
PTMnꢀ10-bitꢀCCRPꢀbitꢀ7~bitꢀ0
PTMnRPH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
Dꢆ
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~2ꢀ
Bitꢀ1~0
Unimplemented,ꢀreadꢀasꢀ“0”
D9~D8:ꢀPTMnꢀCCRPꢀHighꢀByteꢀRegisterꢀbitꢀ1~bitꢀ0
PTMnꢀ10-bitꢀCCRPꢀbitꢀ9~bitꢀ8
Rev. 1.10
106
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Periodic Type TM Operating Modes
TheꢀPeriodicꢀTypeꢀTMꢀcanꢀoperateꢀinꢀoneꢀofꢀfiveꢀoperatingꢀmodes,ꢀCompareꢀMatchꢀOutputꢀMode,ꢀ
PWMꢀOutputꢀMode,ꢀSingleꢀPulseꢀOutputꢀMode,ꢀCaptureꢀInputꢀModeꢀorꢀTimer/CounterꢀMode.ꢀTheꢀ
operatingꢀmodeꢀisꢀselectedꢀusingꢀtheꢀPTnM1ꢀandꢀPTnM0ꢀbitsꢀinꢀtheꢀPTMnC1ꢀregister.
Compare Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀPTnM1ꢀandꢀPTnM0ꢀinꢀtheꢀPTMnC1ꢀregister,ꢀshouldꢀbeꢀsetꢀtoꢀ“00”ꢀ
respectively.ꢀInꢀthisꢀmodeꢀonceꢀtheꢀcounterꢀisꢀenabledꢀandꢀrunningꢀitꢀcanꢀbeꢀclearedꢀbyꢀthreeꢀ
methods.ꢀTheseꢀareꢀaꢀcounterꢀoverflow,ꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀandꢀaꢀcompareꢀmatchꢀ
fromꢀComparatorꢀP.ꢀWhenꢀtheꢀPTnCCLRꢀbitꢀisꢀlow,ꢀthereꢀareꢀtwoꢀwaysꢀinꢀwhichꢀtheꢀcounterꢀcanꢀbeꢀ
cleared.ꢀOneꢀisꢀwhenꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀP,ꢀtheꢀotherꢀisꢀwhenꢀtheꢀCCRPꢀbitsꢀareꢀallꢀ
zeroꢀwhichꢀallowsꢀtheꢀcounterꢀtoꢀoverflow.ꢀHereꢀbothꢀPTMnAFꢀandꢀPTMnPFꢀinterruptꢀrequestꢀflagsꢀ
forꢀComparatorꢀAꢀandꢀComparatorꢀPꢀrespectively,ꢀwillꢀbothꢀbeꢀgenerated.
IfꢀtheꢀPTnCCLRꢀbitꢀinꢀtheꢀPTMnC1ꢀregisterꢀisꢀhighꢀthenꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀ
matchꢀoccursꢀfromꢀComparatorꢀA.ꢀHowever,ꢀhereꢀonlyꢀtheꢀPTMnAFꢀinterruptꢀrequestꢀflagꢀwillꢀ
beꢀgeneratedꢀevenꢀifꢀtheꢀvalueꢀofꢀtheꢀCCRPꢀbitsꢀisꢀlessꢀthanꢀthatꢀofꢀtheꢀCCRAꢀregisters.ꢀThereforeꢀ
whenꢀPTnCCLRꢀisꢀhighꢀnoꢀPTMnPFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀgenerated.ꢀInꢀtheꢀCompareꢀMatchꢀ
OutputꢀMode,ꢀtheꢀCCRAꢀcanꢀnotꢀbeꢀclearedꢀtoꢀ“0”.
IfꢀtheꢀCCRAꢀbitsꢀareꢀallꢀzero,ꢀtheꢀcounterꢀwillꢀoverflowꢀwhenꢀitsꢀreachesꢀitsꢀmaximumꢀ10-bit,ꢀ3FFꢀ
Hex,ꢀvalue,ꢀhoweverꢀhereꢀtheꢀPTMnAFꢀinterruptꢀrequestꢀflagꢀwillꢀnotꢀbeꢀgenerated.
Asꢀtheꢀnameꢀofꢀtheꢀmodeꢀsuggests,ꢀafterꢀaꢀcomparisonꢀisꢀmade,ꢀtheꢀPTMnꢀoutputꢀpin,ꢀwillꢀchangeꢀ
state.ꢀTheꢀPTMnꢀoutputꢀpinꢀconditionꢀhoweverꢀonlyꢀchangesꢀstateꢀwhenꢀaꢀPTMnAFꢀinterruptꢀrequestꢀ
flagꢀisꢀgeneratedꢀafterꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀPTMnPFꢀinterruptꢀrequestꢀ
flag,ꢀgeneratedꢀfromꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀwillꢀhaveꢀnoꢀeffectꢀonꢀtheꢀPTMnꢀ
outputꢀpin.ꢀTheꢀwayꢀinꢀwhichꢀtheꢀPTMnꢀoutputꢀpinꢀchangesꢀstateꢀareꢀdeterminedꢀbyꢀtheꢀconditionꢀofꢀ
theꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀinꢀtheꢀPTMnC1ꢀregister.ꢀTheꢀPTMnꢀoutputꢀpinꢀcanꢀbeꢀselectedꢀusingꢀ
theꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀtoꢀgoꢀhigh,ꢀtoꢀgoꢀlowꢀorꢀtoꢀtoggleꢀfromꢀitsꢀpresentꢀconditionꢀwhenꢀaꢀ
compareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀinitialꢀconditionꢀofꢀtheꢀPTMnꢀoutputꢀpin,ꢀwhichꢀisꢀ
setupꢀafterꢀtheꢀPTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀisꢀsetupꢀusingꢀtheꢀPTnOCꢀbit.ꢀNoteꢀthatꢀifꢀtheꢀ
PTnIO1ꢀandꢀPTnIO0ꢀbitsꢀareꢀzeroꢀthenꢀnoꢀpinꢀchangeꢀwillꢀtakeꢀplace.
Rev. 1.10
107
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Coꢀnteꢁ oveꢁflow
CCRP=0
Coꢀnteꢁ Valꢀe
0x3FF
PTnCCLR = 0; PTnM [1:0] = 00
CCRP > 0
Coꢀnteꢁ cleaꢁed bꢂ CCRP valꢀe
CCRP > 0
Coꢀnteꢁ
Restaꢁt
Resꢀme
Paꢀse
CCRP
CCRA
Stop
Time
PTnON
PTnPAU
PTnPOL
CCRP Int. Flag
PTMnPF
CCRA Int. Flag
PTMnAF
PTMn O/P Pin
Oꢀtpꢀt not affected bꢂ
Oꢀtpꢀt Inveꢁts when
PTnPOL is high
PTMnAF flag. Remains High
ꢀntil ꢁeset bꢂ PTnON bit
Oꢀtpꢀt pin set to
initial Level Low if
PTnOC=0
Oꢀtpꢀt Toggle
with PTMnAF flag
Oꢀtpꢀt Pin
Reset to Initial valꢀe
Oꢀtpꢀt contꢁolled bꢂ otheꢁ
pin-shaꢁed fꢀnction
Heꢁe PTnIO [1:0] = 11
Toggle Oꢀtpꢀt select
Note PTnIO [1:0] = 10
Active High Oꢀtpꢀt select
Compare Match Output Mode – PTnCCLR=0 (n=0, 1 or 2)
Note:ꢀ1.ꢀWithꢀPTnCCLR=0ꢀaꢀComparatorꢀPꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀPTMnꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀPTMnAFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀPTnONꢀbitꢀrisingꢀedge
Rev. 1.10
10ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Coꢀnteꢁ Valꢀe
PTnCCLR = 1; PTnM [1:0] = 00
CCRA = 0
Coꢀnteꢁ oveꢁflow
CCRA > 0 Coꢀnteꢁ cleaꢁed bꢂ CCRA valꢀe
0x3FF
CCRA
CCRP
CCRA=0
Resꢀme
Paꢀse
Stop
Coꢀnteꢁ Restaꢁt
Time
PTnON
PTnPAU
PTnPOL
No PTMnAF flag
geneꢁated on
CCRA oveꢁflow
CCRA Int.
Flag PTMnAF
CCRP Int.
Flag PTMnPF
PTMnPF not
geneꢁated
Oꢀtpꢀt does
not change
PTMn O/P
Pin
Oꢀtpꢀt not affected bꢂ
PTMnAF flag. Remains High
ꢀntil ꢁeset bꢂ PTnON bit
Oꢀtpꢀt Inveꢁts
when PTnPOL is high
Oꢀtpꢀt Toggle
with PTMnAF flag
Oꢀtpꢀt pin set to
initial Level Low if
PTnOC=0
Oꢀtpꢀt Pin
Reset to Initial valꢀe
Oꢀtpꢀt contꢁolled bꢂ
otheꢁ pin-shaꢁed fꢀnction
Note PTnIO [1:0] = 10
Active High Oꢀtpꢀt select
Heꢁe PTnIO [1:0] = 11
Toggle Oꢀtpꢀt select
Compare Match Output Mode – PTnCCLR=1 (n=0, 1 or 2)
Note:ꢀ1.ꢀWithꢀPTnCCLR=1ꢀaꢀComparatorꢀAꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀPTMnꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀPTMnAFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀPTnONꢀbitꢀrisingꢀedge
4.ꢀAꢀPTMnPFꢀflagꢀisꢀnotꢀgeneratedꢀwhenꢀPTnCCLR=1
Rev. 1.10
109
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Timer/Counter Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀPTnM1ꢀandꢀPTnM0ꢀinꢀtheꢀPTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“11”ꢀ
respectively.ꢀTheꢀTimer/CounterꢀModeꢀoperatesꢀinꢀanꢀidenticalꢀwayꢀtoꢀtheꢀCompareꢀMatchꢀOutputꢀ
Modeꢀgeneratingꢀtheꢀsameꢀinterruptꢀflags.ꢀTheꢀexceptionꢀisꢀthatꢀinꢀtheꢀTimer/CounterꢀModeꢀtheꢀ
PTMnꢀoutputꢀpinꢀisꢀnotꢀused.ꢀThereforeꢀtheꢀaboveꢀdescriptionꢀandꢀTimingꢀDiagramsꢀforꢀtheꢀCompareꢀ
MatchꢀOutputꢀModeꢀcanꢀbeꢀusedꢀtoꢀunderstandꢀitsꢀfunction.ꢀAsꢀtheꢀPTMnꢀoutputꢀpinꢀisꢀnotꢀusedꢀinꢀ
thisꢀmode,ꢀtheꢀpinꢀcanꢀbeꢀusedꢀasꢀaꢀnormalꢀI/Oꢀpinꢀorꢀotherꢀpin-sharedꢀfunction.
PWM Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀPTnM1ꢀandꢀPTnM0ꢀinꢀtheꢀPTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“10”ꢀ
respectively.ꢀTheꢀPWMꢀfunctionꢀwithinꢀtheꢀPTMnꢀisꢀusefulꢀforꢀapplicationsꢀwhichꢀrequireꢀfunctionsꢀ
suchꢀasꢀmotorꢀcontrol,ꢀheatingꢀcontrol,ꢀilluminationꢀcontrolꢀetc.ꢀByꢀprovidingꢀaꢀsignalꢀofꢀfixedꢀ
frequencyꢀbutꢀofꢀvaryingꢀdutyꢀcycleꢀonꢀtheꢀPTMnꢀoutputꢀpin,ꢀaꢀsquareꢀwaveꢀACꢀwaveformꢀcanꢀbeꢀ
generatedꢀwithꢀvaryingꢀequivalentꢀDCꢀRMSꢀvalues.
AsꢀbothꢀtheꢀperiodꢀandꢀdutyꢀcycleꢀofꢀtheꢀPWMꢀwaveformꢀcanꢀbeꢀcontrolled,ꢀtheꢀchoiceꢀofꢀgeneratedꢀ
waveformꢀisꢀextremelyꢀflexible.ꢀInꢀtheꢀPWMꢀOutputꢀMode,ꢀtheꢀPTnCCLRꢀbitꢀhasꢀnoꢀeffectꢀonꢀtheꢀ
PWMꢀoperation.ꢀBothꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀtoꢀgenerateꢀtheꢀPWMꢀwaveform,ꢀ
oneꢀregisterꢀisꢀusedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀandꢀthusꢀcontrolꢀtheꢀPWMꢀwaveformꢀfrequency,ꢀ
whileꢀtheꢀotherꢀoneꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdutyꢀcycle.ꢀTheꢀPWMꢀwaveformꢀfrequencyꢀandꢀdutyꢀcycleꢀ
canꢀthereforeꢀbeꢀcontrolledꢀbyꢀtheꢀvaluesꢀinꢀtheꢀCCRAꢀandꢀCCRPꢀregisters.
Anꢀinterruptꢀflag,ꢀoneꢀforꢀeachꢀofꢀtheꢀCCRAꢀandꢀCCRP,ꢀwillꢀbeꢀgeneratedꢀwhenꢀaꢀcompareꢀmatchꢀ
occursꢀfromꢀeitherꢀComparatorꢀAꢀorꢀComparatorꢀP.ꢀTheꢀPTnOCꢀbitꢀinꢀtheꢀPTMnC1ꢀregisterꢀisꢀusedꢀ
toꢀselectꢀtheꢀrequiredꢀpolarityꢀofꢀtheꢀPWMꢀwaveformꢀwhileꢀtheꢀtwoꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀareꢀ
usedꢀtoꢀenableꢀtheꢀPWMꢀoutputꢀorꢀtoꢀforceꢀtheꢀPTMnꢀoutputꢀpinꢀtoꢀaꢀfixedꢀhighꢀorꢀlowꢀlevel.ꢀTheꢀ
PTnPOLꢀbitꢀisꢀusedꢀtoꢀreverseꢀtheꢀpolarityꢀofꢀtheꢀPWMꢀoutputꢀwaveform.
• 10-bit PTMn, PWM Output Mode, Edge-aligned Mode
CCRP
Peꢁiod
Dꢀtꢂ
1~1023
0
1~10ꢅ3
10ꢅꢃ
CCRA
IfꢀfSYS=12MHz,ꢀPTMnꢀclockꢀsourceꢀselectꢀfSYS/4,ꢀCCRP=512ꢀandꢀCCRA=128,ꢀ
TheꢀPTMnꢀPWMꢀoutputꢀfrequency=(fSYS/4)/512=fSYS/2048=5.8594kHz,ꢀduty=128/512=25%.ꢀ
IfꢀtheꢀDutyꢀvalueꢀdefinedꢀbyꢀtheꢀCCRAꢀregisterꢀisꢀequalꢀtoꢀorꢀgreaterꢀthanꢀtheꢀPeriodꢀvalue,ꢀthenꢀtheꢀ
PWMꢀoutputꢀdutyꢀisꢀ100%.ꢀ
Rev. 1.10
110
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Coꢀnteꢁ Valꢀe
PTnM [1:0] = 10
Coꢀnteꢁ cleaꢁed bꢂ
CCRP
Coꢀnteꢁ Reset when
PTnON ꢁetꢀꢁns high
CCRP
CCRA
Coꢀnteꢁ Stop if
PTnON bit low
Paꢀse
Resꢀme
Time
PTnON
PTnPAU
PTnPOL
CCRA Int. Flag
PTMnAF
CCRP Int. Flag
PTMnPF
PTMn O/P Pin
(PTnOC=1)
PTMn O/P Pin
(PTnOC=0)
PWM Dꢀtꢂ Cꢂcle
set bꢂ CCRA
PWM ꢁesꢀmes
opeꢁation
Oꢀtpꢀt contꢁolled bꢂ
otheꢁ pin-shaꢁed fꢀnction
PWM Peꢁiod set bꢂ CCRP
Oꢀtpꢀt Inveꢁts
When PTnPOL = 1
PWM Output Mode (n=0, 1 or 2)
Note:ꢀ1.ꢀCounterꢀclearedꢀbyꢀCCRP
2.ꢀAꢀcounterꢀclearꢀsetsꢀtheꢀPWMꢀPeriod
3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀPTnIO[1:0]=00ꢀorꢀ01
4.ꢀTheꢀPTnCCLRꢀbitꢀhasꢀnoꢀinfluenceꢀonꢀPWMꢀoperation
Rev. 1.10
111
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Single Pulse Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀPTnM1ꢀandꢀPTnM0ꢀinꢀtheꢀPTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“10”ꢀ
respectivelyꢀandꢀalsoꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ“11”ꢀrespectively.ꢀTheꢀSingleꢀ
PulseꢀOutputꢀMode,ꢀasꢀtheꢀnameꢀsuggests,ꢀwillꢀgenerateꢀaꢀsingleꢀshotꢀpulseꢀonꢀtheꢀPTMnꢀoutputꢀpin.
TheꢀtriggerꢀforꢀtheꢀpulseꢀoutputꢀleadingꢀedgeꢀisꢀaꢀlowꢀtoꢀhighꢀtransitionꢀofꢀtheꢀPTnONꢀbit,ꢀwhichꢀ
canꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogram.ꢀHoweverꢀinꢀtheꢀSingleꢀPulseꢀMode,ꢀtheꢀPTnONꢀ
bitꢀcanꢀalsoꢀbeꢀmadeꢀtoꢀautomaticallyꢀchangeꢀfromꢀlowꢀtoꢀhighꢀusingꢀtheꢀexternalꢀPTCKnꢀpin,ꢀ
whichꢀwillꢀinꢀturnꢀinitiateꢀtheꢀSingleꢀPulseꢀoutput.ꢀWhenꢀtheꢀPTnONꢀbitꢀtransitionsꢀtoꢀaꢀhighꢀlevel,ꢀ
theꢀcounterꢀwillꢀstartꢀrunningꢀandꢀtheꢀpulseꢀleadingꢀedgeꢀwillꢀbeꢀgenerated.ꢀTheꢀPTnONꢀbitꢀshouldꢀ
remainꢀhighꢀwhenꢀtheꢀpulseꢀisꢀinꢀitsꢀactiveꢀstate.ꢀTheꢀgeneratedꢀpulseꢀtrailingꢀedgeꢀwillꢀbeꢀgeneratedꢀ
whenꢀtheꢀPTnONꢀbitꢀisꢀclearedꢀtoꢀ“0”,ꢀwhichꢀcanꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogramꢀorꢀ
whenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.
HoweverꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀautomaticallyꢀclearꢀtheꢀPTnONꢀbitꢀandꢀ
thusꢀgenerateꢀtheꢀSingleꢀPulseꢀoutputꢀtrailingꢀedge.ꢀInꢀthisꢀwayꢀtheꢀCCRAꢀvalueꢀcanꢀbeꢀusedꢀtoꢀ
controlꢀtheꢀpulseꢀwidth.ꢀAꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀgenerateꢀaꢀPTMnꢀinterrupt.ꢀ
Theꢀcounterꢀcanꢀonlyꢀbeꢀresetꢀbackꢀtoꢀ“0”ꢀwhenꢀtheꢀPTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhenꢀtheꢀ
counterꢀrestarts.ꢀInꢀtheꢀSingleꢀPulseꢀOutputꢀModeꢀCCRPꢀisꢀnotꢀused.ꢀTheꢀPTnCCLRꢀbitꢀisꢀnotꢀusedꢀ
inꢀthisꢀMode.
CCRA
CCRA
Leading Edge
Trailing Edge
S/W Command SET "PTnON"
S/W Command CLR "PTnON"
or
CCRA Compare Match
PTnON bit
0 → 1
PTnON bit
1 → 0
or
PTCKn Pin Transition
PTPn Output Pin
Pulse Width = CCRA Value
Single Pulse Generation (n=0, 1 or 2)
Rev. 1.10
11ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Coꢀnteꢁ Valꢀe
PTnM [1:0] = 10 ; PTnIO [1:0] = 11
Coꢀnteꢁ stopped bꢂ
CCRA
Coꢀnteꢁ Reset when
PTnON ꢁetꢀꢁns high
CCRA
CCRP
Coꢀnteꢁ Stops bꢂ
softwaꢁe
Resꢀme
Paꢀse
Time
PTnON
Aꢀto. set bꢂ
PTCKn pin
Softwaꢁe Cleaꢁed bꢂ
Softwaꢁe
Tꢁiggeꢁ
Softwaꢁe
Cleaꢁ
Softwaꢁe
Tꢁiggeꢁ
Softwaꢁe
Tꢁiggeꢁ
Tꢁiggeꢁ
CCRA match
PTCKn pin
PTnPAU
PTCKn pin
Tꢁiggeꢁ
PTnPOL
No CCRP Inteꢁꢁꢀpts
geneꢁated
CCRP Int. Flag
PTMnPF
CCRA Int. Flag
PTMnAF
PTMn O/P Pin
(PTnOC=1)
PTMn O/P Pin
(PTnOC=0)
Oꢀtpꢀt Inveꢁts
when PTnPOL = 1
Pꢀlse Width
set bꢂ CCRA
Single Pulse Output Mode (n=0, 1 or 2)
Note:ꢀ1.ꢀCounterꢀstoppedꢀbyꢀCCRA
2.ꢀCCRPꢀisꢀnotꢀused
3.ꢀTheꢀpulseꢀisꢀtriggeredꢀbyꢀtheꢀPTCKnꢀpinꢀorꢀbyꢀsettingꢀtheꢀPTnONꢀbitꢀhigh
4.ꢀAꢀPTCKnꢀpinꢀactiveꢀedgeꢀwillꢀautomaticallyꢀsetꢀtheꢀPTnONꢀbitꢀhighꢀ
5.ꢀInꢀtheꢀSingleꢀPulseꢀOutputꢀMode,ꢀPTnIO[1:0]ꢀmustꢀbeꢀsetꢀtoꢀ“11”ꢀandꢀcannotꢀbeꢀchanged.ꢀ
Rev. 1.10
113
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Capture Input Mode
ToꢀselectꢀthisꢀmodeꢀbitsꢀPTnM1ꢀandꢀPTnM0ꢀinꢀtheꢀPTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“01”ꢀ
respectively.ꢀThisꢀmodeꢀenablesꢀexternalꢀsignalsꢀtoꢀcaptureꢀandꢀstoreꢀtheꢀpresentꢀvalueꢀofꢀtheꢀinternalꢀ
counterꢀandꢀcanꢀthereforeꢀbeꢀusedꢀforꢀapplicationsꢀsuchꢀasꢀpulseꢀwidthꢀmeasurements.ꢀTheꢀexternalꢀ
signalꢀisꢀsuppliedꢀonꢀtheꢀPTPnIꢀorꢀPTCKnꢀpinꢀwhichꢀisꢀselectedꢀusingꢀtheꢀPTnCAPTSꢀbitꢀinꢀtheꢀ
PTMnC1ꢀregister.ꢀTheꢀinputꢀpinꢀactiveꢀedgeꢀcanꢀbeꢀeitherꢀaꢀrisingꢀedge,ꢀaꢀfallingꢀedgeꢀorꢀbothꢀrisingꢀ
andꢀfallingꢀedges;ꢀtheꢀactiveꢀedgeꢀtransitionꢀtypeꢀisꢀselectedꢀusingꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀinꢀ
theꢀPTMnC1ꢀregister.ꢀTheꢀcounterꢀisꢀstartedꢀwhenꢀtheꢀPTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhichꢀisꢀ
initiatedꢀusingꢀtheꢀapplicationꢀprogram.
WhenꢀtheꢀrequiredꢀedgeꢀtransitionꢀappearsꢀonꢀtheꢀPTPnIꢀorꢀPTCKnꢀpinꢀtheꢀpresentꢀvalueꢀinꢀtheꢀ
counterꢀwillꢀbeꢀlatchedꢀintoꢀtheꢀCCRAꢀregistersꢀandꢀaꢀPTMnꢀinterruptꢀgenerated.ꢀIrrespectiveꢀ
ofꢀwhatꢀeventsꢀoccurꢀonꢀtheꢀPTPnIꢀorꢀPTCKnꢀpin,ꢀtheꢀcounterꢀwillꢀcontinueꢀtoꢀfreeꢀrunꢀuntilꢀtheꢀ
PTnONꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow.ꢀWhenꢀaꢀCCRPꢀcompareꢀmatchꢀoccursꢀtheꢀcounterꢀwillꢀresetꢀ
backꢀtoꢀ“0”;ꢀinꢀthisꢀwayꢀtheꢀCCRPꢀvalueꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀmaximumꢀcounterꢀvalue.ꢀWhenꢀaꢀ
CCRPꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀaꢀPTMnꢀinterruptꢀwillꢀalsoꢀbeꢀgenerated.ꢀCountingꢀ
theꢀnumberꢀofꢀoverflowꢀinterruptꢀsignalsꢀfromꢀtheꢀCCRPꢀcanꢀbeꢀaꢀusefulꢀmethodꢀinꢀmeasuringꢀ
longꢀpulseꢀwidths.ꢀTheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀcanꢀselectꢀtheꢀactiveꢀtriggerꢀedgeꢀonꢀtheꢀPTPnIꢀorꢀ
PTCKnꢀpinꢀtoꢀbeꢀaꢀrisingꢀedge,ꢀfallingꢀedgeꢀorꢀbothꢀedgeꢀtypes.ꢀIfꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀareꢀ
bothꢀsetꢀhigh,ꢀthenꢀnoꢀcaptureꢀoperationꢀwillꢀtakeꢀplaceꢀirrespectiveꢀofꢀwhatꢀhappensꢀonꢀtheꢀPTPnIꢀorꢀ
PTCKnꢀpin,ꢀhoweverꢀitꢀmustꢀbeꢀnotedꢀthatꢀtheꢀcounterꢀwillꢀcontinueꢀtoꢀrun.
AsꢀtheꢀPTPnIꢀorꢀPTCKnꢀpinꢀisꢀpinꢀsharedꢀwithꢀotherꢀfunctions,ꢀcareꢀmustꢀbeꢀtakenꢀifꢀtheꢀPTMnꢀisꢀinꢀ
theꢀCaptureꢀInputꢀMode.ꢀThisꢀisꢀbecauseꢀifꢀtheꢀpinꢀisꢀsetupꢀasꢀanꢀoutput,ꢀthenꢀanyꢀtransitionsꢀonꢀthisꢀ
pinꢀmayꢀcauseꢀanꢀinputꢀcaptureꢀoperationꢀtoꢀbeꢀexecuted.ꢀTheꢀPTnCCLR,ꢀPTnOCꢀandꢀPTnPOLꢀbitsꢀ
areꢀnotꢀusedꢀinꢀthisꢀMode.
Rev. 1.10
11ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Coꢀnteꢁ Valꢀe
PTnM[1:0] = 01
Coꢀnteꢁ cleaꢁed bꢂ
CCRP
Coꢀnteꢁ
Stop
Coꢀnteꢁ
Reset
CCRP
YY
Resꢀme
Paꢀse
XX
Time
PTnON
PTnPAU
Active
edge
Active
edge
Active edge
PTMn Captꢀꢁe Pin
PTPnI oꢁ PTCKn
CCRA Int.
Flag PTMnAF
CCRP Int.
Flag PTMnPF
XX
YY
XX
YY
CCRA Valꢀe
00 - Rising edge
01 - Falling edge
10 - Both edges
11 - Disable Captꢀꢁe
PTnIO [1:0] Valꢀe
Capture Input Mode (n=0, 1 or 2)
Note:ꢀ1.ꢀPTnM[1:0]=01ꢀandꢀactiveꢀedgeꢀsetꢀbyꢀtheꢀPTnIO[1:0]ꢀbits
2.ꢀAꢀPTMnꢀCaptureꢀinputꢀpinꢀactiveꢀedgeꢀtransfersꢀtheꢀcounterꢀvalueꢀtoꢀCCRA
3.ꢀPTnCCLRꢀbitꢀnotꢀused
4.ꢀNoꢀoutputꢀfunctionꢀ–ꢀPTnOCꢀandꢀPTnPOLꢀbitsꢀareꢀnotꢀusedꢀ
5.ꢀCCRPꢀdeterminesꢀtheꢀcounterꢀvalueꢀandꢀtheꢀcounterꢀhasꢀaꢀmaximumꢀcountꢀvalueꢀwhenꢀCCRPꢀisꢀequalꢀtoꢀ“0”.
Rev. 1.10
115
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Analog to Digital Converter – ADC
Theꢀneedꢀtoꢀinterfaceꢀtoꢀrealꢀworldꢀanalogꢀsignalsꢀisꢀaꢀcommonꢀrequirementꢀforꢀmanyꢀelectronicꢀ
systems.ꢀHowever,ꢀtoꢀproperlyꢀprocessꢀtheseꢀsignalsꢀbyꢀaꢀmicrocontroller,ꢀtheyꢀmustꢀfirstꢀbeꢀ
convertedꢀintoꢀdigitalꢀsignalsꢀbyꢀA/Dꢀconverters.ꢀByꢀintegratingꢀtheꢀA/Dꢀconversionꢀelectronicꢀ
circuitryꢀintoꢀtheꢀmicrocontroller,ꢀtheꢀneedꢀforꢀexternalꢀcomponentsꢀisꢀreducedꢀsignificantlyꢀwithꢀtheꢀ
correspondingꢀfollow-onꢀbenefitsꢀofꢀlowerꢀcostsꢀandꢀreducedꢀcomponentꢀspaceꢀrequirements.
A/D Overview
Eachꢀdeviceꢀcontainsꢀaꢀhighꢀaccuracyꢀmulti-channelꢀ24-bitꢀDeltaꢀSigmaꢀAnalog-to-DigitalꢀConverterꢀ
whichꢀcanꢀdirectlyꢀinterfaceꢀtoꢀexternalꢀanalogꢀsignals,ꢀsuchꢀasꢀthatꢀfromꢀsensorsꢀorꢀotherꢀcontrolꢀ
signalsꢀandꢀconvertꢀtheseꢀsignalsꢀdirectlyꢀintoꢀaꢀ24-bitꢀdigitalꢀvalue.
Inꢀaddition,ꢀtheꢀPGAꢀgainꢀcontrol,ꢀA/DꢀconverterꢀgainꢀcontrolꢀandꢀA/Dꢀconverterꢀreferenceꢀgainꢀ
controlꢀdetermineꢀtheꢀamplificationꢀgainꢀforꢀA/Dꢀconverterꢀinputꢀsignal.ꢀTheꢀdesignerꢀcanꢀselectꢀ
theꢀbestꢀgainꢀcombinationꢀforꢀtheꢀdesiredꢀamplificationꢀappliedꢀtoꢀtheꢀinputꢀsignal.ꢀTheꢀfollowingꢀ
blockꢀdiagramꢀillustratesꢀtheꢀA/Dꢀconverterꢀbasicꢀoperationalꢀfunction.ꢀTheꢀA/Dꢀconverterꢀinputꢀ
channelꢀcanꢀbeꢀarrangedꢀasꢀfourꢀsingle-endedꢀA/Dꢀinputꢀchannelsꢀorꢀtwoꢀdifferentialꢀinputꢀchannels.ꢀ
TheꢀinputꢀsignalꢀcanꢀbeꢀamplifiedꢀbyꢀPGAꢀbeforeꢀenteringꢀtheꢀ24-bitꢀDeltaꢀSigmaꢀA/Dꢀconverter.ꢀ
TheꢀDeltaꢀSigmaꢀA/DꢀconverterꢀmodulatorꢀwillꢀoutputꢀoneꢀbitꢀconvertedꢀdataꢀtoꢀSINCꢀfilterꢀwhichꢀ
canꢀtransformꢀtheꢀconvertedꢀone-bitꢀdataꢀtoꢀ24ꢀbitsꢀandꢀstoreꢀthemꢀintoꢀtheꢀspecificꢀdataꢀregisters.ꢀ
Additionally,ꢀtheꢀdevicesꢀalsoꢀprovideꢀaꢀtemperatureꢀsensorꢀtoꢀcompensateꢀtheꢀA/Dꢀconverterꢀ
deviationꢀcausedꢀbyꢀtheꢀtemperature.ꢀWithꢀhighꢀaccuracyꢀandꢀperformance,ꢀtheꢀdevicesꢀareꢀveryꢀ
suitableꢀforꢀtheꢀWeightꢀScaleꢀrelatedꢀproducts.
Internal Power Supply
EachꢀdeviceꢀcontainsꢀanꢀLDOꢀandꢀVCMꢀforꢀtheꢀregulatedꢀpowerꢀsupply.ꢀTheꢀaccompanyingꢀblockꢀ
diagramꢀillustratesꢀtheꢀbasicꢀfunctionalꢀoperation.ꢀTheꢀinternalꢀLDOꢀcanꢀprovideꢀtheꢀfixedꢀvoltageꢀ
forꢀPGA,ꢀA/Dꢀconverterꢀorꢀtheꢀexternalꢀcomponents;ꢀasꢀwellꢀtheꢀVCMꢀcanꢀbeꢀusedꢀasꢀtheꢀreferenceꢀ
voltageꢀforꢀA/Dꢀconverterꢀmodule.ꢀThereꢀareꢀfourꢀLDOꢀvoltageꢀlevels,ꢀ2.4V,ꢀ2.6V,ꢀ2.9Vꢀorꢀ3.3V,ꢀ
decidedꢀbyꢀLDOVS1~LDOVS0ꢀbitsꢀinꢀtheꢀPWRCꢀregister,ꢀasꢀwellꢀtheꢀVCMꢀvoltageꢀisꢀfixedꢀatꢀ1.25V.ꢀ
TheꢀLDOꢀandꢀVCMꢀfunctionsꢀcanꢀbeꢀcontrolledꢀbyꢀtheꢀLDOENꢀbitꢀandꢀcanꢀbeꢀpoweredꢀoffꢀtoꢀreduceꢀ
theꢀpowerꢀconsumption.ꢀIfꢀtheꢀVCMꢀisꢀdisabled,ꢀtheꢀVCMꢀoutputꢀpinꢀisꢀfloating.ꢀ
LDO
VIN
VOREG
(Sꢀpplꢂ voltage foꢁ
A/D conveꢁteꢁ & PGA)
ꢅ.ꢃV
ꢅ.6V
ꢅ.9V
3.3V
LDOEN
LDOBPS
LDOVS[1:0]
VCM
1.ꢅ5V
VCM
ADOFF
(Common mode voltage foꢁ
A/D conveꢁteꢁ & D/A conveꢁteꢁ)
Internal Power Supply Block Diagram
Rev. 1.10
116
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Register bits
Output Voltage
ADOFF
LDOEN
Bandgap
Off
VOREG
Disable
Enable
Disable
Enable
VCM
1
1
0
0
0
1
0
1
Disable
Enable
Enable
Enable
On
On
On
Power Control Table
PWRC Register
Bit
Name
R/W
7
LDOEN
R/W
0
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
LDOBPS LDOVS1 LDOVS0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7
LDOEN:ꢀLDOꢀfunctionꢀcontrolꢀbit
0:ꢀDisable
1:ꢀEnable
IfꢀtheꢀLDOꢀisꢀdisabled,ꢀthereꢀwillꢀbeꢀnoꢀpowerꢀconsumptionꢀandꢀLDOꢀoutputꢀwillꢀbeꢀinꢀ
aꢀlowꢀlevelꢀbyꢀaꢀweaklyꢀpull-lowꢀresistor.
Bitꢀ6~3ꢀ
Bitꢀ2
Unimplemented,ꢀreadꢀasꢀ“0”
LDOBPS:ꢀLDOꢀBypassꢀfunctionꢀcontrolꢀbit
0:ꢀDisable
1:ꢀEnable
Bitꢀ1~0
LDOVS1~LDOVS0:ꢀLDOꢀoutputꢀvoltageꢀselection
00:ꢀ2.4V
01:ꢀ2.6V
10:ꢀ2.9V
11:ꢀ3.3V
A/D Data Rate Definition
TheꢀDeltaꢀSigmaꢀA/Dꢀconverterꢀdataꢀrateꢀcanꢀbeꢀcalculatedꢀusingꢀtheꢀfollowingꢀequation:
fADCK fMCLK /N fMCLK
CHOP OSR CHOP OSR NCHOP OSR
Data Rate
fADCK:ꢀA/Dꢀclockꢀinput,ꢀderivedꢀfromꢀfMCLK/N
fMCLK:ꢀA/Dꢀclockꢀsource,ꢀderivedꢀfromꢀfSYSꢀorꢀfSYS/2/(ADCK+1)ꢀusingꢀtheꢀADCKꢀbitꢀfield.
N:ꢀaꢀconstantꢀdividedꢀfactorꢀthatꢀcanꢀbeꢀequalꢀtoꢀ30ꢀorꢀ12ꢀdeterminedꢀbyꢀtheꢀFLMSꢀbitꢀfield.
CHOP:ꢀSamplingꢀdataꢀamountꢀdoublingꢀfunctionꢀcontrolꢀandꢀcanꢀbeꢀequalꢀtoꢀ2ꢀorꢀ1ꢀdeterminedꢀbyꢀ
theꢀFLMSꢀbitꢀfield.
OSR:ꢀOversamplingꢀrateꢀdeterminedꢀbyꢀtheꢀADORꢀfield.
Forꢀexample ifꢀaꢀdataꢀrateꢀofꢀ8Hzꢀisꢀdesired anꢀfMCLKꢀclockꢀsourceꢀwithꢀaꢀfrequencyꢀofꢀ4MHzꢀ
,
,
A/Dꢀconverterꢀcanꢀbeꢀselected.ꢀThenꢀsetꢀtheꢀFLMSꢀfieldꢀtoꢀ“000”ꢀtoꢀobtainꢀanꢀ“N”ꢀequalꢀtoꢀ30ꢀandꢀ
“CHOP”ꢀequalꢀtoꢀ2.ꢀFinally,ꢀsetꢀtheꢀADORꢀfieldꢀtoꢀ“001”ꢀtoꢀselectꢀanꢀoversamplingꢀrateꢀequalꢀtoꢀ
8192.ꢀTherefore,ꢀtheꢀDataꢀRateꢀ=ꢀ4MHzꢀ/ꢀ(30ꢀ×ꢀ2ꢀ×ꢀ8192)ꢀ=ꢀ8Hz.
NoteꢀthatꢀtheꢀA/DꢀconverterꢀhasꢀaꢀnotchꢀrejectionꢀfunctionꢀforꢀanꢀACꢀpowerꢀsupplyꢀwithꢀaꢀfrequencyꢀ
ofꢀ50Hzꢀorꢀ60Hzꢀwhenꢀtheꢀdataꢀrateꢀisꢀequalꢀtoꢀ10Hz.
Rev. 1.10
117
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
ADCK[4:0]
fSYS
fMCLK
CHSP[3:0]
Divider
AN0
AN2
AGS[1:0]
DCSET[2:0]
ADOFF
ADOFF
ADSLP
ADOFF ADRST
IN1
RFC
VCM
VTSOP
ADGN = x1, x2, x4, x8
A/D Converter
Interrupt
PGAOP
PGA
EOC
24
DI+
fADCK
24-bit ∆-Σ
A/D Converter
PGAGN=x1, x2, x4, x8,
x16, x32, x64, x128
INX
VCM
SINC Filter
INIS
ADRH
ADRM
ADRL
DI−
INX[1:0]
PGAON
AN1
AN3
VREFGN = x1, x1/2, x1/4
REFN
ADCDL
REFP
IN2
VCM
VTSON
PGS[2:0]
VGS[1:0]
ADOR[2:0]
VRBUFN
FLMS[2:0]
VIN VCM VOREG
VRBUFP
CHSN[3:0]
DSDACVRS[1:0]
VREFS
VRP
0
VRN
1
1
0
VDACO
12-bit
DSDAC[11:0]
D/A Converter
VCM
AVSS
VREFP
VREFN
DSDACEN
A/D Converter Structure
A/D Converter Register Description
OverallꢀoperationꢀofꢀtheꢀA/Dꢀconverterꢀisꢀcontrolledꢀbyꢀusingꢀ13ꢀregisters.ꢀThreeꢀreadꢀonlyꢀregistersꢀ
existꢀtoꢀstoreꢀtheꢀA/Dꢀconverterꢀdataꢀ24-bitꢀvalue.ꢀAꢀcontrolꢀregisterꢀnamedꢀasꢀPWRCꢀisꢀusedꢀtoꢀcontrolꢀ
theꢀrequiredꢀbiasꢀandꢀsupplyꢀvoltagesꢀforꢀPGAꢀandꢀA/Dꢀconverterꢀandꢀisꢀdescribedꢀinꢀtheꢀ“Internalꢀ
PowerꢀSupply”ꢀsection.ꢀThreeꢀregistersꢀareꢀD/Aꢀconverterꢀcontrolꢀregisters.ꢀTheꢀremainingꢀ6ꢀregistersꢀ
areꢀcontrolꢀregistersꢀwhichꢀsetꢀupꢀtheꢀgainꢀselectionsꢀandꢀcontrolꢀfunctionsꢀofꢀtheꢀA/Dꢀconverter.
Bit
Register
Name
7
—
6
VGS1
INIS
CHSNꢅ
D6
5
VGS0
INX1
4
3
2
1
0
PGS0
—
PGAC0
PGAC1
PGACS
ADRL
AGS1
INX0
CHSN0
Dꢃ
AGS0
PGSꢅ
PGS1
—
DCSETꢅ DCSET1 DCSET0
CHSN3
D7
CHSN1
D5
CHSP3
D3
CHSPꢅ
Dꢅ
CHSP1 CHSP0
D1
D9
D0
Dꢆ
ADRM
D15
Dꢅ3
ADRST
FLMSꢅ
—
D1ꢃ
D13
D1ꢅ
D11
D10
ADRH
Dꢅꢅ
Dꢅ1
Dꢅ0
D19
D1ꢆ
D17
—
D16
VREFS
—
ADCR0
ADCR1
ADCS
ADSLP
FLMS1
—
ADOFF
FLMS0
—
ADORꢅ
ADOR1 ADOR0
VRBUFN VRBUFP ADCDL
EOC
ADCKꢃ
Dꢆ
ADCK3
D7
ADCKꢅ
D6
ADCK1 ADCK0
DSDAH
DSDAL
DSDACC
D11
—
D10
D9
D5
D1
—
Dꢃ
D0
—
—
—
—
D3
Dꢅ
DSDACEN DSDACVRS1
DSDACVRS0
—
—
—
A/D Converter Register List
Rev. 1.10
11ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Programmable Gain Amplifier – PGA
Thereꢀareꢀthreeꢀregistersꢀrelatedꢀtoꢀtheꢀprogrammableꢀgainꢀcontrol,ꢀPGAC0,ꢀPGAC1ꢀandꢀPGACS.ꢀ
TheꢀPGAC0ꢀresisterꢀisꢀusedꢀtoꢀselectꢀtheꢀPGAꢀgain,ꢀA/DꢀconverterꢀgainꢀandꢀtheꢀA/Dꢀconverterꢀ
referenceꢀgain.ꢀAsꢀwell,ꢀtheꢀPGAC1ꢀregisterꢀisꢀusedꢀtoꢀdefineꢀtheꢀinputꢀconnectionꢀandꢀdifferentialꢀ
inputꢀoffsetꢀvoltageꢀadjustmentꢀcontrol.ꢀInꢀaddition,ꢀTheꢀPGACSꢀregisterꢀisꢀusedꢀtoꢀselectꢀtheꢀ
inputꢀendsꢀforꢀtheꢀPGA.ꢀTherefore,ꢀtheꢀinputꢀchannelsꢀhaveꢀtoꢀbeꢀdeterminedꢀbyꢀtheꢀCHSP[3:0]ꢀ
andꢀCHSN[3:0]ꢀbitsꢀtoꢀdetermineꢀwhichꢀanalogꢀchannelꢀinputꢀpins,ꢀtemperatureꢀdetectorꢀinputsꢀorꢀ
internalꢀpowerꢀsupplyꢀareꢀactuallyꢀconnectedꢀtoꢀtheꢀinternalꢀdifferentialꢀA/Dꢀconverter.
PGAC0 Register
Bit
Name
R/W
7
6
VGS1
R/W
0
5
VGS0
R/W
0
4
AGS1
R/W
0
3
AGS0
R/W
0
2
PGSꢅ
R/W
0
1
PGS1
R/W
0
0
PGS0
R/W
0
—
—
—
POR
Bitꢀ7ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ6~5
VGS1~VGS0:ꢀREFP/REFNꢀDifferentialꢀReferenceꢀVoltageꢀGainꢀSelection
00:ꢀVREFGN=1
01:ꢀVREFGN=1/2
10:ꢀVREFGN=1/4
11:ꢀReserved
Bitꢀ4~3
AGS1~AGS0:ꢀA/DꢀConverterꢀPGAOP/PGAONꢀDifferentialꢀInputꢀSignalꢀGainꢀ
Selection
00:ꢀADGN=1
01:ꢀADGN=2
10:ꢀADGN=4
11:ꢀADGN=8
Bitꢀ2~0
PGS2~PGS0:ꢀPGAꢀDI+/DI-ꢀDifferentialꢀChannelꢀInputꢀGainꢀSelection
000:ꢀPGAGN=1
001:ꢀPGAGN=2
010:ꢀPGAGN=4
011:ꢀPGAGN=8
100:ꢀPGAGN=16
101:ꢀPGAGN=32
110:ꢀPGAGN=64
111:ꢀPGAGN=128
Rev. 1.10
119
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
PGAC1 Register
Bit
Name
R/W
7
6
5
INX1
R/W
0
4
INX0
R/W
0
3
2
1
0
—
—
—
INIS
R/W
0
DCSETꢅ DCSET1 DCSET0
—
—
—
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7ꢀ
Bitꢀ6
Unimplemented,ꢀreadꢀasꢀ“0”
INIS:ꢀTheꢀSelectedꢀInputꢀEnds,ꢀIN1ꢀandꢀIN2ꢀInternalꢀConnectionꢀControlꢀBit
0:ꢀNotꢀconnected
1:ꢀConnected
Bitꢀ5~4
Bitꢀ3~1
INX1, INX0:ꢀTheꢀSelectedꢀInputꢀEnds,ꢀIN1/IN2ꢀandꢀtheꢀPGAꢀDifferentialꢀInputꢀEnds,ꢀ
DI+/DI-ꢀConnectionꢀControlꢀBits
INX[1,0]=00
INX[1,0]=01
INX[1,0]=10
INX[1,0]=11
IN1
INꢅ
DI+
DI-
IN1
INꢅ
DI+
DI-
IN1
INꢅ
DI+
DI-
IN1
INꢅ
DI+
DI-
DCSET2~DCSET0:ꢀDifferentialꢀInputꢀSignalꢀPGAOP/PGAONꢀOffsetꢀSelection
000:ꢀDCSETꢀ=ꢀ+0V
001:ꢀDCSETꢀ=ꢀ+0.25×ΔVR_I
010:ꢀDCSETꢀ=ꢀ+0.5×ΔVR_I
011:ꢀDCSETꢀ=ꢀ+0.75×ΔVR_I
100:ꢀDCSETꢀ=ꢀ+0V
101:ꢀDCSETꢀ=ꢀ-0.25×ΔVR_I
110:ꢀDCSETꢀ=ꢀ-0.5×ΔVR_I
111:ꢀDCSETꢀ=ꢀ-0.75×ΔVR_I
Theꢀvoltage,ꢀΔVR_I,ꢀisꢀtheꢀdifferentialꢀreferenceꢀvoltageꢀwhichꢀisꢀamplifiedꢀbyꢀspecificꢀ
gainꢀselectionꢀbasedꢀonꢀtheꢀselectedꢀinputs.
Bitꢀ0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Rev. 1.10
1ꢅ0
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
PGACS Register
Bit
Name
R/W
7
CHSN3
R/W
0
6
CHSNꢅ
R/W
0
5
CHSN1
R/W
0
4
CHSN0
R/W
0
3
CHSP3
R/W
0
2
CHSPꢅ
R/W
0
1
CHSP1
R/W
0
0
CHSP0
R/W
0
POR
Bitꢀ7~4
CHSN3~CHSN0:ꢀNegativeꢀInputꢀEndꢀIN2ꢀSelection
0000:ꢀAN1
0001:ꢀAN3
0010:ꢀReserved
0011:ꢀReserved
0100:ꢀReserved
0101:ꢀVDACO
0110:ꢀVCM
0111:ꢀTemperatureꢀsensorꢀoutputꢀ–ꢀVTSON
1xxx:ꢀReserved
Theseꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀnegativeꢀinput,ꢀIN2.ꢀIfꢀtheꢀIN2ꢀinputꢀisꢀselectedꢀasꢀ
aꢀsingleꢀendꢀinput,ꢀtheꢀVCMꢀvoltageꢀmustꢀbeꢀselectedꢀasꢀtheꢀpositiveꢀinputꢀonꢀIN1ꢀforꢀ
singleꢀendꢀinputꢀapplications.ꢀItꢀisꢀrecommendedꢀthatꢀwhenꢀtheꢀVTSONꢀsignalꢀisꢀselectedꢀ
asꢀtheꢀnegativeꢀinput,ꢀtheꢀVTSOPꢀsignalꢀshouldꢀbeꢀselectedꢀasꢀtheꢀpositiveꢀinputꢀforꢀ
properꢀoperations.
Bitꢀ3~0
CHSP3~CHSP0:ꢀPositiveꢀInputꢀEndꢀIN1Selection
0000:ꢀAN0
0001:ꢀAN2
0010:ꢀReserved
0011:ꢀReserved
0100:ꢀReserved
0101:ꢀVDACO
0110:ꢀVCM
ꢀ
0111:ꢀTemperatureꢀsensorꢀoutputꢀ–ꢀVTSOP
1xxx:ꢀRFC
Theseꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀpositiveꢀinput,ꢀIN1.ꢀIfꢀtheꢀIN1ꢀinputꢀisꢀselectedꢀasꢀaꢀ
singleꢀendꢀinput,ꢀtheꢀVCMꢀvoltageꢀmustꢀbeꢀselectedꢀasꢀtheꢀnegativeꢀinputꢀonꢀIN2ꢀforꢀ
singleꢀendꢀinputꢀapplications.ꢀItꢀisꢀrecommendedꢀthatꢀwhenꢀtheꢀVTSOPꢀsignalꢀisꢀselectedꢀ
asꢀtheꢀpositiveꢀinput,ꢀtheꢀVTSONꢀsignalꢀshouldꢀbeꢀselectedꢀasꢀtheꢀnegativeꢀinputꢀforꢀ
properꢀoperations
Rev. 1.10
1ꢅ1
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
D/A Converter Registers – DSDAH, DSDAL, DSDACC
ThereꢀareꢀthreeꢀregistersꢀrelatedꢀtoꢀtheꢀD/Aꢀconverterꢀoutputꢀcontrol.ꢀ
• DSDAH Register
Bit
Name
R/W
7
6
5
D9
R/W
0
4
Dꢆ
R/W
0
3
D7
R/W
0
2
D6
R/W
0
1
D5
R/W
0
0
Dꢃ
R/W
0
D11
R/W
0
D10
R/W
0
POR
Bitꢀ7~0
D11~D4:ꢀD/AꢀConverterꢀOutputꢀControlꢀCode,ꢀOnlyꢀforꢀ12ꢀbitsꢀD/AꢀConverter
• DSDAL Register
Bit
Name
R/W
7
6
5
4
3
D3
R/W
0
2
Dꢅ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~4ꢀ
Bitꢀ3~0
Unimplemented,ꢀreadꢀasꢀ“0”
D3~D0:ꢀD/AꢀConverterꢀOutputꢀControlꢀCode
Note:ꢀwritingꢀthisꢀregisterꢀonlyꢀwritesꢀtoꢀshadowꢀbuffer,ꢀandꢀuntilꢀwriteꢀDSDAHꢀ
registerꢀwillꢀalsoꢀcopyꢀtheꢀshadowꢀbufferꢀdataꢀtoꢀDSDALꢀregister.
• DSDACC Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
DSDACEN DSDACVRS1 DSDACVRS0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7
DSDACEN:ꢀD/AꢀConverterꢀEnableꢀorꢀDisableꢀControlꢀBit
0:ꢀDisable
1:ꢀEnable
Bitꢀ6~5
Bitꢀ4~0ꢀ
DSDACVRS1~DSDACVRS0:ꢀD/AꢀConverterꢀReferenceꢀVoltageꢀSelection
00:ꢀD/AꢀconverterꢀreferenceꢀvoltageꢀcomesꢀfromꢀVOREG
01:ꢀD/AꢀconverterꢀreferenceꢀvoltageꢀcomesꢀfromꢀVIN
1x:ꢀD/AꢀconverterꢀreferenceꢀvoltageꢀcomesꢀfromꢀVCM
Unimplemented,ꢀreadꢀasꢀ“0”
Rev. 1.10
1ꢅꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
A/D Converter Data Registers – ADRL, ADRM, ADRH
Eachꢀdeviceꢀcontainsꢀanꢀinternalꢀ24-bitꢀDeltaꢀSigmaꢀA/DꢀConverter,ꢀitꢀrequiresꢀthreeꢀdataꢀregistersꢀ
toꢀstoreꢀtheꢀconvertedꢀvalue.ꢀTheseꢀareꢀaꢀhighꢀbyteꢀregister,ꢀknownꢀasꢀADRH,ꢀaꢀmiddleꢀbyteꢀregister,ꢀ
knownꢀasꢀADRM,ꢀandꢀaꢀlowꢀbyteꢀregister,ꢀknownꢀasꢀADRL.ꢀAfterꢀtheꢀconversionꢀprocessꢀtakesꢀ
place,ꢀtheseꢀregistersꢀcanꢀbeꢀdirectlyꢀreadꢀbyꢀtheꢀmicrocontrollerꢀtoꢀobtainꢀtheꢀdigitisedꢀconversionꢀ
value.ꢀD0~D23ꢀareꢀtheꢀA/Dꢀconversionꢀresultꢀdataꢀbits.
• ADRL Register
Bit
Name
R/W
7
D7
R
6
D6
R
5
D5
R
4
Dꢃ
R
3
D3
R
2
Dꢅ
R
1
D1
R
0
D0
R
POR
x
x
x
x
x
x
x
x
“x” ꢀnknown
Bitꢀ7~0
D7~D0:ꢀA/DꢀConversionꢀDataꢀRegisterꢀbitꢀ7~bitꢀ0
• ADRM Register
Bit
Name
R/W
7
D15
R
6
D1ꢃ
R
5
D13
R
4
D1ꢅ
R
3
D11
R
2
D10
R
1
D9
R
0
Dꢆ
R
POR
x
x
x
x
x
x
x
x
“x” ꢀnknown
Bitꢀ7~0
D15~D8:ꢀA/DꢀConversionꢀDataꢀRegisterꢀbitꢀ15~bitꢀ8
• ADRH Register
Bit
Name
R/W
7
Dꢅ3
R
6
Dꢅꢅ
R
5
Dꢅ1
R
4
Dꢅ0
R
3
D19
R
2
D1ꢆ
R
1
D17
R
0
D16
R
POR
x
x
x
x
x
x
x
x
“x” ꢀnknown
Bitꢀ7~0
D23~D16:ꢀA/DꢀConversionꢀDataꢀRegisterꢀbitꢀ23~bitꢀ16
Rev. 1.10
1ꢅ3
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
A/D Converter Control Registers − ADCR0, ADCR1, ADCS
ToꢀcontrolꢀtheꢀfunctionꢀandꢀoperationꢀofꢀtheꢀA/Dꢀconverter,ꢀthreeꢀcontrolꢀregistersꢀknownꢀasꢀADCR0,ꢀ
ADCR1ꢀandꢀADCSꢀareꢀprovided.ꢀTheseꢀ8-bitꢀregistersꢀdefineꢀfunctionsꢀsuchꢀasꢀtheꢀselectionꢀofꢀ
whichꢀreferenceꢀsourceꢀisꢀusedꢀforꢀtheꢀinternalꢀA/Dꢀconverter,ꢀtheꢀA/Dꢀconverterꢀclockꢀsource,ꢀtheꢀ
A/Dꢀconverterꢀoutputꢀdataꢀrateꢀasꢀwellꢀasꢀcontrollingꢀtheꢀpower-upꢀfunctionꢀandꢀmonitoringꢀtheꢀA/Dꢀ
converterꢀendꢀofꢀconversionꢀstatus.ꢀ
• ADCR0 Register
Bit
Name
R/W
7
ADRST
R/W
0
6
ADSLP
R/W
0
5
ADOFF
R/W
1
4
ADORꢅ
R/W
0
3
ADOR1
R/W
0
2
ADOR0
R/W
0
1
0
VREFS
R/W
0
—
—
—
POR
Bitꢀ7ꢀ
ADRST:ꢀA/DꢀConverterꢀSoftwareꢀResetꢀControlꢀbit.
0:ꢀDisable
1:ꢀEnable
ThisꢀbitꢀisꢀusedꢀtoꢀresetꢀtheꢀA/DꢀconverterꢀinternalꢀdigitalꢀSINCꢀfilter.ꢀThisꢀbitꢀisꢀsetꢀ
lowꢀforꢀA/Dꢀnormalꢀoperations.ꢀHowever,ꢀifꢀsetꢀhigh,ꢀtheꢀinternalꢀdigitalꢀSINCꢀfilterꢀ
willꢀbeꢀresetꢀandꢀtheꢀcurrentꢀA/Dꢀconvertedꢀdataꢀwillꢀbeꢀaborted.ꢀAꢀnewꢀA/Dꢀdataꢀ
conversionꢀprocessꢀwillꢀnotꢀbeꢀinitiatedꢀuntilꢀthisꢀbitꢀisꢀsetꢀlowꢀagain.
Bitꢀ6
ADSLP:ꢀA/DꢀConverterꢀSleepꢀModeꢀControlꢀbit
0:ꢀNormalꢀmode
1:ꢀSleepꢀmode
ThisꢀbitꢀisꢀusedꢀtoꢀdetermineꢀwhetherꢀtheꢀA/Dꢀconverterꢀentersꢀtheꢀsleepꢀmodeꢀorꢀ
notꢀwhenꢀtheꢀA/DꢀconverterꢀisꢀpoweredꢀonꢀbyꢀsettingꢀtheꢀADOFFꢀbitꢀlow.ꢀWhenꢀtheꢀ
A/DꢀconverterꢀisꢀpoweredꢀonꢀandꢀtheꢀADSLPꢀbitꢀisꢀlow,ꢀtheꢀA/Dꢀconverterꢀwillꢀoperateꢀ
normally.ꢀHowever,ꢀtheꢀA/DꢀconverterꢀwillꢀenterꢀtheꢀsleepꢀmodeꢀifꢀtheꢀADSLPꢀbitꢀisꢀ
setꢀhighꢀasꢀtheꢀA/Dꢀconverterꢀhasꢀbeenꢀpoweredꢀon.ꢀTheꢀwholeꢀA/Dꢀconverterꢀcircuitꢀ
willꢀbeꢀswitchedꢀoffꢀexceptꢀtheꢀPGAꢀandꢀinternalꢀBandgapꢀcircuitꢀtoꢀreduceꢀtheꢀpowerꢀ
consumptionꢀandꢀVCMꢀstart-upꢀstableꢀtime.
Bitꢀ5
ADOFF:ꢀA/DꢀConverterꢀModuleꢀPowerꢀOn/OffꢀControlꢀbit
0:ꢀPowerꢀon
1:ꢀPowerꢀoff
ThisꢀbitꢀcontrolsꢀtheꢀpowerꢀofꢀtheꢀA/Dꢀconverterꢀmodule.ꢀThisꢀbitꢀshouldꢀbeꢀclearedꢀ
toꢀ“0”ꢀtoꢀenableꢀtheꢀA/Dꢀconverter.ꢀIfꢀtheꢀbitꢀisꢀsetꢀhighꢀthenꢀtheꢀA/Dꢀconverterꢀwillꢀ
beꢀswitchedꢀoffꢀreducingꢀtheꢀdeviceꢀpowerꢀconsumption.ꢀAsꢀtheꢀA/Dꢀconverterꢀwillꢀ
consumeꢀaꢀlimitedꢀamountꢀofꢀpower,ꢀevenꢀwhenꢀnotꢀexecutingꢀaꢀconversion,ꢀthisꢀmayꢀ
beꢀanꢀimportantꢀconsiderationꢀinꢀpowerꢀsensitiveꢀbatteryꢀpoweredꢀapplications.
ItꢀisꢀrecommendedꢀtoꢀsetꢀtheꢀADOFFꢀbitꢀhighꢀbeforeꢀtheꢀdeviceꢀentersꢀtheꢀIDLE/
SLEEPꢀmodeꢀforꢀsavingꢀpower.ꢀSettingꢀtheꢀADOFFꢀbitꢀhighꢀwillꢀpowerꢀdownꢀtheꢀA/Dꢀ
converterꢀmoduleꢀregardlessꢀofꢀtheꢀADSLPꢀandꢀADRSTꢀbitꢀsettings.
Bitꢀ4~2
ADOR2~ADOR0:ꢀA/DꢀConversionꢀOversamplingꢀRateꢀSelection
000:ꢀOversamplingꢀrateꢀOSR=16384
001:ꢀOversamplingꢀrateꢀOSR=8192
010:ꢀOversamplingꢀrateꢀOSR=4096
011:ꢀOversamplingꢀrateꢀOSR=2048
100:ꢀOversamplingꢀrateꢀOSR=1024
101:ꢀOversamplingꢀrateꢀOSR=512
110:ꢀOversamplingꢀrateꢀOSR=256
111:ꢀOversamplingꢀrateꢀOSR=128
Bitꢀ1ꢀ
Bitꢀ0
Unimplemented,ꢀreadꢀasꢀ“0”
VREFS:ꢀA/DꢀConverterꢀReferenceꢀVoltageꢀPairꢀSelection
0:ꢀInternalꢀreferenceꢀvoltageꢀpairꢀ–ꢀVCMꢀ&ꢀAVSS
1:ꢀExternalꢀreferenceꢀvoltageꢀpairꢀ–ꢀVREFPꢀ&ꢀVREFN
Rev. 1.10
1ꢅꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
• ADCR1 Register
Bit
Name
R/W
7
FLMSꢅ
R/W
0
6
FLMS1
R/W
0
5
FLMS0
R/W
0
4
3
2
1
0
VRBUFN VRBUFP ADCDL
EOC
R/W
0
—
—
—
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~5
FLMS2~FLMS0:ꢀA/DꢀConverterꢀClockꢀDividedꢀRatioꢀSelectionꢀandꢀSampledꢀDataꢀ
DoublingꢀFunctionꢀ(CHOP)ꢀEnableꢀControl
000:ꢀCHOP=2,ꢀfADCKꢀ=ꢀfMCLKꢀ/ꢀ30
010:ꢀCHOP=2,ꢀfADCKꢀ=ꢀfMCLKꢀ/ꢀ12
Others:ꢀReserved
WhenꢀtheꢀCHOPꢀbitꢀisꢀequalꢀtoꢀ2,ꢀitꢀmeansꢀthatꢀtheꢀsampledꢀdataꢀamountꢀwillꢀbeꢀ
doubledꢀforꢀtheꢀnormalꢀconversionꢀmode.
Bitꢀ4
Bitꢀ3
Bitꢀ2
VRBUFN:ꢀA/DꢀConverterꢀNegativeꢀReferenceꢀVoltageꢀInputꢀ(VRN)ꢀBufferꢀControl
0:ꢀDisableꢀinputꢀbufferꢀandꢀenableꢀbypassꢀfunction
1:ꢀEnableꢀinputꢀbufferꢀandꢀdisableꢀbypassꢀfunction
VRBUFP:ꢀA/DꢀConverterꢀPositiveꢀReferenceꢀVoltageꢀInputꢀ(VRP)ꢀBufferꢀControl
0:ꢀDisableꢀinputꢀbufferꢀandꢀenableꢀbypassꢀfunction
1:ꢀEnableꢀinputꢀbufferꢀandꢀdisableꢀbypassꢀfunction
ADCDL:ꢀA/DꢀConvertedꢀDataꢀLatchꢀFunctionꢀEnableꢀControl
0:ꢀDisableꢀdataꢀlatchꢀfunction
1:ꢀEnableꢀdataꢀlatchꢀfunction
IfꢀtheꢀA/Dꢀconvertedꢀdataꢀlatchꢀfunctionꢀisꢀenabled,ꢀtheꢀlatestꢀconvertedꢀdataꢀvalueꢀwillꢀ
beꢀlatchedꢀandꢀnotꢀbeꢀupdatedꢀbyꢀanyꢀsubsequentꢀconvertedꢀresultsꢀuntilꢀthisꢀfunctionꢀ
isꢀdisabled.ꢀAlthoughꢀtheꢀconvertedꢀdataꢀisꢀlatchedꢀintoꢀtheꢀdataꢀregisters,ꢀtheꢀA/Dꢀ
converterꢀcircuitsꢀremainꢀoperational,ꢀbutꢀwillꢀnotꢀgenerateꢀinterruptꢀandꢀEOCꢀwillꢀnotꢀ
change.ꢀItꢀisꢀrecommendedꢀthatꢀthisꢀbitꢀshouldꢀbeꢀsetꢀhighꢀbeforeꢀreadingꢀtheꢀconvertedꢀ
dataꢀinꢀtheꢀADRL,ꢀADRMꢀandꢀADRHꢀregisters.ꢀAfterꢀtheꢀconvertedꢀdataꢀhasꢀbeenꢀ
readꢀout,ꢀtheꢀbitꢀcanꢀthenꢀbeꢀclearedꢀtoꢀlowꢀtoꢀdisableꢀtheꢀA/Dꢀconverterꢀdataꢀlatchꢀ
functionꢀandꢀallowꢀfurtherꢀconversionꢀvaluesꢀtoꢀbeꢀstored.ꢀInꢀthisꢀway,ꢀtheꢀpossibilityꢀ
ofꢀobtainingꢀundesiredꢀdataꢀduringꢀA/Dꢀconverterꢀconversionsꢀcanꢀbeꢀprevented.
Bitꢀ1
EOC:ꢀEndꢀofꢀA/DꢀConversionꢀFlag
0:ꢀA/Dꢀconversionꢀinꢀprogress
1:ꢀA/Dꢀconversionꢀended
Thisꢀbitꢀmustꢀbeꢀclearedꢀbyꢀsoftware.
Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ0ꢀ
Rev. 1.10
1ꢅ5
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
• ADCS Register
Bit
Name
R/W
7
6
5
4
ADCKꢃ
R/W
0
3
ADCK3
R/W
0
2
ADCKꢅ
R/W
0
1
ADCK1
R/W
0
0
ADCK0
R/W
0
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~5ꢀ
Bitꢀ4~0
Unimplemented,ꢀreadꢀasꢀ“0”
ADCK4~ADCK0:ꢀA/DꢀConverterꢀClockꢀSourceꢀfMCLKꢀDividedꢀRatioꢀSelection
00000~11110:ꢀfMCLK=fSYS/2ꢀ/ꢀ(ADCK[4:0]+1)
11111:ꢀfMCLK=fSYS
A/D Operation
TheꢀA/Dꢀconverterꢀprovidesꢀthreeꢀoperationalꢀmodes,ꢀwhichꢀareꢀPowerꢀdownꢀmode,ꢀSleepꢀmodeꢀandꢀ
Resetꢀmode,ꢀcontrolledꢀrespectivelyꢀbyꢀtheꢀADOFF,ꢀADSLPꢀandꢀADRSTꢀbitsꢀinꢀtheꢀADCR0ꢀregister.ꢀ
Theꢀfollowingꢀtableꢀillustratesꢀtheꢀoperatingꢀmodeꢀselection.
LDOEN ADOFF ADSLP ADRST
Operating Mode
Description
Bandgap offꢄ LDO offꢄ VCM geneꢁatoꢁ offꢄ
PGA offꢄ ADC offꢄ Tempeꢁatꢀꢁe sensoꢁ offꢄ
VRN/VRP buffer off, SINC filter off
0
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
x
x
1
0
0
1
0
0
x
x
x
0
1
x
0
1
Poweꢁ down mode
Bandgap onꢄ LDO onꢄ VCM geneꢁatoꢁ offꢄ
PGA offꢄ ADC offꢄ Tempeꢁatꢀꢁe sensoꢁ offꢄ
VRN/VRP buffer off, SINC filter off
Poweꢁ down mode
Sleep mode
(Exteꢁnal voltage mꢀst be
Bandgap onꢄ LDO offꢄ VCM geneꢁatoꢁ offꢄ
PGA onꢄ ADC offꢄ Tempeꢁatꢀꢁe sensoꢁ offꢄ
sꢀpplied on LDO oꢀtpꢀt pin) VRN/VRP buffer off, SINC filter on
Noꢁmal mode
(Exteꢁnal voltage mꢀst be
Bandgap onꢄ LDO offꢄ VCM geneꢁatoꢁ on/off(1)ꢄ
PGA onꢄ ADC onꢄ Tempeꢁatꢀꢁe sensoꢁ on/off(ꢅ)ꢄ
sꢀpplied on LDO oꢀtpꢀt pin) VRN/VRP bꢀffeꢁ on/off(3), SINC filter on
Reset mode
(Exteꢁnal voltage mꢀst be
Bandgap onꢄ LDO offꢄ VCM geneꢁatoꢁ on/off(1)ꢄ
PGA onꢄ ADC onꢄTempeꢁatꢀꢁe sensoꢁ on/off(ꢅ)ꢄ
sꢀpplied on LDO oꢀtpꢀt pin) VRN/VRP bꢀffeꢁ on/off(3), SINC filter reset
Bandgap onꢄ LDO onꢄ VCM geneꢁatoꢁ offꢄ
PGA onꢄ ADC offꢄ Tempeꢁatꢀꢁe sensoꢁ offꢄ
VRN/VRP buffer off, SINC filter on
Bandgap onꢄ LDO onꢄ VCM geneꢁatoꢁ on/off(1)ꢄ
PGA onꢄ ADC onꢄ Tempeꢁatꢀꢁe sensoꢁ on/off(ꢅ)ꢄ
VRN/VRP bꢀffeꢁ on/off(3), SINC filter on
Bandgap onꢄ LDO onꢄ VCM geneꢁatoꢁ on/off(1)ꢄ
PGA onꢄ ADC onꢄ Tempeꢁatꢀꢁe sensoꢁ on/off(ꢅ)ꢄ
VRN/VRP bꢀffeꢁ on/off(3), SINC filter reset
Sleep mode
Noꢁmal mode
Reset mode
“x” ꢀnknown
Note:ꢀ1.ꢀTheꢀVCMꢀgeneratorꢀcanꢀbeꢀswitchedꢀonꢀorꢀoffꢀbyꢀtheꢀbandgapꢀonꢀorꢀoff.
2.ꢀTheꢀTemperatureꢀsensorꢀcanꢀbeꢀswitchedꢀonꢀorꢀoffꢀbyꢀconfiguringꢀtheꢀCHSN[3:0]ꢀorꢀCHSP[3:0]ꢀbits
3.ꢀTheꢀVRNꢀbufferꢀcanꢀbeꢀswitchedꢀonꢀorꢀoffꢀbyꢀconfiguringꢀtheꢀVRBUFNꢀbitꢀwhileꢀtheꢀVRPꢀbufferꢀcanꢀbeꢀ
switchedꢀonꢀorꢀoffꢀbyꢀconfiguringꢀtheꢀVRBUFPꢀbit
A/D Operation Mode Selection
Rev. 1.10
1ꢅ6
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
ToꢀenableꢀtheꢀA/Dꢀconverter,ꢀtheꢀfirstꢀstepꢀisꢀtoꢀdisableꢀtheꢀA/Dꢀconverterꢀpowerꢀdownꢀandꢀsleepꢀ
modeꢀbyꢀclearingꢀtheꢀADOFFꢀandꢀADSLPꢀbitsꢀtoꢀmakeꢀsureꢀtheꢀA/Dꢀconverterꢀisꢀpoweredꢀup.ꢀTheꢀ
ADRSTꢀbitꢀinꢀtheꢀADCR0ꢀregisterꢀisꢀusedꢀtoꢀstartꢀandꢀresetꢀtheꢀA/Dꢀconverterꢀafterꢀpowerꢀon.ꢀToꢀsetꢀ
ADRSTꢀbitꢀfromꢀlowꢀtoꢀhighꢀandꢀthenꢀlowꢀagain,ꢀanꢀanalogꢀtoꢀdigitalꢀconvertedꢀdataꢀinꢀSINCꢀfilterꢀ
willꢀbeꢀinitiated.ꢀAfterꢀthisꢀsetupꢀisꢀcomplete,ꢀtheꢀA/DꢀConverterꢀisꢀreadyꢀforꢀoperation.ꢀTheseꢀthreeꢀ
bitsꢀareꢀusedꢀtoꢀcontrolꢀtheꢀoverallꢀstartꢀoperationꢀofꢀtheꢀinternalꢀanalogꢀtoꢀdigitalꢀconverter.
TheꢀEOCꢀbitꢀinꢀtheꢀADCR1ꢀregisterꢀisꢀusedꢀtoꢀindicateꢀwhenꢀtheꢀanalogꢀtoꢀdigitalꢀconversionꢀprocessꢀisꢀ
complete.ꢀThisꢀbitꢀwillꢀbeꢀautomaticallyꢀsetꢀtoꢀ“1”ꢀbyꢀtheꢀHardwareꢀafterꢀaꢀconversionꢀcycleꢀhasꢀended.ꢀ
Inꢀaddition,ꢀtheꢀcorrespondingꢀA/Dꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀsetꢀinꢀtheꢀinterruptꢀcontrolꢀregister,ꢀ
andꢀifꢀtheꢀinterruptsꢀareꢀenabled,ꢀanꢀappropriateꢀinternalꢀinterruptꢀsignalꢀwillꢀbeꢀgenerated.ꢀThisꢀA/Dꢀ
internalꢀinterruptꢀsignalꢀwillꢀdirectꢀtheꢀprogramꢀflowꢀtoꢀtheꢀassociatedꢀA/Dꢀinternalꢀinterruptꢀaddressꢀ
forꢀprocessing.ꢀIfꢀtheꢀA/Dꢀinternalꢀinterruptꢀisꢀdisabled,ꢀtheꢀmicrocontrollerꢀcanꢀpollꢀtheꢀEOCꢀbitꢀinꢀtheꢀ
ADCR1ꢀregisterꢀtoꢀcheckꢀwhetherꢀitꢀhasꢀbeenꢀsetꢀ“1”ꢀasꢀanꢀalternativeꢀmethodꢀofꢀdetectingꢀtheꢀendꢀofꢀ
anꢀA/Dꢀconversionꢀcycle.ꢀTheꢀA/Dꢀconvertedꢀdataꢀwillꢀbeꢀupdatedꢀcontinuouslyꢀbyꢀtheꢀnewꢀconvertedꢀ
data.ꢀIfꢀtheꢀA/Dꢀconvertedꢀdataꢀlatchꢀfunctionꢀisꢀenabled,ꢀtheꢀlatestꢀconvertedꢀdataꢀwillꢀbeꢀlatchedꢀandꢀ
theꢀfollowingꢀnewꢀconvertedꢀdataꢀwillꢀbeꢀdiscardedꢀuntilꢀthisꢀdataꢀlatchꢀfunctionꢀisꢀdisabled.
TheꢀclockꢀsourceꢀforꢀtheꢀA/Dꢀconverterꢀshouldꢀbeꢀtypicallyꢀfixedꢀatꢀaꢀvalueꢀofꢀ4MHz,ꢀwhichꢀ
originatesꢀfromꢀtheꢀsystemꢀclockꢀfSYS,ꢀandꢀcanꢀbeꢀchosenꢀtoꢀbeꢀeitherꢀfSYSꢀorꢀaꢀsubdividedꢀversionꢀ
ofꢀfSYS.ꢀTheꢀdivisionꢀratioꢀvalueꢀisꢀdeterminedꢀbyꢀtheꢀADCK4~ADCK0ꢀbitsꢀinꢀtheꢀADCSꢀregisterꢀtoꢀ
obtainꢀaꢀ4MHzꢀclockꢀsourceꢀforꢀtheꢀA/Dꢀconverter.
TheꢀdifferentialꢀreferenceꢀvoltageꢀsupplyꢀtoꢀtheꢀA/DꢀConverterꢀcanꢀbeꢀsuppliedꢀfromꢀeitherꢀtheꢀ
internalꢀpowerꢀsupply,ꢀVCMꢀandꢀAVSS,ꢀorꢀfromꢀanꢀexternalꢀreferenceꢀsource,ꢀVREFPꢀandꢀVREFN.ꢀ
TheꢀdesiredꢀselectionꢀisꢀmadeꢀusingꢀtheꢀVREFSꢀbitꢀinꢀtheꢀADCR0ꢀregister.
Summary of A/D Conversion Steps
Theꢀfollowingꢀsummarisesꢀtheꢀindividualꢀstepsꢀthatꢀshouldꢀbeꢀexecutedꢀinꢀorderꢀtoꢀimplementꢀanꢀ
A/Dꢀconversionꢀprocess.
•ꢀ Stepꢀ1
EnableꢀtheꢀpowerꢀLDO,ꢀVCMꢀforꢀPGAꢀandꢀA/Dꢀconverter.
•ꢀ Stepꢀ2
SelectꢀtheꢀPGA,ꢀA/Dꢀconverter,ꢀreferenceꢀvoltageꢀgainsꢀbyꢀPGAC0ꢀregister
•ꢀ Stepꢀ3
SelectꢀtheꢀPGAꢀsettingsꢀforꢀinputꢀconnection,ꢀVCMꢀvoltageꢀlevelꢀandꢀbufferꢀoptionꢀbyꢀPGAC1ꢀ
register
•ꢀ Stepꢀ4
SelectꢀtheꢀrequiredꢀA/DꢀconversionꢀclockꢀsourceꢀbyꢀcorrectlyꢀprogrammingꢀbitsꢀADCK4~ADCK0ꢀ
inꢀtheꢀADCSꢀregister.
•ꢀ Stepꢀ5
SelectꢀoutputꢀdataꢀrateꢀbyꢀconfiguringꢀtheꢀADOR[2:0]ꢀbitsꢀinꢀtheꢀADCR0ꢀregisterꢀandꢀFLMS[2:0]ꢀ
bitsꢀinꢀtheꢀADCR1ꢀregister.
•ꢀ Stepꢀ6
SelectꢀwhichꢀchannelꢀisꢀtoꢀbeꢀconnectedꢀtoꢀtheꢀinternalꢀPGAꢀbyꢀcorrectlyꢀprogrammingꢀtheꢀ
CHSP3~CHSP0ꢀandꢀCHSN3~CHSN0ꢀbitsꢀwhichꢀareꢀalsoꢀcontainedꢀinꢀtheꢀPGACSꢀregister.
•ꢀ Stepꢀ7
ReleaseꢀtheꢀpowerꢀdownꢀmodeꢀandꢀsleepꢀmodeꢀbyꢀclearingꢀtheꢀADOFFꢀandꢀADSLPꢀbitsꢀinꢀ
ADCR0ꢀregister.
Rev. 1.10
1ꢅ7
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
•ꢀ Stepꢀ8ꢀ
ResetꢀtheꢀA/DꢀbyꢀsettingꢀtheꢀADRSTꢀtoꢀhighꢀinꢀtheꢀADCR0ꢀregisterꢀandꢀclearingꢀthisꢀbitꢀtoꢀ“0”ꢀtoꢀ
releaseꢀresetꢀstatus.
•ꢀ Stepꢀ9
Ifꢀtheꢀinterruptsꢀareꢀtoꢀbeꢀused,ꢀtheꢀinterruptꢀcontrolꢀregistersꢀmustꢀbeꢀcorrectlyꢀconfiguredꢀtoꢀ
ensureꢀtheꢀA/Dꢀconverterꢀinterruptꢀfunctionꢀisꢀactive.ꢀTheꢀmasterꢀinterruptꢀcontrolꢀbit,ꢀEMI,ꢀandꢀ
theꢀA/Dꢀconverterꢀinterruptꢀbit,ꢀADE,ꢀmustꢀbothꢀbeꢀsetꢀhighꢀtoꢀdoꢀthis.
•ꢀ Stepꢀ10
Toꢀcheckꢀwhenꢀtheꢀanalogꢀtoꢀdigitalꢀconversionꢀprocessꢀisꢀcomplete,ꢀtheꢀEOCꢀbitꢀinꢀtheꢀADCR1ꢀ
registerꢀcanꢀbeꢀpolled.ꢀTheꢀconversionꢀprocessꢀisꢀcompleteꢀwhenꢀthisꢀbitꢀgoesꢀhigh.ꢀWhenꢀthisꢀ
occursꢀtheꢀA/DꢀdataꢀregistersꢀADRL,ꢀADRMꢀandꢀADRHꢀcanꢀbeꢀreadꢀtoꢀobtainꢀtheꢀconversionꢀ
value.ꢀAsꢀanꢀalternativeꢀmethod,ꢀifꢀtheꢀinterruptsꢀareꢀenabledꢀandꢀtheꢀstackꢀisꢀnotꢀfull,ꢀtheꢀprogramꢀ
canꢀwaitꢀforꢀanꢀA/Dꢀinterruptꢀtoꢀoccur.
Note:ꢀWhenꢀcheckingꢀforꢀtheꢀendꢀofꢀtheꢀconversionꢀprocess,ꢀifꢀtheꢀmethodꢀofꢀpollingꢀtheꢀEOCꢀbitꢀinꢀ
theꢀADCR1ꢀregisterꢀisꢀused,ꢀtheꢀinterruptꢀenableꢀstepꢀaboveꢀcanꢀbeꢀomitted.
Programming Considerations
DuringꢀmicrocontrollerꢀoperationsꢀwhereꢀtheꢀA/Dꢀconverterꢀisꢀnotꢀbeingꢀused,ꢀtheꢀA/Dꢀinternalꢀ
circuitryꢀcanꢀbeꢀswitchedꢀoffꢀtoꢀreduceꢀpowerꢀconsumption,ꢀbyꢀsettingꢀbitꢀADOFFꢀhighꢀinꢀtheꢀ
ADCR0ꢀregister.ꢀWhenꢀthisꢀhappens,ꢀtheꢀinternalꢀA/Dꢀconverterꢀcircuitsꢀwillꢀnotꢀconsumeꢀpowerꢀ
irrespectiveꢀofꢀwhatꢀanalogꢀvoltageꢀisꢀappliedꢀtoꢀtheirꢀinputꢀlines.
A/D Converter Transfer Function
Eachꢀdeviceꢀcontainsꢀaꢀ24-bitꢀDeltaꢀSigmaꢀA/Dꢀconverterꢀandꢀitsꢀfull-scaleꢀconvertedꢀdigitisedꢀvalueꢀ
isꢀfromꢀ8388607ꢀtoꢀ-8388608ꢀinꢀdecimalꢀvalue.ꢀTheꢀconvertedꢀdataꢀformatꢀisꢀformedꢀbyꢀaꢀtwo’sꢀ
complementꢀbinaryꢀvalue.ꢀTheꢀMSBꢀofꢀtheꢀconvertedꢀdataꢀisꢀtheꢀsignedꢀbit.ꢀSinceꢀtheꢀfull-scaleꢀ
analogꢀinputꢀvalueꢀisꢀequalꢀtoꢀtheꢀamplifiedꢀvalueꢀofꢀtheꢀVCMꢀorꢀdifferentialꢀreferenceꢀinputꢀvoltage,ꢀ
ΔVR_I,ꢀselectedꢀbyꢀtheꢀVREFSꢀbitꢀinꢀADCR0ꢀregister,ꢀthisꢀgivesꢀaꢀsingleꢀbitꢀanalogꢀinputꢀvalueꢀofꢀ
ΔVR_Iꢀdividedꢀbyꢀ8388608.
1ꢀLSBꢀ=ꢀΔVR_Iꢀ/ꢀ8388608
TheꢀA/DꢀConverterꢀinputꢀvoltageꢀvalueꢀcanꢀbeꢀcalculatedꢀusingꢀtheꢀfollowingꢀequation:
ΔSI_Iꢀ=ꢀ(PGAGNꢀ×ꢀADGNꢀ×ꢀΔDI±)ꢀ+ꢀDCSET
ΔVR_Iꢀ=ꢀVREGNꢀ×ꢀΔVR±
ADC_Conversion_Dataꢀ=ꢀ(ΔSI_Iꢀ/ꢀΔVR_I)ꢀ×ꢀK
WhereꢀKꢀisꢀequalꢀtoꢀ223
Note:ꢀ1.ꢀTheꢀPGAGN,ꢀADGN,ꢀVREGNꢀvaluesꢀareꢀdecidedꢀbyꢀtheꢀPGS,ꢀAGS,ꢀVGSꢀcontrolꢀbits.
2.ꢀΔSI_I:ꢀDifferentialꢀInputꢀSignalꢀafterꢀamplificationꢀandꢀoffsetꢀadjustment.
3.ꢀPGAGN:ꢀProgrammableꢀGainꢀAmplifierꢀgain
4.ꢀADGN:ꢀA/DꢀConverterꢀgain
5.ꢀVREGN:ꢀReferenceꢀvoltageꢀgain
6.ꢀΔDI±:ꢀDifferentialꢀinputꢀsignalꢀderivedꢀfromꢀexternalꢀchannelsꢀorꢀinternalꢀsignals
7.ꢀDCSET:ꢀOffsetꢀvoltage
8.ꢀΔVR±:ꢀDifferentialꢀReferenceꢀvoltage
9.ꢀΔVR_I:ꢀDifferentialꢀReferenceꢀinputꢀvoltageꢀafterꢀamplification
Rev. 1.10
1ꢅꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
DueꢀtoꢀtheꢀdigitalꢀsystemꢀdesignꢀofꢀtheꢀDeltaꢀSigmaꢀA/DꢀConverter,ꢀtheꢀmaximumꢀnumberꢀofꢀtheꢀ
A/Dꢀconvertedꢀvalueꢀisꢀ8388607ꢀandꢀtheꢀminimumꢀvalueꢀisꢀ-8388608,ꢀtherefore,ꢀweꢀcanꢀhaveꢀtheꢀ
middleꢀnumberꢀ0.ꢀTheꢀADC_Conversion_Dataꢀequationꢀillustratesꢀthisꢀrangeꢀofꢀconvertedꢀdataꢀ
variation.
A/D Conversion Data
Decimal Value
(2’s Compliment, Hexadecimal)
0x7FFFFF
0xꢆ00000
ꢆ3ꢆꢆ607
-ꢆ3ꢆꢆ60ꢆ
A/D Conversion Data Range
TheꢀaboveꢀA/DꢀconverterꢀconversionꢀdataꢀtableꢀillustratesꢀtheꢀrangeꢀofꢀA/Dꢀconversionꢀdata.
TheꢀfollowingꢀdiagramꢀshowsꢀtheꢀrelationshipꢀbetweenꢀtheꢀDCꢀinputꢀvalueꢀandꢀtheꢀA/Dꢀconvertedꢀ
dataꢀwhichꢀisꢀpresentedꢀbyꢀtheꢀTwo’sꢀComplement.
ꢅꢃ Digital oꢀtpꢀt
Two's complement
0111 1111 1111 1111 1111 1111
DC inpꢀt valꢀe
0
(D+ - D-) * PGAGN * ADGN + DCSET
(REFP - REFN) * VREGN
1000 0000 0000 0000 0000 0000
Rev. 1.10
1ꢅ9
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
ꢅꢃ Digital oꢀtpꢀt
Two's complement
0111 1111 1111 1111 1111 1111
DC inpꢀt valꢀe
0
(D+ - D-) * PGAGN * ADGN + DCSET
(REFP - REFN) * VREGN
1000 0000 0000 0000 0000 0000
A/D Converted Data
TheꢀA/DꢀconvertedꢀdataꢀisꢀrelatedꢀtoꢀtheꢀinputꢀvoltageꢀandꢀtheꢀPGAꢀselections.ꢀTheꢀformatꢀofꢀtheꢀ
A/Dꢀconverterꢀoutputꢀisꢀaꢀtwo’sꢀcomplementꢀbinaryꢀcode.ꢀTheꢀlengthꢀofꢀthisꢀoutputꢀcodeꢀisꢀ24ꢀbitsꢀ
andꢀtheꢀMSBꢀisꢀaꢀsignedꢀbit.ꢀWhenꢀtheꢀMSBꢀisꢀ“0”,ꢀwhichꢀrepresentsꢀtheꢀinputꢀisꢀ“positive”,ꢀonꢀtheꢀ
otherꢀhand,ꢀasꢀtheꢀMSBꢀisꢀ“1”,ꢀitꢀrepresentsꢀtheꢀinputꢀisꢀ“negative”.ꢀTheꢀmaximumꢀvalueꢀisꢀ8388607ꢀ
andꢀtheꢀminimumꢀvalueꢀisꢀ-8388608.ꢀIfꢀtheꢀinputꢀsignalꢀisꢀoverꢀtheꢀmaximumꢀvalue,ꢀtheꢀconvertedꢀ
dataꢀisꢀlimitedꢀbyꢀtheꢀ8388607,ꢀandꢀifꢀtheꢀinputꢀsignalꢀisꢀlessꢀthanꢀtheꢀminimumꢀvalue,ꢀtheꢀconvertedꢀ
dataꢀisꢀlimitedꢀbyꢀ-8388608.
Rev. 1.10
130
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
A/D Converted Data to Voltage
Theꢀdesignerꢀcanꢀrecoverꢀtheꢀconvertedꢀdataꢀbyꢀtheꢀfollowingꢀequations:
IfꢀMSB=0ꢀ(PositiveꢀConvertedꢀdata):ꢀInputꢀVoltage=
(Converted_data) LSB DCSET
PGA ADGN
IfꢀMSB=1(NegativeꢀConvertedꢀdata):ꢀInputꢀvoltage=ꢀ
Two's_complement_of_Converted_data
PGAADGN
Note:ꢀTwo’sꢀcomplement=One’sꢀcomplementꢀ+1
LSB DCSET
A/D Programming Example
• Example: Using an EOC polling method to detect the end of conversion
#include bh66f2650.inc
data .section
'data'
ꢀ
ꢀ
ꢀ
adc_result_data_lꢀdbꢀ?
adc_result_data_mꢀdbꢀ?
adc_result_data_hꢀdbꢀ?
code .section
start:
‘code’
ꢀ
ꢀ
ꢀ
ꢀ
clrꢀꢀ ADEꢀꢀ
ꢀ
movꢀꢀ a,ꢀ083Hꢀꢀ
movꢀꢀ PWRC,ꢀaꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀDisableꢀA/Dꢀconverterꢀinterrupt
;ꢀPowerꢀcontrolꢀforꢀPGA,ꢀA/Dꢀconverter
;ꢀPWRC=10000011,ꢀLDOꢀenable,ꢀVCMꢀenable,ꢀLDOꢀBypass
;ꢀdisable,ꢀLDOꢀoutputꢀvoltage:ꢀ3.3V
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
mov
a, 000H
ꢀ
movꢀꢀ PGAC0,ꢀaꢀꢀ ꢀ
mov a, 000H
movꢀꢀ PGAC1,ꢀaꢀꢀ ꢀ
ꢀ
ꢀ
;ꢀPGAꢀgain=1,ꢀA/Dꢀconverterꢀgain=1,ꢀVREFꢀgain=1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀVCM=1.25V,ꢀINIS,ꢀINX,ꢀDCSETꢀinꢀdefaultꢀvalue
;ꢀenableꢀbufferꢀforꢀVREF+
;ꢀenableꢀbufferꢀforꢀVREF-
;ꢀforꢀusingꢀexternalꢀreference
;ꢀforꢀ10Hzꢀoutputꢀdataꢀrate,ꢀADOR[2:0]=001,ꢀFLMS[2:0]=000
setꢀꢀ VRBUFPꢀꢀ
setꢀꢀ VRBUFNꢀꢀ
setꢀꢀ VREFSꢀꢀꢀ
clrꢀꢀ ADOR2ꢀꢀꢀ
clrꢀꢀ ADOR1
ꢀ
ꢀ
ꢀ
ꢀ
setꢀꢀ ADOR0
clrꢀꢀ FLMS2
c l r ꢀꢀ F L M S 1
c l r ꢀꢀ F L M S 0
ꢀ
ꢀ
ꢀ
ꢀ
clrꢀꢀ ADOFFꢀꢀꢀ
setꢀꢀ ADRSTꢀꢀꢀ
clrꢀꢀ ADRSTꢀꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀA/Dꢀconverterꢀexitꢀpowerꢀdownꢀmode.
;ꢀA/Dꢀconverterꢀinꢀresetꢀmode
;ꢀA/Dꢀconverterꢀinꢀconvertsionꢀ(continuosꢀmode)
;ꢀClearꢀ“EOC”ꢀflag
clrꢀꢀ EOCꢀꢀ
ꢀ
loop:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
snzꢀꢀ EOCꢀꢀ
jmpꢀꢀ loopꢀꢀ
clrꢀꢀ adc_result_data_h
clrꢀꢀ adc_result_data_m
clrꢀꢀ adc_result_data_l
movꢀꢀ a,ꢀADRL
movꢀꢀ adc_result_data_l,ꢀaꢀꢀ;ꢀGetꢀLowꢀbyteꢀA/Dꢀconverterꢀvalue
movꢀꢀ a,ꢀADRM
movꢀꢀ adc_result_data_m,ꢀaꢀꢀ;ꢀGetꢀMiddleꢀbyteꢀA/Dꢀconverterꢀvalue
movꢀꢀ a,ꢀADRH
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀPollingꢀ“EOC”ꢀflag
;ꢀWaitꢀforꢀreadꢀdata
movꢀꢀ adc_result_data_h,ꢀaꢀꢀ;ꢀGetꢀHighꢀbyteꢀA/Dꢀconverterꢀvalue
get_adc_value_ok:
ꢀ
clrꢀꢀ EOCꢀꢀ
jmp loop
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀClearingꢀreadꢀflag
; for next data read
end
Rev. 1.10
131
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Temperature Sensor
Theꢀdevicesꢀprovideꢀanꢀinternalꢀtemperatureꢀsensorꢀtoꢀcompensateꢀtheꢀdeviceꢀdueꢀtoꢀtemperatureꢀ
effects.ꢀByꢀselectingꢀtheꢀPGAꢀinputꢀchannelsꢀasꢀVTSOPꢀandꢀVTSON,ꢀtheꢀA/DꢀConverterꢀcanꢀobtainꢀ
temperatureꢀinformationꢀallowingꢀcompenstiaonꢀtoꢀbeꢀmadeꢀtoꢀtheꢀA/Dꢀconvertedꢀdata.
VOREG
I
VTSO+
A/D Converter
PGA
VTSO
-
AVSS
Serial Interface Module – SIM
EachꢀdeviceꢀcontainsꢀaꢀSerialꢀInterfaceꢀModule,ꢀwhichꢀincludesꢀbothꢀtheꢀfourꢀlineꢀSPIꢀinterfaceꢀandꢀ
theꢀtwoꢀlineꢀI2Cꢀinterfaceꢀtypes,ꢀtoꢀallowꢀanꢀeasyꢀmethodꢀofꢀcommunicationꢀwithꢀexternalꢀperipheralꢀ
hardware.ꢀHavingꢀrelativelyꢀsimpleꢀcommunicationꢀprotocols,ꢀtheseꢀserialꢀinterfaceꢀtypesꢀallowꢀtheꢀ
microcontrollerꢀtoꢀinterfaceꢀtoꢀexternalꢀSPIꢀorꢀI2Cꢀbasedꢀhardwareꢀsuchꢀasꢀsensors,ꢀFlashꢀmemory,ꢀ
etc.ꢀAsꢀbothꢀinterfaceꢀtypesꢀshareꢀtheꢀsameꢀpinsꢀandꢀregisters,ꢀtheꢀchoiceꢀofꢀwhetherꢀtheꢀSPIꢀorꢀI2Cꢀ
typeꢀisꢀusedꢀisꢀmadeꢀusingꢀtheꢀSIMꢀoperatingꢀmodeꢀcontrolꢀbits,ꢀnamedꢀSIM2~SIM0,ꢀinꢀtheꢀSIMC0ꢀ
register.ꢀTheseꢀpull-highꢀresistorsꢀofꢀtheꢀSIMꢀpin-sharedꢀI/Oꢀpinsꢀareꢀselectedꢀusingꢀpull-highꢀcontrolꢀ
registersꢀwhenꢀtheꢀSIMꢀfunctionꢀisꢀenabledꢀandꢀtheꢀcorrespondingꢀpinsꢀareꢀusedꢀasꢀSIMꢀinputꢀpins.
SPI Interface
TheꢀSPIꢀinterfaceꢀisꢀoftenꢀusedꢀtoꢀcommunicateꢀwithꢀexternalꢀperipheralꢀdevicesꢀsuchꢀasꢀsensors,ꢀ
Flashꢀmemoryꢀdevicesꢀetc.ꢀOriginallyꢀdevelopedꢀbyꢀMotorola,ꢀtheꢀfourꢀlineꢀSPIꢀinterfaceꢀisꢀaꢀ
synchronousꢀserialꢀdataꢀinterfaceꢀthatꢀhasꢀaꢀrelativelyꢀsimpleꢀcommunicationꢀprotocolꢀsimplifyingꢀ
theꢀprogrammingꢀrequirementsꢀwhenꢀcommunicatingꢀwithꢀexternalꢀhardwareꢀdevices.
Theꢀcommunicationꢀisꢀfullꢀduplexꢀandꢀoperatesꢀasꢀaꢀslave/masterꢀtype,ꢀwhereꢀtheꢀdevicesꢀcanꢀbeꢀ
eitherꢀmasterꢀorꢀslave.ꢀAlthoughꢀtheꢀSPIꢀinterfaceꢀspecificationꢀcanꢀcontrolꢀmultipleꢀslaveꢀdevicesꢀ
fromꢀaꢀsingleꢀmaster,ꢀbutꢀtheseꢀdevicesꢀareꢀprovidedꢀonlyꢀoneꢀSCSꢀpin.ꢀIfꢀtheꢀmasterꢀneedsꢀtoꢀcontrolꢀ
multipleꢀslaveꢀdevicesꢀfromꢀaꢀsingleꢀmaster,ꢀtheꢀmasterꢀcanꢀuseꢀI/Oꢀpinꢀtoꢀselectꢀtheꢀslaveꢀdevices.
SPI Masteꢁ
SCK
SPI Slave
SCK
SDO
SDI
SDI
SDO
SCS
SCS
SPI Master/Slave Connection
Rev. 1.10
13ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
SPI Interface Operation
TheꢀSPIꢀinterfaceꢀisꢀaꢀfullꢀduplexꢀsynchronousꢀserialꢀdataꢀlink.ꢀItꢀisꢀaꢀfourꢀlineꢀinterfaceꢀwithꢀpinꢀ
namesꢀSDI,ꢀSDO,ꢀSCKꢀandꢀSCS.ꢀPinsꢀSDIꢀandꢀSDOꢀareꢀtheꢀSerialꢀDataꢀInputꢀandꢀSerialꢀDataꢀOutputꢀ
lines;ꢀSCKꢀisꢀtheꢀSerialꢀClockꢀlineꢀandꢀSCSꢀisꢀtheꢀSlaveꢀSelectꢀline.ꢀAsꢀtheꢀSPIꢀinterfaceꢀpinsꢀareꢀpin-
sharedꢀwithꢀnormalꢀI/OꢀpinsꢀandꢀwithꢀtheꢀI2Cꢀfunctionꢀpins,ꢀtheꢀSPIꢀinterfaceꢀmustꢀfirstꢀbeꢀenabledꢀ
byꢀsettingꢀtheꢀcorrectꢀbitsꢀinꢀtheꢀSIMC0ꢀandꢀSIMC2ꢀregisters.ꢀTheꢀSPIꢀcanꢀbeꢀdisabledꢀorꢀenabledꢀ
usingꢀtheꢀSIMENꢀbitꢀinꢀtheꢀSIMC0ꢀregister.ꢀCommunicationꢀbetweenꢀdevicesꢀconnectedꢀtoꢀtheꢀSPIꢀ
interfaceꢀisꢀcarriedꢀoutꢀinꢀaꢀslave/masterꢀmodeꢀwithꢀallꢀdataꢀtransferꢀinitiationsꢀbeingꢀimplementedꢀ
byꢀtheꢀmaster.ꢀTheꢀMasterꢀalsoꢀcontrolsꢀtheꢀclockꢀsignal.ꢀAsꢀtheseꢀdevicesꢀonlyꢀcontainsꢀaꢀsingleꢀSCSꢀ
pinꢀonlyꢀoneꢀslaveꢀdeviceꢀcanꢀbeꢀutilized.ꢀTheꢀSCSꢀpinꢀisꢀcontrolledꢀbyꢀsoftware,ꢀsetꢀCSENꢀbitꢀtoꢀ“1”ꢀ
toꢀenableꢀSCSꢀpinꢀfunction,ꢀsetꢀCSENꢀbitꢀtoꢀ“0”ꢀtheꢀSCSꢀpinꢀwillꢀbeꢀfloatingꢀstate.
Data Bꢀs
SIMD
SDI Pin
TX/RX Shift Register
SDO Pin
CKEG
CKPOLB
Clock Edge/Polaꢁitꢂ
Contꢁol
WCOL
TRF
Bꢀsꢂ Statꢀs
SCK Pin
SIMICF
Clock
Soꢀꢁce
Select
fSYS
fSUB
PTMꢅ CCRP match fꢁeqꢀencꢂ/ꢅ
SCS Pin
CSEN
SPI Block Diagram
TheꢀSPIꢀfunctionꢀinꢀtheseꢀdevicesꢀofferꢀtheꢀfollowingꢀfeatures:ꢀ
•ꢀ Fullꢀduplexꢀsynchronousꢀdataꢀtransferꢀ
•ꢀ BothꢀMasterꢀandꢀSlaveꢀmodesꢀ
•ꢀ LSBꢀfirstꢀorꢀMSBꢀfirstꢀdataꢀtransmissionꢀmodesꢀ
•ꢀ Transmissionꢀcompleteꢀflagꢀ
•ꢀ Risingꢀorꢀfallingꢀactiveꢀclockꢀedgeꢀ
TheꢀstatusꢀofꢀtheꢀSPIꢀinterfaceꢀpinsꢀisꢀdeterminedꢀbyꢀaꢀnumberꢀofꢀfactorsꢀsuchꢀasꢀwhetherꢀtheꢀdeviceꢀ
isꢀinꢀtheꢀmasterꢀorꢀslaveꢀmodeꢀandꢀuponꢀtheꢀconditionꢀofꢀcertainꢀcontrolꢀbitsꢀsuchꢀasꢀCSENꢀandꢀ
SIMEN.ꢀ
Rev. 1.10
133
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
SPI Registers
ThereꢀareꢀthreeꢀinternalꢀregistersꢀwhichꢀcontrolꢀtheꢀoverallꢀoperationꢀofꢀtheꢀSPIꢀinterface.ꢀTheseꢀareꢀ
theꢀSIMDꢀdataꢀregisterꢀandꢀtwoꢀregistersꢀSIMC0ꢀandꢀSIMC2.ꢀNoteꢀthatꢀtheꢀSIMC1ꢀregisterꢀisꢀonlyꢀ
usedꢀbyꢀtheꢀI2Cꢀinterface.
Bit
Register
Name
7
SIMꢅ
D7
6
SIM1
D6
5
4
3
2
1
0
SIMC0
SIMD
SIM0
D5
—
Dꢃ
SIMDEB1
D3
SIMDEB0
Dꢅ
SIMEN SIMICF
D1
D0
SIMCꢅ
D7
D6
CKPOLB CKEG
MLS
CSEN
WCOL
TRF
SIM Registers List
TheꢀSIMDꢀregisterꢀisꢀusedꢀtoꢀstoreꢀtheꢀdataꢀbeingꢀtransmittedꢀandꢀreceived.ꢀTheꢀsameꢀregisterꢀisꢀusedꢀ
byꢀbothꢀtheꢀSPIꢀandꢀI2Cꢀfunctions.ꢀBeforeꢀtheꢀdeviceꢀwritesꢀdataꢀtoꢀtheꢀSPIꢀbus,ꢀtheꢀactualꢀdataꢀtoꢀ
beꢀtransmittedꢀmustꢀbeꢀplacedꢀinꢀtheꢀSIMDꢀregister.ꢀAfterꢀtheꢀdataꢀisꢀreceivedꢀfromꢀtheꢀSPIꢀbus,ꢀtheꢀ
deviceꢀcanꢀreadꢀitꢀfromꢀtheꢀSIMDꢀregister.ꢀAnyꢀtransmissionꢀorꢀreceptionꢀofꢀdataꢀfromꢀtheꢀSPIꢀbusꢀ
mustꢀbeꢀmadeꢀviaꢀtheꢀSIMDꢀregister.
• SIMD Register
Bit
Name
R/W
7
D7
R/W
x
6
D6
R/W
x
5
D5
R/W
x
4
Dꢃ
R/W
x
3
D3
R/W
x
2
Dꢅ
R/W
x
1
D1
R/W
x
0
D0
R/W
POR
x
“x” ꢀnknown
ThereꢀareꢀalsoꢀtwoꢀcontrolꢀregistersꢀforꢀtheꢀSPIꢀinterface,ꢀSIMC0ꢀandꢀSIMC2.ꢀNoteꢀthatꢀtheꢀSIMC2ꢀ
registerꢀalsoꢀhasꢀtheꢀnameꢀSIMAꢀwhichꢀisꢀusedꢀbyꢀtheꢀI2Cꢀfunction.ꢀTheꢀSIMC1ꢀregisterꢀisꢀnotꢀusedꢀ
byꢀtheꢀSPIꢀfunction,ꢀonlyꢀbyꢀtheꢀI2Cꢀfunction.ꢀRegisterꢀSIMC0ꢀisꢀusedꢀtoꢀcontrolꢀtheꢀenable/disableꢀ
functionꢀandꢀtoꢀsetꢀtheꢀdataꢀtransmissionꢀclockꢀfrequency.ꢀAlthoughꢀnotꢀconnectedꢀwithꢀtheꢀSPIꢀ
function,ꢀtheꢀSIMC0ꢀregisterꢀisꢀalsoꢀusedꢀtoꢀcontrolꢀtheꢀPeripheralꢀClockꢀPrescaler.ꢀRegisterꢀSIMC2ꢀ
isꢀusedꢀforꢀotherꢀcontrolꢀfunctionsꢀsuchꢀasꢀLSB/MSBꢀselection,ꢀwriteꢀcollisionꢀflagꢀetc.
• SIMC0 Register
Bit
Name
R/W
7
SIMꢅ
R/W
1
6
SIM1
R/W
1
5
SIM0
R/W
1
4
3
SIMDEB1
R/W
2
SIMDEB0
R/W
1
SIMEN
R/W
0
0
SIMICF
R/W
0
—
—
—
POR
0
0
Bitꢀ7~5
SIM2~SIM0:ꢀSIMꢀOperatingꢀModeꢀControl
000:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/4
001:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/16
010:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/64
011:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSUB
100:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀPTM2ꢀCCRPꢀmatchꢀfrequency/2
101:ꢀSPIꢀslaveꢀmode
110:ꢀI2Cꢀslaveꢀmode
111:ꢀUnusedꢀmode
TheseꢀbitsꢀsetupꢀtheꢀoverallꢀoperatingꢀmodeꢀofꢀtheꢀSIMꢀfunction.ꢀAsꢀwellꢀasꢀselectingꢀ
ifꢀtheꢀI2CꢀorꢀSPIꢀfunction,ꢀtheyꢀareꢀusedꢀtoꢀcontrolꢀtheꢀSPIꢀMaster/Slaveꢀselectionꢀandꢀ
theꢀSPIꢀMasterꢀclockꢀfrequency.ꢀTheꢀSPIꢀclockꢀisꢀaꢀfunctionꢀofꢀtheꢀsystemꢀclockꢀbutꢀ
canꢀalsoꢀbeꢀchosenꢀtoꢀbeꢀsourcedꢀfromꢀtheꢀPTM2.ꢀIfꢀtheꢀSPIꢀSlaveꢀModeꢀisꢀselectedꢀ
thenꢀtheꢀclockꢀwillꢀbeꢀsuppliedꢀbyꢀanꢀexternalꢀMasterꢀdevice.
Bitꢀ4ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Rev. 1.10
13ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ3~2
Bitꢀ1
SIMDEB[1:0]:ꢀI2CꢀDebounceꢀTimeꢀSelection
TheꢀSIMDEB[1:0]ꢀbitsꢀareꢀofꢀnoꢀusedꢀinꢀSPIꢀmodeꢀofꢀSIM,ꢀpleaseꢀignoreꢀtheseꢀ
selectionꢀbitsꢀwhenꢀoperateꢀinꢀSPIꢀmode.
SIMEN:ꢀSIMꢀControl
0:ꢀDisable
1:ꢀEnable
Theꢀbitꢀisꢀtheꢀoverallꢀon/offꢀcontrolꢀforꢀtheꢀSIMꢀinterface.ꢀWhenꢀtheꢀSIMENꢀbitꢀisꢀ
clearedꢀtoꢀ“0”ꢀtoꢀdisableꢀtheꢀSIMꢀinterface,ꢀtheꢀSDI,ꢀSDO,ꢀSCKꢀandꢀSCS,ꢀorꢀSDAꢀ
andꢀSCLꢀlinesꢀwillꢀbeꢀinꢀaꢀfloatingꢀconditionꢀandꢀtheꢀSIMꢀoperatingꢀcurrentꢀwillꢀbeꢀ
reducedꢀtoꢀaꢀminimumꢀvalue.ꢀWhenꢀtheꢀbitꢀisꢀhighꢀtheꢀSIMꢀinterfaceꢀisꢀenabled.ꢀTheꢀ
SIMꢀconfigurationꢀoptionꢀmustꢀhaveꢀfirstꢀenabledꢀtheꢀSIMꢀinterfaceꢀforꢀthisꢀbitꢀtoꢀbeꢀ
effective.ꢀIfꢀtheꢀSIMꢀisꢀconfiguredꢀtoꢀoperateꢀasꢀanꢀSPIꢀinterfaceꢀviaꢀtheꢀSIM2~SIM0ꢀ
bits,ꢀtheꢀcontentsꢀofꢀtheꢀSPIꢀcontrolꢀregistersꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀwhenꢀ
theꢀSIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀandꢀshouldꢀthereforeꢀbeꢀfirstꢀinitialisedꢀbyꢀ
theꢀapplicationꢀprogram.ꢀIfꢀtheꢀSIMꢀisꢀconfiguredꢀtoꢀoperateꢀasꢀanꢀI2Cꢀinterfaceꢀviaꢀtheꢀ
SIM2~SIM0ꢀbitsꢀandꢀtheꢀSIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀtheꢀcontentsꢀofꢀtheꢀI2Cꢀ
controlꢀbitsꢀsuchꢀasꢀHTXꢀandꢀTXAKꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀandꢀshouldꢀ
thereforeꢀbeꢀfirstꢀinitialisedꢀbyꢀtheꢀapplicationꢀprogramꢀwhileꢀtheꢀrelevantꢀI2Cꢀflagsꢀ
suchꢀasꢀHCF,ꢀHAAS,ꢀHBB,ꢀSRWꢀandꢀRXAKꢀwillꢀbeꢀsetꢀtoꢀtheirꢀdefaultꢀstates.
Bitꢀ0
SIMICF:ꢀSIMꢀSPIꢀIncompleteꢀFlag
0:ꢀSIMꢀSPIꢀincompletedꢀisꢀnotꢀoccurred
1:ꢀSIMꢀSPIꢀincompletedꢀisꢀoccurred
TheꢀSIMICFꢀbitꢀisꢀdeterminedꢀbyꢀSCSꢀpin.ꢀWhenꢀSCSꢀpinꢀisꢀsetꢀhigh,ꢀitꢀwillꢀclearꢀtheꢀ
SPIꢀcounter.ꢀMeanwhile,ꢀtheꢀinterruptꢀisꢀoccurredꢀandꢀtheꢀincompleteꢀflag,ꢀSIMICF,ꢀisꢀ
setꢀhigh.
• SIMC2 Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
CKPOLB
R/W
4
CKEG
R/W
0
3
2
CSEN
R/W
0
1
WCOL
R/W
0
0
MLS
R/W
0
TRF
R/W
0
POR
0
Bitꢀ7~6ꢀ
Bitꢀ5
D7~D6:ꢀUndefinedꢀbit
Thisꢀbitꢀcanꢀbeꢀreadꢀorꢀwrittenꢀbyꢀuserꢀsoftwareꢀprogram.
CKPOLB:ꢀDeterminesꢀtheꢀBaseꢀConditionꢀofꢀtheꢀClockꢀLine
0:ꢀTheꢀSCKꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive
1:ꢀTheꢀSCKꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive
TheꢀCKPOLBꢀbitꢀdeterminesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline,ꢀifꢀtheꢀbitꢀisꢀhigh,ꢀ
thenꢀtheꢀSCKꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀWhenꢀtheꢀCKPOLBꢀbitꢀisꢀ
low,ꢀthenꢀtheꢀSCKꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive.
Bitꢀ4
CKEG:ꢀDeterminesꢀSPIꢀSCKꢀActiveꢀClockꢀEdgeꢀType
CKPOLB=0
0:ꢀSCKꢀisꢀhighꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀrisingꢀedge
1:ꢀSCKꢀisꢀhighꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀfallingꢀedge
CKPOLB=1
0:ꢀSCKꢀisꢀlowꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀfallingꢀedge
1:ꢀSCKꢀisꢀlowꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀrisingꢀedge
TheꢀCKEGꢀandꢀCKPOLBꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀwayꢀthatꢀtheꢀclockꢀsignalꢀoutputsꢀ
andꢀinputsꢀdataꢀonꢀtheꢀSPIꢀbus.ꢀTheseꢀtwoꢀbitsꢀmustꢀbeꢀconfiguredꢀbeforeꢀdataꢀtransferꢀ
isꢀexecutedꢀotherwiseꢀanꢀerroneousꢀclockꢀedgeꢀmayꢀbeꢀgenerated.ꢀTheꢀCKPOLBꢀbitꢀ
determinesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline,ꢀifꢀtheꢀbitꢀisꢀhigh,ꢀthenꢀtheꢀSCKꢀlineꢀ
willꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀWhenꢀtheꢀCKPOLBꢀbitꢀisꢀlow,ꢀthenꢀtheꢀSCKꢀ
lineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀTheꢀCKEGꢀbitꢀdeterminesꢀactiveꢀclockꢀ
edgeꢀtypeꢀwhichꢀdependsꢀuponꢀtheꢀconditionꢀofꢀCKPOLBꢀbit.
Rev. 1.10
135
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ3
Bitꢀ2
MLS:ꢀSPIꢀDataꢀShiftꢀOrder
0:ꢀLSB
1:ꢀMSB
Thisꢀisꢀtheꢀdataꢀshiftꢀselectꢀbitꢀandꢀisꢀusedꢀtoꢀselectꢀhowꢀtheꢀdataꢀisꢀtransferred,ꢀeitherꢀ
MSBꢀorꢀLSBꢀfirst.ꢀSettingꢀtheꢀbitꢀhighꢀwillꢀselectꢀMSBꢀfirstꢀandꢀlowꢀforꢀLSBꢀfirst.
CSEN:ꢀSPIꢀSCSꢀPinꢀControl
0:ꢀDisable
1:ꢀEnable
TheꢀCSENꢀbitꢀisꢀusedꢀasꢀanꢀenable/disableꢀforꢀtheꢀSCSꢀpin.ꢀIfꢀthisꢀbitꢀisꢀlow,ꢀthenꢀtheꢀ
SCSꢀpinꢀwillꢀbeꢀdisabledꢀandꢀplacedꢀintoꢀaꢀfloatingꢀcondition.ꢀIfꢀtheꢀbitꢀisꢀhighꢀtheꢀSCSꢀ
pinꢀwillꢀbeꢀenabledꢀandꢀusedꢀasꢀaꢀselectꢀpin.
Bitꢀ1
Bitꢀ0
WCOL:ꢀSPIꢀWriteꢀCollisionꢀFlag
0:ꢀNoꢀcollision
1:ꢀCollision
TheꢀWCOLꢀflagꢀisꢀusedꢀtoꢀdetectꢀifꢀaꢀdataꢀcollisionꢀhasꢀoccurred.ꢀIfꢀthisꢀbitꢀisꢀhighꢀitꢀ
meansꢀthatꢀdataꢀhasꢀbeenꢀattemptedꢀtoꢀbeꢀwrittenꢀtoꢀtheꢀSIMDꢀregisterꢀduringꢀaꢀdataꢀ
transferꢀoperation.ꢀThisꢀwritingꢀoperationꢀwillꢀbeꢀignoredꢀifꢀdataꢀisꢀbeingꢀtransferred.ꢀ
Theꢀbitꢀcanꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.ꢀ
TRF:ꢀSPIꢀTransmit/ReceiveꢀCompleteꢀFlag
0:ꢀDataꢀisꢀbeingꢀtransferred
1:ꢀSPIꢀdataꢀtransmissionꢀisꢀcompleted
TheꢀTRFꢀbitꢀisꢀtheꢀTransmit/ReceiveꢀCompleteꢀflagꢀandꢀisꢀsetꢀhighꢀautomaticallyꢀwhenꢀ
anꢀSPIꢀdataꢀtransmissionꢀisꢀcompleted,ꢀbutꢀmustꢀclearedꢀtoꢀ“0”ꢀbyꢀtheꢀapplicationꢀ
program.ꢀItꢀcanꢀbeꢀusedꢀtoꢀgenerateꢀanꢀinterrupt.
SPI Communication
AfterꢀtheꢀSPIꢀinterfaceꢀisꢀenabledꢀbyꢀsettingꢀtheꢀSIMENꢀbitꢀhigh,ꢀthenꢀinꢀtheꢀMasterꢀMode,ꢀwhenꢀ
dataꢀisꢀwrittenꢀtoꢀtheꢀSIMDꢀregister,ꢀtransmission/receptionꢀwillꢀbeginꢀsimultaneously.ꢀWhenꢀtheꢀ
dataꢀtransferꢀisꢀcomplete,ꢀtheꢀTRFꢀflagꢀwillꢀbeꢀsetꢀautomatically,ꢀbutꢀmustꢀbeꢀclearedꢀusingꢀtheꢀ
applicationꢀprogram.ꢀInꢀtheꢀSlaveꢀMode,ꢀwhenꢀtheꢀclockꢀsignalꢀfromꢀtheꢀmasterꢀhasꢀbeenꢀreceived,ꢀ
anyꢀdataꢀinꢀtheꢀSIMDꢀregisterꢀwillꢀbeꢀtransmittedꢀandꢀanyꢀdataꢀonꢀtheꢀSDIꢀpinꢀwillꢀbeꢀshiftedꢀintoꢀ
theꢀSIMDꢀregister.ꢀTheꢀmasterꢀshouldꢀoutputꢀanꢀSCSꢀsignalꢀtoꢀenableꢀtheꢀslaveꢀdeviceꢀbeforeꢀaꢀ
clockꢀsignalꢀisꢀprovided.ꢀTheꢀslaveꢀdataꢀtoꢀbeꢀtransferredꢀshouldꢀbeꢀwellꢀpreparedꢀatꢀtheꢀappropriateꢀ
momentꢀrelativeꢀtoꢀtheꢀSCSꢀsignalꢀdependingꢀuponꢀtheꢀconfigurationsꢀofꢀtheꢀCKPOLBꢀbitꢀandꢀCKEGꢀ
bit.ꢀTheꢀaccompanyingꢀtimingꢀdiagramꢀshowsꢀtheꢀrelationshipꢀbetweenꢀtheꢀslaveꢀdataꢀandꢀSCSꢀsignalꢀ
forꢀvariousꢀconfigurationsꢀofꢀtheꢀCKPOLBꢀandꢀCKEGꢀbits.
TheꢀSPIꢀwillꢀcontinueꢀtoꢀfunctionꢀinꢀspecialꢀIDLEꢀModesꢀifꢀtheꢀclockꢀsourceꢀusedꢀbyꢀtheꢀSPIꢀ
interfaceꢀisꢀstillꢀactive.
Rev. 1.10
136
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
SIMEN=1ꢄ CSEN=0 (Exteꢁnal Pꢀll-high)
SCS
SIMENꢄ CSEN=1
SCK (CKPOLB=1ꢄ CKEG=0)
SCK (CKPOLB=0ꢄ CKEG=0)
SCK (CKPOLB=1ꢄ CKEG=1)
SCK (CKPOLB=0ꢄ CKEG=1)
SDO (CKEG=0)
D7/D0 D6/D1 D5/Dꢅ Dꢃ/D3 D3/Dꢃ Dꢅ/D5 D1/D6 D0/D7
D7/D0 D6/D1 D5/Dꢅ Dꢃ/D3 D3/Dꢃ Dꢅ/D5 D1/D6 D0/D7
SDO (CKEG=1)
SDI Data Captꢀꢁe
Wꢁite to SIMD
SPI Master Mode Timing
SCS
SCK (CKPOLB=1)
SCK (CKPOLB=0)
SDO
D7/D0 D6/D1 D5/Dꢅ Dꢃ/D3 D3/Dꢃ Dꢅ/D5 D1/D6 D0/D7
SDI Data Captꢀꢁe
Wꢁite to SIMD
(SDO does not change ꢀntil fiꢁst SCK edge)
SPI Slave Mode Timing – CKEG=0
SCS
SCK (CKPOLB=1)
SCK (CKPOLB=0)
SDO
D7/D0 D6/D1 D5/Dꢅ Dꢃ/D3 D3/Dꢃ Dꢅ/D5 D1/D6 D0/D7
SDI Data Captꢀꢁe
Wꢁite to SIMD
(SDO changes as soon as wꢁiting occꢀꢁs; SDO is floating if SCS=1)
Note: Foꢁ SPI slave modeꢄ if SIMEN=1 and CSEN=0ꢄ SPI is alwaꢂs enabled
and ignoꢁes the SCS level.
SPI Slave Mode Timing – CKEG=1
Rev. 1.10
137
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
SPI Tꢁansfeꢁ
A
Wꢁite Data
Cleaꢁ WCOL
into SIMD
Masteꢁ
Slave
Masteꢁ oꢁ Slave
?
Y
WCOL=1?
SIM[ꢅ:0]=000ꢄ 001ꢄ
010ꢄ 011 oꢁ 100
SIM[ꢅ:0]=101
N
Tꢁansmission
N
completed?
(TRF=1?)
Configꢀꢁe CKPOLBꢄ
CKEGꢄ CSEN and MLS
Y
Read Data
fꢁom SIMD
SIMEN=1
A
Cleaꢁ TRF
N
Tꢁansfeꢁ finished?
Y
END
SPI Transfer Control Flowchart
Rev. 1.10
13ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
I2C Interface
TheꢀI2Cꢀinterfaceꢀisꢀusedꢀtoꢀcommunicateꢀwithꢀexternalꢀperipheralꢀdevicesꢀsuchꢀasꢀsensorsꢀetc.ꢀ
OriginallyꢀdevelopedꢀbyꢀPhilips,ꢀitꢀisꢀaꢀtwoꢀlineꢀlowꢀspeedꢀserialꢀinterfaceꢀforꢀsynchronousꢀserialꢀ
dataꢀtransfer.ꢀTheꢀadvantageꢀofꢀonlyꢀtwoꢀlinesꢀforꢀcommunication,ꢀrelativelyꢀsimpleꢀcommunicationꢀ
protocolꢀandꢀtheꢀabilityꢀtoꢀaccommodateꢀmultipleꢀdevicesꢀonꢀtheꢀsameꢀbusꢀhasꢀmadeꢀitꢀanꢀextremelyꢀ
popularꢀinterfaceꢀtypeꢀforꢀmanyꢀapplications.
VDD
SDA
SCL
Device
Slave
Device
Masteꢁ
Device
Slave
I2C Master/Slave Bus Connection
I2C Interface Operation
TheꢀI2Cꢀserialꢀinterfaceꢀisꢀaꢀtwoꢀlineꢀinterface,ꢀaꢀserialꢀdataꢀline,ꢀSDA,ꢀandꢀserialꢀclockꢀline,ꢀSCL.ꢀAsꢀ
manyꢀdevicesꢀmayꢀbeꢀconnectedꢀtogetherꢀonꢀtheꢀsameꢀbus,ꢀtheirꢀoutputsꢀareꢀbothꢀopenꢀdrainꢀtypes.ꢀ
Forꢀthisꢀreasonꢀitꢀisꢀnecessaryꢀthatꢀexternalꢀpull-highꢀresistorsꢀareꢀconnectedꢀtoꢀtheseꢀoutputs.ꢀNoteꢀ
thatꢀnoꢀchipꢀselectꢀlineꢀexists,ꢀasꢀeachꢀdeviceꢀonꢀtheꢀI2Cꢀbusꢀisꢀidentifiedꢀbyꢀaꢀuniqueꢀaddressꢀwhichꢀ
willꢀbeꢀtransmittedꢀandꢀreceivedꢀonꢀtheꢀI2Cꢀbus.ꢀ
WhenꢀtwoꢀdevicesꢀcommunicateꢀwithꢀeachꢀotherꢀonꢀtheꢀbidirectionalꢀI2Cꢀbus,ꢀoneꢀisꢀknownꢀasꢀtheꢀ
masterꢀdeviceꢀandꢀoneꢀasꢀtheꢀslaveꢀdevice.ꢀBothꢀmasterꢀandꢀslaveꢀcanꢀtransmitꢀandꢀreceiveꢀdata;ꢀ
however,ꢀitꢀisꢀtheꢀmasterꢀdeviceꢀthatꢀhasꢀoverallꢀcontrolꢀofꢀtheꢀbus.ꢀForꢀtheꢀdevices,ꢀwhichꢀonlyꢀ
operateꢀinꢀslaveꢀmode,ꢀthereꢀareꢀtwoꢀmethodsꢀofꢀtransferringꢀdataꢀonꢀtheꢀI2Cꢀbus,ꢀtheꢀslaveꢀtransmitꢀ
modeꢀandꢀtheꢀslaveꢀreceiveꢀmode.ꢀTheꢀpull-upꢀcontrolꢀfunctionꢀpin-sharedꢀwithꢀSCL/SDAꢀpinꢀisꢀstillꢀ
applicableꢀevenꢀifꢀI2Cꢀdeviceꢀisꢀactivatedꢀandꢀtheꢀrelatedꢀinternalꢀpull-upꢀregisterꢀcouldꢀbeꢀcontrolledꢀ
byꢀitsꢀcorrespondingꢀpull-upꢀcontrolꢀregister.
Data Bꢀs
IꢅC Data Registeꢁ
(SIMD)
IꢅC Addꢁess Registeꢁ
(SIMA)
Addꢁess Match–HAAS
Addꢁess
IꢅC Inteꢁꢁꢀpt
Diꢁection Contꢁol
HTX
Compaꢁatoꢁ
fSYS
SCL Pin
SDA Pin
Deboꢀnce
Ciꢁcꢀitꢁꢂ
Data in MSB
Shift Registeꢁ
Read/Wꢁite Slave
SRW
M
U
X
Data oꢀt MSB
TXAK
SIMDEB[1:0]
ꢆ-bit Data Tꢁansfeꢁ Conplete–HCF
Tꢁansmit/Receive
Contꢁol Unit
Detect Staꢁt oꢁ Stop
HBB
SIMTOF
fSUB
SIMTOEN
Time-oꢀt Contꢁol
Addꢁess Match
I2C Block Diagram
Rev. 1.10
139
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
START signal
fꢁom Masteꢁ
Send slave addꢁess
and R/W bit fꢁom Masteꢁ
Acknowledge
fꢁom slave
Send data bꢂte
fꢁom Masteꢁ
Acknowledge
fꢁom slave
STOP signal
fꢁom Masteꢁ
I2C Registers
ThereꢀareꢀthreeꢀcontrolꢀregistersꢀassociatedꢀwithꢀtheꢀI2Cꢀbus,ꢀSIMC0,ꢀSIMC1ꢀandꢀSIMTOC,ꢀoneꢀ
addressꢀregister,ꢀSIMAꢀandꢀoneꢀdataꢀregister,ꢀSIMD.ꢀTheꢀSIMDꢀregister,ꢀwhichꢀisꢀshownꢀinꢀtheꢀ
aboveꢀSPIꢀsection,ꢀisꢀusedꢀtoꢀstoreꢀtheꢀdataꢀbeingꢀtransmittedꢀandꢀreceivedꢀonꢀtheꢀI2Cꢀbus.ꢀNoteꢀthatꢀ
theꢀSIMAꢀregisterꢀalsoꢀhasꢀtheꢀnameꢀSIMC2ꢀwhichꢀisꢀusedꢀbyꢀtheꢀSPIꢀfunction.ꢀBitꢀSIMENꢀandꢀbitsꢀ
SIM2~SIM0ꢀinꢀregisterꢀSIMC0ꢀareꢀusedꢀbyꢀtheꢀI2Cꢀinterface.ꢀTheꢀSIMTOCꢀregisterꢀisꢀusedꢀforꢀI2Cꢀ
time-outꢀcontrol.
Bit
Register
Name
7
6
5
4
—
3
2
1
0
SIMICF
RXAK
D0
SIMC0
SIMC1
SIMD
SIMꢅ
HCF
D7
SIM1
HAAS
D6
SIM0
HBB
D5
SIMDEB1 SIMDEB0 SIMEN
HTX
Dꢃ
A3
TXAK
D3
SRW
Dꢅ
IAMWU
D1
SIMA
A6
A5
Aꢃ
Aꢅ
A1
A0
D0
SIMTOC SIMTOEN SIMTOF SIMTOS5 SIMTOSꢃ SIMTOS3 SIMTOSꢅ SIMTOS1 SIMTOS0
I2C Register List
• SIMC0 Register
Bit
Name
R/W
7
SIMꢅ
R/W
1
6
SIM1
R/W
1
5
SIM0
R/W
1
4
3
2
1
SIMEN
R/W
0
0
SIMICF
R/W
0
—
—
—
SIMDEB1 SIMDEB0
R/W
0
R/W
0
POR
Bitꢀ7~5
SIM2~SIM0:ꢀSIMꢀOperatingꢀModeꢀControl
000:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/4
001:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/16
010:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/64
011:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSUB
100:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀPTM2ꢀCCRPꢀmatchꢀfrequency/2
101:ꢀSPIꢀslaveꢀmode
110:ꢀI2Cꢀslaveꢀmode
111:ꢀUnusedꢀmode
TheseꢀbitsꢀsetupꢀtheꢀoverallꢀoperatingꢀmodeꢀofꢀtheꢀSIMꢀfunction.ꢀAsꢀwellꢀasꢀselectingꢀ
ifꢀtheꢀI2CꢀorꢀSPIꢀfunction,ꢀtheyꢀareꢀusedꢀtoꢀcontrolꢀtheꢀSPIꢀMaster/Slaveꢀselectionꢀandꢀ
theꢀSPIꢀMasterꢀclockꢀfrequency.ꢀTheꢀSPIꢀclockꢀisꢀaꢀfunctionꢀofꢀtheꢀsystemꢀclockꢀbutꢀ
canꢀalsoꢀbeꢀchosenꢀtoꢀbeꢀsourcedꢀfromꢀtheꢀPTM2.ꢀIfꢀtheꢀSPIꢀSlaveꢀModeꢀisꢀselectedꢀ
thenꢀtheꢀclockꢀwillꢀbeꢀsuppliedꢀbyꢀanꢀexternalꢀMasterꢀdevice.
Rev. 1.10
1ꢃ0
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ4ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ3~2
SIMDEB1~SIMDEB0:ꢀI2CꢀDebounceꢀTimeꢀSelection
00:ꢀNoꢀdebounce
01:ꢀ2ꢀsystemꢀclockꢀdebounce
1x:ꢀ4ꢀsystemꢀclockꢀdebounce
Bitꢀ1
SIMEN:ꢀSIMꢀControl
0:ꢀDisable
1:ꢀEnable
Theꢀbitꢀisꢀtheꢀoverallꢀon/offꢀcontrolꢀforꢀtheꢀSIMꢀinterface.ꢀWhenꢀtheꢀSIMENꢀbitꢀisꢀ
clearedꢀtoꢀ“0”ꢀtoꢀdisableꢀtheꢀSIMꢀinterface,ꢀtheꢀSDI,ꢀSDO,ꢀSCKꢀandꢀSCS,ꢀorꢀSDAꢀ
andꢀSCLꢀlinesꢀwillꢀbeꢀinꢀaꢀfloatingꢀconditionꢀandꢀtheꢀSIMꢀoperatingꢀcurrentꢀwillꢀbeꢀ
reducedꢀtoꢀaꢀminimumꢀvalue.ꢀWhenꢀtheꢀbitꢀisꢀhighꢀtheꢀSIMꢀinterfaceꢀisꢀenabled.ꢀTheꢀ
SIMꢀconfigurationꢀoptionꢀmustꢀhaveꢀfirstꢀenabledꢀtheꢀSIMꢀinterfaceꢀforꢀthisꢀbitꢀtoꢀbeꢀ
effective.ꢀIfꢀtheꢀSIMꢀisꢀconfiguredꢀtoꢀoperateꢀasꢀanꢀSPIꢀinterfaceꢀviaꢀtheꢀSIM2~SIM0ꢀ
bits,ꢀtheꢀcontentsꢀofꢀtheꢀSPIꢀcontrolꢀregistersꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀwhenꢀ
theꢀSIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀandꢀshouldꢀthereforeꢀbeꢀfirstꢀinitialisedꢀbyꢀ
theꢀapplicationꢀprogram.ꢀIfꢀtheꢀSIMꢀisꢀconfiguredꢀtoꢀoperateꢀasꢀanꢀI2Cꢀinterfaceꢀviaꢀtheꢀ
SIM2~SIM0ꢀbitsꢀandꢀtheꢀSIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀtheꢀcontentsꢀofꢀtheꢀI2Cꢀ
controlꢀbitsꢀsuchꢀasꢀHTXꢀandꢀTXAKꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀandꢀshouldꢀ
thereforeꢀbeꢀfirstꢀinitialisedꢀbyꢀtheꢀapplicationꢀprogramꢀwhileꢀtheꢀrelevantꢀI2Cꢀflagsꢀ
suchꢀasꢀHCF,ꢀHAAS,ꢀHBB,ꢀSRWꢀandꢀRXAKꢀwillꢀbeꢀsetꢀtoꢀtheirꢀdefaultꢀstates.
Bitꢀ0
SIMICF:ꢀSIMꢀSPIꢀIncompleteꢀFlag
SIMICFꢀisꢀofꢀnoꢀusedꢀinꢀI2CꢀmodeꢀofꢀSIM,ꢀpleaseꢀignoreꢀthisꢀflagꢀwhenꢀoperateꢀinꢀI2Cꢀ
mode.
• SIMC1 Register
Bit
Name
R/W
7
HCF
R
6
HAAS
R
5
HBB
R
4
3
TXAK
R/W
0
2
SRW
R
1
IAMWU
R/W
0
0
RXAK
R
HTX
R/W
0
POR
1
0
0
0
1
Bitꢀ7
HCF:ꢀI2CꢀBusꢀDataꢀTransferꢀCompletionꢀFlag
0:ꢀDataꢀisꢀbeingꢀtransferred
1:ꢀCompletionꢀofꢀanꢀ8-bitꢀdataꢀtransfer
TheꢀHCFꢀflagꢀisꢀtheꢀdataꢀtransferꢀflag.ꢀThisꢀflagꢀwillꢀbeꢀ“0”ꢀwhenꢀdataꢀisꢀbeingꢀ
transferred.ꢀUponꢀcompletionꢀofꢀanꢀ8-bitꢀdataꢀtransferꢀtheꢀflagꢀwillꢀgoꢀhighꢀandꢀanꢀ
interruptꢀwillꢀbeꢀgenerated.
Bitꢀ6
Bitꢀ5
HAAS:ꢀI2CꢀBusꢀAddressꢀMatchꢀFlag
0:ꢀNotꢀaddressꢀmatch
1:ꢀAddressꢀmatch
TheꢀHAASꢀflagꢀisꢀtheꢀaddressꢀmatchꢀflag.ꢀThisꢀflagꢀisꢀusedꢀtoꢀdetermineꢀifꢀtheꢀslaveꢀ
deviceꢀaddressꢀisꢀtheꢀsameꢀasꢀtheꢀmasterꢀtransmitꢀaddress.ꢀIfꢀtheꢀaddressesꢀmatchꢀthenꢀ
thisꢀbitꢀwillꢀbeꢀhigh,ꢀifꢀthereꢀisꢀnoꢀmatchꢀthenꢀtheꢀflagꢀwillꢀbeꢀlow.
HBB:ꢀI2CꢀBusꢀBusyꢀFlag
0:ꢀI2CꢀBusꢀisꢀnotꢀbusy
1:ꢀI2CꢀBusꢀisꢀbusy
TheꢀHBBꢀflagꢀisꢀtheꢀI2Cꢀbusyꢀflag.ꢀThisꢀflagꢀwillꢀbeꢀ“1”ꢀwhenꢀtheꢀI2Cꢀbusꢀisꢀbusyꢀ
whichꢀwillꢀoccurꢀwhenꢀaꢀSTARTꢀsignalꢀisꢀdetected.ꢀTheꢀflagꢀwillꢀbeꢀclearedꢀtoꢀ“0”ꢀ
whenꢀtheꢀbusꢀisꢀfreeꢀwhichꢀwillꢀoccurꢀwhenꢀaꢀSTOPꢀsignalꢀisꢀdetected.
Rev. 1.10
1ꢃ1
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ4
Bitꢀ3
HTX:ꢀSelectꢀI2CꢀSlaveꢀDeviceꢀisꢀTransmitterꢀorꢀReceiver
0:ꢀSlaveꢀdeviceꢀisꢀtheꢀreceiver
1:ꢀSlaveꢀdeviceꢀisꢀtheꢀtransmitter
TXAK:ꢀI2CꢀBusꢀTransmitꢀAcknowledgeꢀFlag
0:ꢀSlaveꢀsendꢀacknowledgeꢀflag
1:ꢀSlaveꢀdoꢀnotꢀsendꢀacknowledgeꢀflag
TheꢀTXAKꢀbitꢀisꢀtheꢀtransmitꢀacknowledgeꢀflag.ꢀAfterꢀtheꢀslaveꢀdeviceꢀreceiptꢀofꢀ8-bitꢀ
ofꢀdata,ꢀthisꢀbitꢀwillꢀbeꢀtransmittedꢀtoꢀtheꢀbusꢀonꢀtheꢀ9thꢀclockꢀfromꢀtheꢀslaveꢀdevice.ꢀ
TheꢀslaveꢀdeviceꢀmustꢀalwaysꢀsetꢀTXAKꢀbitꢀtoꢀ“0”ꢀbeforeꢀfurtherꢀdataꢀisꢀreceived.
Bitꢀ2
SRW:ꢀI2CꢀSlaveꢀRead/WriteꢀFlag
0:ꢀSlaveꢀdeviceꢀshouldꢀbeꢀinꢀreceiveꢀmode
1:ꢀSlaveꢀdeviceꢀshouldꢀbeꢀinꢀtransmitꢀmode
TheꢀSRWꢀflagꢀisꢀtheꢀI2CꢀSlaveꢀRead/Writeꢀflag.ꢀThisꢀflagꢀdeterminesꢀwhetherꢀ
theꢀmasterꢀdeviceꢀwishesꢀtoꢀtransmitꢀorꢀreceiveꢀdataꢀfromꢀtheꢀI2Cꢀbus.ꢀWhenꢀtheꢀ
transmittedꢀaddressꢀandꢀslaveꢀaddressꢀisꢀmatch,ꢀthatꢀisꢀwhenꢀtheꢀHAASꢀflagꢀisꢀsetꢀhigh,ꢀ
theꢀslaveꢀdeviceꢀwillꢀcheckꢀtheꢀSRWꢀflagꢀtoꢀdetermineꢀwhetherꢀitꢀshouldꢀbeꢀinꢀtransmitꢀ
modeꢀorꢀreceiveꢀmode.ꢀIfꢀtheꢀSRWꢀflagꢀisꢀhigh,ꢀtheꢀmasterꢀisꢀrequestingꢀtoꢀreadꢀdataꢀ
fromꢀtheꢀbus,ꢀsoꢀtheꢀslaveꢀdeviceꢀshouldꢀbeꢀinꢀtransmitꢀmode.ꢀWhenꢀtheꢀSRWꢀflagꢀisꢀ“0”,ꢀ
theꢀmasterꢀwillꢀwriteꢀdataꢀtoꢀtheꢀbus,ꢀthereforeꢀtheꢀslaveꢀdeviceꢀshouldꢀbeꢀinꢀreceiveꢀ
modeꢀtoꢀreadꢀthisꢀdata.
Bitꢀ1
Bitꢀ0
IAMWU:ꢀI2CꢀAddressꢀMatchꢀWakeꢀUpꢀFunctionꢀControl
0:ꢀDisable
1:ꢀEnable
Thisꢀbitꢀshouldꢀbeꢀsetꢀtoꢀ“1”ꢀtoꢀenableꢀtheꢀI2CꢀaddressꢀmatchꢀwakeꢀupꢀfromꢀtheꢀSLEEPꢀ
orꢀIDLEꢀMode.ꢀIfꢀtheꢀIAMWUꢀbitꢀhasꢀbeenꢀsetꢀbeforeꢀenteringꢀeitherꢀtheꢀSLEEPꢀorꢀ
IDLEꢀmodeꢀtoꢀenableꢀtheꢀI2Cꢀaddressꢀmatchꢀwakeꢀup,ꢀthenꢀthisꢀbitꢀmustꢀbeꢀclearedꢀbyꢀ
theꢀapplicationꢀprogramꢀafterꢀwake-upꢀtoꢀensureꢀcorrectꢀdeviceꢀoperation.
RXAK:ꢀI2CꢀBusꢀReceiveꢀAcknowledgeꢀFlag
0:ꢀSlaveꢀreceivesꢀacknowledgeꢀflag
1:ꢀSlaveꢀdoesꢀnotꢀreceiveꢀacknowledgeꢀflag
TheꢀRXAKꢀflagꢀisꢀtheꢀreceiverꢀacknowledgeꢀflag.ꢀWhenꢀtheꢀRXAKꢀflagꢀisꢀ“0”,ꢀitꢀ
meansꢀthatꢀaꢀacknowledgeꢀsignalꢀhasꢀbeenꢀreceivedꢀatꢀtheꢀ9thꢀclock,ꢀafterꢀ8ꢀbitsꢀofꢀdataꢀ
haveꢀbeenꢀtransmitted.ꢀWhenꢀtheꢀslaveꢀdeviceꢀinꢀtheꢀtransmitꢀmode,ꢀtheꢀslaveꢀdeviceꢀ
checksꢀtheꢀRXAKꢀflagꢀtoꢀdetermineꢀifꢀtheꢀmasterꢀreceiveꢀwishesꢀtoꢀreceiveꢀtheꢀnextꢀ
byte.ꢀTheꢀslaveꢀtransmitterꢀwillꢀthereforeꢀcontinueꢀsendingꢀoutꢀdataꢀuntilꢀtheꢀRXAKꢀ
flagꢀisꢀ“1”.ꢀWhenꢀthisꢀoccurs,ꢀtheꢀslaveꢀtransmitterꢀwillꢀreleaseꢀtheꢀSDAꢀlineꢀtoꢀallowꢀ
theꢀmasterꢀtoꢀsendꢀaꢀSTOPꢀsignalꢀtoꢀreleaseꢀtheꢀI2Cꢀbus.
Rev. 1.10
1ꢃꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
TheꢀSIMDꢀregisterꢀisꢀusedꢀtoꢀstoreꢀtheꢀdataꢀbeingꢀtransmittedꢀandꢀreceived.ꢀTheꢀsameꢀregisterꢀisꢀ
usedꢀbyꢀbothꢀtheꢀSPIꢀandꢀI2Cꢀfunctions.ꢀBeforeꢀtheꢀdeviceꢀwriteꢀdataꢀtoꢀtheꢀI2Cꢀbus,ꢀtheꢀactualꢀdataꢀtoꢀ
beꢀtransmittedꢀmustꢀbeꢀplacedꢀinꢀtheꢀSIMDꢀregister.ꢀAfterꢀtheꢀdataꢀisꢀreceivedꢀfromꢀtheꢀI2Cꢀbus,ꢀtheꢀ
deviceꢀcanꢀreadꢀitꢀfromꢀtheꢀSIMDꢀregister.ꢀAnyꢀtransmissionꢀorꢀreceptionꢀofꢀdataꢀfromꢀtheꢀI2Cꢀbusꢀ
mustꢀbeꢀmadeꢀviaꢀtheꢀSIMDꢀregister.
• SIMD Register
Bit
Name
R/W
7
D7
R/W
x
6
D6
R/W
x
5
D5
R/W
x
4
Dꢃ
R/W
x
3
D3
R/W
x
2
Dꢅ
R/W
x
1
D1
R/W
x
0
D0
R/W
POR
x
“x” ꢀnknown
• SIMA Register
Bit
Name
R/W
7
A6
R/W
0
6
A5
R/W
0
5
Aꢃ
R/W
0
4
A3
R/W
0
3
Aꢅ
R/W
0
2
A1
R/W
0
1
A0
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~1ꢀ
A6~A0:ꢀI2CꢀSlaveꢀaddress
A6~A0ꢀisꢀtheꢀI2Cꢀslaveꢀaddressꢀbitꢀ6~bitꢀ0.
TheꢀSIMAꢀregisterꢀisꢀalsoꢀusedꢀbyꢀtheꢀSPIꢀinterfaceꢀbutꢀhasꢀtheꢀnameꢀSIMC2.ꢀTheꢀ
SIMAꢀregisterꢀisꢀtheꢀlocationꢀwhereꢀtheꢀ7-bitꢀslaveꢀaddressꢀofꢀtheꢀslaveꢀdeviceꢀisꢀ
stored.ꢀBitꢀ7~Bitꢀ1ꢀofꢀtheꢀSIMAꢀregisterꢀdefineꢀtheꢀdeviceꢀslaveꢀaddress.ꢀBitꢀ0ꢀisꢀnotꢀ
defined.
Whenꢀaꢀmasterꢀdevice,ꢀwhichꢀisꢀconnectedꢀtoꢀtheꢀI2Cꢀbus,ꢀsendsꢀoutꢀanꢀaddress,ꢀwhichꢀ
matchesꢀtheꢀslaveꢀaddressꢀinꢀtheꢀSIMAꢀregister,ꢀtheꢀslaveꢀdeviceꢀwillꢀbeꢀselected.ꢀNoteꢀ
thatꢀtheꢀSIMAꢀregisterꢀisꢀtheꢀsameꢀregisterꢀaddressꢀasꢀSIMC2ꢀwhichꢀisꢀusedꢀbyꢀtheꢀSPIꢀ
interface.
Bitꢀ0
D0:ꢀUndefinedꢀbit
Thisꢀbitꢀcanꢀbeꢀreadꢀorꢀwrittenꢀbyꢀuserꢀsoftwareꢀprogram.
• SIMTOC Register
Bit
7
6
5
4
3
2
1
0
Name SIMTOEN SIMTOF SIMTOS5 SIMTOSꢃ SIMTOS3 SIMTOSꢅ SIMTOS1 SIMTOS0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7ꢀ
SIMTOEN:ꢀI2CꢀinterfaceꢀTime-outꢀcontrol
0:ꢀDisable
1:ꢀEnable
Bitꢀ6
SIMTOF:ꢀI2CꢀinterfaceꢀTime-outꢀflag
0:ꢀNoꢀoccurred
1:ꢀOccurred
TheꢀSIMTOFꢀflagꢀisꢀsetꢀbyꢀtheꢀtime-outꢀcircuitryꢀwhenꢀtheꢀtime-outꢀeventꢀoccursꢀandꢀ
clearedꢀbyꢀsoftwareꢀprogram.
Bitꢀ5~0
SIMTOS5~SIMTOS0:ꢀI2CꢀinterfaceꢀTime-outꢀperiodꢀselection
TheꢀI2CꢀTime-OutꢀclockꢀsourceꢀisꢀfSUB/32.ꢀ
TheꢀI2CꢀTime-Outꢀtimeꢀisꢀ([SIMTOS5:SIMTOS0]ꢀ+ꢀ1)ꢀ×ꢀ(32/fSUB
)
Rev. 1.10
1ꢃ3
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
I2C Bus Communication
CommunicationꢀonꢀtheꢀI2Cꢀbusꢀrequiresꢀfourꢀseparateꢀsteps,ꢀaꢀSTARTꢀsignal,ꢀaꢀslaveꢀdeviceꢀaddressꢀ
transmission,ꢀaꢀdataꢀtransmissionꢀandꢀfinallyꢀaꢀSTOPꢀsignal.ꢀWhenꢀaꢀSTARTꢀsignalꢀisꢀplacedꢀonꢀtheꢀ
I2Cꢀbus,ꢀallꢀdevicesꢀonꢀtheꢀbusꢀwillꢀreceiveꢀthisꢀsignalꢀandꢀbeꢀnotifiedꢀofꢀtheꢀimminentꢀarrivalꢀofꢀdataꢀ
onꢀtheꢀbus.ꢀTheꢀfirstꢀsevenꢀbitsꢀofꢀtheꢀdataꢀwillꢀbeꢀtheꢀslaveꢀaddressꢀwithꢀtheꢀfirstꢀbitꢀbeingꢀtheꢀMSB.ꢀ
Ifꢀtheꢀaddressꢀofꢀtheꢀslaveꢀdeviceꢀmatchesꢀthatꢀofꢀtheꢀtransmittedꢀaddress,ꢀtheꢀHAASꢀbitꢀinꢀtheꢀSIMC1ꢀ
registerꢀwillꢀbeꢀsetꢀandꢀanꢀI2Cꢀinterruptꢀwillꢀbeꢀgenerated.ꢀAfterꢀenteringꢀtheꢀinterruptꢀserviceꢀroutine,ꢀ
theꢀslaveꢀdeviceꢀmustꢀfirstꢀcheckꢀtheꢀconditionꢀofꢀtheꢀHAASꢀbitꢀandꢀSIMTOFꢀbitꢀtoꢀdetermineꢀ
whetherꢀtheꢀinterruptꢀsourceꢀoriginatesꢀfromꢀanꢀaddressꢀmatchꢀorꢀfromꢀtheꢀcompletionꢀofꢀanꢀ8-bitꢀdataꢀ
transferꢀorꢀfromꢀtheꢀI2Cꢀcommunicationꢀtime-out.ꢀDuringꢀaꢀdataꢀtransfer,ꢀnoteꢀthatꢀafterꢀtheꢀ7-bitꢀslaveꢀ
addressꢀhasꢀbeenꢀtransmitted,ꢀtheꢀfollowingꢀbit,ꢀwhichꢀisꢀtheꢀ8thꢀbit,ꢀisꢀtheꢀread/writeꢀbitꢀwhoseꢀvalueꢀ
willꢀbeꢀplacedꢀinꢀtheꢀSRWꢀbit.ꢀThisꢀbitꢀwillꢀbeꢀcheckedꢀbyꢀtheꢀslaveꢀdeviceꢀtoꢀdetermineꢀwhetherꢀtoꢀgoꢀ
intoꢀtransmitꢀorꢀreceiveꢀmode.ꢀBeforeꢀanyꢀtransferꢀofꢀdataꢀtoꢀorꢀfromꢀtheꢀI2Cꢀbus,ꢀtheꢀmicrocontrollerꢀ
mustꢀinitialiseꢀtheꢀbus,ꢀtheꢀfollowingꢀareꢀstepsꢀtoꢀachieveꢀthis:ꢀ
•ꢀ Stepꢀ1
SetꢀtheꢀSIM2~SIM0ꢀbitsꢀtoꢀ“110”ꢀandꢀtheꢀSIMENꢀbitsꢀtoꢀ“1”ꢀinꢀtheꢀSIMC0ꢀregisterꢀtoꢀenableꢀtheꢀ
I2Cꢀbus.
•ꢀ Stepꢀ2
WriteꢀtheꢀslaveꢀaddressꢀtoꢀtheꢀI2CꢀbusꢀaddressꢀregisterꢀSIMA.
•ꢀ Stepꢀ3
SetꢀtheꢀinterruptꢀenableꢀbitꢀSIMEꢀtoꢀenableꢀtheꢀSIMꢀinterrupt.
Staꢁt
Set SIM[ꢅ:0]=110
Set SIMEN
Wꢁite Slave
Addꢁess to SIMA
IꢅC Bꢀs
Inteꢁꢁꢀpt=?
No
Yes
CLR SIME
SET SIME
Wait foꢁ Inteꢁꢁꢀpt
Poll SIMF to decide when
to go to IꢅC Bꢀs ISR
Goto Main Pꢁogꢁam
Goto Main Pꢁogꢁam
I2C Bus Initialisation Flowchart
Rev. 1.10
1ꢃꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
I2C Bus Start Signal
TheꢀSTARTꢀsignalꢀcanꢀonlyꢀbeꢀgeneratedꢀbyꢀtheꢀmasterꢀdeviceꢀconnectedꢀtoꢀtheꢀI2Cꢀbusꢀandꢀnotꢀbyꢀ
theꢀslaveꢀdevice.ꢀThisꢀSTARTꢀsignalꢀwillꢀbeꢀdetectedꢀbyꢀallꢀdevicesꢀconnectedꢀtoꢀtheꢀI2Cꢀbus.ꢀWhenꢀ
detected,ꢀthisꢀindicatesꢀthatꢀtheꢀI2CꢀbusꢀisꢀbusyꢀandꢀthereforeꢀtheꢀHBBꢀbitꢀwillꢀbeꢀset.ꢀAꢀSTARTꢀ
conditionꢀoccursꢀwhenꢀaꢀhighꢀtoꢀlowꢀtransitionꢀonꢀtheꢀSDAꢀlineꢀtakesꢀplaceꢀwhenꢀtheꢀSCLꢀlineꢀ
remainsꢀhigh.ꢀ
Slave Address
TheꢀtransmissionꢀofꢀaꢀSTARTꢀsignalꢀbyꢀtheꢀmasterꢀwillꢀbeꢀdetectedꢀbyꢀallꢀdevicesꢀonꢀtheꢀI2Cꢀbus.ꢀ
Toꢀdetermineꢀwhichꢀslaveꢀdeviceꢀtheꢀmasterꢀwishesꢀtoꢀcommunicateꢀwith,ꢀtheꢀaddressꢀofꢀtheꢀslaveꢀ
deviceꢀwillꢀbeꢀsentꢀoutꢀimmediatelyꢀfollowingꢀtheꢀSTARTꢀsignal.ꢀAllꢀslaveꢀdevices,ꢀafterꢀreceivingꢀ
thisꢀ7-bitꢀaddressꢀdata,ꢀwillꢀcompareꢀitꢀwithꢀtheirꢀownꢀ7-bitꢀslaveꢀaddress.ꢀIfꢀtheꢀaddressꢀsentꢀoutꢀbyꢀ
theꢀmasterꢀmatchesꢀtheꢀinternalꢀaddressꢀofꢀtheꢀmicrocontrollerꢀslaveꢀdevice,ꢀthenꢀanꢀinternalꢀI2Cꢀbusꢀ
interruptꢀsignalꢀwillꢀbeꢀgenerated.ꢀTheꢀnextꢀbitꢀfollowingꢀtheꢀaddress,ꢀwhichꢀisꢀtheꢀ8thꢀbit,ꢀdefinesꢀ
theꢀread/writeꢀstatusꢀandꢀwillꢀbeꢀsavedꢀtoꢀtheꢀSRWꢀbitꢀofꢀtheꢀSIMC1ꢀregister.ꢀTheꢀslaveꢀdeviceꢀwillꢀ
thenꢀtransmitꢀanꢀacknowledgeꢀbit,ꢀwhichꢀisꢀaꢀlowꢀlevel,ꢀasꢀtheꢀ9thꢀbit.ꢀTheꢀslaveꢀdeviceꢀwillꢀalsoꢀsetꢀ
theꢀstatusꢀflagꢀHAASꢀwhenꢀtheꢀaddressesꢀmatch.ꢀ
AsꢀanꢀI2Cꢀbusꢀinterruptꢀcanꢀcomeꢀfromꢀthreeꢀsources,ꢀwhenꢀtheꢀprogramꢀentersꢀtheꢀinterruptꢀ
subroutine,ꢀtheꢀHAASꢀbitꢀandꢀSIMTOFꢀbitꢀshouldꢀbeꢀexaminedꢀtoꢀseeꢀwhetherꢀtheꢀinterruptꢀsourceꢀ
hasꢀcomeꢀfromꢀaꢀmatchingꢀslaveꢀaddressꢀorꢀfromꢀtheꢀcompletionꢀofꢀaꢀdataꢀbyteꢀtransferꢀorꢀfromꢀtheꢀ
I2Cꢀcommunicationꢀtime-out.ꢀWhenꢀaꢀslaveꢀaddressꢀisꢀmatched,ꢀtheꢀdeviceꢀmustꢀbeꢀplacedꢀinꢀeitherꢀ
theꢀtransmitꢀmodeꢀandꢀthenꢀwriteꢀdataꢀtoꢀtheꢀSIMDꢀregister,ꢀorꢀinꢀtheꢀreceiveꢀmodeꢀwhereꢀitꢀmustꢀ
implementꢀaꢀdummyꢀreadꢀfromꢀtheꢀSIMDꢀregisterꢀtoꢀreleaseꢀtheꢀSCLꢀline.ꢀ
I2C Bus Read/Write Signal
TheꢀSRWꢀbitꢀinꢀtheꢀSIMC1ꢀregisterꢀdefinesꢀwhetherꢀtheꢀslaveꢀdeviceꢀwishesꢀtoꢀreadꢀdataꢀfromꢀtheꢀ
I2CꢀbusꢀorꢀwriteꢀdataꢀtoꢀtheꢀI2Cꢀbus.ꢀTheꢀslaveꢀdeviceꢀshouldꢀexamineꢀthisꢀbitꢀtoꢀdetermineꢀifꢀitꢀisꢀtoꢀ
beꢀaꢀtransmitterꢀorꢀaꢀreceiver.ꢀIfꢀtheꢀSRWꢀflagꢀisꢀ“1”ꢀthenꢀthisꢀindicatesꢀthatꢀtheꢀmasterꢀdeviceꢀwishesꢀ
toꢀreadꢀdataꢀfromꢀtheꢀI2Cꢀbus,ꢀthereforeꢀtheꢀslaveꢀdeviceꢀmustꢀbeꢀsetupꢀtoꢀsendꢀdataꢀtoꢀtheꢀI2Cꢀbusꢀasꢀ
aꢀtransmitter.ꢀIfꢀtheꢀSRWꢀflagꢀisꢀ“0”ꢀthenꢀthisꢀindicatesꢀthatꢀtheꢀmasterꢀwishesꢀtoꢀsendꢀdataꢀtoꢀtheꢀI2Cꢀ
bus,ꢀthereforeꢀtheꢀslaveꢀdeviceꢀmustꢀbeꢀsetupꢀtoꢀreadꢀdataꢀfromꢀtheꢀI2Cꢀbusꢀasꢀaꢀreceiver.ꢀ
I2C Bus Slave Address Acknowledge Signal
Afterꢀtheꢀmasterꢀhasꢀtransmittedꢀaꢀcallingꢀaddress,ꢀanyꢀslaveꢀdeviceꢀonꢀtheꢀI2Cꢀbus,ꢀwhoseꢀ
ownꢀinternalꢀaddressꢀmatchesꢀtheꢀcallingꢀaddress,ꢀmustꢀgenerateꢀanꢀacknowledgeꢀsignal.ꢀTheꢀ
acknowledgeꢀsignalꢀwillꢀinformꢀtheꢀmasterꢀthatꢀaꢀslaveꢀdeviceꢀhasꢀacceptedꢀitsꢀcallingꢀaddress.ꢀIfꢀnoꢀ
acknowledgeꢀsignalꢀisꢀreceivedꢀbyꢀtheꢀmasterꢀthenꢀaꢀSTOPꢀsignalꢀmustꢀbeꢀtransmittedꢀbyꢀtheꢀmasterꢀ
toꢀendꢀtheꢀcommunication.ꢀWhenꢀtheꢀHAASꢀflagꢀisꢀhigh,ꢀtheꢀaddressesꢀhaveꢀmatchedꢀandꢀtheꢀslaveꢀ
deviceꢀmustꢀcheckꢀtheꢀSRWꢀflagꢀtoꢀdetermineꢀifꢀitꢀisꢀtoꢀbeꢀaꢀtransmitterꢀorꢀaꢀreceiver.ꢀIfꢀtheꢀSRWꢀflagꢀ
isꢀhigh,ꢀtheꢀslaveꢀdeviceꢀshouldꢀbeꢀsetupꢀtoꢀbeꢀaꢀtransmitterꢀsoꢀtheꢀHTXꢀbitꢀinꢀtheꢀSIMC1ꢀregisterꢀ
shouldꢀbeꢀsetꢀhigh.ꢀIfꢀtheꢀSRWꢀflagꢀisꢀlow,ꢀthenꢀtheꢀmicrocontrollerꢀslaveꢀdeviceꢀshouldꢀbeꢀsetupꢀasꢀaꢀ
receiverꢀandꢀtheꢀHTXꢀbitꢀinꢀtheꢀSIMC1ꢀregisterꢀshouldꢀbeꢀclearedꢀtoꢀ“0”.
Rev. 1.10
1ꢃ5
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
I2C Bus Data and Acknowledge Signal
Theꢀtransmittedꢀdataꢀisꢀ8-bitꢀwideꢀandꢀisꢀtransmittedꢀafterꢀtheꢀslaveꢀdeviceꢀhasꢀacknowledgedꢀreceiptꢀ
ofꢀitsꢀslaveꢀaddress.ꢀTheꢀorderꢀofꢀserialꢀbitꢀtransmissionꢀisꢀtheꢀMSBꢀfirstꢀandꢀtheꢀLSBꢀlast.ꢀAfterꢀ
receiptꢀofꢀ8-bitꢀofꢀdata,ꢀtheꢀreceiverꢀmustꢀtransmitꢀanꢀacknowledgeꢀsignal,ꢀlevelꢀ“0”,ꢀbeforeꢀitꢀcanꢀ
receiveꢀtheꢀnextꢀdataꢀbyte.ꢀIfꢀtheꢀslaveꢀtransmitterꢀdoesꢀnotꢀreceiveꢀanꢀacknowledgeꢀbitꢀsignalꢀfromꢀ
theꢀmasterꢀreceiver,ꢀthenꢀtheꢀslaveꢀtransmitterꢀwillꢀreleaseꢀtheꢀSDAꢀlineꢀtoꢀallowꢀtheꢀmasterꢀtoꢀsendꢀ
aꢀSTOPꢀsignalꢀtoꢀreleaseꢀtheꢀI2CꢀBus.ꢀTheꢀcorrespondingꢀdataꢀwillꢀbeꢀstoredꢀinꢀtheꢀSIMDꢀregister.ꢀ
Ifꢀsetupꢀasꢀaꢀtransmitter,ꢀtheꢀslaveꢀdeviceꢀmustꢀfirstꢀwriteꢀtheꢀdataꢀtoꢀbeꢀtransmittedꢀintoꢀtheꢀSIMDꢀ
register.ꢀIfꢀsetupꢀasꢀaꢀreceiver,ꢀtheꢀslaveꢀdeviceꢀmustꢀreadꢀtheꢀtransmittedꢀdataꢀfromꢀtheꢀSIMDꢀregister.
Whenꢀtheꢀslaveꢀreceiverꢀreceivesꢀtheꢀdataꢀbyte,ꢀitꢀmustꢀgenerateꢀanꢀacknowledgeꢀbit,ꢀknownꢀasꢀ
TXAK,ꢀonꢀtheꢀ9thꢀclock.ꢀTheꢀslaveꢀdevice,ꢀwhichꢀisꢀsetupꢀasꢀaꢀtransmitterꢀwillꢀcheckꢀtheꢀRXAKꢀbitꢀ
inꢀtheꢀSIMC1ꢀregisterꢀtoꢀdetermineꢀifꢀitꢀisꢀtoꢀsendꢀanotherꢀdataꢀbyte,ꢀifꢀnotꢀthenꢀitꢀwillꢀreleaseꢀtheꢀ
SDAꢀlineꢀandꢀawaitꢀtheꢀreceiptꢀofꢀaꢀSTOPꢀsignalꢀfromꢀtheꢀmaster.
Staꢁt
Slave Addꢁess
SRW
ACK
SCL
1
0
1
1
0
1
0
1
0
SDA
Data
ACK
Stop
SCL
SDA
1
0
0
1
0
1
0
0
S=Staꢁt (1 bit)
SA=Slave Addꢁess (7 bits)
SR=SRW bit (1 bit)
M=Slave device send acknowledge bit (1 bit)
D=Data (ꢆ bits)
A=ACK (RXAK bit for transmitter, TXAK bit for receiver, 1 bit)
P=Stop (1 bit)
S
SA SR
M
D
A
D
A
……
S
SA SR
M
D
A
D
A
……
P
I2C Communication Timing Diagram
Note:ꢀWhenꢀaꢀslaveꢀaddressꢀisꢀmatched,ꢀtheꢀdeviceꢀmustꢀbeꢀplacedꢀinꢀeitherꢀtheꢀtransmitꢀmodeꢀ
andꢀthenꢀwriteꢀdataꢀtoꢀtheꢀSIMDꢀregister,ꢀorꢀinꢀtheꢀreceiveꢀmodeꢀwhereꢀitꢀmustꢀimplementꢀaꢀ
dummyꢀreadꢀfromꢀtheꢀSIMDꢀregisterꢀtoꢀreleaseꢀtheꢀSCLꢀline.
Rev. 1.10
1ꢃ6
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Staꢁt
No
Yes
SIMTOF=1?
No
Yes
SET SIMTOEN
CLR SIMTOF
HAAS=1?
No
Yes
Yes
No
HTX=1?
SRW=1?
RETI
Read fꢁom SIMD to
ꢁelease SCL Line
CLR HTX
CLR TXAK
SET HTX
RETI
Wꢁite data to SIMD to
ꢁelease SCL Line
Dꢀmmꢂ ꢁead fꢁom SIMD
to ꢁelease SCL Line
Yes
RXAK=1?
RETI
RETI
No
CLR HTX
CLR TXAK
Wꢁite data to SIMD to
ꢁelease SCL Line
Dꢀmmꢂ ꢁead fꢁom SIMD
to ꢁelease SCL Line
RETI
RETI
I2C Bus ISR Flowchart
I2C Time-out Function
InꢀorderꢀtoꢀreduceꢀtheꢀI2Cꢀlockupꢀproblemꢀdueꢀtoꢀreceptionꢀofꢀerroneousꢀclockꢀsources,ꢀaꢀtime-outꢀ
functionꢀisꢀprovided.ꢀIfꢀtheꢀclockꢀsourceꢀconnectedꢀtoꢀtheꢀI2Cꢀbusꢀisꢀnotꢀreceivedꢀforꢀaꢀwhile,ꢀthenꢀ
theꢀI2CꢀcircuitryꢀandꢀtheꢀSIMC1ꢀregisterꢀwillꢀbeꢀreset,ꢀtheꢀSIMTOFꢀbitꢀinꢀtheꢀSIMTOCꢀregisterꢀwillꢀ
beꢀsetꢀhighꢀafterꢀaꢀcertainꢀtime-outꢀperiod.ꢀTheꢀTimeꢀOutꢀfunctionꢀenable/disableꢀandꢀtheꢀtime-outꢀ
periodꢀareꢀmanagedꢀbyꢀtheꢀSIMTOCꢀregister.
I2C Time-out Operation
Theꢀtime-outꢀcounterꢀstartsꢀtoꢀcountꢀonꢀanꢀI2Cꢀbusꢀ“START”ꢀ&ꢀ“addressꢀmatch”ꢀcondition,ꢀandꢀ
isꢀclearedꢀbyꢀanꢀSCLꢀfallingꢀedge.ꢀBeforeꢀtheꢀnextꢀSCLꢀfallingꢀedgeꢀarrives,ꢀifꢀtheꢀtimeꢀelapsedꢀisꢀ
greaterꢀthanꢀtheꢀtime-outꢀperiodꢀspecifiedꢀbyꢀtheꢀSIMTOCꢀregister,ꢀthenꢀaꢀtime-outꢀconditionꢀwillꢀ
occur.ꢀTheꢀtime-outꢀfunctionꢀwillꢀstopꢀwhenꢀanꢀI2Cꢀ“STOP”ꢀconditionꢀoccurs.ꢀThereꢀareꢀ64ꢀtime-outꢀ
periodꢀselectionsꢀwhichꢀcanꢀbeꢀselectedꢀusingꢀtheꢀSIMTOS0~SIMTOS5ꢀbitsꢀinꢀtheꢀSIMTOCꢀregister.
Rev. 1.10
1ꢃ7
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Staꢁt
Slave Addꢁess
SRW
1
ACK
0
SCL
SDA
1
0
1
1
0
1
0
IꢅC time-oꢀt
coꢀnteꢁ staꢁt
Stop
SCL
SDA
1
0
0
1
0
1
0
0
IꢅC time-oꢀt coꢀnteꢁ ꢁeset on
SCL negative tꢁansition
I2C Time-out Diagram
WhenꢀanꢀI2Cꢀtime-outꢀcounterꢀoverflowꢀoccurs,ꢀtheꢀcounterꢀwillꢀstopꢀandꢀtheꢀSIMTOENꢀbitꢀwillꢀ
beꢀclearedꢀtoꢀ“0”ꢀandꢀtheꢀSIMTOFꢀbitꢀwillꢀbeꢀsetꢀhighꢀtoꢀindicateꢀthatꢀaꢀtime-outꢀconditionꢀhasꢀ
occurred.ꢀWhenꢀanꢀI2Cꢀtime-outꢀoccurs,ꢀtheꢀI2Cꢀinternalꢀcircuitryꢀwillꢀbeꢀresetꢀandꢀtheꢀregistersꢀwillꢀ
beꢀresetꢀintoꢀtheꢀfollowingꢀcondition:
Registers
SIMDꢄ SIMAꢄ SIMC0
SIMC1
After I2C Time-out
No change
Reset to POR condition
I2C Registers after Time-out
Serial Peripheral Interface – SPIA
EachꢀdeviceꢀcontainsꢀanꢀindependentꢀSPIꢀfunction.ꢀItꢀisꢀimportantꢀnotꢀtoꢀconfuseꢀthisꢀindependentꢀ
SPIꢀfunctionꢀwithꢀtheꢀadditionalꢀoneꢀcontainedꢀwithinꢀtheꢀcombinedꢀSIMꢀfunction,ꢀwhichꢀisꢀ
describedꢀinꢀanotherꢀsectionꢀofꢀthisꢀdatasheet.ꢀThisꢀindependentꢀSPIꢀfunctionꢀwillꢀcarryꢀtheꢀnameꢀ
SPIAꢀtoꢀdistinguishꢀitꢀfromꢀtheꢀotherꢀoneꢀinꢀtheꢀSIM.
TheꢀSPIAꢀinterfaceꢀisꢀoftenꢀusedꢀtoꢀcommunicateꢀwithꢀexternalꢀperipheralꢀdevicesꢀsuchꢀasꢀsensors,ꢀ
FlashꢀorꢀEEPROMꢀmemoryꢀdevicesꢀetc.ꢀOriginallyꢀdevelopedꢀbyꢀMotorola,ꢀtheꢀfourꢀlineꢀSPIAꢀ
interfaceꢀisꢀaꢀsynchronousꢀserialꢀdataꢀinterfaceꢀthatꢀhasꢀaꢀrelativelyꢀsimpleꢀcommunicationꢀprotocolꢀ
simplifyingꢀtheꢀprogrammingꢀrequirementsꢀwhenꢀcommunicatingꢀwithꢀexternalꢀhardwareꢀdevices.
Theꢀcommunicationꢀisꢀfullꢀduplexꢀandꢀoperatesꢀasꢀaꢀslave/masterꢀtype,ꢀwhereꢀtheꢀdevicesꢀcanꢀbeꢀ
eitherꢀmasterꢀorꢀslave.ꢀAlthoughꢀtheꢀSPIAꢀinterfaceꢀspecificationꢀcanꢀcontrolꢀmultipleꢀslaveꢀdevicesꢀ
fromꢀaꢀsingleꢀmaster,ꢀhoweverꢀtheꢀdeviceꢀisꢀprovidedꢀwithꢀonlyꢀoneꢀSCSA pin.ꢀIfꢀtheꢀmasterꢀneedsꢀtoꢀ
ꢀ
controlꢀmultipleꢀslaveꢀdevicesꢀfromꢀaꢀsingleꢀmaster,ꢀtheꢀmasterꢀcanꢀuseꢀI/Oꢀpinsꢀtoꢀselectꢀtheꢀslaveꢀ
devices.
SPIA Interface Operation
TheꢀSPIAꢀinterfaceꢀisꢀaꢀfullꢀduplexꢀsynchronousꢀserialꢀdataꢀlink.ꢀItꢀisꢀaꢀfourꢀlineꢀinterfaceꢀwithꢀpinꢀ
namesꢀSDIA,ꢀSDOA,ꢀSCKAꢀandꢀSCSA.ꢀPinsꢀSDIAꢀandꢀSDOAꢀareꢀtheꢀSerialꢀDataꢀInputꢀandꢀSerialꢀ
DataꢀOutputꢀlines,ꢀtheꢀSCKAꢀpinꢀisꢀtheꢀSerialꢀClockꢀlineꢀandꢀSCSAꢀisꢀtheꢀSlaveꢀSelectꢀline.ꢀAsꢀtheꢀ
SPIAꢀinterfaceꢀpinsꢀareꢀpin-sharedꢀwithꢀnormalꢀI/Oꢀpins,ꢀtheꢀSPIAꢀinterfaceꢀmustꢀfirstꢀbeꢀenabledꢀbyꢀ
configuringꢀtheꢀcorrespondingꢀselectionꢀbitsꢀinꢀtheꢀpin-sharedꢀfunctionꢀselectionꢀregisters.ꢀTheꢀSPIAꢀ
canꢀbeꢀdisabledꢀorꢀenabledꢀusingꢀtheꢀSPIAENꢀbitꢀinꢀtheꢀSPIAC0ꢀregister.ꢀCommunicationꢀbetweenꢀ
devicesꢀconnectedꢀtoꢀtheꢀSPIAꢀinterfaceꢀisꢀcarriedꢀoutꢀinꢀaꢀslave/masterꢀmodeꢀwithꢀallꢀdataꢀtransferꢀ
Rev. 1.10
1ꢃꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
initiationsꢀbeingꢀimplementedꢀbyꢀtheꢀmaster.ꢀTheꢀMasterꢀalsoꢀcontrolsꢀtheꢀclockꢀsignal.ꢀAsꢀeachꢀ
deviceꢀonlyꢀcontainsꢀaꢀsingleꢀSCSAꢀpinꢀonlyꢀoneꢀslaveꢀdeviceꢀcanꢀbeꢀutilized.
TheꢀSCSAꢀpinꢀisꢀcontrolledꢀbyꢀtheꢀapplicationꢀprogram,ꢀsetꢀtheꢀSACSENꢀbitꢀtoꢀ“1”ꢀtoꢀenableꢀtheꢀ
SCSAꢀpinꢀfunctionꢀandꢀclearꢀtheꢀSACSENꢀbitꢀtoꢀ“0”ꢀtoꢀplaceꢀtheꢀSCSA pinꢀintoꢀaꢀfloatingꢀstate.
ꢀ
SPIA Masteꢁ
SCKA
SPIA Slave
SCKA
SDOA
SDIA
SDIA
SDOA
SCSA
SCSA
SPIA Master/Slave Connection
TheꢀSPIAꢀfunctionꢀinꢀtheseꢀdevicesꢀofferꢀtheꢀfollowingꢀfeatures:
•ꢀ Fullꢀduplexꢀsynchronousꢀdataꢀtransfer
•ꢀ BothꢀMasterꢀandꢀSlaveꢀmodes
•ꢀ LSBꢀfirstꢀorꢀMSBꢀfirstꢀdataꢀtransmissionꢀmodes
•ꢀ Transmissionꢀcompleteꢀflag
•ꢀ Risingꢀorꢀfallingꢀactiveꢀclockꢀedge
TheꢀstatusꢀofꢀtheꢀSPIAꢀinterfaceꢀpinsꢀisꢀdeterminedꢀbyꢀaꢀnumberꢀofꢀfactorsꢀsuchꢀasꢀwhetherꢀtheꢀ
deviceꢀisꢀinꢀtheꢀmasterꢀorꢀslaveꢀmodeꢀandꢀuponꢀtheꢀconditionꢀofꢀcertainꢀcontrolꢀbitsꢀsuchꢀasꢀSACSENꢀ
andꢀSPIAEN.
Data Bꢀs
SPIAD
SDIA
TX/RX Shift Register
SDOA
Clock
Edge/Polaꢁitꢂ
Contꢁol
SACKEG
SACKPOLB
SAWCOL
SATRF
SPIAICF
Bꢀsꢂ
Statꢀs
SCKA
fSYS
fSUB
Clock Soꢀꢁce
Select
PTM1 CCRP match fꢁeqꢀencꢂ/ꢅ
SCSA
SACSEN
SPIA Block Diagram
Rev. 1.10
1ꢃ9
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
SPIA Registers
ThereꢀareꢀthreeꢀinternalꢀregistersꢀwhichꢀcontrolꢀtheꢀoverallꢀoperationꢀofꢀtheꢀSPIAꢀinterface.ꢀTheseꢀareꢀ
theꢀSPIADꢀdataꢀregisterꢀandꢀtwoꢀregisters,ꢀSPIAC0ꢀandꢀSPIAC1.
Bit
Register
Name
7
6
5
4
3
2
1
0
SPIAC0 SASPIꢅ SASPI1
SASPI0
—
—
—
SPIAEN SPIAICF
SPIAC1
SPIAD
—
—
SACKPOLB SACKEG SAMLS SACSEN SAWCOL SATRF
D7
D6
D5
Dꢃ
D3
Dꢅ
D1
D0
SPIA Registers List
SPIA Data Register
TheꢀSPIADꢀregisterꢀisꢀusedꢀtoꢀstoreꢀtheꢀdataꢀbeingꢀtransmittedꢀandꢀreceived.ꢀBeforeꢀtheꢀdeviceꢀ
writesꢀdataꢀtoꢀtheꢀSPIAꢀbus,ꢀtheꢀactualꢀdataꢀtoꢀbeꢀtransmittedꢀmustꢀbeꢀplacedꢀinꢀtheꢀSPIADꢀregister.ꢀ
AfterꢀtheꢀdataꢀisꢀreceivedꢀfromꢀtheꢀSPIAꢀbus,ꢀtheꢀdeviceꢀcanꢀreadꢀitꢀfromꢀtheꢀSPIADꢀregister.ꢀAnyꢀ
transmissionꢀorꢀreceptionꢀofꢀdataꢀfromꢀtheꢀSPIAꢀbusꢀmustꢀbeꢀmadeꢀviaꢀtheꢀSPIADꢀregister.
• SPIAD Register
Bit
Name
R/W
7
D7
R/W
x
6
D6
R/W
x
5
D5
R/W
x
4
Dꢃ
R/W
x
3
D3
R/W
x
2
Dꢅ
R/W
x
1
D1
R/W
x
0
D0
R/W
POR
x
“x” ꢀnknown
Bitꢀ7~0
D7~D0:ꢀSPIAꢀDataꢀRegisterꢀbitꢀ7~bitꢀ0
SPIA Control Registers
ThereꢀareꢀalsoꢀtwoꢀcontrolꢀregistersꢀforꢀtheꢀSPIAꢀinterface,ꢀSPIAC0ꢀandꢀSPIAC1.ꢀTheꢀSPIAC0ꢀ
registerꢀisꢀusedꢀtoꢀcontrolꢀtheꢀenable/disableꢀfunctionꢀandꢀtoꢀsetꢀtheꢀdataꢀtransmissionꢀclockꢀ
frequency.ꢀTheꢀSPIAC1ꢀregisterꢀisꢀusedꢀforꢀotherꢀcontrolꢀfunctionsꢀsuchꢀasꢀLSB/MSBꢀselection,ꢀ
writeꢀcollisionꢀflagꢀetc.
• SPIAC0 Register
Bit
Name
R/W
7
SASPIꢅ
R/W
1
6
SASPI1
R/W
1
5
SASPI0
R/W
1
4
3
2
1
SPIAEN
R/W
0
0
SPIAICF
R/W
—
—
—
—
—
—
—
—
—
POR
0
Bitꢀ7~5ꢀ
:ꢀSPIAꢀOperatingꢀModeꢀControl
SASPI2~SASPI0
000:ꢀSPIAꢀmasterꢀmode;ꢀSPIAꢀclockꢀisꢀfSYS/4
001:ꢀSPIAꢀmasterꢀmode;ꢀSPIAꢀclockꢀisꢀfSYS/16
010:ꢀSPIAꢀmasterꢀmode;ꢀSPIAꢀclockꢀisꢀfSYS/64
011:ꢀSPIAꢀmasterꢀmode;ꢀSPIAꢀclockꢀisꢀfSUB
100:ꢀSPIAꢀmasterꢀmode;ꢀSPIAꢀclockꢀisꢀPTM1ꢀCCRPꢀmatchꢀfrequency/2
101:ꢀSPIAꢀslaveꢀmode
110:ꢀUnimplemented
111:ꢀUnimplemented
TheseꢀbitsꢀareꢀusedꢀtoꢀcontrolꢀtheꢀSPIAꢀMaster/SlaveꢀselectionꢀandꢀtheꢀSPIAꢀMasterꢀ
clockꢀfrequency.ꢀTheꢀSPIAꢀclockꢀisꢀaꢀfunctionꢀofꢀtheꢀsystemꢀclockꢀbutꢀcanꢀalsoꢀbeꢀ
chosenꢀtoꢀbeꢀsourcedꢀfromꢀPTM1ꢀandꢀfSUB.ꢀIfꢀtheꢀSPIAꢀSlaveꢀModeꢀisꢀselectedꢀthenꢀtheꢀ
clockꢀwillꢀbeꢀsuppliedꢀbyꢀanꢀexternalꢀMasterꢀdevice.
Bitꢀ4~2ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Rev. 1.10
150
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ1
:ꢀSPIAꢀEnableꢀControl
SPIAEN
0:ꢀDisable
1:ꢀEnable
Theꢀbitꢀisꢀtheꢀoverallꢀon/offꢀcontrolꢀforꢀtheꢀSPIAꢀinterface.ꢀWhenꢀtheꢀSPIAENꢀbitꢀ
isꢀclearedꢀtoꢀ“0”ꢀtoꢀdisableꢀtheꢀSPIAꢀinterface,ꢀtheꢀSDIA,ꢀSDOA,ꢀSCKAꢀandꢀSCSAꢀ
linesꢀwillꢀloseꢀtheirꢀSPIAꢀfunctionꢀandꢀtheꢀSPIAꢀoperatingꢀcurrentꢀwillꢀbeꢀreducedꢀtoꢀaꢀ
minimumꢀvalue.ꢀWhenꢀtheꢀbitꢀisꢀhighꢀtheꢀSPIAꢀinterfaceꢀisꢀenabled.
Bitꢀ0
SPIAICF: SPIAꢀIncompleteꢀFlag
0:ꢀSPIAꢀincompleteꢀconditionꢀisꢀnotꢀoccurred
1:ꢀSPIAꢀincompleteꢀconditionꢀisꢀoccured
ThisꢀbitꢀisꢀonlyꢀavailableꢀwhenꢀtheꢀSPIAꢀisꢀconfiguredꢀtoꢀoperateꢀinꢀanꢀSPIAꢀslaveꢀ
mode.ꢀIfꢀtheꢀSPIAꢀoperatesꢀinꢀtheꢀslaveꢀmodeꢀwithꢀtheꢀSPIAENꢀandꢀSACSENꢀbitsꢀ
bothꢀbeingꢀsetꢀtoꢀ“1”ꢀbutꢀtheꢀSCSAꢀlineꢀisꢀpulledꢀhighꢀbyꢀtheꢀexternalꢀmasterꢀdeviceꢀ
beforeꢀtheꢀSPIAꢀdataꢀtransferꢀisꢀcompletelyꢀfinished,ꢀtheꢀSPIAICFꢀbitꢀwillꢀbeꢀsetꢀtoꢀ1ꢀ
togetherꢀwithꢀtheꢀSATRFꢀbit.ꢀWhenꢀthisꢀconditionꢀoccurs,ꢀtheꢀcorrespondingꢀinterruptꢀ
willꢀoccurꢀifꢀtheꢀinterruptꢀfunctionꢀisꢀenabled.ꢀHowever,ꢀtheꢀSATRFꢀbitꢀwillꢀnotꢀbeꢀsetꢀ
toꢀ“1”ꢀifꢀtheꢀSPIAICFꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀbyꢀsoftwareꢀapplicationꢀprogram.
• SPIAC1 Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
—
—
—
—
—
—
SACKPOLB SACKEG SAMLS SACSEN SAWCOL SATRF
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5
Unimplemented,ꢀreadꢀasꢀ“0”
SACKPOLB:ꢀSPIAꢀClockꢀLineꢀBaseꢀConditionꢀSelection
0:ꢀTheꢀSCKAꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive
1:ꢀTheꢀSCKAꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive
TheꢀSACKPOLBꢀbitꢀdeterminesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline,ꢀifꢀtheꢀbitꢀisꢀhigh,ꢀ
thenꢀtheꢀSCKAꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀWhenꢀtheꢀSACKPOLBꢀbitꢀ
isꢀlow,ꢀthenꢀtheꢀSCKAꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive.
Bitꢀ4
SACKEG:ꢀSPIAꢀSCKAꢀClockꢀActiveꢀEdgeꢀTypeꢀSelection
SACKPOLB=0
0:ꢀSCKAꢀhasꢀhighꢀbaseꢀlevelꢀwithꢀdataꢀcaptureꢀonꢀSCKAꢀrisingꢀedge
1:ꢀSCKAꢀhasꢀhighꢀbaseꢀlevelꢀwithꢀdataꢀcaptureꢀonꢀSCKAꢀfallingꢀedge
SACKPOLB=1
0:ꢀSCKAꢀhasꢀlowꢀbaseꢀlevelꢀwithꢀdataꢀcaptureꢀonꢀSCKAꢀfallingꢀedge
1:ꢀSCKAꢀhasꢀlowꢀbaseꢀlevelꢀwithꢀdataꢀcaptureꢀonꢀSCKAꢀrisingꢀedge
TheꢀSACKEGꢀandꢀSACKPOLBꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀwayꢀthatꢀtheꢀclockꢀsignalꢀ
outputsꢀandꢀinputsꢀdataꢀonꢀtheꢀSPIAꢀbus.ꢀTheseꢀtwoꢀbitsꢀmustꢀbeꢀconfiguredꢀbeforeꢀaꢀ
dataꢀtransferꢀisꢀexecutedꢀotherwiseꢀanꢀerroneousꢀclockꢀedgeꢀmayꢀbeꢀgenerated.ꢀTheꢀ
SACKPOLBꢀbitꢀdeterminesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline,ꢀifꢀtheꢀbitꢀisꢀhigh,ꢀ
thenꢀtheꢀSCKAꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀWhenꢀtheꢀSACKPOLBꢀ
bitꢀisꢀlow,ꢀthenꢀtheꢀSCKAꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀTheꢀSACKEGꢀ
bitꢀdeterminesꢀactiveꢀclockꢀedgeꢀtypeꢀwhichꢀdependsꢀuponꢀtheꢀconditionꢀofꢀtheꢀ
SACKPOLBꢀbit.
Bitꢀ3
Bitꢀ2
SAMLS:ꢀSPIAꢀDataꢀShiftꢀOrder
0:ꢀLSBꢀfirst
1:ꢀMSBꢀfirst
Thisꢀisꢀtheꢀdataꢀshiftꢀselectꢀbitꢀandꢀisꢀusedꢀtoꢀselectꢀhowꢀtheꢀdataꢀisꢀtransferred,ꢀeitherꢀ
MSBꢀorꢀLSBꢀfirst.ꢀSettingꢀtheꢀbitꢀhighꢀwillꢀselectꢀMSBꢀfirstꢀandꢀlowꢀforꢀLSBꢀfirst.
SACSEN:ꢀSPIAꢀSCSAꢀPinꢀControl
0:ꢀ
Disable
1:ꢀEnable
Rev. 1.10
151
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
TheꢀSACSENꢀbitꢀisꢀusedꢀasꢀanꢀenable/disableꢀforꢀtheꢀSCSAꢀpin.ꢀIfꢀthisꢀbitꢀisꢀlow,ꢀthenꢀ
theꢀSCSAꢀpinꢀwillꢀbeꢀdisabledꢀandꢀplacedꢀintoꢀaꢀfloatingꢀstate.ꢀIfꢀtheꢀbitꢀisꢀhighꢀtheꢀ
SCSAꢀpinꢀwillꢀbeꢀenabledꢀandꢀusedꢀasꢀaꢀselectꢀpin.
Bitꢀ1
Bitꢀ0
SAWCOL:ꢀSPIAꢀWriteꢀCollisionꢀFlag
0:ꢀNoꢀcollision
1:ꢀCollision
TheꢀSAWCOLꢀflagꢀisꢀusedꢀtoꢀdetectꢀifꢀaꢀdataꢀcollisionꢀhasꢀoccurred.ꢀIfꢀthisꢀbitꢀisꢀhighꢀ
itꢀmeansꢀthatꢀdataꢀhasꢀbeenꢀattemptedꢀtoꢀbeꢀwrittenꢀtoꢀtheꢀSPIADꢀregisterꢀduringꢀaꢀdataꢀ
transferꢀoperation.ꢀThisꢀwritingꢀoperationꢀwillꢀbeꢀignoredꢀifꢀdataꢀisꢀbeingꢀtransferred.ꢀ
Theꢀbitꢀcanꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.ꢀ
SATRF:ꢀSPIAꢀTransmit/ReceiveꢀCompleteꢀFlag
0:ꢀSPIAꢀdataꢀisꢀbeingꢀtransferred
1:ꢀSPIAꢀdataꢀtransmissionꢀisꢀcompleted
TheꢀSATRFꢀbitꢀisꢀtheꢀTransmit/ReceiveꢀCompleteꢀflagꢀandꢀisꢀsetꢀ“1”ꢀautomaticallyꢀ
whenꢀanꢀSPIAꢀdataꢀtransmissionꢀisꢀcompleted,ꢀbutꢀmustꢀsetꢀtoꢀ“0”ꢀbyꢀtheꢀapplicationꢀ
program.ꢀItꢀcanꢀbeꢀusedꢀtoꢀgenerateꢀanꢀinterrupt.
SPIA Communication
AfterꢀtheꢀSPIAꢀinterfaceꢀisꢀenabledꢀbyꢀsettingꢀtheꢀSPIAENꢀbitꢀhigh,ꢀthenꢀinꢀtheꢀMasterꢀMode,ꢀwhenꢀ
dataꢀisꢀwrittenꢀtoꢀtheꢀSPIADꢀregister,ꢀtransmission/receptionꢀwillꢀbeginꢀsimultaneously.ꢀWhenꢀtheꢀ
dataꢀtransferꢀisꢀcomplete,ꢀtheꢀSATRFꢀflagꢀwillꢀbeꢀsetꢀautomatically,ꢀbutꢀmustꢀbeꢀclearedꢀusingꢀtheꢀ
applicationꢀprogram.ꢀInꢀtheꢀSlaveꢀMode,ꢀwhenꢀtheꢀclockꢀsignalꢀfromꢀtheꢀmasterꢀhasꢀbeenꢀreceived,ꢀ
anyꢀdataꢀinꢀtheꢀSPIADꢀregisterꢀwillꢀbeꢀtransmittedꢀandꢀanyꢀdataꢀonꢀtheꢀSDIAꢀpinꢀwillꢀbeꢀshiftedꢀintoꢀ
theꢀSPIADꢀregister.
TheꢀmasterꢀshouldꢀoutputꢀanꢀSCSAꢀsignalꢀtoꢀenableꢀtheꢀslaveꢀdeviceꢀbeforeꢀaꢀclockꢀsignalꢀisꢀprovided.ꢀ
Theꢀslaveꢀdataꢀtoꢀbeꢀtransferredꢀshouldꢀbeꢀwellꢀpreparedꢀatꢀtheꢀappropriateꢀmomentꢀrelativeꢀtoꢀtheꢀ
SCSAꢀsignalꢀdependingꢀuponꢀtheꢀconfigurationsꢀofꢀtheꢀSACKPOLBꢀbitꢀandꢀSACKEGꢀbit.ꢀTheꢀ
accompanyingꢀtimingꢀdiagramꢀshowsꢀtheꢀrelationshipꢀbetweenꢀtheꢀslaveꢀdataꢀandꢀSCSAꢀsignalꢀforꢀ
variousꢀconfigurationsꢀofꢀtheꢀSACKPOLBꢀandꢀSACKEGꢀbits.
TheꢀSPIAꢀwillꢀcontinueꢀtoꢀfunctionꢀevenꢀinꢀtheꢀIDLEꢀMode.
SPIAEN=1ꢄ SACSEN=0 (Exteꢁnal Pꢀll-high)
SPIAENꢄ SACSEN=1
SCSA
SCKA (SACKPOLB=1ꢄ SACKEG=0)
SCKA (SACKPOLB=0ꢄ SACKEG=0)
SCKA (SACKPOLB=1ꢄ SACKEG=1)
SCKA (SACKPOLB=0ꢄ SACKEG=1)
SDOA (SACKEG=0)
D7/D0 D6/D1 D5/Dꢅ Dꢃ/D3 D3/Dꢃ Dꢅ/D5 D1/D6 D0/D7
D7/D0 D6/D1 D5/Dꢅ Dꢃ/D3 D3/Dꢃ Dꢅ/D5 D1/D6 D0/D7
SDOA (SACKEG=1)
SDIA Data Captꢀꢁe
Wꢁite to SPIAD
SPIA Master Mode Timing
Rev. 1.10
15ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
SCSA
SCKA (SACKPOLB=1)
SCKA (SACKPOLB=0)
SDOA
Dꢅ/D5
D7/D0 D6/D1 D5/Dꢅ Dꢃ/D3 D3/Dꢃ
D1/D6 D0/D7
SDIA Data Captꢀꢁe
Wꢁite to SPIAD
(SDOA does not change ꢀntil fiꢁst SCKA edge)
SPIA Slave Mode Timing – SACKEG=0
SCSA
SCKA (SACKPOLB=1)
SCKA (SACKPOLB=0)
SDOA
D7/D0 D6/D1 D5/Dꢅ Dꢃ/D3 D3/Dꢃ Dꢅ/D5 D1/D6 D0/D7
SDIA Data Captꢀꢁe
Wꢁite to SPIAD
(SDOA changes as soon as wꢁiting occꢀꢁs; SDOA is floating if SCSA=1)
Note: Foꢁ SPIA slave modeꢄ if SPIAEN=1 and SACSEN=0ꢄ SPIA is alwaꢂs
enabled and ignoꢁes the SCSA level.
SPIA Slave Mode Timing – SACKEG=1
Rev. 1.10
153
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
SPIA Tꢁansfeꢁ
A
Wꢁite Data
Cleaꢁ SAWCOL
into SPIAD
Masteꢁ
Slave
Masteꢁ oꢁ Slave
?
Yes
SAWCOL=1?
SASPI[ꢅ:0]=000ꢄ 001ꢄ
010ꢄ 011 oꢁ 100
SASPIA[ꢅ:0]=101
No
Tꢁansmission
completed?
(SATRF=1?)
No
Configꢀꢁe SACKPOLBꢄ
SACKEGꢄ SACSEN and SAMLS
Yes
Read Data
fꢁom SPIAD
SPIAEN=1
A
Cleaꢁ SATRF
No
Tꢁansfeꢁ finished?
Yes
END
SPIA Transfer Control Flowchart
Rev. 1.10
15ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
SPIA Bus Enable/Disable
ToꢀenableꢀtheꢀSPIAꢀbus,ꢀsetꢀSACSEN=1ꢀandꢀSCSA=0,ꢀthenꢀwaitꢀforꢀdataꢀtoꢀbeꢀwrittenꢀintoꢀtheꢀ
SPIADꢀ(TXRXꢀbuffer)ꢀregister.ꢀForꢀtheꢀMasterꢀMode,ꢀafterꢀdataꢀhasꢀbeenꢀwrittenꢀtoꢀtheꢀSPIADꢀ
(TXRXꢀbuffer)ꢀregister,ꢀthenꢀtransmissionꢀorꢀreceptionꢀwillꢀstartꢀautomatically.ꢀWhenꢀallꢀtheꢀdataꢀhasꢀ
beenꢀtransferredꢀtheꢀSATRFꢀbitꢀshouldꢀbeꢀset.ꢀForꢀtheꢀSlaveꢀMode,ꢀwhenꢀclockꢀpulsesꢀareꢀreceivedꢀ
onꢀSCKA,ꢀdataꢀinꢀtheꢀTXRXꢀbufferꢀwillꢀbeꢀshiftedꢀoutꢀorꢀdataꢀonꢀSDIAꢀwillꢀbeꢀshiftedꢀin.
ToꢀdisableꢀtheꢀSPIAꢀbusꢀSCKA,ꢀSDIA,ꢀSDOA,ꢀSCSAꢀwillꢀbecomeꢀI/Oꢀpinsꢀorꢀtheꢀotherꢀfunctions.
SPIA Operation
Allꢀcommunicationꢀisꢀcarriedꢀoutꢀusingꢀtheꢀ4-lineꢀinterfaceꢀforꢀeitherꢀMasterꢀorꢀSlaveꢀMode.
TheꢀSACSENꢀbitꢀinꢀtheꢀSPIAC1ꢀregisterꢀcontrolsꢀtheꢀoverallꢀfunctionꢀofꢀtheꢀSPIAꢀinterface.ꢀSettingꢀ
thisꢀbitꢀhighꢀwillꢀenableꢀtheꢀSPIAꢀinterfaceꢀbyꢀallowingꢀtheꢀSCSAꢀlineꢀtoꢀbeꢀactive,ꢀwhichꢀcanꢀthenꢀ
beꢀusedꢀtoꢀcontrolꢀtheꢀSPIAꢀinterface.ꢀIfꢀtheꢀSACSENꢀbitꢀisꢀlow,ꢀtheꢀSPIAꢀinterfaceꢀwillꢀbeꢀdisabledꢀ
andꢀtheꢀSCSAꢀlineꢀwillꢀbeꢀanꢀI/Oꢀpinꢀorꢀtheꢀotherꢀfunctionsꢀandꢀcanꢀthereforeꢀnotꢀbeꢀusedꢀforꢀcontrolꢀ
ofꢀtheꢀSPIAꢀinterface.ꢀIfꢀtheꢀSACSENꢀbitꢀandꢀtheꢀSPIAENꢀbitꢀinꢀtheꢀSPIAC0ꢀregisterꢀareꢀsetꢀhigh,ꢀ
thisꢀwillꢀplaceꢀtheꢀSDIAꢀlineꢀinꢀaꢀfloatingꢀconditionꢀandꢀtheꢀSDOAꢀlineꢀhigh.ꢀIfꢀinꢀMasterꢀModeꢀtheꢀ
SCKAꢀlineꢀwillꢀbeꢀeitherꢀhighꢀorꢀlowꢀdependingꢀuponꢀtheꢀclockꢀpolarityꢀselectionꢀbitꢀSACKPOLBꢀ
inꢀtheꢀSPIAC1ꢀregister.ꢀIfꢀinꢀSlaveꢀModeꢀtheꢀSCKAꢀlineꢀwillꢀbeꢀinꢀaꢀfloatingꢀcondition.ꢀIfꢀSPIAENꢀisꢀ
lowꢀthenꢀtheꢀbusꢀwillꢀbeꢀdisabledꢀandꢀSCSA,ꢀSDIA,ꢀSDOAꢀandꢀSCKAꢀwillꢀallꢀbecomeꢀI/Oꢀpinsꢀorꢀtheꢀ
otherꢀfunctions.ꢀInꢀtheꢀMasterꢀModeꢀtheꢀMasterꢀwillꢀalwaysꢀgenerateꢀtheꢀclockꢀsignal.ꢀTheꢀclockꢀandꢀ
dataꢀtransmissionꢀwillꢀbeꢀinitiatedꢀafterꢀdataꢀhasꢀbeenꢀwrittenꢀintoꢀtheꢀSPIADꢀregister.ꢀInꢀtheꢀSlaveꢀ
Mode,ꢀtheꢀclockꢀsignalꢀwillꢀbeꢀreceivedꢀfromꢀanꢀexternalꢀmasterꢀdeviceꢀforꢀbothꢀdataꢀtransmissionꢀ
andꢀreception.ꢀTheꢀfollowingꢀsequencesꢀshowꢀtheꢀorderꢀtoꢀbeꢀfollowedꢀforꢀdataꢀtransferꢀinꢀbothꢀ
MasterꢀandꢀSlaveꢀMode.
Master Mode
•ꢀ Stepꢀ1
SelectꢀtheꢀclockꢀsourceꢀandꢀMasterꢀmodeꢀusingꢀtheꢀSASPI2~SASPI0ꢀbitsꢀinꢀtheꢀSPIAC0ꢀcontrolꢀ
register.
•ꢀ Stepꢀ2
SetupꢀtheꢀSACSENꢀbitꢀandꢀsetupꢀtheꢀSAMLSꢀbitꢀtoꢀchooseꢀifꢀtheꢀdataꢀisꢀMSBꢀorꢀLSBꢀfirst,ꢀthisꢀ
mustꢀbeꢀsameꢀasꢀtheꢀSlaveꢀdevice.
•ꢀ Stepꢀ3
SetupꢀtheꢀSPIAENꢀbitꢀinꢀtheꢀSPIAC0ꢀcontrolꢀregisterꢀtoꢀenableꢀtheꢀSPIAꢀinterface.
•ꢀ Stepꢀ4
Forꢀwriteꢀoperations:ꢀwriteꢀtheꢀdataꢀtoꢀtheꢀSPIADꢀregister,ꢀwhichꢀwillꢀactuallyꢀplaceꢀtheꢀdataꢀintoꢀ
theꢀTXRXꢀbuffer.ꢀThenꢀuseꢀtheꢀSCKAꢀandꢀSCSAꢀlinesꢀtoꢀoutputꢀtheꢀdata.ꢀAfterꢀthisꢀgoꢀtoꢀstepꢀ5.
Forꢀreadꢀoperations:ꢀtheꢀdataꢀtransferredꢀinꢀonꢀtheꢀSDIAꢀlineꢀwillꢀbeꢀstoredꢀinꢀtheꢀTXRXꢀbufferꢀ
untilꢀallꢀtheꢀdataꢀhasꢀbeenꢀreceivedꢀatꢀwhichꢀpointꢀitꢀwillꢀbeꢀlatchedꢀintoꢀtheꢀSPIADꢀregister.
•ꢀ Stepꢀ5
CheckꢀtheꢀSAWCOLꢀbitꢀifꢀsetꢀhighꢀthenꢀaꢀcollisionꢀerrorꢀhasꢀoccurredꢀsoꢀreturnꢀtoꢀstepꢀ4.ꢀIfꢀequalꢀ
toꢀ“0”ꢀthenꢀgoꢀtoꢀtheꢀfollowingꢀstep.
•ꢀ Stepꢀ6
CheckꢀtheꢀSATRFꢀbitꢀorꢀwaitꢀforꢀaꢀSPIAꢀserialꢀbusꢀinterrupt.
Rev. 1.10
155
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
•ꢀ Stepꢀ7
ReadꢀdataꢀfromꢀtheꢀSPIADꢀregister.
•ꢀ Stepꢀ8
ClearꢀSATRF.
•ꢀ Stepꢀ9
Goꢀtoꢀstepꢀ4.
Slave Mode
•ꢀ Stepꢀ1
SelectꢀtheꢀSPIAꢀSlaveꢀmodeꢀusingꢀtheꢀSASPI2~SASPI0ꢀbitsꢀinꢀtheꢀSPIAC0ꢀcontrolꢀregister.
•ꢀ Stepꢀ2
SetupꢀtheꢀSACSENꢀbitꢀandꢀsetupꢀtheꢀSAMLSꢀbitꢀtoꢀchooseꢀifꢀtheꢀdataꢀisꢀMSBꢀorꢀLSBꢀfirst,ꢀthisꢀ
settingꢀmustꢀbeꢀtheꢀsameꢀwithꢀtheꢀMasterꢀdevice.
•ꢀ Stepꢀ3
SetupꢀtheꢀSPIAENꢀbitꢀinꢀtheꢀSPIAC0ꢀcontrolꢀregisterꢀtoꢀenableꢀtheꢀSPIAꢀinterface.
•ꢀ Stepꢀ4
Forꢀwriteꢀoperations:ꢀwriteꢀtheꢀdataꢀtoꢀtheꢀSPIADꢀregister,ꢀwhichꢀwillꢀactuallyꢀplaceꢀtheꢀdataꢀintoꢀ
theꢀTXRXꢀbuffer.ꢀThenꢀwaitꢀforꢀtheꢀmasterꢀclockꢀSCKAꢀandꢀSCSAꢀsignal.ꢀAfterꢀthis,ꢀgoꢀtoꢀstepꢀ5.
Forꢀreadꢀoperations:ꢀtheꢀdataꢀtransferredꢀinꢀonꢀtheꢀSDIAꢀlineꢀwillꢀbeꢀstoredꢀinꢀtheꢀTXRXꢀbufferꢀ
untilꢀallꢀtheꢀdataꢀhasꢀbeenꢀreceivedꢀatꢀwhichꢀpointꢀitꢀwillꢀbeꢀlatchedꢀintoꢀtheꢀSPIADꢀregister.
•ꢀ Stepꢀ5
CheckꢀtheꢀSAWCOLꢀbitꢀifꢀsetꢀhighꢀthenꢀaꢀcollisionꢀerrorꢀhasꢀoccurredꢀsoꢀreturnꢀtoꢀstepꢀ4.ꢀIfꢀequalꢀ
toꢀ“0”ꢀthenꢀgoꢀtoꢀtheꢀfollowingꢀstep.
•ꢀ Stepꢀ6
CheckꢀtheꢀSATRFꢀbitꢀorꢀwaitꢀforꢀaꢀSPIAꢀserialꢀbusꢀinterrupt.
•ꢀ Stepꢀ7
ReadꢀdataꢀfromꢀtheꢀSPIADꢀregister.
•ꢀ Stepꢀ8
ClearꢀSATRF.
•ꢀ Stepꢀ9
Goꢀtoꢀstepꢀ4.
Error Detection
TheꢀSAWCOLꢀbitꢀinꢀtheꢀSPIAC1ꢀregisterꢀisꢀprovidedꢀtoꢀindicateꢀerrorsꢀduringꢀdataꢀtransfer.ꢀTheꢀbitꢀ
isꢀsetꢀbyꢀtheꢀSPIAꢀserialꢀInterfaceꢀbutꢀmustꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.ꢀThisꢀbitꢀindicatesꢀ
aꢀdataꢀcollisionꢀhasꢀoccurredꢀwhichꢀhappensꢀifꢀaꢀwriteꢀtoꢀtheꢀSPIADꢀregisterꢀtakesꢀplaceꢀduringꢀaꢀ
dataꢀtransferꢀoperationꢀandꢀwillꢀpreventꢀtheꢀwriteꢀoperationꢀfromꢀcontinuing.
Rev. 1.10
156
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
UART Interface
Eachꢀdeviceꢀcontainsꢀanꢀintegratedꢀfull-duplexꢀasynchronousꢀserialꢀcommunicationsꢀUARTꢀinterfaceꢀ
thatꢀenablesꢀcommunicationꢀwithꢀexternalꢀdevicesꢀthatꢀcontainꢀaꢀserialꢀinterface.ꢀTheꢀUARTꢀfunctionꢀ
hasꢀmanyꢀfeaturesꢀandꢀcanꢀtransmitꢀandꢀreceiveꢀdataꢀseriallyꢀbyꢀtransferringꢀaꢀframeꢀofꢀdataꢀwithꢀ
eightꢀorꢀnineꢀdataꢀbitsꢀperꢀtransmissionꢀasꢀwellꢀasꢀbeingꢀableꢀtoꢀdetectꢀerrorsꢀwhenꢀtheꢀdataꢀisꢀ
overwrittenꢀorꢀincorrectlyꢀframed.ꢀTheꢀUARTꢀfunctionꢀpossessesꢀitsꢀownꢀinternalꢀinterruptꢀwhichꢀ
canꢀbeꢀusedꢀtoꢀindicateꢀwhenꢀaꢀreceptionꢀoccursꢀorꢀwhenꢀaꢀtransmissionꢀterminates.
TheꢀintegratedꢀUARTꢀfunctionꢀcontainsꢀtheꢀfollowingꢀfeatures:
•ꢀ Full-duplex,ꢀUniversalꢀAsynchronousꢀReceiverꢀandꢀTransmitterꢀ(UART)ꢀcommunication
•ꢀ 8ꢀorꢀ9ꢀbitsꢀcharacterꢀlength
•ꢀ Even,ꢀoddꢀorꢀnoꢀparityꢀoptions
•ꢀ Oneꢀorꢀtwoꢀstopꢀbits
•ꢀ Baudꢀrateꢀgeneratorꢀwithꢀ8-bitꢀprescaler
•ꢀ Parity,ꢀframing,ꢀnoiseꢀandꢀoverrunꢀerrorꢀdetection
•ꢀ Supportꢀforꢀinterruptꢀonꢀaddressꢀdetectꢀ(lastꢀcharacterꢀbit=1)
•ꢀ Transmitterꢀandꢀreceiverꢀenabledꢀindependently
•ꢀ 2-byteꢀdeepꢀFIFOꢀreceiveꢀdataꢀbuffer
•ꢀ Transmitꢀandꢀreceiveꢀmultipleꢀinterruptꢀgenerationꢀsources
ꢀ
♦
ꢀ
♦
ꢀ
♦
ꢀ
♦
ꢀ
♦
ꢀ
♦
Transmitterꢀempty
Transmitterꢀidle
Receiverꢀfull
Receiverꢀoverrun
Addressꢀmodeꢀdetect
RXꢀpinꢀwake-upꢀinterruptꢀ(RXꢀenable,ꢀRXꢀfallingꢀedge)
UART External Pin Interfacing
Toꢀcommunicateꢀwithꢀanꢀexternalꢀserialꢀinterface,ꢀtheꢀinternalꢀUARTꢀhasꢀtwoꢀexternalꢀpinsꢀknownꢀ
asꢀTXꢀandꢀRX.ꢀTheꢀTXꢀandꢀRXꢀpinsꢀareꢀtheꢀUARTꢀtransmitterꢀandꢀreceiverꢀpinsꢀrespectively.ꢀAlongꢀ
withꢀtheꢀUARTENꢀbit,ꢀtheꢀTXENꢀandꢀRXENꢀbits,ꢀifꢀset,ꢀwillꢀautomaticallyꢀsetupꢀtheseꢀI/Oꢀorꢀotherꢀ
pin-sharedꢀfunctionalꢀpinsꢀtoꢀtheirꢀrespectiveꢀTXꢀoutputꢀandꢀRXꢀinputꢀconditionsꢀandꢀdisableꢀanyꢀ
pull-highꢀresistorꢀoptionꢀwhichꢀmayꢀexistꢀonꢀtheꢀTXꢀorꢀRXꢀpins.ꢀWhenꢀtheꢀTXꢀorꢀRXꢀpinꢀfunctionꢀ
isꢀdisabledꢀbyꢀclearingꢀtheꢀUARTENꢀandꢀTXENꢀorꢀRXENꢀbit,ꢀtheꢀTXꢀorꢀRXꢀpinꢀcanꢀbeꢀusedꢀasꢀaꢀ
generalꢀpurposeꢀI/Oꢀorꢀotherꢀpin-sharedꢀfunctionalꢀpin.
UART Data Transfer Scheme
TheꢀblockꢀdiagramꢀshowsꢀtheꢀoverallꢀdataꢀtransferꢀstructureꢀarrangementꢀforꢀtheꢀUARTꢀinterface.ꢀ
TheꢀactualꢀdataꢀtoꢀbeꢀtransmittedꢀfromꢀtheꢀMCUꢀisꢀfirstꢀtransferredꢀtoꢀtheꢀTXRꢀregisterꢀbyꢀtheꢀ
applicationꢀprogram.ꢀTheꢀdataꢀwillꢀthenꢀbeꢀtransferredꢀtoꢀtheꢀTransmitꢀShiftꢀRegisterꢀfromꢀwhereꢀitꢀ
willꢀbeꢀshiftedꢀout,ꢀLSBꢀfirst,ꢀontoꢀtheꢀTXꢀpinꢀatꢀaꢀrateꢀcontrolledꢀbyꢀtheꢀBaudꢀRateꢀGenerator.ꢀOnlyꢀ
theꢀTXRꢀregisterꢀisꢀmappedꢀontoꢀtheꢀMCUꢀDataꢀMemory,ꢀtheꢀTransmitꢀShiftꢀRegisterꢀisꢀnotꢀmappedꢀ
andꢀisꢀthereforeꢀinaccessibleꢀtoꢀtheꢀapplicationꢀprogram.
DataꢀtoꢀbeꢀreceivedꢀbyꢀtheꢀUARTꢀisꢀacceptedꢀonꢀtheꢀexternalꢀRXꢀpin,ꢀfromꢀwhereꢀitꢀisꢀshiftedꢀin,ꢀ
LSBꢀfirst,ꢀtoꢀtheꢀReceiverꢀShiftꢀRegisterꢀatꢀaꢀrateꢀcontrolledꢀbyꢀtheꢀBaudꢀRateꢀGenerator.ꢀWhenꢀ
theꢀshiftꢀregisterꢀisꢀfull,ꢀtheꢀdataꢀwillꢀthenꢀbeꢀtransferredꢀfromꢀtheꢀshiftꢀregisterꢀtoꢀtheꢀinternalꢀRXRꢀ
register,ꢀwhereꢀitꢀisꢀbufferedꢀandꢀcanꢀbeꢀmanipulatedꢀbyꢀtheꢀapplicationꢀprogram.ꢀOnlyꢀtheꢀRXRꢀ
registerꢀisꢀmappedꢀontoꢀtheꢀMCUꢀDataꢀMemory,ꢀtheꢀReceiverꢀShiftꢀRegisterꢀisꢀnotꢀmappedꢀandꢀisꢀ
thereforeꢀinaccessibleꢀtoꢀtheꢀapplicationꢀprogram.
Rev. 1.10
157
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Itꢀshouldꢀbeꢀnotedꢀthatꢀtheꢀactualꢀregisterꢀforꢀdataꢀtransmissionꢀandꢀreception,ꢀalthoughꢀreferredꢀtoꢀ
inꢀtheꢀtext,ꢀandꢀinꢀapplicationꢀprograms,ꢀasꢀseparateꢀTXRꢀandꢀRXRꢀregisters,ꢀonlyꢀexistsꢀasꢀaꢀsingleꢀ
sharedꢀregisterꢀinꢀtheꢀDataꢀMemory.ꢀThisꢀsharedꢀregisterꢀknownꢀasꢀtheꢀTXR_RXRꢀregisterꢀisꢀusedꢀ
forꢀbothꢀdataꢀtransmissionꢀandꢀdataꢀreception.
Tꢁansmitteꢁ Shift Registeꢁ
Receiveꢁ Shift Registeꢁ
MSB ………………………… LSB
TX Pin
RX Pin
MSB ………………………… LSB
Baꢀd Rate
Geneꢁatoꢁ
RXR Register
fH
TXR Register
Bꢀffeꢁ
MCU Data Bꢀs
UART Data Transfer Scheme
UART Status and Control Registers
ThereꢀareꢀfiveꢀcontrolꢀregistersꢀassociatedꢀwithꢀtheꢀUARTꢀfunction.ꢀTheꢀUSR,ꢀUCR1ꢀandꢀUCR2ꢀ
registersꢀcontrolꢀtheꢀoverallꢀfunctionꢀofꢀtheꢀUART,ꢀwhileꢀtheꢀBRGꢀregisterꢀcontrolsꢀtheꢀBaudꢀrate.ꢀ
TheꢀactualꢀdataꢀtoꢀbeꢀtransmittedꢀandꢀreceivedꢀonꢀtheꢀserialꢀinterfaceꢀisꢀmanagedꢀthroughꢀtheꢀTXR_
RXRꢀdataꢀregister.
Bit
Register
Name
7
PERR
UARTEN
TXEN
D7
6
NF
5
4
3
2
RXIF
TXBRK
RIE
1
TIDLE
RX8
TIIE
D1
0
USR
FERR
PREN
BRGH
D5
OERR
PRT
RIDLE
STOPS
WAKE
D3
TXIF
TX8
TEIE
D0
UCR1
BNO
RXEN
D6
UCRꢅ
ADDEN
Dꢃ
TXR_RXR
BRG
Dꢅ
D7
D6
D5
Dꢃ
D3
Dꢅ
D1
D0
UART Register List
USR Register
TheꢀUSRꢀregisterꢀisꢀtheꢀstatusꢀregisterꢀforꢀtheꢀUART,ꢀwhichꢀcanꢀbeꢀreadꢀbyꢀtheꢀprogramꢀtoꢀdetermineꢀ
theꢀpresentꢀstatusꢀofꢀtheꢀUART.ꢀAllꢀflagsꢀwithinꢀtheꢀUSRꢀregisterꢀareꢀreadꢀonly.ꢀFurtherꢀexplanationꢀ
onꢀeachꢀofꢀtheꢀflagsꢀisꢀgivenꢀbelow.
Bit
Name
R/W
7
PERR
R
6
NF
R
5
FERR
R
4
OERR
R
3
RIDLE
R
2
RXIF
R
1
TIDLE
R
0
TXIF
R
POR
0
0
0
0
1
0
1
1
Bitꢀ7
PERR:ꢀParityꢀErrorꢀFlag
0:ꢀNoꢀparityꢀerrorꢀisꢀdetected
1:ꢀParityꢀerrorꢀisꢀdetected
TheꢀPERRꢀflagꢀisꢀtheꢀparityꢀerrorꢀflag.ꢀWhenꢀthisꢀreadꢀonlyꢀflagꢀisꢀ“0”,ꢀitꢀindicatesꢀaꢀ
parityꢀerrorꢀhasꢀnotꢀbeenꢀdetected.ꢀWhenꢀtheꢀflagꢀisꢀ“1”,ꢀitꢀindicatesꢀthatꢀtheꢀparityꢀofꢀ
theꢀreceivedꢀwordꢀisꢀincorrect.ꢀThisꢀerrorꢀflagꢀisꢀapplicableꢀonlyꢀifꢀParityꢀmodeꢀ(oddꢀorꢀ
even)ꢀisꢀselected.ꢀTheꢀflagꢀcanꢀalsoꢀbeꢀclearedꢀbyꢀaꢀsoftwareꢀsequenceꢀwhichꢀinvolvesꢀ
aꢀreadꢀtoꢀtheꢀstatusꢀregisterꢀUSRꢀfollowedꢀbyꢀanꢀaccessꢀtoꢀtheꢀRXRꢀdataꢀregister.
Rev. 1.10
15ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ6
NF:ꢀNoiseꢀFlag
0:ꢀNoꢀnoiseꢀisꢀdetected
1:ꢀNoiseꢀisꢀdetected
TheꢀNFꢀflagꢀisꢀtheꢀnoiseꢀflag.ꢀWhenꢀthisꢀreadꢀonlyꢀflagꢀisꢀ“0”,ꢀitꢀindicatesꢀnoꢀnoiseꢀ
condition.ꢀWhenꢀtheꢀflagꢀisꢀ“1”,ꢀitꢀindicatesꢀthatꢀtheꢀUARTꢀhasꢀdetectedꢀnoiseꢀonꢀtheꢀ
receiverꢀinput.ꢀTheꢀNFꢀflagꢀisꢀsetꢀduringꢀtheꢀsameꢀcycleꢀasꢀtheꢀRXIFꢀflagꢀbutꢀwillꢀnotꢀ
beꢀsetꢀinꢀtheꢀcaseꢀofꢀasꢀoverrun.ꢀTheꢀNFꢀflagꢀcanꢀbeꢀclearedꢀbyꢀaꢀsoftwareꢀsequenceꢀ
whichꢀwillꢀinvolveꢀaꢀreadꢀtoꢀtheꢀstatusꢀregisterꢀUSRꢀfollowedꢀbyꢀanꢀaccessꢀtoꢀtheꢀRXRꢀ
dataꢀregister.
Bitꢀ5
FERR:ꢀFramingꢀErrorꢀFlag
0:ꢀNoꢀframingꢀerrorꢀisꢀdetected
1:ꢀFramingꢀerrorꢀisꢀdetected
TheꢀFERRꢀflagꢀisꢀtheꢀframingꢀerrorꢀflag.ꢀWhenꢀthisꢀreadꢀonlyꢀflagꢀisꢀ“0”,ꢀitꢀindicatesꢀ
thatꢀthereꢀisꢀnoꢀframingꢀerror.ꢀWhenꢀtheꢀflagꢀisꢀ“1”,ꢀitꢀindicatesꢀthatꢀaꢀframingꢀerrorꢀ
hasꢀbeenꢀdetectedꢀforꢀtheꢀcurrentꢀcharacter.ꢀTheꢀflagꢀcanꢀalsoꢀbeꢀclearedꢀbyꢀaꢀsoftwareꢀ
sequenceꢀwhichꢀwillꢀinvolveꢀaꢀreadꢀtoꢀtheꢀstatusꢀregisterꢀUSRꢀfollowedꢀbyꢀanꢀaccessꢀtoꢀ
theꢀRXRꢀdataꢀregister.
Bitꢀ4
OERR:ꢀOverrunꢀErrorꢀFlag
0:ꢀNoꢀoverrunꢀerrorꢀisꢀdetected
1:ꢀOverrunꢀerrorꢀisꢀdetected
TheꢀOERRꢀflagꢀisꢀtheꢀoverrunꢀerrorꢀflagꢀwhichꢀindicatesꢀwhenꢀtheꢀreceiverꢀbufferꢀhasꢀ
overflowed.ꢀWhenꢀthisꢀreadꢀonlyꢀflagꢀisꢀ“0”,ꢀitꢀindicatesꢀthatꢀthereꢀisꢀnoꢀoverrunꢀerror.ꢀ
Whenꢀtheꢀflagꢀisꢀ“1”,ꢀitꢀindicatesꢀthatꢀanꢀoverrunꢀerrorꢀoccursꢀwhichꢀwillꢀinhibitꢀfurtherꢀ
transfersꢀtoꢀtheꢀRXRꢀreceiveꢀdataꢀregister.ꢀTheꢀflagꢀisꢀclearedꢀbyꢀaꢀsoftwareꢀsequence,ꢀ
whichꢀisꢀaꢀreadꢀtoꢀtheꢀstatusꢀregisterꢀUSRꢀfollowedꢀbyꢀanꢀaccessꢀtoꢀtheꢀRXRꢀdataꢀ
register.
Bitꢀ3
RIDLE:ꢀReceiverꢀStatus
0:ꢀDataꢀreceptionꢀisꢀinꢀprogressꢀ(dataꢀbeingꢀreceived)
1:ꢀNoꢀdataꢀreceptionꢀisꢀinꢀprogressꢀ(receiverꢀisꢀidle)
TheꢀRIDLEꢀflagꢀisꢀtheꢀreceiverꢀstatusꢀflag.ꢀWhenꢀthisꢀreadꢀonlyꢀflagꢀisꢀ“0”,ꢀitꢀindicatesꢀ
thatꢀtheꢀreceiverꢀisꢀbetweenꢀtheꢀinitialꢀdetectionꢀofꢀtheꢀstartꢀbitꢀandꢀtheꢀcompletionꢀofꢀ
theꢀstopꢀbit.ꢀWhenꢀtheꢀflagꢀisꢀ“1”,ꢀitꢀindicatesꢀthatꢀtheꢀreceiverꢀisꢀidle.ꢀBetweenꢀtheꢀ
completionꢀofꢀtheꢀstopꢀbitꢀandꢀtheꢀdetectionꢀofꢀtheꢀnextꢀstartꢀbit,ꢀtheꢀRIDLEꢀbitꢀisꢀ“1”ꢀ
indicatingꢀthatꢀtheꢀUARTꢀreceiverꢀisꢀidleꢀandꢀtheꢀRXꢀpinꢀstaysꢀinꢀlogicꢀhighꢀcondition.
Bitꢀ2
RXIF:ꢀReceiveꢀRXRꢀDataꢀRegisterꢀStatus
0:ꢀRXRꢀdataꢀregisterꢀisꢀempty
1:ꢀRXRꢀdataꢀregisterꢀhasꢀavailableꢀdata
TheꢀRXIFꢀflagꢀisꢀtheꢀreceiveꢀdataꢀregisterꢀstatusꢀflag.ꢀWhenꢀthisꢀreadꢀonlyꢀflagꢀisꢀ“0”,ꢀ
itꢀindicatesꢀthatꢀtheꢀRXRꢀreadꢀdataꢀregisterꢀisꢀempty.ꢀWhenꢀtheꢀflagꢀisꢀ“1”,ꢀitꢀindicatesꢀ
thatꢀtheꢀRXRꢀreadꢀdataꢀregisterꢀcontainsꢀnewꢀdata.ꢀWhenꢀtheꢀcontentsꢀofꢀtheꢀshiftꢀ
registerꢀareꢀtransferredꢀtoꢀtheꢀRXRꢀregister,ꢀanꢀinterruptꢀisꢀgeneratedꢀifꢀRIE=1ꢀinꢀtheꢀ
UCR2ꢀregister.ꢀIfꢀoneꢀorꢀmoreꢀerrorsꢀareꢀdetectedꢀinꢀtheꢀreceivedꢀword,ꢀtheꢀappropriateꢀ
receive-relatedꢀflagsꢀNF,ꢀFERR,ꢀand/orꢀPERRꢀareꢀsetꢀwithinꢀtheꢀsameꢀclockꢀcycle.ꢀTheꢀ
RXIFꢀflagꢀisꢀclearedꢀwhenꢀtheꢀUSRꢀregisterꢀisꢀreadꢀwithꢀRXIFꢀset,ꢀfollowedꢀbyꢀaꢀreadꢀ
fromꢀtheꢀRXRꢀregister,ꢀandꢀifꢀtheꢀRXRꢀregisterꢀhasꢀnoꢀdataꢀavailable.
Bitꢀ1
TIDLE:ꢀTransmissionꢀIdle
0:ꢀDataꢀtransmissionꢀisꢀinꢀprogressꢀ(dataꢀbeingꢀtransmitted)
1:ꢀNoꢀdataꢀtransmissionꢀisꢀinꢀprogressꢀ(transmitterꢀisꢀidle)
TheꢀTIDLEꢀflagꢀisꢀknownꢀasꢀtheꢀtransmissionꢀcompleteꢀflag.ꢀWhenꢀthisꢀreadꢀonlyꢀ
flagꢀisꢀ“0”,ꢀitꢀindicatesꢀthatꢀaꢀtransmissionꢀisꢀinꢀprogress.ꢀThisꢀflagꢀwillꢀbeꢀsetꢀtoꢀ“1”ꢀ
whenꢀtheꢀTXIFꢀflagꢀisꢀ“1”ꢀandꢀwhenꢀthereꢀisꢀnoꢀtransmitꢀdataꢀorꢀbreakꢀcharacterꢀbeingꢀ
transmitted.ꢀWhenꢀTIDLEꢀisꢀequalꢀtoꢀ“1”,ꢀtheꢀTXꢀpinꢀbecomesꢀidleꢀwithꢀtheꢀpinꢀstateꢀ
inꢀlogicꢀhighꢀcondition.ꢀTheꢀTIDLEꢀflagꢀisꢀclearedꢀbyꢀreadingꢀtheꢀUSRꢀregisterꢀwithꢀ
TIDLEꢀsetꢀandꢀthenꢀwritingꢀtoꢀtheꢀTXRꢀregister.ꢀTheꢀflagꢀisꢀnotꢀgeneratedꢀwhenꢀaꢀdataꢀ
characterꢀorꢀaꢀbreakꢀisꢀqueuedꢀandꢀreadyꢀtoꢀbeꢀsent.
Rev. 1.10
159
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ0
TXIF:ꢀTransmitꢀTXRꢀDataꢀRegisterꢀStatus
0:ꢀCharacterꢀisꢀnotꢀtransferredꢀtoꢀtheꢀtransmitꢀshiftꢀregister
1:ꢀCharacterꢀhasꢀtransferredꢀtoꢀtheꢀtransmitꢀshiftꢀregisterꢀ(TXRꢀdataꢀregisterꢀisꢀ
empty)
TheꢀTXIFꢀflagꢀisꢀtheꢀtransmitꢀdataꢀregisterꢀemptyꢀflag.ꢀWhenꢀthisꢀreadꢀonlyꢀflagꢀisꢀ“0”,ꢀ
itꢀindicatesꢀthatꢀtheꢀcharacterꢀisꢀnotꢀtransferredꢀtoꢀtheꢀtransmitterꢀshiftꢀregister.ꢀWhenꢀ
theꢀflagꢀisꢀ“1”,ꢀitꢀindicatesꢀthatꢀtheꢀtransmitterꢀshiftꢀregisterꢀhasꢀreceivedꢀaꢀcharacterꢀ
fromꢀtheꢀTXRꢀdataꢀregister.ꢀTheꢀTXIFꢀflagꢀisꢀclearedꢀbyꢀreadingꢀtheꢀUARTꢀstatusꢀ
registerꢀ(USR)ꢀwithꢀTXIFꢀsetꢀandꢀthenꢀwritingꢀtoꢀtheꢀTXRꢀdataꢀregister.ꢀNoteꢀthatꢀ
whenꢀtheꢀTXENꢀbitꢀisꢀset,ꢀtheꢀTXIFꢀflagꢀbitꢀwillꢀalsoꢀbeꢀsetꢀsinceꢀtheꢀtransmitꢀdataꢀ
registerꢀisꢀnotꢀyetꢀfull.ꢀ
UCR1 Register
TheꢀUCR1ꢀregisterꢀtogetherꢀwithꢀtheꢀUCR2ꢀregisterꢀareꢀtheꢀtwoꢀUARTꢀcontrolꢀregistersꢀthatꢀareꢀusedꢀ
toꢀsetꢀtheꢀvariousꢀoptionsꢀforꢀtheꢀUARTꢀfunction,ꢀsuchꢀasꢀoverallꢀon/offꢀcontrol,ꢀparityꢀcontrol,ꢀdataꢀ
transferꢀbitꢀlengthꢀetc.ꢀFurtherꢀexplanationꢀonꢀeachꢀofꢀtheꢀbitsꢀisꢀgivenꢀbelow.
Bit
Name
R/W
7
UARTEN
R/W
6
5
PREN
R/W
0
4
3
STOPS
R/W
0
2
TXBRK
R/W
0
1
RX8
R
0
BNO
R/W
0
PRT
R/W
0
TX8
W
0
POR
0
x
“x” ꢀnknown
Bitꢀ7
UARTEN:ꢀUARTꢀFunctionꢀEnableꢀControl
0:ꢀDisableꢀUART.ꢀTXꢀandꢀRXꢀpinsꢀareꢀinꢀaꢀfloatingꢀstate
1:ꢀEnableꢀUART.ꢀTXꢀandꢀRXꢀpinsꢀfunctionꢀasꢀUARTꢀpins
TheꢀUARTENꢀbitꢀisꢀtheꢀUARTꢀenableꢀbit.ꢀWhenꢀthisꢀbitꢀisꢀequalꢀtoꢀ“0”,ꢀtheꢀUARTꢀ
willꢀbeꢀdisabledꢀandꢀtheꢀRXꢀpinꢀasꢀwellꢀasꢀtheꢀTXꢀpinꢀwillꢀbeꢀsetꢀinꢀaꢀfloatingꢀstate.ꢀ
Whenꢀtheꢀbitꢀisꢀequalꢀtoꢀ“1”,ꢀtheꢀUARTꢀwillꢀbeꢀenabledꢀandꢀtheꢀTXꢀandꢀRXꢀpinsꢀwillꢀ
functionꢀasꢀdefinedꢀbyꢀtheꢀTXENꢀandꢀRXENꢀenableꢀcontrolꢀbits.ꢀ
WhenꢀtheꢀUARTꢀisꢀdisabled,ꢀitꢀwillꢀemptyꢀtheꢀbufferꢀsoꢀanyꢀcharacterꢀremainingꢀinꢀ
theꢀbufferꢀwillꢀbeꢀdiscarded.ꢀInꢀaddition,ꢀtheꢀvalueꢀofꢀtheꢀbaudꢀrateꢀcounterꢀwillꢀbeꢀ
reset.ꢀIfꢀtheꢀUARTꢀisꢀdisabled,ꢀallꢀerrorꢀandꢀstatusꢀflagsꢀwillꢀbeꢀreset.ꢀAlsoꢀtheꢀTXEN,ꢀ
RXEN,ꢀTXBRK,ꢀRXIF,ꢀOERR,ꢀFERR,ꢀPERRꢀandꢀNFꢀbitsꢀwillꢀbeꢀcleared,ꢀwhileꢀtheꢀ
TIDLE,ꢀTXIFꢀandꢀRIDLEꢀbitsꢀwillꢀbeꢀset.ꢀOtherꢀcontrolꢀbitsꢀinꢀUCR1,ꢀUCR2ꢀandꢀ
BRGꢀregistersꢀwillꢀremainꢀunaffected.ꢀIfꢀtheꢀUARTꢀisꢀactiveꢀandꢀtheꢀUARTENꢀbitꢀisꢀ
cleared,ꢀallꢀpendingꢀtransmissionsꢀandꢀreceptionsꢀwillꢀbeꢀterminatedꢀandꢀtheꢀmoduleꢀ
willꢀbeꢀresetꢀasꢀdefinedꢀabove.ꢀWhenꢀtheꢀUARTꢀisꢀre-enabled,ꢀitꢀwillꢀrestartꢀinꢀtheꢀ
sameꢀconfiguration.
Bitꢀ6
BNO:ꢀNumberꢀofꢀDataꢀTransferꢀBitsꢀSelection
0:ꢀ8-bitꢀdataꢀtransfer
1:ꢀ9-bitꢀdataꢀtransfer
Thisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀdataꢀlengthꢀformat,ꢀwhichꢀcanꢀhaveꢀaꢀchoiceꢀofꢀeitherꢀ
8-bitꢀorꢀ9-bitꢀformat.ꢀWhenꢀthisꢀbitꢀisꢀequalꢀtoꢀ“1”,ꢀaꢀ9-bitꢀdataꢀlengthꢀformatꢀwillꢀbeꢀ
selected.ꢀIfꢀtheꢀbitꢀisꢀequalꢀtoꢀ“0”,ꢀthenꢀanꢀ8-bitꢀdataꢀlengthꢀformatꢀwillꢀbeꢀselected.ꢀIfꢀ
9-bitꢀdataꢀlengthꢀformatꢀisꢀselected,ꢀthenꢀbitsꢀRX8ꢀandꢀTX8ꢀwillꢀbeꢀusedꢀtoꢀstoreꢀtheꢀ9thꢀ
bitꢀofꢀtheꢀreceivedꢀandꢀtransmittedꢀdataꢀrespectively.
Note:ꢀIfꢀBNO=1ꢀ(9-bitꢀdataꢀtransfer),ꢀparityꢀfunctionꢀisꢀenabled,ꢀtheꢀ9thꢀbitꢀofꢀdataꢀisꢀ
theꢀparityꢀbitꢀwhichꢀwillꢀnotꢀbeꢀtransferredꢀtoꢀRX8.ꢀ
IfꢀBNO=0ꢀ(8-bitꢀdataꢀtransfer),ꢀparityꢀfunctionꢀisꢀenabled,ꢀtheꢀ8thꢀbitꢀofꢀdataꢀisꢀ
theꢀparityꢀbitꢀwhichꢀwillꢀnotꢀbeꢀtransferredꢀtoꢀRX7.
Bitꢀ5
PREN:ꢀParityꢀFunctionꢀEnableꢀControl
0:ꢀParityꢀfunctionꢀisꢀdisabled
1:ꢀParityꢀfunctionꢀisꢀenabled
Thisꢀisꢀtheꢀparityꢀenableꢀbit.ꢀWhenꢀthisꢀbitꢀisꢀequalꢀtoꢀ“1”,ꢀtheꢀparityꢀfunctionꢀwillꢀbeꢀ
enabled.ꢀIfꢀtheꢀbitꢀisꢀequalꢀtoꢀ“0”,ꢀthenꢀtheꢀparityꢀfunctionꢀwillꢀbeꢀdisabled.ꢀ
Rev. 1.10
160
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ4
Bitꢀ3
PRT:ꢀParityꢀTypeꢀSelectionꢀBit
0:ꢀEvenꢀparityꢀforꢀparityꢀgenerator
1:ꢀOddꢀparityꢀforꢀparityꢀgenerator
Thisꢀbitꢀisꢀtheꢀparityꢀtypeꢀselectionꢀbit.ꢀWhenꢀthisꢀbitꢀisꢀequalꢀtoꢀ“1”,ꢀoddꢀparityꢀtypeꢀ
willꢀbeꢀselected.ꢀIfꢀtheꢀbitꢀisꢀequalꢀtoꢀ“0”,ꢀthenꢀevenꢀparityꢀtypeꢀwillꢀbeꢀselected.
STOPS:ꢀNumberꢀofꢀStopꢀBitsꢀSelection
0:ꢀOneꢀstopꢀbitꢀformatꢀisꢀused
1:ꢀTwoꢀstopꢀbitsꢀformatꢀisꢀused
ThisꢀbitꢀdeterminesꢀifꢀoneꢀorꢀtwoꢀstopꢀbitsꢀareꢀtoꢀbeꢀusedꢀforꢀtheꢀTXꢀpin.ꢀWhenꢀthisꢀbitꢀ
isꢀequalꢀtoꢀ“1”,ꢀtwoꢀstopꢀbitsꢀareꢀused.ꢀIfꢀthisꢀbitꢀisꢀequalꢀtoꢀ“0”,ꢀthenꢀonlyꢀoneꢀstopꢀbitꢀ
isꢀused.
Bitꢀ2
TXBRK:ꢀTransmitꢀBreakꢀCharacter
0:ꢀNoꢀbreakꢀcharacterꢀisꢀtransmitted
1:ꢀBreakꢀcharactersꢀtransmit
TheꢀTXBRKꢀbitꢀisꢀtheꢀTransmitꢀBreakꢀCharacterꢀbit.ꢀWhenꢀthisꢀbitꢀisꢀ“0”,ꢀthereꢀareꢀ
noꢀbreakꢀcharactersꢀandꢀtheꢀTXꢀpinꢀoperatesꢀnormally.ꢀWhenꢀtheꢀbitꢀisꢀ“1”,ꢀthereꢀareꢀ
transmitꢀbreakꢀcharactersꢀandꢀtheꢀtransmitterꢀwillꢀsendꢀlogicꢀzeros.ꢀWhenꢀthisꢀbitꢀisꢀ
equalꢀtoꢀ“1”,ꢀafterꢀtheꢀbufferedꢀdataꢀhasꢀbeenꢀtransmitted,ꢀtheꢀtransmitterꢀoutputꢀisꢀheldꢀ
lowꢀforꢀaꢀminimumꢀofꢀaꢀ13-bitꢀlengthꢀandꢀuntilꢀtheꢀTXBRKꢀbitꢀisꢀreset.
Bitꢀ1
Bitꢀ0
RX8:ꢀReceiveꢀDataꢀBitꢀ8ꢀforꢀ9-bitꢀDataꢀTransferꢀFormatꢀ(readꢀonly)
Thisꢀbitꢀisꢀonlyꢀusedꢀifꢀ9-bitꢀdataꢀtransfersꢀareꢀused,ꢀinꢀwhichꢀcaseꢀthisꢀbitꢀlocationꢀwillꢀ
storeꢀtheꢀ9thꢀbitꢀofꢀtheꢀreceivedꢀdataꢀknownꢀasꢀRX8.ꢀTheꢀBNOꢀbitꢀisꢀusedꢀtoꢀdetermineꢀ
whetherꢀdataꢀtransfersꢀareꢀinꢀ8-bitꢀorꢀ9-bitꢀformat.
TX8:ꢀTransmitꢀDataꢀBitꢀ8ꢀforꢀ9-bitꢀDataꢀTransferꢀFormatꢀ(writeꢀonly)
Thisꢀbitꢀisꢀonlyꢀusedꢀifꢀ9-bitꢀdataꢀtransfersꢀareꢀused,ꢀinꢀwhichꢀcaseꢀthisꢀbitꢀlocationꢀ
willꢀstoreꢀtheꢀ9thꢀbitꢀofꢀtheꢀtransmittedꢀdataꢀknownꢀasꢀTX8.ꢀTheꢀBNOꢀbitꢀisꢀusedꢀtoꢀ
determineꢀwhetherꢀdataꢀtransfersꢀareꢀinꢀ8-bitꢀorꢀ9-bitꢀformat.
UCR2 register
TheꢀUCR2ꢀregisterꢀisꢀtheꢀsecondꢀofꢀtheꢀtwoꢀUARTꢀcontrolꢀregistersꢀandꢀservesꢀseveralꢀpurposes.ꢀOneꢀ
ofꢀitsꢀmainꢀfunctionsꢀisꢀtoꢀcontrolꢀtheꢀbasicꢀenable/disableꢀoperationꢀofꢀtheꢀUARTꢀTransmitterꢀandꢀ
ReceiverꢀasꢀwellꢀasꢀenablingꢀtheꢀvariousꢀUARTꢀinterruptꢀsources.ꢀTheꢀregisterꢀalsoꢀservesꢀtoꢀcontrolꢀ
theꢀbaudꢀrateꢀspeed,ꢀreceiverꢀwake-upꢀenableꢀandꢀtheꢀaddressꢀdetectꢀenable.ꢀFurtherꢀexplanationꢀonꢀ
eachꢀofꢀtheꢀbitsꢀisꢀgivenꢀbelow.
Bit
Name
R/W
7
TXEN
R/W
0
6
RXEN
R/W
0
5
BRGH
R/W
0
4
ADDEN
R/W
0
3
WAKE
R/W
0
2
RIE
R/W
0
1
0
TEIE
R/W
0
TIIE
R/W
0
POR
Bitꢀ7ꢀ
TXEN:ꢀUARTꢀTransmitterꢀEnableꢀControl
0:ꢀUARTꢀtransmitterꢀisꢀdisabled
1:ꢀUARTꢀtransmitterꢀisꢀenabled
TheꢀbitꢀnamedꢀTXENꢀisꢀtheꢀTransmitterꢀEnableꢀBit.ꢀWhenꢀthisꢀbitꢀisꢀequalꢀtoꢀ“0”,ꢀtheꢀ
transmitterꢀwillꢀbeꢀdisabledꢀwithꢀanyꢀpendingꢀdataꢀtransmissionsꢀbeingꢀaborted.ꢀInꢀ
additionꢀtheꢀbuffersꢀwillꢀbeꢀreset.ꢀInꢀthisꢀsituationꢀtheꢀTXꢀpinꢀwillꢀbeꢀsetꢀinꢀaꢀfloatingꢀ
state.
IfꢀtheꢀTXENꢀbitꢀisꢀequalꢀtoꢀ“1”ꢀandꢀtheꢀUARTENꢀbitꢀisꢀalsoꢀequalꢀtoꢀ“1”,ꢀtheꢀtransmitterꢀ
willꢀbeꢀenabledꢀandꢀtheꢀTXꢀpinꢀwillꢀbeꢀcontrolledꢀbyꢀtheꢀUART.ꢀClearingꢀtheꢀTXENꢀbitꢀ
duringꢀaꢀtransmissionꢀwillꢀcauseꢀtheꢀdataꢀtransmissionꢀtoꢀbeꢀabortedꢀandꢀwillꢀresetꢀtheꢀ
transmitter.ꢀIfꢀthisꢀsituationꢀoccurs,ꢀtheꢀTXꢀpinꢀwillꢀbeꢀsetꢀinꢀaꢀfloatingꢀstate.
Rev. 1.10
161
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ6
RXEN:ꢀUARTꢀReceiverꢀEnableꢀControl
0:ꢀUARTꢀreceiverꢀisꢀdisabled
1:ꢀUARTꢀreceiverꢀisꢀenabled
TheꢀbitꢀnamedꢀRXENꢀisꢀtheꢀReceiverꢀEnableꢀBit.ꢀWhenꢀthisꢀbitꢀisꢀequalꢀtoꢀ“0”,ꢀtheꢀ
receiverꢀwillꢀbeꢀdisabledꢀwithꢀanyꢀpendingꢀdataꢀreceptionsꢀbeingꢀaborted.ꢀInꢀadditionꢀ
theꢀreceiveꢀbuffersꢀwillꢀbeꢀreset.ꢀInꢀthisꢀsituationꢀtheꢀRXꢀpinꢀwillꢀbeꢀsetꢀinꢀaꢀfloatingꢀ
state.ꢀIfꢀtheꢀRXENꢀbitꢀisꢀequalꢀtoꢀ“1”ꢀandꢀtheꢀUARTENꢀbitꢀisꢀalsoꢀequalꢀtoꢀ“1”,ꢀtheꢀ
receiverꢀwillꢀbeꢀenabledꢀandꢀtheꢀRXꢀpinꢀwillꢀbeꢀcontrolledꢀbyꢀtheꢀUART.ꢀClearingꢀtheꢀ
RXENꢀbitꢀduringꢀaꢀreceptionꢀwillꢀcauseꢀtheꢀdataꢀreceptionꢀtoꢀbeꢀabortedꢀandꢀwillꢀresetꢀ
theꢀreceiver.ꢀIfꢀthisꢀsituationꢀoccurs,ꢀtheꢀRXꢀpinꢀwillꢀbeꢀsetꢀinꢀaꢀfloatingꢀstate.
Bitꢀ5
Bitꢀ4
BRGH:ꢀBaudꢀRateꢀSpeedꢀSelection
0:ꢀLowꢀspeedꢀbaudꢀrate
1:ꢀHighꢀspeedꢀbaudꢀrate
TheꢀbitꢀnamedꢀBRGHꢀselectsꢀtheꢀhighꢀorꢀlowꢀspeedꢀmodeꢀofꢀtheꢀBaudꢀRateꢀGenerator.ꢀ
Thisꢀbit,ꢀtogetherꢀwithꢀtheꢀvalueꢀplacedꢀinꢀtheꢀbaudꢀrateꢀregisterꢀBRG,ꢀcontrolsꢀtheꢀ
BaudꢀRateꢀofꢀtheꢀUART.ꢀIfꢀthisꢀbitꢀisꢀequalꢀtoꢀ“1”,ꢀtheꢀhighꢀspeedꢀmodeꢀisꢀselected.ꢀIfꢀ
theꢀbitꢀisꢀequalꢀtoꢀ“0”,ꢀtheꢀlowꢀspeedꢀmodeꢀisꢀselected.
ADDEN:ꢀAddressꢀDetectꢀFunctionꢀEnableꢀControl
0:ꢀAddressꢀdetectionꢀfunctionꢀisꢀdisabled
1:ꢀAddressꢀdetectionꢀfunctionꢀisꢀenabled
TheꢀbitꢀnamedꢀADDENꢀisꢀtheꢀaddressꢀdetectꢀfunctionꢀenableꢀcontrolꢀbit.ꢀWhenꢀthisꢀ
bitꢀisꢀequalꢀtoꢀ“1”,ꢀtheꢀaddressꢀdetectꢀfunctionꢀisꢀenabled.ꢀWhenꢀitꢀoccurs,ꢀifꢀtheꢀ8thꢀ
bit,ꢀwhichꢀcorrespondsꢀtoꢀRX7ꢀifꢀBNO=0ꢀorꢀtheꢀ9thꢀbit,ꢀwhichꢀcorrespondsꢀtoꢀRX8ꢀifꢀ
BNO=1,ꢀhasꢀaꢀvalueꢀofꢀ“1”,ꢀthenꢀtheꢀreceivedꢀwordꢀwillꢀbeꢀidentifiedꢀasꢀanꢀaddress,ꢀ
ratherꢀthanꢀdata.ꢀIfꢀtheꢀcorrespondingꢀinterruptꢀisꢀenabled,ꢀanꢀinterruptꢀrequestꢀwillꢀbeꢀ
generatedꢀeachꢀtimeꢀtheꢀreceivedꢀwordꢀhasꢀtheꢀaddressꢀbitꢀset,ꢀwhichꢀisꢀtheꢀ8thꢀorꢀ9thꢀ
bitꢀdependingꢀonꢀtheꢀvalueꢀofꢀBNO.ꢀIfꢀtheꢀaddressꢀbitꢀknownꢀasꢀtheꢀ8thꢀorꢀ9thꢀbitꢀofꢀtheꢀ
receivedꢀwordꢀisꢀ“0”ꢀwithꢀtheꢀaddressꢀdetectꢀfunctionꢀbeingꢀenabled,ꢀanꢀinterruptꢀwillꢀ
notꢀbeꢀgeneratedꢀandꢀtheꢀreceivedꢀdataꢀwillꢀbeꢀdiscarded.
Bitꢀ3
WAKE:ꢀRXꢀPinꢀFallingꢀEdgeꢀWake-upꢀUARTꢀFunctionꢀEnableꢀControl
0:ꢀRXꢀpinꢀwake-upꢀUARTꢀfunctionꢀisꢀdisabled
1:ꢀRXꢀpinꢀwake-upꢀUARTꢀfunctionꢀisꢀenabled
Thisꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀwake-upꢀUARTꢀfunctionꢀwhenꢀaꢀfallingꢀedgeꢀonꢀtheꢀRXꢀ
pinꢀoccurs.ꢀNoteꢀthatꢀthisꢀbitꢀisꢀonlyꢀavailableꢀwhenꢀtheꢀUARTꢀclockꢀ(fH)ꢀisꢀswitchedꢀ
off.ꢀThereꢀwillꢀbeꢀnoꢀRXꢀpinꢀwake-upꢀUARTꢀfunctionꢀifꢀtheꢀUARTꢀclockꢀ(fH)ꢀexists.ꢀ
IfꢀtheꢀWAKEꢀbitꢀisꢀsetꢀtoꢀ1ꢀasꢀtheꢀUARTꢀclockꢀ(fH)ꢀisꢀswitchedꢀoff,ꢀaꢀUARTꢀwake-
upꢀrequestꢀwillꢀbeꢀinitiatedꢀwhenꢀaꢀfallingꢀedgeꢀonꢀtheꢀRXꢀpinꢀoccurs.ꢀWhenꢀthisꢀ
requestꢀhappensꢀandꢀtheꢀcorrespondingꢀinterruptꢀisꢀenabled,ꢀanꢀRXꢀpinꢀwake-upꢀUARTꢀ
interruptꢀwillꢀbeꢀgeneratedꢀtoꢀinformꢀtheꢀMCUꢀtoꢀwakeꢀupꢀtheꢀUARTꢀfunctionꢀbyꢀ
switchingꢀonꢀtheꢀUARTꢀclockꢀ(fH)ꢀviaꢀtheꢀapplicationꢀprogram.ꢀOtherwise,ꢀtheꢀUARTꢀ
functionꢀcanꢀnotꢀresumeꢀevenꢀifꢀthereꢀisꢀaꢀfallingꢀedgeꢀonꢀtheꢀRXꢀpinꢀwhenꢀtheꢀWAKEꢀ
bitꢀisꢀclearedꢀtoꢀ“0”.
Bitꢀ2
RIE:ꢀReceiverꢀInterruptꢀEnableꢀControl
0:ꢀReceiverꢀrelatedꢀinterruptꢀisꢀdisabled
1:ꢀReceiverꢀrelatedꢀinterruptꢀisꢀenabled
Thisꢀbitꢀenablesꢀorꢀdisablesꢀtheꢀreceiverꢀinterrupt.ꢀIfꢀthisꢀbitꢀisꢀequalꢀtoꢀ“1”ꢀandꢀwhenꢀ
theꢀreceiverꢀoverrunꢀflagꢀOERRꢀorꢀreceiveꢀdataꢀavailableꢀflagꢀRXIFꢀisꢀset,ꢀtheꢀUARTꢀ
interruptꢀrequestꢀflagꢀwillꢀbeꢀset.ꢀIfꢀthisꢀbitꢀisꢀequalꢀtoꢀ“0”,ꢀtheꢀUARTꢀinterruptꢀrequestꢀ
flagꢀwillꢀnotꢀbeꢀinfluencedꢀbyꢀtheꢀconditionꢀofꢀtheꢀOERRꢀorꢀRXIFꢀflags.
Rev. 1.10
16ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ1
TIIE:ꢀTransmitterꢀIdleInterruptꢀEnableꢀControl
0:ꢀTransmitterꢀidleꢀinterruptꢀisꢀdisabled
1:ꢀTransmitterꢀidleꢀinterruptꢀisꢀenabled
Thisꢀbitꢀenablesꢀorꢀdisablesꢀtheꢀtransmitterꢀidleꢀinterrupt.ꢀIfꢀthisꢀbitꢀisꢀequalꢀtoꢀ“1”ꢀandꢀ
whenꢀtheꢀtransmitterꢀidleꢀflagꢀTIDLEꢀisꢀset,ꢀdueꢀtoꢀaꢀtransmitterꢀidleꢀcondition,ꢀtheꢀ
UARTꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀset.ꢀIfꢀthisꢀbitꢀisꢀequalꢀtoꢀ“0”,ꢀtheꢀUARTꢀinterruptꢀ
requestꢀflagꢀwillꢀnotꢀbeꢀinfluencedꢀbyꢀtheꢀconditionꢀofꢀtheꢀTIDLEꢀflag.
Bitꢀ0
TEIE:ꢀTransmitterꢀEmptyꢀInterruptꢀEnableꢀControl
0:ꢀTransmitterꢀemptyꢀinterruptꢀisꢀdisabled
1:ꢀTransmitterꢀemptyꢀinterruptꢀisꢀenabled
Thisꢀbitꢀenablesꢀorꢀdisablesꢀtheꢀtransmitterꢀemptyꢀinterrupt.ꢀIfꢀthisꢀbitꢀisꢀequalꢀtoꢀ“1”ꢀ
andꢀwhenꢀtheꢀtransmitterꢀemptyꢀflagꢀTXIFꢀisꢀset,ꢀdueꢀtoꢀaꢀtransmitterꢀemptyꢀcondition,ꢀ
theꢀUARTꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀset.ꢀIfꢀthisꢀbitꢀisꢀequalꢀtoꢀ“0”,ꢀtheꢀUARTꢀ
interruptꢀrequestꢀflagꢀwillꢀnotꢀbeꢀinfluencedꢀbyꢀtheꢀconditionꢀofꢀtheꢀTXIFꢀflag.
TXR_RXR Register
TheꢀTXR_RXRꢀregisterꢀisꢀtheꢀdataꢀregisterꢀwhichꢀisꢀusedꢀtoꢀstoreꢀtheꢀdataꢀtoꢀbeꢀtransmittedꢀonꢀtheꢀ
TXꢀpinꢀorꢀbeingꢀreceivedꢀfromꢀtheꢀRXꢀpin.
Bit
Name
R/W
7
D7
R/W
x
6
D6
R/W
x
5
D5
R/W
x
4
Dꢃ
R/W
x
3
D3
R/W
x
2
Dꢅ
R/W
x
1
D1
R/W
x
0
D0
R/W
POR
x
“x” ꢀnknown
Bitꢀ7~0
D7~D0: UARTꢀTransmit/ReceiveꢀDataꢀbitꢀ7~bitꢀ0
Baud Rate Generator
Toꢀsetupꢀtheꢀspeedꢀofꢀtheꢀserialꢀdataꢀcommunication,ꢀtheꢀUARTꢀfunctionꢀcontainsꢀitsꢀownꢀdedicatedꢀ
baudꢀrateꢀgenerator.ꢀTheꢀbaudꢀrateꢀisꢀcontrolledꢀbyꢀitsꢀownꢀinternalꢀfreeꢀrunningꢀ8-bitꢀtimer,ꢀtheꢀperiodꢀ
ofꢀwhichꢀisꢀdeterminedꢀbyꢀtwoꢀfactors.ꢀTheꢀfirstꢀofꢀtheseꢀisꢀtheꢀvalueꢀplacedꢀinꢀtheꢀbaudꢀrateꢀregisterꢀ
BRGꢀandꢀtheꢀsecondꢀisꢀtheꢀvalueꢀofꢀtheꢀBRGHꢀbitꢀwithꢀtheꢀcontrolꢀregisterꢀUCR2.ꢀTheꢀBRGHꢀbitꢀ
decidesꢀifꢀtheꢀbaudꢀrateꢀgeneratorꢀisꢀtoꢀbeꢀusedꢀinꢀaꢀhighꢀspeedꢀmodeꢀorꢀlowꢀspeedꢀmode,ꢀwhichꢀinꢀ
turnꢀdeterminesꢀtheꢀformulaꢀthatꢀisꢀusedꢀtoꢀcalculateꢀtheꢀbaudꢀrate.ꢀTheꢀvalueꢀinꢀtheꢀBRGꢀregister,ꢀN,ꢀ
whichꢀisꢀusedꢀinꢀtheꢀfollowingꢀbaudꢀrateꢀcalculationꢀformulaꢀdeterminesꢀtheꢀdivisionꢀfactor.ꢀNoteꢀthatꢀ
NꢀisꢀtheꢀdecimalꢀvalueꢀplacedꢀinꢀtheꢀBRGꢀregisterꢀandꢀhasꢀaꢀrangeꢀofꢀbetweenꢀ0ꢀandꢀ255.
UCR2 BRGH Bit
0
1
Baꢀd Rate (BR)
fH / [6ꢃ (N+1)]
fH / [16 (N+1)]
ByꢀprogrammingꢀtheꢀBRGHꢀbitꢀwhichꢀallowsꢀselectionꢀofꢀtheꢀrelatedꢀformulaꢀandꢀprogrammingꢀtheꢀ
requiredꢀvalueꢀinꢀtheꢀBRGꢀregister,ꢀtheꢀrequiredꢀbaudꢀrateꢀcanꢀbeꢀsetup.ꢀNoteꢀthatꢀbecauseꢀtheꢀactualꢀ
baudꢀrateꢀisꢀdeterminedꢀusingꢀaꢀdiscreteꢀvalue,ꢀN,ꢀplacedꢀinꢀtheꢀBRGꢀregister,ꢀthereꢀwillꢀbeꢀanꢀerrorꢀ
associatedꢀbetweenꢀtheꢀactualꢀandꢀrequestedꢀvalue.ꢀTheꢀfollowingꢀexampleꢀshowsꢀhowꢀtheꢀBRGꢀ
registerꢀvalueꢀNꢀandꢀtheꢀerrorꢀvalueꢀcanꢀbeꢀcalculated.
Rev. 1.10
163
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
• BRG Register
Bit
7
6
D6
R/W
x
5
D5
R/W
x
4
Dꢃ
R/W
x
3
D3
R/W
x
2
Dꢅ
R/W
x
1
D1
R/W
x
0
Name
R/W
D7
R/W
x
D0
R/W
POR
x
“x” ꢀnknown
Bitꢀ7~0
D7~D0:ꢀBaudꢀRateValues
ByꢀprogrammingꢀtheꢀBRGHꢀbitꢀinꢀUCR2ꢀRegisterꢀwhichꢀallowsꢀselectionꢀofꢀtheꢀ
relatedꢀformulaꢀdescribedꢀaboveꢀandꢀprogrammingꢀtheꢀrequiredꢀvalueꢀinꢀtheꢀBRGꢀ
register,ꢀtheꢀrequiredꢀbaudꢀrateꢀcanꢀbeꢀsetup.
Calculating the Baud Rate and error values
Forꢀaꢀclockꢀfrequencyꢀofꢀ4MHz,ꢀandꢀwithꢀBRGHꢀsetꢀtoꢀ“0”ꢀdetermineꢀtheꢀBRGꢀregisterꢀvalueꢀN,ꢀtheꢀ
actualꢀbaudꢀrateꢀandꢀtheꢀerrorꢀvalueꢀforꢀaꢀdesiredꢀbaudꢀrateꢀofꢀ4800.ꢀ
FromꢀtheꢀaboveꢀtableꢀtheꢀdesiredꢀbaudꢀrateꢀBRꢀ=ꢀfHꢀ/ꢀ[64ꢀ(N+1)]
Re-arrangingꢀthisꢀequationꢀgivesꢀNꢀ=ꢀ[fHꢀ/ꢀ(BRꢀ×ꢀ64)]ꢀ−ꢀ1
GivingꢀaꢀvalueꢀforꢀNꢀ=ꢀ[4000000ꢀ/ꢀ(4800×64)]ꢀ−ꢀ1ꢀ=ꢀ12.0208
Toꢀobtainꢀtheꢀclosestꢀvalue,ꢀaꢀdecimalꢀvalueꢀofꢀ12ꢀshouldꢀbeꢀplacedꢀintoꢀtheꢀBRGꢀregister.ꢀThisꢀgivesꢀ
anꢀactualꢀorꢀcalculatedꢀbaudꢀrateꢀvalueꢀofꢀBRꢀ=ꢀ4000000ꢀ/ꢀ[64ꢀ×ꢀ(12ꢀ+ꢀ1)]ꢀ=ꢀ4808
Thereforeꢀtheꢀerrorꢀisꢀequalꢀtoꢀ(4808ꢀ−ꢀ4800)ꢀ/ꢀ4800ꢀ=ꢀ0.16%
TheꢀfollowingꢀtableꢀshowsꢀactualꢀvaluesꢀofꢀbaudꢀrateꢀandꢀerrorꢀvaluesꢀforꢀtheꢀtwoꢀvaluesꢀofꢀBRGH.
fSYS=8MHz
Baud Rate
K/BPS
Baud Rates for BRGH=0
Baud Rates for BRGH=1
BRG
Kbaud
—
Error (%)
BRG
Kbaud
—
Error (%)
0.3
1.ꢅ
—
103
51
ꢅ5
1ꢅ
6
—
—
—
ꢅ07
103
51
ꢅ5
1ꢅ
ꢆ
—
—
1.ꢅ0ꢅ
ꢅ.ꢃ0ꢃ
ꢃ.ꢆ0ꢆ
9.615
17.ꢆꢆ57
ꢃ1.667
6ꢅ.500
1ꢅ5
0.16
0.16
0.16
0.16
-6.99
ꢆ.51
ꢆ.51
ꢆ.51
—
—
ꢅ.ꢃ
ꢅ.ꢃ0ꢃ
ꢃ.ꢆ0ꢆ
9.615
19.ꢅ31
3ꢆ.ꢃ6ꢅ
55.556
1ꢅ5
0.16
0.16
0.16
0.16
0.16
-3.55
ꢆ.51
0
ꢃ.ꢆ
9.6
19.ꢅ
3ꢆ.ꢃ
57.6
115.ꢅ
ꢅ50
ꢅ
1
0
3
—
—
1
ꢅ50
Baud Rates and Error Values
Rev. 1.10
16ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
UART Setup and Control
Forꢀdataꢀtransfer,ꢀtheꢀUARTꢀfunctionꢀutilizesꢀaꢀnon-return-to-zero,ꢀmoreꢀcommonlyꢀknownꢀasꢀNRZ,ꢀ
format.ꢀThisꢀisꢀcomposedꢀofꢀoneꢀstartꢀbit,ꢀeightꢀorꢀnineꢀdataꢀbits,ꢀandꢀoneꢀorꢀtwoꢀstopꢀbits.ꢀParityꢀ
isꢀsupportedꢀbyꢀtheꢀUARTꢀhardware,ꢀandꢀcanꢀbeꢀsetupꢀtoꢀbeꢀeven,ꢀoddꢀorꢀnoꢀparity.ꢀForꢀtheꢀmostꢀ
commonꢀdataꢀformat,ꢀ8ꢀdataꢀbitsꢀalongꢀwithꢀnoꢀparityꢀandꢀoneꢀstopꢀbit,ꢀdenotedꢀasꢀ8,ꢀN,ꢀ1,ꢀisꢀusedꢀ
asꢀtheꢀdefaultꢀsetting,ꢀwhichꢀisꢀtheꢀsettingꢀatꢀpower-on.ꢀTheꢀnumberꢀofꢀdataꢀbitsꢀandꢀstopꢀbits,ꢀalongꢀ
withꢀtheꢀparity,ꢀareꢀsetupꢀbyꢀprogrammingꢀtheꢀcorrespondingꢀBNO,ꢀPRT,ꢀPREN,ꢀandꢀSTOPSꢀbitsꢀ
inꢀtheꢀUCR1ꢀregister.ꢀTheꢀbaudꢀrateꢀusedꢀtoꢀtransmitꢀandꢀreceiveꢀdataꢀisꢀsetupꢀusingꢀtheꢀinternalꢀ
8-bitꢀbaudꢀrateꢀgenerator,ꢀwhileꢀtheꢀdataꢀisꢀtransmittedꢀandꢀreceivedꢀLSBꢀfirst.ꢀAlthoughꢀtheꢀUARTꢀ
transmitterꢀandꢀreceiverꢀareꢀfunctionallyꢀindependent,ꢀtheyꢀbothꢀuseꢀtheꢀsameꢀdataꢀformatꢀandꢀbaudꢀ
rate.ꢀInꢀallꢀcasesꢀstopꢀbitsꢀwillꢀbeꢀusedꢀforꢀdataꢀtransmission.
Enabling/Disabling the UART Interface
Theꢀbasicꢀon/offꢀfunctionꢀofꢀtheꢀinternalꢀUARTꢀfunctionꢀisꢀcontrolledꢀusingꢀtheꢀUARTENꢀbitꢀinꢀtheꢀ
UCR1ꢀregister.ꢀIfꢀtheꢀUARTEN,ꢀTXENꢀandꢀRXENꢀbitsꢀareꢀset,ꢀthenꢀtheseꢀtwoꢀUARTꢀpinsꢀwillꢀactꢀ
asꢀnormalꢀTXꢀoutputꢀpinꢀandꢀRXꢀinputꢀpinꢀrespectively.ꢀIfꢀnoꢀdataꢀisꢀbeingꢀtransmittedꢀonꢀtheꢀTXꢀ
pin,ꢀthenꢀitꢀwillꢀdefaultꢀtoꢀaꢀlogicꢀhighꢀvalue.
ClearingꢀtheꢀUARTENꢀbitꢀwillꢀdisableꢀtheꢀTXꢀandꢀRXꢀpinsꢀandꢀallowꢀtheseꢀtwoꢀpinsꢀtoꢀbeꢀusedꢀasꢀ
normalꢀI/Oꢀorꢀotherꢀpin-sharedꢀfunctionalꢀpins.ꢀWhenꢀtheꢀUARTꢀfunctionꢀisꢀdisabledꢀtheꢀbufferꢀwillꢀ
beꢀresetꢀtoꢀanꢀemptyꢀcondition,ꢀatꢀtheꢀsameꢀtimeꢀdiscardingꢀanyꢀremainingꢀresidualꢀdata.ꢀDisablingꢀ
theꢀUARTꢀwillꢀalsoꢀresetꢀtheꢀerrorꢀandꢀstatusꢀflagsꢀwithꢀbitsꢀTXEN,ꢀRXEN,ꢀTXBRK,ꢀRXIF,ꢀOERR,ꢀ
FERR,ꢀPERRꢀandꢀNFꢀbeingꢀclearedꢀwhileꢀbitsꢀTIDLE,ꢀTXIFꢀandꢀRIDLEꢀwillꢀbeꢀset.ꢀTheꢀremainingꢀ
controlꢀbitsꢀinꢀtheꢀUCR1,ꢀUCR2ꢀandꢀBRGꢀregistersꢀwillꢀremainꢀunaffected.ꢀIfꢀtheꢀUARTENꢀbitꢀinꢀ
theꢀUCR1ꢀregisterꢀisꢀclearedꢀwhileꢀtheꢀUARTꢀisꢀactive,ꢀthenꢀallꢀpendingꢀtransmissionsꢀandꢀreceptionsꢀ
willꢀbeꢀimmediatelyꢀsuspendedꢀandꢀtheꢀUARTꢀwillꢀbeꢀresetꢀtoꢀaꢀconditionꢀasꢀdefinedꢀabove.ꢀIfꢀtheꢀ
UARTꢀisꢀthenꢀsubsequentlyꢀre-enabled,ꢀitꢀwillꢀrestartꢀagainꢀinꢀtheꢀsameꢀconfiguration.
Data, Parity and Stop Bit Selection
Theꢀformatꢀofꢀtheꢀdataꢀtoꢀbeꢀtransferredꢀisꢀcomposedꢀofꢀvariousꢀfactorsꢀsuchꢀasꢀdataꢀbitꢀlength,ꢀ
parityꢀon/off,ꢀparityꢀtype,ꢀaddressꢀbitsꢀandꢀtheꢀnumberꢀofꢀstopꢀbits.ꢀTheseꢀfactorsꢀareꢀdeterminedꢀbyꢀ
theꢀsetupꢀofꢀvariousꢀbitsꢀwithinꢀtheꢀUCR1ꢀregister.ꢀTheꢀBNOꢀbitꢀcontrolsꢀtheꢀnumberꢀofꢀdataꢀbitsꢀ
whichꢀcanꢀbeꢀsetꢀtoꢀeitherꢀ8ꢀorꢀ9,ꢀtheꢀPRTꢀbitꢀcontrolsꢀtheꢀchoiceꢀofꢀoddꢀorꢀevenꢀparity,ꢀtheꢀPRENꢀ
bitꢀcontrolsꢀtheꢀparityꢀon/offꢀfunctionꢀandꢀtheꢀSTOPSꢀbitꢀdecidesꢀwhetherꢀoneꢀorꢀtwoꢀstopꢀbitsꢀareꢀtoꢀ
beꢀused.ꢀTheꢀfollowingꢀtableꢀshowsꢀvariousꢀformatsꢀforꢀdataꢀtransmission.ꢀTheꢀaddressꢀbit,ꢀwhichꢀisꢀ
theꢀMSBꢀofꢀtheꢀdataꢀbyte,ꢀidentifiesꢀtheꢀframeꢀasꢀanꢀaddressꢀcharacterꢀorꢀdataꢀifꢀtheꢀaddressꢀdetectꢀ
functionꢀisꢀenabled.ꢀTheꢀnumberꢀofꢀstopꢀbits,ꢀwhichꢀcanꢀbeꢀeitherꢀoneꢀorꢀtwo,ꢀisꢀindependentꢀofꢀtheꢀ
dataꢀlengthꢀandꢀareꢀonlyꢀtoꢀbeꢀusedꢀforꢀTransmitter.ꢀThereꢀisꢀonlyꢀoneꢀstopꢀbitꢀforꢀReceiver.
Start Bit
Data Bits
Address Bits
Parity Bits
Stop Bit
Example of 8-bit Data Formats
1
1
1
ꢆ
7
7
0
0
1
0
1
0
1
1
1
Example of 9-bit Data Formats
1
1
1
9
ꢆ
ꢆ
0
0
1
0
1
0
1
1
1
Transmitter Receiver Data Format
Rev. 1.10
165
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Theꢀfollowingꢀdiagramꢀshowsꢀtheꢀtransmitꢀandꢀreceiveꢀwaveformsꢀforꢀbothꢀ8-bitꢀandꢀ9-bitꢀdataꢀ
formats.
Paꢁitꢂ Bit
Next
Staꢁt
Bit
Staꢁt Bit
Staꢁt Bit
Bit 0
Bit 1
Bit ꢅ
Bit 3
Bit ꢃ
Bit 5
Bit 6
Bit 7
Stop Bit
8-bit data format
Paꢁitꢂ Bit
Bit ꢆ
Next
Staꢁt
Bit
Bit 0
Bit 1
Bit ꢅ
Bit 3
Bit ꢃ
Bit 5
Bit 6
Bit 7
Stop Bit
9-bit data format
UART Transmitter
Dataꢀwordꢀlengthsꢀofꢀeitherꢀ8ꢀorꢀ9ꢀbitsꢀcanꢀbeꢀselectedꢀbyꢀprogrammingꢀtheꢀBNOꢀbitꢀinꢀtheꢀUCR1ꢀ
register.ꢀWhenꢀBNOꢀbitꢀisꢀset,ꢀtheꢀwordꢀlengthꢀwillꢀbeꢀsetꢀtoꢀ9ꢀbits.ꢀInꢀthisꢀcaseꢀtheꢀ9thꢀbit,ꢀwhichꢀ
isꢀtheꢀMSB,ꢀneedsꢀtoꢀbeꢀstoredꢀinꢀtheꢀTX8ꢀbitꢀinꢀtheꢀUCR1ꢀregister.ꢀAtꢀtheꢀtransmitterꢀcoreꢀliesꢀtheꢀ
TransmitterꢀShiftꢀRegister,ꢀmoreꢀcommonlyꢀknownꢀasꢀtheꢀTSR,ꢀwhoseꢀdataꢀisꢀobtainedꢀfromꢀtheꢀ
transmitꢀdataꢀregister,ꢀwhichꢀisꢀknownꢀasꢀtheꢀTXRꢀregister.ꢀTheꢀdataꢀtoꢀbeꢀtransmittedꢀisꢀloadedꢀ
intoꢀthisꢀTXRꢀregisterꢀbyꢀtheꢀapplicationꢀprogram.ꢀTheꢀTSRꢀregisterꢀisꢀnotꢀwrittenꢀtoꢀwithꢀnewꢀdataꢀ
untilꢀtheꢀstopꢀbitꢀfromꢀtheꢀpreviousꢀtransmissionꢀhasꢀbeenꢀsentꢀout.ꢀAsꢀsoonꢀasꢀthisꢀstopꢀbitꢀhasꢀbeenꢀ
transmitted,ꢀtheꢀTSRꢀcanꢀthenꢀbeꢀloadedꢀwithꢀnewꢀdataꢀfromꢀtheꢀTXRꢀregister,ꢀifꢀitꢀisꢀavailable.ꢀItꢀ
shouldꢀbeꢀnotedꢀthatꢀtheꢀTSRꢀregister,ꢀunlikeꢀmanyꢀotherꢀregisters,ꢀisꢀnotꢀdirectlyꢀmappedꢀintoꢀtheꢀ
DataꢀMemoryꢀareaꢀandꢀasꢀsuchꢀisꢀnotꢀavailableꢀtoꢀtheꢀapplicationꢀprogramꢀforꢀdirectꢀread/writeꢀ
operations.ꢀAnꢀactualꢀtransmissionꢀofꢀdataꢀwillꢀnormallyꢀbeꢀenabledꢀwhenꢀtheꢀTXENꢀbitꢀisꢀset,ꢀbutꢀ
theꢀdataꢀwillꢀnotꢀbeꢀtransmittedꢀuntilꢀtheꢀTXRꢀregisterꢀhasꢀbeenꢀloadedꢀwithꢀdataꢀandꢀtheꢀbaudꢀrateꢀ
generatorꢀhasꢀdefinedꢀaꢀshiftꢀclockꢀsource.ꢀHowever,ꢀtheꢀtransmissionꢀcanꢀalsoꢀbeꢀinitiatedꢀbyꢀfirstꢀ
loadingꢀdataꢀintoꢀtheꢀTXRꢀregister,ꢀafterꢀwhichꢀtheꢀTXENꢀbitꢀcanꢀbeꢀset.ꢀWhenꢀaꢀtransmissionꢀofꢀ
dataꢀbegins,ꢀtheꢀTSRꢀisꢀnormallyꢀempty,ꢀinꢀwhichꢀcaseꢀaꢀtransferꢀtoꢀtheꢀTXRꢀregisterꢀwillꢀresultꢀinꢀ
anꢀimmediateꢀtransferꢀtoꢀtheꢀTSR.ꢀIfꢀduringꢀaꢀtransmissionꢀtheꢀTXENꢀbitꢀisꢀcleared,ꢀtheꢀtransmissionꢀ
willꢀimmediatelyꢀceaseꢀandꢀtheꢀtransmitterꢀwillꢀbeꢀreset.ꢀTheꢀTXꢀoutputꢀpinꢀwillꢀthenꢀreturnꢀtoꢀtheꢀ
I/Oꢀorꢀotherꢀpin-sharedꢀfunction.
Transmitting Data
WhenꢀtheꢀUARTꢀisꢀtransmittingꢀdata,ꢀtheꢀdataꢀisꢀshiftedꢀonꢀtheꢀTXꢀpinꢀfromꢀtheꢀshiftꢀregister,ꢀwithꢀ
theꢀleastꢀsignificantꢀbitꢀfirst.ꢀInꢀtheꢀtransmitꢀmode,ꢀtheꢀTXRꢀregisterꢀformsꢀaꢀbufferꢀbetweenꢀtheꢀ
internalꢀbusꢀandꢀtheꢀtransmitterꢀshiftꢀregister.ꢀItꢀshouldꢀbeꢀnotedꢀthatꢀifꢀ9-bitꢀdataꢀformatꢀhasꢀbeenꢀ
selected,ꢀthenꢀtheꢀMSBꢀwillꢀbeꢀtakenꢀfromꢀtheꢀTX8ꢀbitꢀinꢀtheꢀUCR1ꢀregister.ꢀTheꢀstepsꢀtoꢀinitiateꢀaꢀ
dataꢀtransferꢀcanꢀbeꢀsummarizedꢀasꢀfollows:
•ꢀ MakeꢀtheꢀcorrectꢀselectionꢀofꢀtheꢀBNO,ꢀPRT,ꢀPRENꢀandꢀSTOPSꢀbitsꢀtoꢀdefineꢀtheꢀrequiredꢀwordꢀ
length,ꢀparityꢀtypeꢀandꢀnumberꢀofꢀstopꢀbits.
•ꢀ SetupꢀtheꢀBRGꢀregisterꢀtoꢀselectꢀtheꢀdesiredꢀbaudꢀrate.
•ꢀ SetꢀtheꢀTXENꢀbitꢀtoꢀensureꢀthatꢀtheꢀUARTꢀtransmitterꢀisꢀenabledꢀandꢀtheꢀTXꢀpinꢀisꢀusedꢀasꢀaꢀ
UARTꢀtransmitterꢀpin.
•ꢀ AccessꢀtheꢀUSRꢀregisterꢀandꢀwriteꢀtheꢀdataꢀthatꢀisꢀtoꢀbeꢀtransmittedꢀintoꢀtheꢀTXRꢀregister.ꢀNoteꢀ
thatꢀthisꢀstepꢀwillꢀclearꢀtheꢀTXIFꢀbit.
Rev. 1.10
166
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Thisꢀsequenceꢀofꢀeventsꢀcanꢀnowꢀbeꢀrepeatedꢀtoꢀsendꢀadditionalꢀdata.ꢀItꢀshouldꢀbeꢀnotedꢀthatꢀwhenꢀ
TXIFꢀisꢀ“0”,ꢀdataꢀwillꢀbeꢀinhibitedꢀfromꢀbeingꢀwrittenꢀtoꢀtheꢀTXRꢀregister.ꢀClearingꢀtheꢀTXIFꢀflagꢀisꢀ
alwaysꢀachievedꢀusingꢀtheꢀfollowingꢀsoftwareꢀsequence:
•ꢀ AꢀUSRꢀregisterꢀaccess
•ꢀ AꢀTXRꢀregisterꢀwriteꢀexecution
Theꢀread-onlyꢀTXIFꢀflagꢀisꢀsetꢀbyꢀtheꢀUARTꢀhardwareꢀandꢀifꢀsetꢀindicatesꢀthatꢀtheꢀTXRꢀregisterꢀisꢀ
emptyꢀandꢀthatꢀotherꢀdataꢀcanꢀnowꢀbeꢀwrittenꢀintoꢀtheꢀTXRꢀregisterꢀwithoutꢀoverwritingꢀtheꢀpreviousꢀ
data.ꢀIfꢀtheꢀTEIEꢀbitꢀisꢀsetꢀthenꢀtheꢀTXIFꢀflagꢀwillꢀgenerateꢀanꢀinterrupt.ꢀDuringꢀaꢀdataꢀtransmission,ꢀ
aꢀwriteꢀinstructionꢀtoꢀtheꢀTXRꢀregisterꢀwillꢀplaceꢀtheꢀdataꢀintoꢀtheꢀTXRꢀregister,ꢀwhichꢀwillꢀbeꢀ
copiedꢀtoꢀtheꢀshiftꢀregisterꢀatꢀtheꢀendꢀofꢀtheꢀpresentꢀtransmission.ꢀWhenꢀthereꢀisꢀnoꢀdataꢀtransmissionꢀ
inꢀprogress,ꢀaꢀwriteꢀinstructionꢀtoꢀtheꢀTXRꢀregisterꢀwillꢀplaceꢀtheꢀdataꢀdirectlyꢀintoꢀtheꢀshiftꢀregister,ꢀ
resultingꢀinꢀtheꢀcommencementꢀofꢀdataꢀtransmission,ꢀandꢀtheꢀTXIFꢀbitꢀbeingꢀimmediatelyꢀset.ꢀWhenꢀ
aꢀframeꢀtransmissionꢀisꢀcomplete,ꢀwhichꢀhappensꢀafterꢀstopꢀbitsꢀareꢀsentꢀorꢀafterꢀtheꢀbreakꢀframe,ꢀtheꢀ
TIDLEꢀbitꢀwillꢀbeꢀset.ꢀToꢀclearꢀtheꢀTIDLEꢀbitꢀtheꢀfollowingꢀsoftwareꢀsequenceꢀisꢀused:
•ꢀ AꢀUSRꢀregisterꢀaccess
•ꢀ AꢀTXRꢀregisterꢀwriteꢀexecution
NoteꢀthatꢀbothꢀtheꢀTXIFꢀandꢀTIDLEꢀbitsꢀareꢀclearedꢀbyꢀtheꢀsameꢀsoftwareꢀsequence.
Transmit Break
IfꢀtheꢀTXBRKꢀbitꢀisꢀsetꢀthenꢀbreakꢀcharactersꢀwillꢀbeꢀsentꢀonꢀtheꢀnextꢀtransmission.ꢀBreakꢀcharacterꢀ
transmissionꢀconsistsꢀofꢀaꢀstartꢀbit,ꢀfollowedꢀbyꢀ13×Nꢀ‘0’ꢀbitsꢀandꢀstopꢀbits,ꢀwhereꢀN=1,ꢀ2,ꢀetc.ꢀIfꢀaꢀ
breakꢀcharacterꢀisꢀtoꢀbeꢀtransmittedꢀthenꢀtheꢀTXBRKꢀbitꢀmustꢀbeꢀfirstꢀsetꢀbyꢀtheꢀapplicationꢀprogramꢀ
andꢀthenꢀclearedꢀtoꢀgenerateꢀtheꢀstopꢀbits.ꢀTransmittingꢀaꢀbreakꢀcharacterꢀwillꢀnotꢀgenerateꢀaꢀtransmitꢀ
interrupt.ꢀNoteꢀthatꢀaꢀbreakꢀconditionꢀlengthꢀisꢀatꢀleastꢀ13ꢀbitsꢀlong.ꢀIfꢀtheꢀTXBRKꢀbitꢀisꢀcontinuallyꢀ
keptꢀatꢀaꢀlogicꢀhighꢀlevelꢀthenꢀtheꢀtransmitterꢀcircuitryꢀwillꢀtransmitꢀcontinuousꢀbreakꢀcharacters.ꢀ
AfterꢀtheꢀapplicationꢀprogramꢀhasꢀclearedꢀtheꢀTXBRKꢀbit,ꢀtheꢀtransmitterꢀwillꢀfinishꢀtransmittingꢀtheꢀ
lastꢀbreakꢀcharacterꢀandꢀsubsequentlyꢀsendꢀoutꢀoneꢀorꢀtwoꢀstopꢀbits.ꢀTheꢀautomaticꢀlogicꢀhighsꢀatꢀtheꢀ
endꢀofꢀtheꢀlastꢀbreakꢀcharacterꢀwillꢀensureꢀthatꢀtheꢀstartꢀbitꢀofꢀtheꢀnextꢀframeꢀisꢀrecognized.
UART Receiver
TheꢀUARTꢀisꢀcapableꢀofꢀreceivingꢀwordꢀlengthsꢀofꢀeitherꢀ8ꢀorꢀ9ꢀbitsꢀcanꢀbeꢀselectedꢀbyꢀprogrammingꢀ
theꢀBNOꢀbitꢀinꢀtheꢀUCRꢀregister.ꢀIfꢀtheꢀBNOꢀbitꢀisꢀset,ꢀtheꢀwordꢀlengthꢀwillꢀbeꢀsetꢀtoꢀ9ꢀbitsꢀwithꢀtheꢀ
MSBꢀbeingꢀstoredꢀinꢀtheꢀRX8ꢀbitꢀofꢀtheꢀUCR1ꢀregister.ꢀAtꢀtheꢀreceiverꢀcoreꢀliesꢀtheꢀReceiveꢀSerialꢀ
ShiftꢀRegister,ꢀcommonlyꢀknownꢀasꢀtheꢀRSR.ꢀTheꢀdataꢀwhichꢀisꢀreceivedꢀonꢀtheꢀRXꢀexternalꢀinputꢀ
pinꢀisꢀsentꢀtoꢀtheꢀdataꢀrecoveryꢀblock.ꢀTheꢀdataꢀrecoveryꢀblockꢀoperatingꢀspeedꢀisꢀ16ꢀtimesꢀthatꢀofꢀtheꢀ
baudꢀrate,ꢀwhileꢀtheꢀmainꢀreceiveꢀserialꢀshifterꢀoperatesꢀatꢀtheꢀbaudꢀrate.ꢀAfterꢀtheꢀRXꢀpinꢀisꢀsampledꢀ
forꢀtheꢀstopꢀbit,ꢀtheꢀreceivedꢀdataꢀinꢀRSRꢀisꢀtransferredꢀtoꢀtheꢀreceiveꢀdataꢀregister,ꢀifꢀtheꢀregisterꢀisꢀ
empty.ꢀTheꢀdataꢀwhichꢀisꢀreceivedꢀonꢀtheꢀexternalꢀRXꢀinputꢀpinꢀisꢀsampledꢀthreeꢀtimesꢀbyꢀaꢀmajorityꢀ
detectꢀcircuitꢀtoꢀdetermineꢀtheꢀlogicꢀlevelꢀthatꢀhasꢀbeenꢀplacedꢀontoꢀtheꢀRXꢀpin.ꢀItꢀshouldꢀbeꢀnotedꢀ
thatꢀtheꢀRSRꢀregister,ꢀunlikeꢀmanyꢀotherꢀregisters,ꢀisꢀnotꢀdirectlyꢀmappedꢀintoꢀtheꢀDataꢀMemoryꢀareaꢀ
andꢀasꢀsuchꢀisꢀnotꢀavailableꢀtoꢀtheꢀapplicationꢀprogramꢀforꢀdirectꢀread/writeꢀoperations.
Rev. 1.10
167
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Receiving Data
WhenꢀtheꢀUARTꢀreceiverꢀisꢀreceivingꢀdata,ꢀtheꢀdataꢀisꢀseriallyꢀshiftedꢀinꢀonꢀtheꢀexternalꢀRXꢀinputꢀ
pinꢀtoꢀtheꢀshiftꢀregister,ꢀwithꢀtheꢀleastꢀsignificantꢀbitꢀLSBꢀfirst.ꢀTheꢀRXRꢀregisterꢀisꢀaꢀtwoꢀbyteꢀdeepꢀ
FIFOꢀdataꢀbuffer,ꢀwhereꢀtwoꢀbytesꢀcanꢀbeꢀheldꢀinꢀtheꢀFIFOꢀwhileꢀaꢀthirdꢀbyteꢀcanꢀcontinueꢀtoꢀbeꢀ
received.ꢀNoteꢀthatꢀtheꢀapplicationꢀprogramꢀmustꢀensureꢀthatꢀtheꢀdataꢀisꢀreadꢀfromꢀRXRꢀbeforeꢀtheꢀ
thirdꢀbyteꢀhasꢀbeenꢀcompletelyꢀshiftedꢀin,ꢀotherwiseꢀthisꢀthirdꢀbyteꢀwillꢀbeꢀdiscardedꢀandꢀanꢀoverrunꢀ
errorꢀOERRꢀwillꢀbeꢀsubsequentlyꢀindicated.ꢀTheꢀstepsꢀtoꢀinitiateꢀaꢀdataꢀtransferꢀcanꢀbeꢀsummarizedꢀ
asꢀfollows:
•ꢀ MakeꢀtheꢀcorrectꢀselectionꢀofꢀBNO,ꢀPRTꢀandꢀPRENꢀbitsꢀtoꢀdefineꢀtheꢀwordꢀlengthꢀandꢀparityꢀ
type.
•ꢀ SetupꢀtheꢀBRGꢀregisterꢀtoꢀselectꢀtheꢀdesiredꢀbaudꢀrate.
•ꢀ SetꢀtheꢀRXENꢀbitꢀtoꢀensureꢀthatꢀtheꢀUARTꢀreceiverꢀisꢀenabledꢀandꢀtheꢀRXꢀpinꢀisꢀusedꢀasꢀaꢀUARTꢀ
receiverꢀpin.
Atꢀthisꢀpointꢀtheꢀreceiverꢀwillꢀbeꢀenabledꢀwhichꢀwillꢀbeginꢀtoꢀlookꢀforꢀaꢀstartꢀbit.
Whenꢀaꢀcharacterꢀisꢀreceived,ꢀtheꢀfollowingꢀsequenceꢀofꢀeventsꢀwillꢀoccur:
•ꢀ TheꢀRXIFꢀbitꢀinꢀtheꢀUSRꢀregisterꢀwillꢀbeꢀsetꢀwhenꢀtheꢀRXRꢀregisterꢀhasꢀdataꢀavailable.ꢀThereꢀ
willꢀbeꢀatꢀmostꢀoneꢀmoreꢀcharactersꢀavailableꢀbeforeꢀanꢀoverrunꢀerrorꢀoccurs.
•ꢀ WhenꢀtheꢀcontentsꢀofꢀtheꢀshiftꢀregisterꢀhaveꢀbeenꢀtransferredꢀtoꢀtheꢀRXRꢀregisterꢀandꢀifꢀtheꢀRIEꢀ
bitꢀisꢀset,ꢀthenꢀanꢀinterruptꢀwillꢀbeꢀgenerated.
•ꢀ Ifꢀduringꢀreception,ꢀaꢀframeꢀerror,ꢀnoiseꢀerror,ꢀparityꢀerror,ꢀorꢀanꢀoverrunꢀerrorꢀhasꢀbeenꢀdetected,ꢀ
thenꢀtheꢀerrorꢀflagsꢀcanꢀbeꢀset.
TheꢀRXIFꢀbitꢀcanꢀbeꢀclearedꢀusingꢀtheꢀfollowingꢀsoftwareꢀsequence:
•ꢀ AꢀUSRꢀregisterꢀaccess
•ꢀ AnꢀRXRꢀregisterꢀreadꢀexecution
Receive Break
AnyꢀbreakꢀcharacterꢀreceivedꢀbyꢀtheꢀUARTꢀwillꢀbeꢀmanagedꢀasꢀaꢀframingꢀerror.ꢀTheꢀreceiverꢀwillꢀ
countꢀandꢀexpectꢀaꢀcertainꢀnumberꢀofꢀbitꢀtimesꢀasꢀspecifiedꢀbyꢀtheꢀvaluesꢀprogrammedꢀintoꢀtheꢀ
BNOꢀandꢀplusingꢀoneꢀSTOPꢀbit.ꢀIfꢀtheꢀbreakꢀisꢀmuchꢀlongerꢀthanꢀ13ꢀbitꢀtimes,ꢀtheꢀreceptionꢀwillꢀ
beꢀconsideredꢀasꢀcompleteꢀafterꢀtheꢀnumberꢀofꢀbitꢀtimesꢀspecifiedꢀbyꢀBNOꢀandꢀplusingꢀoneꢀSTOPꢀ
bit.ꢀTheꢀRXIFꢀbitꢀisꢀset,ꢀFERRꢀisꢀset,ꢀzerosꢀareꢀloadedꢀintoꢀtheꢀreceiveꢀdataꢀregister,ꢀinterruptsꢀareꢀ
generatedꢀifꢀappropriateꢀandꢀtheꢀRIDLEꢀbitꢀisꢀset.ꢀAꢀbreakꢀisꢀregardedꢀasꢀaꢀcharacterꢀthatꢀcontainsꢀ
onlyꢀzerosꢀwithꢀtheꢀFERRꢀflagꢀset.ꢀIfꢀaꢀlongꢀbreakꢀsignalꢀhasꢀbeenꢀdetected,ꢀtheꢀreceiverꢀwillꢀregardꢀ
itꢀasꢀaꢀdataꢀframeꢀincludingꢀaꢀstartꢀbit,ꢀdataꢀbitsꢀandꢀtheꢀinvalidꢀstopꢀbitꢀandꢀtheꢀFERRꢀflagꢀwillꢀbeꢀ
set.ꢀTheꢀreceiverꢀmustꢀwaitꢀforꢀaꢀvalidꢀstopꢀbitꢀbeforeꢀlookingꢀforꢀtheꢀnextꢀstartꢀbit.ꢀTheꢀreceiverꢀwillꢀ
notꢀmakeꢀtheꢀassumptionꢀthatꢀtheꢀbreakꢀconditionꢀonꢀtheꢀlineꢀisꢀtheꢀnextꢀstartꢀbit.ꢀTheꢀbreakꢀcharacterꢀ
willꢀbeꢀloadedꢀintoꢀtheꢀbufferꢀandꢀnoꢀfurtherꢀdataꢀwillꢀbeꢀreceivedꢀuntilꢀstopꢀbitsꢀareꢀreceived.ꢀItꢀ
shouldꢀbeꢀnotedꢀthatꢀtheꢀRIDLEꢀreadꢀonlyꢀflagꢀwillꢀgoꢀhighꢀwhenꢀtheꢀstopꢀbitsꢀhaveꢀnotꢀyetꢀbeenꢀ
received.ꢀTheꢀreceptionꢀofꢀaꢀbreakꢀcharacterꢀonꢀtheꢀUARTꢀregistersꢀwillꢀresultꢀinꢀtheꢀfollowing:
•ꢀ Theꢀframingꢀerrorꢀflag,ꢀFERR,ꢀwillꢀbeꢀset
•ꢀ Theꢀreceiveꢀdataꢀregister,ꢀRXR,ꢀwillꢀbeꢀcleared
•ꢀ TheꢀOERR,ꢀNF,ꢀPERR,ꢀRIDLEꢀorꢀRXIFꢀflagsꢀwillꢀpossiblyꢀbeꢀset
Rev. 1.10
16ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Idle Status
Whenꢀtheꢀreceiverꢀisꢀreadingꢀdata,ꢀwhichꢀmeansꢀitꢀwillꢀbeꢀinꢀbetweenꢀtheꢀdetectionꢀofꢀaꢀstartꢀbitꢀandꢀ
theꢀreadingꢀofꢀaꢀstopꢀbit,ꢀtheꢀreceiverꢀstatusꢀflagꢀinꢀtheꢀUSRꢀregister,ꢀotherwiseꢀknownꢀasꢀtheꢀRIDLEꢀ
flag,ꢀwillꢀhaveꢀaꢀzeroꢀvalue.ꢀInꢀbetweenꢀtheꢀreceptionꢀofꢀaꢀstopꢀbitꢀandꢀtheꢀdetectionꢀofꢀtheꢀnextꢀstartꢀ
bit,ꢀtheꢀRIDLEꢀflagꢀwillꢀhaveꢀaꢀhighꢀvalue,ꢀwhichꢀindicatesꢀtheꢀreceiverꢀisꢀinꢀanꢀidleꢀcondition.
Receiver Interrupt
TheꢀreadꢀonlyꢀreceiveꢀinterruptꢀflagꢀRXIFꢀinꢀtheꢀUSRꢀregisterꢀisꢀsetꢀbyꢀanꢀedgeꢀgeneratedꢀbyꢀtheꢀ
receiver.ꢀAnꢀinterruptꢀisꢀgeneratedꢀifꢀRIEꢀbitꢀisꢀ“1”,ꢀwhenꢀaꢀwordꢀisꢀtransferredꢀfromꢀtheꢀReceiveꢀ
ShiftꢀRegister,ꢀRSR,ꢀtoꢀtheꢀReceiveꢀDataꢀRegister,ꢀRXR.ꢀAnꢀoverrunꢀerrorꢀcanꢀalsoꢀgenerateꢀanꢀ
interruptꢀifꢀRIEꢀisꢀ“1”.
Managing Receiver Errors
SeveralꢀtypesꢀofꢀreceptionꢀerrorsꢀcanꢀoccurꢀwithinꢀtheꢀUARTꢀmodule,ꢀtheꢀfollowingꢀsectionꢀdescribesꢀ
theꢀvariousꢀtypesꢀandꢀhowꢀtheyꢀareꢀmanagedꢀbyꢀtheꢀUART.
Overrun Error – OERR flag
TheꢀRXRꢀregisterꢀisꢀcomposedꢀofꢀaꢀtwoꢀbyteꢀdeepꢀFIFOꢀdataꢀbuffer,ꢀwhereꢀtwoꢀbytesꢀcanꢀbeꢀheldꢀ
inꢀtheꢀFIFOꢀregister,ꢀwhileꢀaꢀthirdꢀbyteꢀcanꢀcontinueꢀtoꢀbeꢀreceived.ꢀBeforeꢀthisꢀthirdꢀbyteꢀhasꢀbeenꢀ
entirelyꢀshiftedꢀin,ꢀtheꢀdataꢀshouldꢀbeꢀreadꢀfromꢀtheꢀRXRꢀregister.ꢀIfꢀthisꢀisꢀnotꢀdone,ꢀtheꢀoverrunꢀ
errorꢀflagꢀOERRꢀwillꢀbeꢀconsequentlyꢀindicated.ꢀ
Inꢀtheꢀeventꢀofꢀanꢀoverrunꢀerrorꢀoccurring,ꢀtheꢀfollowingꢀwillꢀhappen:
•ꢀ TheꢀOERRꢀflagꢀinꢀtheꢀUSRꢀregisterꢀwillꢀbeꢀset.
•ꢀ TheꢀRXRꢀcontentsꢀwillꢀnotꢀbeꢀlost.
•ꢀ Theꢀshiftꢀregisterꢀwillꢀbeꢀoverwritten.
•ꢀ AnꢀinterruptꢀwillꢀbeꢀgeneratedꢀifꢀtheꢀRIEꢀbitꢀisꢀset.
TheꢀOERRꢀflagꢀcanꢀbeꢀclearedꢀbyꢀanꢀaccessꢀtoꢀtheꢀUSRꢀregisterꢀfollowedꢀbyꢀaꢀreadꢀtoꢀtheꢀRXRꢀ
register.
Noise Error – NF Flag
Over-samplingꢀisꢀusedꢀforꢀdataꢀrecoveryꢀtoꢀidentifyꢀvalidꢀincomingꢀdataꢀandꢀnoise.ꢀIfꢀnoiseꢀisꢀ
detectedꢀwithinꢀaꢀframeꢀtheꢀfollowingꢀwillꢀoccur:
•ꢀ Theꢀreadꢀonlyꢀnoiseꢀflag,ꢀNF,ꢀinꢀtheꢀUSRꢀregisterꢀwillꢀbeꢀsetꢀonꢀtheꢀrisingꢀedgeꢀofꢀtheꢀRXIFꢀbit.
•ꢀ DataꢀwillꢀbeꢀtransferredꢀfromꢀtheꢀShiftꢀregisterꢀtoꢀtheꢀRXRꢀregister.
•ꢀ Noꢀinterruptꢀwillꢀbeꢀgenerated.ꢀHoweverꢀthisꢀbitꢀrisesꢀatꢀtheꢀsameꢀtimeꢀasꢀtheꢀRXIFꢀbitꢀwhichꢀ
itselfꢀgeneratesꢀanꢀinterrupt.
NoteꢀthatꢀtheꢀNFꢀflagꢀisꢀresetꢀbyꢀaꢀUSRꢀregisterꢀreadꢀoperationꢀfollowedꢀbyꢀanꢀRXRꢀregisterꢀreadꢀ
operation.
Rev. 1.10
169
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Framing Error – FERR Flag
Theꢀreadꢀonlyꢀframingꢀerrorꢀflag,ꢀFERR,ꢀinꢀtheꢀUSRꢀregister,ꢀisꢀsetꢀifꢀaꢀzeroꢀisꢀdetectedꢀinsteadꢀofꢀ
stopꢀbits.ꢀIfꢀtwoꢀstopꢀbitsꢀareꢀselected,ꢀonlyꢀtheꢀfirstꢀstopꢀbitꢀisꢀdetected,ꢀitꢀmustꢀbeꢀhigh.ꢀIfꢀtheꢀfirstꢀ
stopꢀbitꢀisꢀlow,ꢀtheꢀFERRꢀflagꢀwillꢀbeꢀset.ꢀTheꢀFERRꢀflagꢀandꢀtheꢀreceivedꢀdataꢀwillꢀbeꢀrecordedꢀinꢀ
theꢀUSRꢀandꢀRXRꢀregistersꢀrespectively,ꢀandꢀtheꢀflagꢀisꢀclearedꢀinꢀanyꢀreset.
Parity Error – PERR Flag
Theꢀreadꢀonlyꢀparityꢀerrorꢀflag,ꢀPERR,ꢀinꢀtheꢀUSRꢀregister,ꢀisꢀsetꢀifꢀtheꢀparityꢀofꢀtheꢀreceivedꢀwordꢀisꢀ
incorrect.ꢀThisꢀerrorꢀflagꢀisꢀonlyꢀapplicableꢀifꢀtheꢀparityꢀisꢀenabled,ꢀPRENꢀbitꢀisꢀ“1”,ꢀandꢀifꢀtheꢀparityꢀ
type,ꢀoddꢀorꢀevenꢀisꢀselected.ꢀTheꢀreadꢀonlyꢀPERRꢀflagꢀandꢀtheꢀreceivedꢀdataꢀwillꢀbeꢀrecordedꢀinꢀ
theꢀUSRꢀandꢀRXRꢀregistersꢀrespectively.ꢀItꢀisꢀclearedꢀonꢀanyꢀreset,ꢀitꢀshouldꢀbeꢀnotedꢀthatꢀtheꢀflags,ꢀ
FERRꢀandꢀPERR,ꢀinꢀtheꢀUSRꢀregisterꢀshouldꢀfirstꢀbeꢀreadꢀbyꢀtheꢀapplicationꢀprogramꢀbeforeꢀreadingꢀ
theꢀdataꢀword.
UART Module Interrupt Structure
SeveralꢀindividualꢀUARTꢀconditionsꢀcanꢀgenerateꢀaꢀUARTꢀinterrupt.ꢀWhenꢀtheseꢀconditionsꢀexist,ꢀ
aꢀlowꢀpulseꢀwillꢀbeꢀgeneratedꢀtoꢀgetꢀtheꢀattentionꢀofꢀtheꢀmicrocontroller.ꢀTheseꢀconditionsꢀareꢀaꢀ
transmitterꢀdataꢀregisterꢀempty,ꢀtransmitterꢀidle,ꢀreceiverꢀdataꢀavailable,ꢀreceiverꢀoverrun,ꢀaddressꢀ
detectꢀandꢀanꢀRXꢀpinꢀwake-up.ꢀWhenꢀanyꢀofꢀtheseꢀconditionsꢀareꢀcreated,ꢀifꢀitsꢀcorrespondingꢀ
interruptꢀcontrolꢀisꢀenabledꢀandꢀtheꢀstackꢀisꢀnotꢀfull,ꢀtheꢀprogramꢀwillꢀjumpꢀtoꢀitsꢀcorrespondingꢀ
interruptꢀvectorꢀwhereꢀitꢀcanꢀbeꢀservicedꢀbeforeꢀreturningꢀtoꢀtheꢀmainꢀprogram.ꢀFourꢀofꢀtheseꢀ
conditionsꢀhaveꢀtheꢀcorrespondingꢀUSRꢀregisterꢀflagsꢀwhichꢀwillꢀgenerateꢀaꢀUARTꢀinterruptꢀifꢀitsꢀ
associatedꢀinterruptꢀenableꢀcontrolꢀbitꢀinꢀtheꢀUCR2ꢀregisterꢀisꢀset.ꢀTheꢀtwoꢀtransmitterꢀinterruptꢀ
conditionsꢀhaveꢀtheirꢀownꢀcorrespondingꢀenableꢀcontrolꢀbits,ꢀwhileꢀtheꢀtwoꢀreceiverꢀinterruptꢀ
conditionsꢀhaveꢀaꢀsharedꢀenableꢀcontrolꢀbit.ꢀTheseꢀenableꢀbitsꢀcanꢀbeꢀusedꢀtoꢀmaskꢀoutꢀindividualꢀ
UARTꢀinterruptꢀsources.
Theꢀaddressꢀdetectꢀcondition,ꢀwhichꢀisꢀalsoꢀaꢀUARTꢀinterruptꢀsource,ꢀdoesꢀnotꢀhaveꢀanꢀassociatedꢀ
flag,ꢀbutꢀwillꢀgenerateꢀaꢀUARTꢀinterruptꢀwhenꢀanꢀaddressꢀdetectꢀconditionꢀoccursꢀifꢀitsꢀfunctionꢀisꢀ
enabledꢀbyꢀsettingꢀtheꢀADDENꢀbitꢀinꢀtheꢀUCR2ꢀregister.ꢀAnꢀRXꢀpinꢀwake-up,ꢀwhichꢀisꢀalsoꢀaꢀUARTꢀ
interruptꢀsource,ꢀdoesꢀnotꢀhaveꢀanꢀassociatedꢀflag,ꢀbutꢀwillꢀgenerateꢀaꢀUARTꢀinterruptꢀifꢀtheꢀUARTꢀ
clockꢀ(fH)ꢀisꢀswitchedꢀoffꢀandꢀtheꢀWAKEꢀandꢀRIEꢀbitsꢀinꢀtheꢀUCR2ꢀregisterꢀareꢀsetꢀwhenꢀaꢀfallingꢀ
edgeꢀonꢀtheꢀRXꢀpinꢀoccurs.ꢀ
NoteꢀthatꢀtheꢀUSRꢀregisterꢀflagsꢀareꢀreadꢀonlyꢀandꢀcannotꢀbeꢀclearedꢀorꢀsetꢀbyꢀtheꢀapplicationꢀ
program,ꢀneitherꢀwillꢀtheyꢀbeꢀclearedꢀwhenꢀtheꢀprogramꢀjumpsꢀtoꢀtheꢀcorrespondingꢀinterruptꢀ
servicingꢀroutine,ꢀasꢀisꢀtheꢀcaseꢀforꢀsomeꢀofꢀtheꢀotherꢀinterrupts.ꢀTheꢀflagsꢀwillꢀbeꢀclearedꢀ
automaticallyꢀwhenꢀcertainꢀactionsꢀareꢀtakenꢀbyꢀtheꢀUART,ꢀtheꢀdetailsꢀofꢀwhichꢀareꢀgivenꢀinꢀtheꢀ
UARTꢀregisterꢀsection.ꢀTheꢀoverallꢀUARTꢀinterruptꢀcanꢀbeꢀdisabledꢀorꢀenabledꢀbyꢀtheꢀrelatedꢀ
interruptꢀenableꢀcontrolꢀbitsꢀinꢀtheꢀinterruptꢀcontrolꢀregistersꢀofꢀtheꢀmicrocontrollerꢀtoꢀdecideꢀwhetherꢀ
theꢀinterruptꢀrequestedꢀbyꢀtheꢀUARTꢀmoduleꢀisꢀmaskedꢀoutꢀorꢀallowed.
Rev. 1.10
170
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
USR Registeꢁ
UCRꢅ Registeꢁ
Tꢁansmitteꢁ Emptꢂ
TEIE
TIIE
0
1
Flag TXIF
INTC0
INTCꢅ
Registeꢁ
Registeꢁ
UART Inteꢁꢁꢀpt
Reqꢀest Flag
URF
Tꢁansmitteꢁ Idle
Flag TIDLE
EMI
0
1
URE
Receiveꢁ Oveꢁꢁꢀn
Flag OERR
RIE
0
1
OR
Receiveꢁ Data
Available RXIF
ADDEN
0
1
0
1
RX Pin
Wake-ꢀp
WAKE
0
1
RX7 if BNO=0
RX8 if BNO=1
UCRꢅ Registeꢁ
UART Interrupt Scheme
Address Detect Mode
SettingꢀtheꢀAddressꢀDetectꢀModeꢀbit,ꢀADDEN,ꢀinꢀtheꢀUCR2ꢀregister,ꢀenablesꢀthisꢀspecialꢀmode.ꢀ
IfꢀthisꢀbitꢀisꢀenabledꢀthenꢀanꢀadditionalꢀqualifierꢀwillꢀbeꢀplacedꢀonꢀtheꢀgenerationꢀofꢀaꢀReceiverꢀ
DataꢀAvailableꢀinterrupt,ꢀwhichꢀisꢀrequestedꢀbyꢀtheꢀRXIFꢀflag.ꢀIfꢀtheꢀADDENꢀbitꢀisꢀ“1”,ꢀthenꢀwhenꢀ
dataꢀisꢀavailable,ꢀanꢀinterruptꢀwillꢀonlyꢀbeꢀgenerated,ꢀifꢀtheꢀhighestꢀreceivedꢀbitꢀhasꢀaꢀhighꢀvalue.ꢀ
NoteꢀthatꢀtheꢀrelatedꢀinterruptꢀenableꢀcontrolꢀbitꢀandꢀtheꢀEMIꢀbitꢀmustꢀalsoꢀbeꢀenabledꢀforꢀcorrectꢀ
interruptꢀgeneration.ꢀThisꢀhighestꢀaddressꢀbitꢀisꢀtheꢀ9thꢀbitꢀifꢀBNOꢀbitꢀisꢀ“1”ꢀorꢀtheꢀ8thꢀbitꢀifꢀBNOꢀ
bitꢀisꢀ“0”.ꢀIfꢀthisꢀbitꢀisꢀhigh,ꢀthenꢀtheꢀreceivedꢀwordꢀwillꢀbeꢀdefinedꢀasꢀanꢀaddressꢀratherꢀthanꢀdata.ꢀAꢀ
DataꢀAvailableꢀinterruptꢀwillꢀbeꢀgeneratedꢀeveryꢀtimeꢀtheꢀlastꢀbitꢀofꢀtheꢀreceivedꢀwordꢀisꢀset.ꢀIfꢀtheꢀ
ADDENꢀbitꢀisꢀ“0”,ꢀthenꢀaꢀReceiverꢀDataꢀAvailableꢀinterruptꢀwillꢀbeꢀgeneratedꢀeachꢀtimeꢀtheꢀRXIFꢀ
flagꢀisꢀset,ꢀirrespectiveꢀofꢀtheꢀdataꢀlastꢀbitꢀstatus.ꢀTheꢀaddressꢀdetectꢀmodeꢀandꢀparityꢀenableꢀareꢀ
mutuallyꢀexclusiveꢀfunctions.ꢀThereforeꢀifꢀtheꢀaddressꢀdetectꢀmodeꢀisꢀenabled,ꢀthenꢀtoꢀensureꢀcorrectꢀ
operation,ꢀtheꢀparityꢀfunctionꢀshouldꢀbeꢀdisabledꢀbyꢀresettingꢀtheꢀparityꢀenableꢀbitꢀPRENꢀtoꢀ“0”.
Bit 9 if BNO=1
Bit 8 if BNO=0
UART Interrupt
Generated
ADDEN
0
1
0
1
√
√
×
√
0
1
ADDEN Bit Function
Rev. 1.10
171
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
UART Power Down and Wake-up
WhenꢀtheꢀUARTꢀclockꢀ(fH)ꢀisꢀswitchedꢀoff,ꢀtheꢀUARTꢀwillꢀceaseꢀtoꢀfunction,ꢀallꢀclockꢀsourcesꢀtoꢀ
theꢀmoduleꢀareꢀshutdown.ꢀIfꢀtheꢀUARTꢀclockꢀ(fH)ꢀisꢀoffꢀwhileꢀaꢀtransmissionꢀisꢀstillꢀinꢀprogress,ꢀthenꢀ
theꢀtransmissionꢀwillꢀbeꢀpausedꢀuntilꢀtheꢀUARTꢀclockꢀ(fH)ꢀsourceꢀderivedꢀfromꢀtheꢀmicrocontrollerꢀ
isꢀactivated.ꢀInꢀaꢀsimilarꢀway,ꢀifꢀtheꢀdeviceꢀexecutesꢀtheꢀ“HALT”ꢀinstructionꢀandꢀswitchesꢀoffꢀtheꢀ
systemꢀclockꢀwhileꢀreceivingꢀdata,ꢀthenꢀtheꢀreceptionꢀofꢀdataꢀwillꢀlikewiseꢀbeꢀpaused.ꢀWhenꢀtheꢀ
deviceꢀentersꢀtheꢀIDLEꢀorꢀSLEEPꢀMode,ꢀnoteꢀthatꢀtheꢀUSR,ꢀUCR1,ꢀUCR2,ꢀtransmitꢀandꢀreceiveꢀ
registers,ꢀasꢀwellꢀasꢀtheꢀBRGꢀregisterꢀwillꢀnotꢀbeꢀaffected.ꢀItꢀisꢀrecommendedꢀtoꢀmakeꢀsureꢀfirstꢀthatꢀ
theꢀUARTꢀdataꢀtransmissionꢀorꢀreceptionꢀhasꢀbeenꢀfinishedꢀbeforeꢀtheꢀmicrocontrollerꢀentersꢀtheꢀ
IDLEꢀorꢀSLEEPꢀmode.
TheꢀUARTꢀfunctionꢀcontainsꢀaꢀreceiverꢀRXꢀpinꢀwake-upꢀfunction,ꢀwhichꢀisꢀenabledꢀorꢀdisabledꢀ
byꢀtheꢀWAKEꢀbitꢀinꢀtheꢀUCR2ꢀregister.ꢀIfꢀthisꢀbit,ꢀalongꢀwithꢀtheꢀUARTꢀenableꢀbit,ꢀUARTEN,ꢀtheꢀ
receiverꢀenableꢀbit,ꢀRXENꢀandꢀtheꢀreceiverꢀinterruptꢀbit,ꢀRIE,ꢀareꢀallꢀsetꢀwhenꢀtheꢀUARTꢀclockꢀ(fH)ꢀ
isꢀoff,ꢀthenꢀaꢀfallingꢀedgeꢀonꢀtheꢀRXꢀpinꢀwillꢀtriggerꢀanꢀRXꢀpinꢀwake-upꢀUARTꢀinterrupt.ꢀNoteꢀthatꢀ
asꢀitꢀtakesꢀcertainꢀsystemꢀclockꢀcyclesꢀafterꢀaꢀwake-up,ꢀbeforeꢀnormalꢀmicrocontrollerꢀoperationꢀ
resumes,ꢀanyꢀdataꢀreceivedꢀduringꢀthisꢀtimeꢀonꢀtheꢀRXꢀpinꢀwillꢀbeꢀignored.
ForꢀaꢀUARTꢀwake-upꢀinterruptꢀtoꢀoccur,ꢀinꢀadditionꢀtoꢀtheꢀbitsꢀforꢀtheꢀwake-upꢀbeingꢀset,ꢀtheꢀglobalꢀ
interruptꢀenableꢀbit,ꢀEMI,ꢀandꢀtheꢀUARTꢀinterruptꢀenableꢀbit,ꢀURE,ꢀmustꢀalsoꢀbeꢀset.ꢀIfꢀtheseꢀtwoꢀ
bitsꢀareꢀnotꢀsetꢀthenꢀonlyꢀaꢀwakeꢀupꢀeventꢀwillꢀoccurꢀandꢀnoꢀinterruptꢀwillꢀbeꢀgenerated.ꢀNoteꢀalsoꢀ
thatꢀasꢀitꢀtakesꢀcertainꢀsystemꢀclockꢀcyclesꢀafterꢀaꢀwake-upꢀbeforeꢀnormalꢀmicrocontrollerꢀresumes,ꢀ
theꢀUARTꢀinterruptꢀwillꢀnotꢀbeꢀgeneratedꢀuntilꢀafterꢀthisꢀtimeꢀhasꢀelapsed.
Rev. 1.10
17ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Body Fat Measurement Function
Theꢀbodyꢀfatꢀcircuitꢀconsistsꢀofꢀsineꢀgenerator,ꢀoperationalꢀamplifierꢀandꢀfilter.ꢀItꢀisꢀhighꢀquality,ꢀ
flexibilityꢀandꢀhighꢀintegrationꢀforꢀbodyꢀfatꢀmeasurement.ꢀTheꢀwholeꢀmoduleꢀpowerꢀisꢀfromꢀLDO.
Sine Wave Generator
Theꢀsineꢀgeneratorꢀconsistsꢀofꢀaꢀfrequencyꢀdivider,ꢀcounter,ꢀRAM,ꢀ10-bitꢀD/AꢀconverterꢀandꢀOP0.ꢀItꢀ
offersꢀtheꢀwideꢀrangeꢀ5kHz~500kHzꢀsineꢀwaveꢀgeneratorꢀandꢀ32×9ꢀbitsꢀRAMꢀforꢀsineꢀwaveꢀpatternꢀ
byꢀsoftwareꢀsetting.TheꢀfrequencyꢀdividerꢀwillꢀmultiplyꢀbyꢀDN/Mꢀtoꢀgenerateꢀaꢀclockꢀtoꢀcounter.ꢀTheꢀ
relatedꢀdetailsꢀreferꢀtoꢀfollowingꢀformula.
•ꢀ Systemꢀclockꢀ/ꢀMꢀ=ꢀsineꢀwaveꢀfrequency
•ꢀ Systemꢀclockꢀ×ꢀ(DN/M)ꢀ=ꢀcounterꢀcountꢀrate
•ꢀ TheꢀMꢀmustꢀbeꢀtheꢀmultipleꢀofꢀNꢀandꢀ8.
•ꢀ Mꢀ=ꢀNꢀ×ꢀDN
•ꢀ DNRꢀ=ꢀDNꢀ/ꢀ2
•ꢀ DN:ꢀsineꢀwaveꢀcycleꢀdataꢀnumberꢀ(DNꢀ 64)
≤
•ꢀ DNR:ꢀ1/2ꢀsineꢀwaveꢀcycleꢀstoredꢀinꢀRAM(DNRꢀ 32)ꢀdataꢀnumber
≤
Pleaseꢀreferꢀtoꢀfollowingꢀtableꢀandꢀfigureꢀinꢀdetails.
System Frequency
4MHz
50
8MHz
50
12MHz
50
The Frequency of Sine Wave (kHz) 500
5
ꢆ00
ꢅ0
500
16
1
5
500
5
M
ꢆ
1
ꢆ
ꢃ
ꢆ0
160 1600 ꢅꢃ
ꢅꢃ0 ꢅꢃ00
N
ꢅ
ꢃ
ꢅ5
6ꢃ
3ꢅ
1
5
50
ꢃꢆ
ꢅꢃ
DN
DNR
ꢃ0
ꢃ0
16
ꢆ
ꢃ0
ꢅ0
ꢅꢃ
1ꢅ
ꢃꢆ
ꢅꢃ
ꢅ0
ꢅ0
Note:ꢀTheꢀsineꢀwaveꢀgeneratorꢀcircuitꢀconsistsꢀofꢀaꢀ10-bitꢀD/Aꢀconverterꢀandꢀaꢀsmoothingꢀfilterꢀ
whoseꢀfrequencyꢀatꢀ-3dBꢀisꢀequalꢀtoꢀ489kHz.ꢀWhenꢀtheꢀoutputꢀfrequencyꢀisꢀ500kHz,ꢀtheꢀ
outputꢀwaveꢀamplitudeꢀwillꢀdecreaseꢀandꢀthereforeꢀitꢀisꢀimpossibleꢀtoꢀachieveꢀaꢀfullꢀrangeꢀofꢀ
VOREG~0.
Rev. 1.10
173
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
511
0
Pꢅ
P1
PDNR-3 PDNR-1
PDNR-ꢅ
P0
-51ꢅ
ItꢀisꢀonlyꢀnecessaryꢀtoꢀgenerateꢀaꢀhalfꢀsineꢀwaveꢀpatternꢀP0~PDNR-1ꢀwhichꢀisꢀstoredꢀinꢀRAMꢀsectorꢀ
3ꢀ(00H~3FH).ꢀTheꢀsineꢀpatternꢀ[7:0]ꢀisꢀstoredꢀusingꢀevenꢀaddressesꢀandꢀtheꢀsineꢀpatternꢀ[8]ꢀisꢀstoredꢀ
usingꢀoddꢀaddresses.ꢀOnceꢀtheꢀsineꢀgeneratorꢀisꢀenabled,ꢀtheꢀCPUꢀcannotꢀwrites/readꢀanyꢀdataꢀto/
fromꢀthisꢀRAM.ꢀTheꢀsineꢀgeneratorꢀwillꢀthenꢀreadꢀthisꢀRAMꢀdataꢀandꢀtransmitꢀitꢀtoꢀanꢀ10-bitꢀD/Aꢀ
converter.
TheꢀcontrollerꢀreadsꢀaꢀhalfꢀsineꢀpatternꢀfromꢀRAMꢀandꢀgeneratesꢀaꢀsineꢀwaveformꢀonꢀtheꢀSINꢀpin.ꢀ
Referꢀtoꢀfollowingꢀfigure.
Rev. 1.10
17ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
DN_CNT>=DNR
“0”
“1”
0
1
D[9]
SINE[ꢆ:0]
0
D[ꢆ:0]
+
D[9:0]
DAC
ꢅ's
1
Complement
00H
01H
0ꢅH
SINE0[7:0]
SINE1[7:0]
SINE0[ꢆ]
SINE1[ꢆ]
03H
SINE0[ꢆ:0]
SINE1[ꢆ:0]
SINEꢅ[ꢆ:0]
SINE3[ꢆ:0]
3BH
3CH
3DH
3EH
3FH
SINE30[7:0]
SINE31[7:0]
SINE30[ꢆ:0]
SINE31[ꢆ:0]
SINE30[ꢆ]
SINE31[ꢆ]
SINE Wave Pattern
RAM (Sector 3)
Rev. 1.10
175
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Body Fat Measurement Registers
Thereꢀareꢀaꢀseriesꢀofꢀregistersꢀcontrolꢀtheꢀoverallꢀoperationꢀofꢀtheꢀbodyꢀfatꢀmeasurementꢀfunction.
Sine Wave Generator
Theꢀsineꢀwaveꢀgeneratorꢀisꢀcontrolledꢀbyꢀthreeꢀregisters.ꢀDetailsꢀareꢀgivenꢀasꢀbelow.
• SGC Register
Bit
Name
R/W
7
SGEN
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
BREN
R/W
0
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7
SGEN:ꢀSineꢀGeneratorꢀEnabled
0:ꢀDisable
1:ꢀEnable
Whenꢀthisꢀbitꢀisꢀequalꢀtoꢀ“0”,ꢀtheꢀOP0ꢀandꢀ10-bitꢀD/Aꢀconverterꢀwillꢀbeꢀinꢀaꢀpowerꢀ
downꢀmode.
Bitꢀ6~5
Bitꢀ4ꢀ
D6~D5:ꢀReservedꢀbits,ꢀmustꢀbeꢀfixedꢀasꢀ“00”.
BREN:ꢀBiasꢀResistorsꢀControlꢀbit
0:ꢀDisableꢀ–ꢀpowerꢀdownꢀmode
1:ꢀEnableꢀ–ꢀnormalꢀmode
Bitꢀ3~0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
• SGN Register
Bit
7
6
5
D5
R/W
0
4
Dꢃ
R/W
0
3
D3
R/W
0
2
Dꢅ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
Name
R/W
—
—
—
—
—
—
POR
Bitꢀ7~6ꢀꢀꢀꢀꢀꢀ Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ5~0 D5~D0:ꢀSineꢀGeneratorꢀData
Theꢀmultiplicatorꢀofꢀsystemꢀfrequencyꢀ(N)
Theꢀmultiplicatorꢀ(N)ꢀisꢀequalꢀtoꢀD[5:0]+1
• SGDNR Register
Bit
Name
R/W
7
6
5
4
Dꢃ
R/W
0
3
D3
R/W
0
2
Dꢅ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~5ꢀꢀꢀꢀꢀꢀ Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ4~0 D4~D0:ꢀDataꢀNumberꢀofꢀSample
1/2ꢀsineꢀwaveꢀcycleꢀnumericalꢀvalueꢀisꢀstoredꢀinꢀRAMꢀSectorꢀ3.ꢀDNRꢀisꢀequalꢀtoꢀ
D[4:0]+1.
Rev. 1.10
176
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Amplifier
Fiveꢀregistersꢀareꢀassociatedꢀwithꢀtheꢀamplifierꢀoperation.ꢀTheꢀOPACꢀregisterꢀforꢀcontrollingꢀtheꢀ
operationalꢀamplifier,ꢀtheꢀSWC0,ꢀSWC1ꢀandꢀSWC2ꢀregistersꢀforꢀconfiguringꢀtheꢀswitchꢀconditionꢀasꢀ
wellꢀasꢀtheꢀDACOꢀregisterꢀforꢀsettingꢀtheꢀ6-bitꢀD/Aꢀconverterꢀoutput.
• OPAC Register
Bit
Name
R/W
7
OPAEN
R/W
0
6
5
4
3
OPꢅG3
R/W
0
2
OPꢅGꢅ
R/W
0
1
OPꢅG1
R/W
0
0
OPꢅG0
R/W
0
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7ꢀ
OPAEN:ꢀOperationalꢀAmplifierꢀControlꢀ
0:ꢀDisable
1:ꢀEnable
Whenꢀthisꢀbitꢀisꢀequalꢀtoꢀ“0”,ꢀOP1,ꢀOP2ꢀandꢀ6-bitꢀD/Aꢀconverterꢀwillꢀbeꢀinꢀaꢀpowerꢀ
downꢀmode.
Bitꢀ6~4ꢀ
Bitꢀ3~0
Unimplemented,ꢀreadꢀasꢀ“0”
OP2G3~OP2G0:ꢀOP2ꢀGainꢀControlꢀ
0001:ꢀ1.14
0010:ꢀ1.31
0011:ꢀ1.50
0100:ꢀ1.73
0101:ꢀ2.00
0110:ꢀ2.33
0111:ꢀ2.75
1000:ꢀ3.285
1001:ꢀ4.00
1010:ꢀ5.00
others:ꢀ1.00
• SWC0 Register
Bit
Name
R/W
7
IHRꢅ
R/W
0
6
VHR1
R/W
0
5
4
VHLꢅ
R/W
0
3
2
VFR1
R/W
0
1
0
VFLꢅ
R/W
0
IHL1
R/W
0
IFRꢅ
R/W
0
IFL1
R/W
0
POR
Bitꢀ7
IHR2:ꢀSwitchꢀIHR2ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
Bitꢀ6
Bitꢀ5
Bitꢀ4
Bitꢀ3
Bitꢀ2
VHR1:ꢀSwitchꢀVHR1ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
IHL1:ꢀSwitchꢀIHL1ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
VHL2:ꢀSwitchꢀVHL2ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
IFR2:ꢀSwitchꢀIFR2ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
VFR1:ꢀSwitchꢀVFR1ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
Rev. 1.10
177
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ1
Bitꢀ0
IFL1:ꢀSwitchꢀIFL1ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
VFL2:ꢀSwitchꢀVFL2ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
• SWC1 Register
Bit
Name
R/W
7
6
VHL1
R/W
0
5
4
VRFN
R/W
0
3
VRFP1
R/W
0
2
1
VRFPꢅ
R/W
0
0
—
—
—
IHLꢅ
R/W
0
IRF1
R/W
0
IRFꢅ
R/W
0
POR
Bitꢀ7ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ6
Bitꢀ5
Bitꢀ4
Bitꢀ3
Bitꢀ2
Bitꢀ1
Bitꢀ0
VHL1:ꢀSwitchꢀVHL1ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
IHL2:ꢀSwitchꢀIHL1ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
VRFN:ꢀSwitchꢀVRFNꢀControlꢀBit
0:ꢀOff
1:ꢀOn
VRFP1:ꢀSwitchꢀVRFP1ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
IRF1:ꢀSwitchꢀIRF1ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
VRFP2:ꢀSwitchꢀVRFP2ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
IRF2:ꢀSwitchꢀIRF2ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
• SWC2 register
Bit
Name
R/W
7
6
VHRꢅ
R/W
0
5
IHR1
R/W
0
4
VFL1
R/W
0
3
VFRꢅ
R/W
0
2
1
0
—
—
—
IFLꢅ
R/W
0
IFR1
R/W
0
—
—
—
POR
Bitꢀ7ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ6
Bitꢀ5
Bitꢀ4
VHR2:ꢀswitchꢀVHR2ꢀcontrolꢀbit
0:ꢀOff
1:ꢀOn
IHR1:ꢀswitchꢀIHR1ꢀcontrolꢀbit
0:ꢀOff
1:ꢀOn
VFL1:ꢀswitchꢀVFL1ꢀcontrolꢀbit
0:ꢀOff
1:ꢀOn
Rev. 1.10
17ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ3
Bitꢀ2
Bitꢀ1
Bitꢀ0ꢀ
VFR2:ꢀswitchꢀVFR2ꢀcontrolꢀbit
0:ꢀOff
1:ꢀOn
IFL2:ꢀswitchꢀIFL2ꢀcontrolꢀbit
0:ꢀOff
1:ꢀOn
IFR1:ꢀswitchꢀIFR1ꢀcontrolꢀbit
0:ꢀOff
1:ꢀOn
Unimplemented,ꢀreadꢀasꢀ“0”
• DACO Register
Bit
Name
R/W
7
6
5
D5
R/W
0
4
Dꢃ
R/W
0
3
D3
R/W
0
2
Dꢅ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
—
—
—
—
—
—
POR
Bitꢀ7~6ꢀꢀ
Bitꢀ5~0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
D5~D0:ꢀ6-bitꢀD/AꢀConverterꢀOutputꢀVoltage=0.5VOREGꢀ×ꢀ((D[5:0]+1)/64)
Filter
TheꢀFTRCꢀregisterꢀcontrolsꢀtheꢀoperationꢀofꢀtheꢀfilterꢀpart.
• FTRC Register
Bit
Name
R/W
7
FTREN
R/W
0
6
5
4
HYSEN
R/W
0
3
2
1
SW19
R/W
0
0
SW1ꢆ
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7
FTREN:ꢀFilterꢀControlꢀBit
0:ꢀDisable
1:ꢀEnable
Whenꢀthisꢀbitꢀisꢀequalꢀtoꢀ“0”,ꢀCP0ꢀandꢀPMOSꢀwillꢀbeꢀinꢀaꢀpowerꢀdownꢀmode.
Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ6~5ꢀ
Bitꢀ4
HYSEN:ꢀCP0ꢀHysteresisꢀcontrolꢀbit
0:ꢀDisable
1:ꢀEnable
Bitꢀ3~2ꢀ
Bitꢀ1
Unimplemented,ꢀreadꢀasꢀ“0”
SW19:ꢀSwitchꢀ19ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
Bitꢀ0
SW18:ꢀSwitchꢀ18ꢀControlꢀBit
0:ꢀOff
1:ꢀOn
Rev. 1.10
179
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Interrupts
Interruptsꢀareꢀanꢀimportantꢀpartꢀofꢀanyꢀmicrocontrollerꢀsystem.ꢀWhenꢀanꢀexternalꢀeventꢀorꢀanꢀ
internalꢀfunctionꢀsuchꢀasꢀaꢀTimerꢀModuleꢀorꢀanꢀA/Dꢀconverterꢀrequiresꢀmicrocontrollerꢀattention,ꢀ
theirꢀcorrespondingꢀinterruptꢀwillꢀenforceꢀaꢀtemporaryꢀsuspensionꢀofꢀtheꢀmainꢀprogramꢀallowingꢀtheꢀ
microcontrollerꢀtoꢀdirectꢀattentionꢀtoꢀtheirꢀrespectiveꢀneeds.ꢀTheꢀdevicesꢀcontainꢀseveralꢀexternalꢀ
interruptꢀandꢀinternalꢀinterruptꢀfunctions.ꢀTheꢀexternalꢀinterruptsꢀareꢀgeneratedꢀbyꢀtheꢀactionꢀofꢀtheꢀ
externalꢀINT0~INT1ꢀpins,ꢀwhileꢀtheꢀinternalꢀinterruptsꢀareꢀgeneratedꢀbyꢀvariousꢀinternalꢀfunctionsꢀ
suchꢀasꢀtheꢀTimerꢀModulesꢀ(TMs),ꢀTimeꢀBases,ꢀSerialꢀInterfaceꢀModuleꢀ(SIM),ꢀSerialꢀPeripheralꢀ
Interfaceꢀ(SPIA),ꢀUART,ꢀLowꢀVoltageꢀDetectorꢀ(LVD),ꢀEEPROMꢀandꢀtheꢀA/Dꢀconverter.
Interrupt Registers
Overallꢀinterruptꢀcontrol,ꢀwhichꢀbasicallyꢀmeansꢀtheꢀsettingꢀofꢀrequestꢀflagsꢀwhenꢀcertainꢀ
microcontrollerꢀconditionsꢀoccurꢀandꢀtheꢀsettingꢀofꢀinterruptꢀenableꢀbitsꢀbyꢀtheꢀapplicationꢀprogram,ꢀ
isꢀcontrolledꢀbyꢀaꢀseriesꢀofꢀregisters,ꢀlocatedꢀinꢀtheꢀSpecialꢀPurposeꢀDataꢀMemory.ꢀTheꢀregistersꢀfallꢀ
intoꢀthreeꢀcategories.ꢀTheꢀfirstꢀisꢀtheꢀINTC0~INTC3ꢀregistersꢀwhichꢀsetupꢀtheꢀprimaryꢀinterrupts,ꢀ
theꢀsecondꢀisꢀtheꢀMFI0~MFI2ꢀregistersꢀwhichꢀsetupꢀtheꢀMulti-functionꢀinterrupts.ꢀFinallyꢀthereꢀisꢀanꢀ
INTEGꢀregisterꢀtoꢀsetupꢀtheꢀexternalꢀinterruptsꢀtriggerꢀedgeꢀtype.
Eachꢀregisterꢀcontainsꢀaꢀnumberꢀofꢀenableꢀbitsꢀtoꢀenableꢀorꢀdisableꢀindividualꢀregistersꢀasꢀwellꢀasꢀ
interruptꢀflagsꢀtoꢀindicateꢀtheꢀpresenceꢀofꢀanꢀinterruptꢀrequest.ꢀTheꢀnamingꢀconventionꢀofꢀtheseꢀ
followsꢀaꢀspecificꢀpattern.ꢀFirstꢀisꢀlistedꢀanꢀabbreviatedꢀinterruptꢀtype,ꢀthenꢀtheꢀ(optional)ꢀnumberꢀofꢀ
thatꢀinterruptꢀfollowedꢀbyꢀeitherꢀanꢀ“E”ꢀforꢀenable/disableꢀbitꢀorꢀ“F”ꢀforꢀrequestꢀflag.
Function
Global
Enable Bit
EMI
Request Flag
—
Notes
—
INTn Pin
A/D Conveꢁteꢁ
Mꢀlti-fꢀnction
Time Base
LVD
INTnE
ADE
INTnF
ADF
n=0~1
—
MFnE
TBnE
MFnF
TBnF
n=0~ꢅ
n=0~1
—
LVE
LVF
EEPROM
UART
DEE
DEF
—
URE
URF
—
SIM
SIME
SIMF
—
SPIA
SPIAE
STMPE
STMAE
PTMnPE
PTMnAE
SPIAF
STMPF
STMAF
PTMnPF
PTMnAF
—
STM
PTM
—
n=0~ꢅ
Interrupt Register Bit Naming Conventions
Bit
Register
Name
7
—
6
—
5
4
3
INT1S1
ADE
—
2
1
0
INTEG
INTC0
INTC1
INTCꢅ
INTC3
MFI0
—
—
INT1S0
INT1E
MFꢅE
URE
INT0S1
INT0E
MF1E
TB1E
—
INT0S0
EMI
—
ADF
MFꢅF
URF
—
INT1F
MF1F
TB1F
—
INT0F
MF0F
TB0F
SPIAF
—
MF0E
TB0E
SPIAE
STMPE
SIMF
—
SIME
—
—
PTM0AF PTM0PF STMAF
STMPF PTM0AE PTM0PE STMAE
MFI1
PTMꢅAF PTMꢅPF PTM1AF PTM1PF PTMꢅAE PTMꢅPE PTM1AE PTM1PE
DEF LVF DEE LVE
MFIꢅ
—
—
—
—
Interrupt Register List
Rev. 1.10
1ꢆ0
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
INTEG Register
Bit
Name
R/W
7
6
5
4
3
INT1S1
R/W
0
2
INT1S0
R/W
0
1
INT0S1
R/W
0
0
INT0S0
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~4ꢀ
Bitꢀ3~2
Unimplemented,ꢀreadꢀasꢀ“0”
INT1S1~INT1S0:ꢀInterruptꢀEdgeꢀControlꢀforꢀINT1ꢀPin
00:ꢀDisable
01:ꢀRisingꢀedge
10:ꢀFallingꢀedge
11:ꢀRisingꢀandꢀfallingꢀedges
Bitꢀ1~0
INT0S1~INT0S0:ꢀInterruptꢀEdgeꢀControlꢀforꢀINT0ꢀPin
00:ꢀDisable
01:ꢀRisingꢀedge
10:ꢀFallingꢀedge
11:ꢀRisingꢀandꢀfallingꢀedges
INTC0 Register
Bit
Name
R/W
7
6
5
INT1F
R/W
0
4
INT0F
R/W
0
3
2
INT1E
R/W
0
1
INT0E
R/W
0
0
—
—
—
ADF
R/W
0
ADE
R/W
0
EMI
R/W
0
POR
Bitꢀ7ꢀ
Bitꢀ6
Unimplemented,ꢀreadꢀasꢀ“0”
ADF:ꢀA/DꢀConverterꢀInterruptꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ5
Bitꢀ4
Bitꢀ3
Bitꢀ2
Bitꢀ1
Bitꢀ0
INT1F:ꢀExternalꢀInterruptꢀ1RequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
INT0F:ꢀExternalꢀInterruptꢀ0ꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
ADE:ꢀA/DꢀConverterꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
INT1E:ꢀExternalꢀInterruptꢀ1ꢀControl
0:ꢀDisable
1:ꢀEnable
INT0E:ꢀExternalꢀInterruptꢀ0ꢀControl
0:ꢀDisable
1:ꢀEnable
EMI:ꢀGlobalꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
Rev. 1.10
1ꢆ1
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
INTC1 Register
Bit
Name
R/W
7
6
MFꢅF
R/W
0
5
MF1F
R/W
0
4
MF0F
R/W
0
3
2
MFꢅE
R/W
0
1
MF1E
R/W
0
0
MF0E
R/W
0
—
—
—
—
—
—
POR
Bitꢀ7ꢀ
Bitꢀ6
Unimplemented,ꢀreadꢀasꢀ“0”
MF2F:ꢀMulti-functionꢀInterruptꢀ2ꢀRequestꢀFlagꢀ
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ5
Bitꢀ4
MF1F:ꢀMulti-functionꢀInterruptꢀ1ꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
MF0F:ꢀMulti-functionꢀInterruptꢀ0ꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ3ꢀ
Bitꢀ2
Unimplemented,ꢀreadꢀasꢀ“0”
MF2E:ꢀMulti-functionꢀInterruptꢀ2ꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ1
Bitꢀ0
MF1E:ꢀMulti-functionꢀInterruptꢀ1ꢀControl
0:ꢀDisable
1:ꢀEnable
MF0E:ꢀMulti-functionꢀInterruptꢀ0ꢀControl
0:ꢀDisable
1:ꢀEnable
INTC2 Register
Bit
Name
R/W
7
SIMF
R/W
0
6
5
TB1F
R/W
0
4
TB0F
R/W
0
3
SIME
R/W
0
2
1
TB1E
R/W
0
0
TB0E
R/W
0
URF
R/W
0
URE
R/W
0
POR
Bitꢀ7
Bitꢀ6
Bitꢀ5
Bitꢀ4
Bitꢀ3
Bitꢀ2
SIMF:ꢀSerialꢀInterfaceꢀModuleꢀInterruptꢀRequestꢀFlagꢀ
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
URF:ꢀUARTꢀInterruptꢀRequestꢀFlagꢀ
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
TB1F:ꢀTimeꢀBaseꢀ1ꢀInterruptꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
TB0F:ꢀTimeꢀBaseꢀ0ꢀInterruptꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
SIME:ꢀSerialꢀInterfaceꢀModuleꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
URE:ꢀSerialꢀInterfaceꢀModuleꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
Rev. 1.10
1ꢆꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Bitꢀ1
Bitꢀ0
TB1E:ꢀTimeꢀBaseꢀ1ꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
TB0E:ꢀTimeꢀBaseꢀ0ꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
INTC3 Register
Bit
Name
R/W
7
6
5
4
SPIAF
R/W
0
3
2
1
0
SPIAE
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~5ꢀ
Bitꢀ4
Unimplemented,ꢀreadꢀasꢀ“0”
SPIAF:ꢀSPIAꢀInterruptꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ3~1ꢀ
Bitꢀ0
Unimplemented,ꢀreadꢀasꢀ“0”
SPIAE:ꢀSPIAꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
MFI0 Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
PTM0AF PTM0PF STMAF
STMPF PTM0AE PTM0PE STMAE STMPE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7
Bitꢀ6
Bitꢀ5
Bitꢀ4
Bitꢀ3
Bitꢀ2
Bitꢀ1
Bitꢀ0
PTM0AF:ꢀPTM0ꢀCCRAꢀComparatorꢀInterruptꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
PTM0PF:ꢀPTM0ꢀCCRPꢀComparatorꢀInterruptꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
STMAF:ꢀSTMꢀCCRAꢀComparatorꢀInterruptꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
STMPF:ꢀSTMꢀCCRPꢀComparatorꢀInterruptꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
PTM0AE:ꢀPTM0ꢀCCRAꢀComparatorꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
PTM0PE:ꢀPTM0ꢀCCRPꢀComparatorꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
STMAE:ꢀSTMꢀCCRAꢀComparatorꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
STMPE:ꢀSTMꢀCCRPꢀComparatorꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
Rev. 1.10
1ꢆ3
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
MFI1 Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
PTMꢅAF PTMꢅPF PTM1AF PTM1PF PTMꢅAE PTMꢅPE PTM1AE PTM1PE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7ꢀ
Bitꢀ6
Bitꢀ5
Bitꢀ4
Bitꢀ3
Bitꢀ2
Bitꢀ1
Bitꢀ0
PTM2AF:ꢀPTM2ꢀCCRAꢀComparatorꢀInterruptꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
PTM2PF:ꢀPTM2ꢀCCRPꢀComparatorꢀInterruptꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
PTM1AF:ꢀPTM1ꢀCCRAꢀComparatorꢀInterruptꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
PTM1PF:ꢀPTM1ꢀCCRPꢀComparatorꢀInterruptꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
PTM2AE:ꢀPTM2ꢀCCRAꢀComparatorꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
PTM2PE:ꢀPTM2ꢀCCRPꢀComparatorꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
PTM1AE:ꢀPTM1ꢀCCRAꢀComparatorꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
PTM1PE:ꢀPTM1ꢀCCRPꢀComparatorꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
MFI2 Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
—
—
—
—
—
—
DEF
R/W
0
LVF
R/W
0
—
—
—
—
—
—
DEE
R/W
0
LVE
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5
Unimplemented,ꢀreadꢀasꢀ“0”
DEF:ꢀDataꢀEEPROMꢀInterruptꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ4
LVF:ꢀLVDꢀInterruptꢀRequestꢀFlag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ3~2ꢀ
Bitꢀ1
Unimplemented,ꢀreadꢀasꢀ“0”
DEE:ꢀDataꢀEEPROMꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ0
LVE:ꢀLVDꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
Rev. 1.10
1ꢆꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Interrupt Operation
Whenꢀtheꢀconditionsꢀforꢀanꢀinterruptꢀeventꢀoccur,ꢀsuchꢀasꢀaꢀTMꢀComparatorꢀP,ꢀComparatorꢀAꢀ
matchꢀorꢀA/Dꢀconversionꢀcompletionꢀetc.,ꢀtheꢀrelevantꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀset.ꢀWhetherꢀ
theꢀrequestꢀflagꢀactuallyꢀgeneratesꢀaꢀprogramꢀjumpꢀtoꢀtheꢀrelevantꢀinterruptꢀvectorꢀisꢀdeterminedꢀbyꢀ
theꢀconditionꢀofꢀtheꢀinterruptꢀenableꢀbit.ꢀIfꢀtheꢀenableꢀbitꢀisꢀsetꢀhighꢀthenꢀtheꢀprogramꢀwillꢀjumpꢀtoꢀ
itsꢀrelevantꢀvector;ꢀifꢀtheꢀenableꢀbitꢀisꢀ“0”ꢀthenꢀalthoughꢀtheꢀinterruptꢀrequestꢀflagꢀisꢀsetꢀanꢀactualꢀ
interruptꢀwillꢀnotꢀbeꢀgeneratedꢀandꢀtheꢀprogramꢀwillꢀnotꢀjumpꢀtoꢀtheꢀrelevantꢀinterruptꢀvector.ꢀTheꢀ
globalꢀinterruptꢀenableꢀbit,ꢀifꢀclearedꢀtoꢀzero,ꢀwillꢀdisableꢀallꢀinterrupts.ꢀ
Whenꢀanꢀinterruptꢀisꢀgenerated,ꢀtheꢀProgramꢀCounter,ꢀwhichꢀstoresꢀtheꢀaddressꢀofꢀtheꢀnextꢀinstructionꢀ
toꢀbeꢀexecuted,ꢀwillꢀbeꢀtransferredꢀontoꢀtheꢀstack.ꢀTheꢀProgramꢀCounterꢀwillꢀthenꢀbeꢀloadedꢀwithꢀaꢀ
newꢀaddressꢀwhichꢀwillꢀbeꢀtheꢀvalueꢀofꢀtheꢀcorrespondingꢀinterruptꢀvector.ꢀTheꢀmicrocontrollerꢀwillꢀ
thenꢀfetchꢀitsꢀnextꢀinstructionꢀfromꢀthisꢀinterruptꢀvector.ꢀTheꢀinstructionꢀatꢀthisꢀvectorꢀwillꢀusuallyꢀ
beꢀaꢀ“JMP”ꢀwhichꢀwillꢀjumpꢀtoꢀanotherꢀsectionꢀofꢀprogramꢀwhichꢀisꢀknownꢀasꢀtheꢀinterruptꢀserviceꢀ
routine.ꢀHereꢀisꢀlocatedꢀtheꢀcodeꢀtoꢀcontrolꢀtheꢀappropriateꢀinterrupt.ꢀTheꢀinterruptꢀserviceꢀroutineꢀ
mustꢀbeꢀterminatedꢀwithꢀaꢀ“RETI”,ꢀwhichꢀretrievesꢀtheꢀoriginalꢀProgramꢀCounterꢀaddressꢀfromꢀ
theꢀstackꢀandꢀallowsꢀtheꢀmicrocontrollerꢀtoꢀcontinueꢀwithꢀnormalꢀexecutionꢀatꢀtheꢀpointꢀwhereꢀtheꢀ
interruptꢀoccurred.ꢀ
Theꢀvariousꢀinterruptꢀenableꢀbits,ꢀtogetherꢀwithꢀtheirꢀassociatedꢀrequestꢀflags,ꢀareꢀshownꢀinꢀtheꢀ
accompanyingꢀdiagramsꢀwithꢀtheirꢀorderꢀofꢀpriority.ꢀSomeꢀinterruptꢀsourcesꢀhaveꢀtheirꢀownꢀ
individualꢀvectorꢀwhileꢀothersꢀshareꢀtheꢀsameꢀmulti-functionꢀinterruptꢀvector.ꢀOnceꢀanꢀinterruptꢀ
subroutineꢀisꢀserviced,ꢀallꢀtheꢀotherꢀinterruptsꢀwillꢀbeꢀblocked,ꢀasꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀ
EMIꢀbitꢀwillꢀbeꢀclearedꢀautomatically.ꢀThisꢀwillꢀpreventꢀanyꢀfurtherꢀinterruptꢀnestingꢀfromꢀoccurring.ꢀ
However,ꢀifꢀotherꢀinterruptꢀrequestsꢀoccurꢀduringꢀthisꢀinterval,ꢀalthoughꢀtheꢀinterruptꢀwillꢀnotꢀbeꢀ
immediatelyꢀserviced,ꢀtheꢀrequestꢀflagꢀwillꢀstillꢀbeꢀrecorded.ꢀ
Ifꢀanꢀinterruptꢀrequiresꢀimmediateꢀservicingꢀwhileꢀtheꢀprogramꢀisꢀalreadyꢀinꢀanotherꢀinterruptꢀserviceꢀ
routine,ꢀtheꢀEMIꢀbitꢀshouldꢀbeꢀsetꢀafterꢀenteringꢀtheꢀroutine,ꢀtoꢀallowꢀinterruptꢀnesting.ꢀIfꢀtheꢀstackꢀ
isꢀfull,ꢀtheꢀinterruptꢀrequestꢀwillꢀnotꢀbeꢀacknowledged,ꢀevenꢀifꢀtheꢀrelatedꢀinterruptꢀisꢀenabled,ꢀuntilꢀ
theꢀStackꢀPointerꢀisꢀdecremented.ꢀIfꢀimmediateꢀserviceꢀisꢀdesired,ꢀtheꢀstackꢀmustꢀbeꢀpreventedꢀfromꢀ
becomingꢀfull.ꢀInꢀcaseꢀofꢀsimultaneousꢀrequests,ꢀtheꢀaccompanyingꢀdiagramꢀshowsꢀtheꢀpriorityꢀthatꢀ
isꢀapplied.ꢀAllꢀofꢀtheꢀinterruptꢀrequestꢀflagsꢀwhenꢀsetꢀwillꢀwake-upꢀtheꢀdeviceꢀifꢀitꢀisꢀinꢀSLEEPꢀorꢀ
IDLEꢀMode,ꢀhoweverꢀtoꢀpreventꢀaꢀwake-upꢀfromꢀoccurringꢀtheꢀcorrespondingꢀflagꢀshouldꢀbeꢀsetꢀ
beforeꢀtheꢀdeviceꢀisꢀinꢀSLEEPꢀorꢀIDLEꢀMode.
Rev. 1.10
1ꢆ5
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
EMI aꢀto disabled in ISR
Legend
xxF Reqꢀest Flagꢄ no aꢀto ꢁeset in ISR
Inteꢁꢁꢀpt
Name
Reqꢀest
Flags
Enable
Bits
Masteꢁ
Enable
Vectoꢁ
0ꢃH
Pꢁioꢁitꢂ
High
xxF Reqꢀest Flagꢄ aꢀto ꢁeset in ISR
xxE Enable Bits
INT0 Pin
INT1 Pin
INT0F
INT1F
ADF
INT0E
INT1E
ADE
EMI
EMI
EMI
EMI
Inteꢁꢁꢀpt
Name
Reqꢀest
Flags
Enable
Bits
0ꢆH
0CH
10H
STM P
STM A
STMPF
STMAF
STMPE
STMAE
A/D Conveꢁteꢁ
M. Fꢀnct. 0
MF0F
MF0E
PTM0 P
PTM0 A
PTM0PF
PTM0AF
PTM0PE
PTM0AE
1ꢃH
1ꢆH
ꢅ0H
ꢅꢃH
ꢅꢆH
ꢅCH
30H
EMI
EMI
EMI
EMI
EMI
EMI
EMI
M. Fꢀnct. 1
M. Fꢀnct. ꢅ
Time Base 0
Time Base 1
UART
MF1F
MFꢅF
TB0F
TB1F
URF
MF1E
MFꢅE
TB0E
TB1E
URE
PTM1 P
PTM1 A
PTMꢅ P
PTMꢅ A
PTM1PF
PTM1AF
PTMꢅPF
PTMꢅAF
PTM1PE
PTM1AE
PTMꢅPE
PTMꢅAE
LVD
LVF
LVE
DEF
EEPROM
DEE
Inteꢁꢁꢀpts contained within
Mꢀlti-Fꢀnction Inteꢁꢁꢀpts
SIM
SIMF
SPIAF
SIME
SPIAE
SPIA
Low
Interrupt Structure
External Interrupt
TheꢀexternalꢀinterruptsꢀareꢀcontrolledꢀbyꢀsignalꢀtransitionsꢀonꢀtheꢀpinsꢀINT0~INT1.ꢀAnꢀexternalꢀ
interruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀexternalꢀinterruptꢀrequestꢀflags,ꢀINT0F~INT1F,ꢀareꢀset,ꢀ
whichꢀwillꢀoccurꢀwhenꢀaꢀtransition,ꢀwhoseꢀtypeꢀisꢀchosenꢀbyꢀtheꢀedgeꢀselectꢀbits,ꢀappearsꢀonꢀtheꢀ
externalꢀinterruptꢀpins.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀ
theꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀandꢀrespectiveꢀexternalꢀinterruptꢀenableꢀbit,ꢀINT0E~INT1E,ꢀ
mustꢀfirstꢀbeꢀset.ꢀAdditionallyꢀtheꢀcorrectꢀinterruptꢀedgeꢀtypeꢀmustꢀbeꢀselectedꢀusingꢀtheꢀINTEGꢀ
registerꢀtoꢀenableꢀtheꢀexternalꢀinterruptꢀfunctionꢀandꢀtoꢀchooseꢀtheꢀtriggerꢀedgeꢀtype.ꢀAsꢀtheꢀexternalꢀ
interruptꢀpinsꢀareꢀpin-sharedꢀwithꢀI/Oꢀpins,ꢀtheyꢀcanꢀonlyꢀbeꢀconfiguredꢀasꢀexternalꢀinterruptꢀpinsꢀifꢀ
theirꢀexternalꢀinterruptꢀenableꢀbitꢀinꢀtheꢀcorrespondingꢀinterruptꢀregisterꢀhasꢀbeenꢀsetꢀandꢀtheꢀexternalꢀ
interruptꢀpinꢀisꢀselectedꢀbyꢀtheꢀcorrespondingꢀpin-sharedꢀfunctionꢀselectionꢀbits.ꢀTheꢀpinꢀmustꢀalsoꢀ
beꢀsetupꢀasꢀanꢀinputꢀbyꢀsettingꢀtheꢀcorrespondingꢀbitꢀinꢀtheꢀportꢀcontrolꢀregister.ꢀ
Whenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀtheꢀcorrectꢀtransitionꢀtypeꢀappearsꢀonꢀtheꢀ
externalꢀinterruptꢀpin,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀexternalꢀinterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀ
interruptꢀisꢀserviced,ꢀtheꢀexternalꢀinterruptꢀrequestꢀflags,ꢀINT0F~INT1F,ꢀwillꢀbeꢀautomaticallyꢀ
resetꢀandꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts.ꢀNoteꢀthatꢀanyꢀpull-
highꢀresistorꢀselectionsꢀonꢀtheꢀexternalꢀinterruptꢀpinsꢀwillꢀremainꢀvalidꢀevenꢀifꢀtheꢀpinꢀisꢀusedꢀasꢀanꢀ
externalꢀinterruptꢀinput.ꢀTheꢀINTEGꢀregisterꢀisꢀusedꢀtoꢀselectꢀtheꢀtypeꢀofꢀactiveꢀedgeꢀthatꢀwillꢀtriggerꢀ
theꢀexternalꢀinterrupt.ꢀAꢀchoiceꢀofꢀeitherꢀrisingꢀorꢀfallingꢀorꢀbothꢀedgeꢀtypesꢀcanꢀbeꢀchosenꢀtoꢀtriggerꢀ
anꢀexternalꢀinterrupt.ꢀNoteꢀthatꢀtheꢀINTEGꢀregisterꢀcanꢀalsoꢀbeꢀusedꢀtoꢀdisableꢀtheꢀexternalꢀinterruptꢀ
function.
Rev. 1.10
1ꢆ6
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
LVD Interrupt
TheꢀLowꢀVoltageꢀDetectorꢀInterruptꢀisꢀcontainedꢀwithinꢀtheꢀMulti-functionꢀInterrupt.ꢀAnꢀLVDꢀ
InterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀLVDꢀInterruptꢀrequestꢀflag,ꢀLVF,ꢀisꢀset,ꢀwhichꢀoccursꢀ
whenꢀtheꢀLowꢀVoltageꢀDetectorꢀfunctionꢀdetectsꢀaꢀlowꢀpowerꢀsupplyꢀvoltage.ꢀToꢀallowꢀtheꢀprogramꢀ
toꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀLowꢀVoltageꢀ
Interruptꢀenableꢀbit,ꢀLVE,ꢀandꢀassociatedꢀMulti-functionꢀinterruptꢀenableꢀbit,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀ
theꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀaꢀlowꢀvoltageꢀconditionꢀoccurs,ꢀaꢀsubroutineꢀcallꢀtoꢀ
theꢀMulti-functionꢀInterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀLowꢀVoltageꢀInterruptꢀisꢀserviced,ꢀtheꢀ
EMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts,ꢀhoweverꢀonlyꢀtheꢀMulti-functionꢀ
interruptꢀrequestꢀflagꢀwillꢀbeꢀalsoꢀautomaticallyꢀcleared.ꢀAsꢀtheꢀLVFꢀflagꢀwillꢀnotꢀbeꢀautomaticallyꢀ
cleared,ꢀitꢀhasꢀtoꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.
EEPROM Interrupt
TheꢀEEPROMꢀInterruptꢀisꢀcontainedꢀwithinꢀtheꢀMulti-functionꢀInterrupt.ꢀAnꢀEEPROMꢀInterruptꢀ
requestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀEEPROMꢀInterruptꢀrequestꢀflag,ꢀDEF,ꢀisꢀset,ꢀwhichꢀoccursꢀ
whenꢀanꢀEEPROMꢀWriteꢀcycleꢀends.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀ
vectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀandꢀEEPROMꢀInterruptꢀenableꢀbit,ꢀDEE,ꢀandꢀ
associatedꢀMulti-functionꢀinterruptꢀenableꢀbit,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀ
stackꢀisꢀnotꢀfullꢀandꢀanꢀEEPROMꢀWriteꢀcycleꢀends,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀrespectiveꢀEEPROMꢀ
Interruptꢀvectorꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀEEPROMꢀInterruptꢀisꢀserviced,ꢀtheꢀEMIꢀbitꢀwillꢀbeꢀ
automaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts,ꢀhoweverꢀonlyꢀtheꢀMulti-functionꢀinterruptꢀrequestꢀ
flagꢀwillꢀbeꢀalsoꢀautomaticallyꢀcleared.ꢀAsꢀtheꢀDEFꢀflagꢀwillꢀnotꢀbeꢀautomaticallyꢀcleared,ꢀitꢀhasꢀtoꢀbeꢀ
clearedꢀbyꢀtheꢀapplicationꢀprogram.
A/D Converter Interrupt
TheꢀA/DꢀConverterꢀInterruptꢀisꢀcontrolledꢀbyꢀtheꢀterminationꢀofꢀanꢀA/Dꢀconversionꢀprocess.ꢀAnꢀ
A/DꢀConverterꢀInterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀA/DꢀConverterꢀInterruptꢀrequestꢀflag,ꢀADF,ꢀ
isꢀset,ꢀwhichꢀoccursꢀwhenꢀtheꢀA/Dꢀconversionꢀprocessꢀfinishes.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀ
respectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀandꢀA/DꢀInterruptꢀenableꢀbit,ꢀ
ADE,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀtheꢀA/Dꢀconversionꢀ
processꢀhasꢀended,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀA/DꢀConverterꢀInterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀ
interruptꢀisꢀserviced,ꢀtheꢀA/DꢀConverterꢀInterruptꢀflag,ꢀADF,ꢀwillꢀbeꢀautomaticallyꢀcleared.ꢀTheꢀEMIꢀ
bitꢀwillꢀalsoꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts.
Multi-function Interrupts
WithinꢀtheseꢀdevicesꢀthereꢀareꢀthreeꢀMulti-functionꢀinterrupts.ꢀUnlikeꢀtheꢀotherꢀindependentꢀ
interrupts,ꢀtheseꢀinterruptsꢀhaveꢀnoꢀindependentꢀsource,ꢀbutꢀratherꢀareꢀformedꢀfromꢀotherꢀexistingꢀ
interruptꢀsources,ꢀnamelyꢀtheꢀTMꢀInterrupts,ꢀEEPROMꢀinterruptꢀandꢀLVDꢀinterrupt.ꢀ
AꢀMulti-functionꢀinterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀanyꢀofꢀtheꢀMulti-functionꢀinterruptꢀrequestꢀ
flags,ꢀMFnFꢀareꢀset.ꢀTheꢀMulti-functionꢀinterruptꢀflagsꢀwillꢀbeꢀsetꢀwhenꢀanyꢀofꢀtheirꢀincludedꢀfunctionsꢀ
generateꢀanꢀinterruptꢀrequestꢀflag.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀ
address,ꢀwhenꢀtheꢀMulti-functionꢀinterruptꢀisꢀenabledꢀandꢀtheꢀstackꢀisꢀnotꢀfull,ꢀandꢀeitherꢀoneꢀofꢀtheꢀ
interruptsꢀcontainedꢀwithinꢀeachꢀofꢀMulti-functionꢀinterruptꢀoccurs,ꢀaꢀsubroutineꢀcallꢀtoꢀoneꢀofꢀtheꢀ
Multi-functionꢀinterruptꢀvectorsꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀrelatedꢀMulti-
FunctionꢀrequestꢀflagꢀwillꢀbeꢀautomaticallyꢀresetꢀandꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀ
disableꢀotherꢀinterrupts.
However,ꢀitꢀmustꢀbeꢀnotedꢀthat,ꢀalthoughꢀtheꢀMulti-functionꢀInterruptꢀflagsꢀwillꢀbeꢀautomaticallyꢀ
resetꢀwhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀrequestꢀflagsꢀfromꢀtheꢀoriginalꢀsourceꢀofꢀtheꢀMulti-functionꢀ
interruptsꢀwillꢀnotꢀbeꢀautomaticallyꢀresetꢀandꢀmustꢀbeꢀmanuallyꢀresetꢀbyꢀtheꢀapplicationꢀprogram.
Rev. 1.10
1ꢆ7
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Serial Interface Module Interrupt
TheꢀSerialꢀInterfaceꢀModuleꢀInterruptꢀisꢀalsoꢀknownꢀasꢀtheꢀSIMꢀInterrupt.ꢀAꢀSIMꢀInterruptꢀrequestꢀ
willꢀtakeꢀplaceꢀwhenꢀtheꢀSIMꢀInterruptꢀrequestꢀflag,ꢀSIMF,ꢀisꢀset,ꢀwhichꢀoccursꢀwhenꢀaꢀbyteꢀofꢀ
dataꢀhasꢀbeenꢀreceivedꢀorꢀtransmittedꢀbyꢀtheꢀSIMꢀinterface,ꢀanꢀI2CꢀaddressꢀmatchꢀorꢀI2Cꢀtime-outꢀ
occurrence.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀ
interruptꢀenableꢀbit,ꢀEMI,ꢀandꢀtheꢀSerialꢀInterfaceꢀInterruptꢀenableꢀbit,ꢀSIME,ꢀmustꢀfirstꢀbeꢀset.ꢀ
Whenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀanyꢀofꢀtheꢀaboveꢀdescribedꢀsituationsꢀoccurs,ꢀ
aꢀsubroutineꢀcallꢀtoꢀtheꢀSIMꢀinterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀSIMꢀInterfaceꢀInterruptꢀisꢀ
serviced,ꢀtheꢀinterruptꢀrequestꢀflag,ꢀSIMF,ꢀwillꢀbeꢀautomaticallyꢀresetꢀandꢀtheꢀEMIꢀbitꢀwillꢀbeꢀclearedꢀ
toꢀdisableꢀotherꢀinterrupts.
SPIA Interrupt
TheꢀSerialꢀPeripheralꢀInterfaceꢀInterrupt,ꢀalsoꢀknownꢀasꢀtheꢀSPIAꢀInterrupt,ꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀ
SPIAꢀInterruptꢀrequestꢀflag,ꢀSPIAF,ꢀisꢀset,ꢀwhichꢀoccursꢀwhenꢀaꢀbyteꢀofꢀdataꢀhasꢀbeenꢀreceivedꢀorꢀ
transmittedꢀbyꢀtheꢀSPIAꢀinterface.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀ
address,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀandꢀtheꢀSerialꢀInterfaceꢀInterruptꢀenableꢀbit,ꢀSPIAE,ꢀ
mustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀaꢀbyteꢀofꢀdataꢀhasꢀbeenꢀ
transmittedꢀorꢀreceivedꢀbyꢀtheꢀSPIAꢀinterface,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀrespectiveꢀInterruptꢀvector,ꢀ
willꢀtakeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀSerialꢀInterfaceꢀInterruptꢀflag,ꢀSPIAF,ꢀwillꢀbeꢀ
automaticallyꢀcleared.ꢀTheꢀEMIꢀbitꢀwillꢀalsoꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts.
UART Interrupt
SeveralꢀindividualꢀUARTꢀconditionsꢀcanꢀgenerateꢀaꢀUARTꢀInterrupt.ꢀWhenꢀtheseꢀconditionsꢀexist,ꢀ
aꢀlowꢀpulseꢀwillꢀbeꢀgeneratedꢀtoꢀgetꢀtheꢀattentionꢀofꢀtheꢀmicrocontroller.ꢀTheseꢀconditionsꢀareꢀaꢀ
transmitterꢀdataꢀregisterꢀempty,ꢀtransmitterꢀidle,ꢀreceiverꢀdataꢀavailable,ꢀreceiverꢀoverrun,ꢀaddressꢀ
detectꢀandꢀanꢀRXꢀpinꢀwake-up.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀtheꢀrespectiveꢀinterruptꢀvectorꢀ
addresses,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀandꢀUARTꢀInterruptꢀenableꢀbit,ꢀURE,ꢀmustꢀfirstꢀ
beꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀanyꢀofꢀtheseꢀconditionsꢀareꢀcreated,ꢀ
aꢀsubroutineꢀcallꢀtoꢀtheꢀUARTꢀInterruptꢀvectorꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀ
UARTꢀInterruptꢀflag,ꢀURF,ꢀwillꢀbeꢀautomaticallyꢀcleared.ꢀTheꢀEMIꢀbitꢀwillꢀalsoꢀbeꢀautomaticallyꢀ
clearedꢀtoꢀdisableꢀotherꢀinterrupts.ꢀHowever,ꢀtheꢀUSRꢀregisterꢀflagsꢀwillꢀbeꢀclearedꢀautomaticallyꢀ
whenꢀcertainꢀactionsꢀareꢀtakenꢀbyꢀtheꢀUART,ꢀtheꢀdetailsꢀofꢀwhichꢀareꢀgivenꢀinꢀtheꢀUARTꢀsection.
Time Base Interrupts
TheꢀfunctionꢀofꢀtheꢀTimeꢀBaseꢀInterruptsꢀisꢀtoꢀprovideꢀregularꢀtimeꢀsignalꢀinꢀtheꢀformꢀofꢀanꢀinternalꢀ
interrupt.ꢀTheyꢀareꢀcontrolledꢀbyꢀtheꢀoverflowꢀsignalsꢀfromꢀtheirꢀrespectiveꢀtimerꢀfunctions.ꢀWhenꢀ
theseꢀhappensꢀtheirꢀrespectiveꢀinterruptꢀrequestꢀflags,ꢀTB0FꢀorꢀTB1Fꢀwillꢀbeꢀset.ꢀToꢀallowꢀtheꢀ
programꢀtoꢀbranchꢀtoꢀtheirꢀrespectiveꢀinterruptꢀvectorꢀaddresses,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMIꢀ
andꢀTimeꢀBaseꢀenableꢀbits,ꢀTB0EꢀorꢀTB1E,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀ
isꢀnotꢀfullꢀandꢀtheꢀTimeꢀBaseꢀoverflows,ꢀaꢀsubroutineꢀcallꢀtoꢀtheirꢀrespectiveꢀvectorꢀlocationsꢀwillꢀ
takeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀrespectiveꢀinterruptꢀrequestꢀflag,ꢀTB0FꢀorꢀTB1F,ꢀwillꢀ
beꢀautomaticallyꢀresetꢀandꢀtheꢀEMIꢀbitꢀwillꢀbeꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts.ꢀ
TheꢀpurposeꢀofꢀtheꢀTimeꢀBaseꢀInterruptꢀisꢀtoꢀprovideꢀanꢀinterruptꢀsignalꢀatꢀfixedꢀtimeꢀperiods.ꢀItsꢀ
clockꢀsource,ꢀfPSC,ꢀoriginatesꢀfromꢀtheꢀinternalꢀclockꢀsourceꢀfSYS,ꢀfSYS/4ꢀorꢀfSUBꢀandꢀthenꢀpassesꢀ
throughꢀaꢀdivider,ꢀtheꢀdivisionꢀratioꢀofꢀwhichꢀisꢀselectedꢀbyꢀprogrammingꢀtheꢀappropriateꢀbitsꢀinꢀtheꢀ
TB0CꢀandꢀTB1Cꢀregistersꢀtoꢀobtainꢀlongerꢀinterruptꢀperiodsꢀwhoseꢀvalueꢀranges.ꢀTheꢀclockꢀsourceꢀ
whichꢀinꢀturnꢀcontrolsꢀtheꢀTimeꢀBaseꢀinterruptꢀperiodꢀisꢀselectedꢀusingꢀtheꢀCLKSEL1~CLKSEL0ꢀ
bitsꢀinꢀtheꢀPSCRꢀregister.
Rev. 1.10
1ꢆꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
TB0[ꢅ:0]
TB0ON
fPSC/ꢅꢆ ~ fPSC/ꢅ15
M
U
X
Time Base 0 Inteꢁꢁꢀpt
Time Base 1 Inteꢁꢁꢀpt
fSYS
M
U
X
fPSC
Pꢁescaleꢁ
fSYS/ꢃ
fSUB
fPSC/ꢅꢆ ~ fPSC/ꢅ15
M
U
X
CLKSEL[1:0]
TB1ON
TB1[ꢅ:0]
Time Base Interrupt
PSCR Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLKSEL1
CLKSEL0
R/W
0
R/W
0
POR
Bitꢀ7~2ꢀ
Bitꢀ1~0
Unimplemented,ꢀreadꢀasꢀ“0”
CLKSEL1~CLKSEL0:ꢀPrescalerꢀclockꢀsourceꢀselection
00:ꢀfSYS
01:ꢀfSYS/4
1x:ꢀfSUB
TB0C Register
Bit
Name
R/W
7
TB0ON
R/W
0
6
5
4
3
2
1
0
TB00
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
TB0ꢅ
R/W
0
TB01
R/W
0
POR
Bitꢀ7ꢀ
TB0ON:ꢀTimeꢀBaseꢀ0ꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ6~3ꢀ
Bitꢀ2~0
Unimplemented,ꢀreadꢀasꢀ“0”
TB02~TB00:ꢀSelectꢀTimeꢀBaseꢀ0ꢀTime-outꢀPeriod
000:ꢀ28/fPSC
001:ꢀ29/fPSC
010:ꢀ210/fPSC
011:ꢀ211/fPSC
100:ꢀ212/fPSC
101:ꢀ213/fPSC
110:ꢀ214/fPSC
111:ꢀ215/fPSC
Rev. 1.10
1ꢆ9
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
TB1C Register
Bit
Name
R/W
7
TB1ON
R/W
0
6
5
4
3
2
TB1ꢅ
R/W
0
1
TB11
R/W
0
0
TB10
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7ꢀ
TB1ON:ꢀTimeꢀBaseꢀ1ꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ6~3ꢀ
Bitꢀ2~0
Unimplemented,ꢀreadꢀasꢀ“0”
TB12~TB10:ꢀSelectꢀTimeꢀBaseꢀ1ꢀTime-outꢀPeriod
000:ꢀ28/fPSC
001:ꢀ29/fPSC
010:ꢀ210/fPSC
011:ꢀ211/fPSC
100:ꢀ212/fPSC
101:ꢀ213/fPSC
110:ꢀ214/fPSC
111:ꢀ215/fPSC
Timer Module Interrupts
EachꢀofꢀtheꢀStandardꢀTypeꢀTMꢀandꢀPeriodicꢀTypeꢀTMꢀhasꢀtwoꢀinterrupts.ꢀAllꢀofꢀtheꢀTMꢀinterruptsꢀ
areꢀcontainedꢀwithinꢀtheꢀMulti-functionꢀInterrupts.ꢀForꢀtheꢀStandardꢀTypeꢀTMꢀandꢀtheꢀPeriodicꢀ
TypeꢀTM,ꢀeachꢀhasꢀtwoꢀinterruptꢀrequestꢀflagsꢀofꢀSTMPF,ꢀSTMAFꢀandꢀPTMnPF,ꢀPTMnAFꢀandꢀtwoꢀ
enableꢀbitsꢀofꢀSTMPE,ꢀSTMAEꢀandꢀPTMnPE,ꢀPTMnAE.ꢀAꢀTMꢀinterruptꢀrequestꢀwillꢀtakeꢀplaceꢀ
whenꢀanyꢀofꢀtheꢀTMꢀrequestꢀflagsꢀareꢀset,ꢀaꢀsituationꢀwhichꢀoccursꢀwhenꢀaꢀTMꢀcomparatorꢀPꢀorꢀAꢀ
matchꢀsituationꢀhappens.ꢀ
Toꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀ
bit,ꢀEMI,ꢀrespectiveꢀTMꢀInterruptꢀenableꢀbit,ꢀandꢀrelevantꢀMulti-functionꢀInterruptꢀenableꢀbit,ꢀMFnE,ꢀ
mustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀaꢀTMꢀcomparatorꢀmatchꢀ
situationꢀoccurs,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀrelevantꢀMulti-functionꢀInterruptꢀvectorꢀlocations,ꢀwillꢀtakeꢀ
place.ꢀWhenꢀtheꢀTMꢀinterruptꢀisꢀserviced,ꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀ
interrupts,ꢀhoweverꢀonlyꢀtheꢀrelatedꢀMFnFꢀflagꢀwillꢀbeꢀautomaticallyꢀcleared.ꢀAsꢀtheꢀTMꢀinterruptꢀ
requestꢀflagsꢀwillꢀnotꢀbeꢀautomaticallyꢀcleared,ꢀtheyꢀhaveꢀtoꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.
Interrupt Wake-up Function
Eachꢀofꢀtheꢀinterruptꢀfunctionsꢀhasꢀtheꢀcapabilityꢀofꢀwakingꢀupꢀtheꢀmicrocontrollerꢀwhenꢀinꢀtheꢀ
SLEEPꢀorꢀIDLEꢀMode.ꢀAꢀwake-upꢀisꢀgeneratedꢀwhenꢀanꢀinterruptꢀrequestꢀflagꢀchangesꢀfromꢀlowꢀtoꢀ
highꢀandꢀisꢀindependentꢀofꢀwhetherꢀtheꢀinterruptꢀisꢀenabledꢀorꢀnot.ꢀTherefore,ꢀevenꢀthoughꢀtheꢀdeviceꢀ
isꢀinꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀandꢀitsꢀsystemꢀoscillatorꢀstopped,ꢀsituationsꢀsuchꢀasꢀexternalꢀedgeꢀ
transitionsꢀonꢀtheꢀexternalꢀinterruptꢀpinsꢀorꢀaꢀlowꢀpowerꢀsupplyꢀvoltageꢀmayꢀcauseꢀtheirꢀrespectiveꢀ
interruptꢀflagꢀtoꢀbeꢀsetꢀhighꢀandꢀconsequentlyꢀgenerateꢀanꢀinterrupt.ꢀCareꢀmustꢀthereforeꢀbeꢀtakenꢀifꢀ
spuriousꢀwake-upꢀsituationsꢀareꢀtoꢀbeꢀavoided.ꢀIfꢀanꢀinterruptꢀwake-upꢀfunctionꢀisꢀtoꢀbeꢀdisabledꢀthenꢀ
theꢀcorrespondingꢀinterruptꢀrequestꢀflagꢀshouldꢀbeꢀsetꢀhighꢀbeforeꢀtheꢀdeviceꢀentersꢀtheꢀSLEEPꢀorꢀ
IDLEꢀMode.ꢀTheꢀinterruptꢀenableꢀbitsꢀhaveꢀnoꢀeffectꢀonꢀtheꢀinterruptꢀwake-upꢀfunction.
Rev. 1.10
190
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Programming Considerations
Byꢀdisablingꢀtheꢀrelevantꢀinterruptꢀenableꢀbits,ꢀaꢀrequestedꢀinterruptꢀcanꢀbeꢀpreventedꢀfromꢀbeingꢀ
serviced,ꢀhowever,ꢀonceꢀanꢀinterruptꢀrequestꢀflagꢀisꢀset,ꢀitꢀwillꢀremainꢀinꢀthisꢀconditionꢀinꢀtheꢀ
interruptꢀregisterꢀuntilꢀtheꢀcorrespondingꢀinterruptꢀisꢀservicedꢀorꢀuntilꢀtheꢀrequestꢀflagꢀisꢀclearedꢀbyꢀ
theꢀapplicationꢀprogram.
WhereꢀaꢀcertainꢀinterruptꢀisꢀcontainedꢀwithinꢀaꢀMulti-functionꢀinterrupt,ꢀthenꢀwhenꢀtheꢀinterruptꢀ
serviceꢀroutineꢀisꢀexecuted,ꢀasꢀonlyꢀtheꢀMulti-functionꢀinterruptꢀrequestꢀflags,ꢀMFnF,ꢀwillꢀbeꢀ
automaticallyꢀcleared,ꢀtheꢀindividualꢀrequestꢀflagꢀforꢀtheꢀfunctionꢀneedsꢀtoꢀbeꢀclearedꢀbyꢀtheꢀ
applicationꢀprogram.
Itꢀisꢀrecommendedꢀthatꢀprogramsꢀdoꢀnotꢀuseꢀtheꢀ“CALL”ꢀinstructionꢀwithinꢀtheꢀinterruptꢀserviceꢀ
subroutine.ꢀInterruptsꢀoftenꢀoccurꢀinꢀanꢀunpredictableꢀmannerꢀorꢀneedꢀtoꢀbeꢀservicedꢀimmediately.ꢀ
Ifꢀonlyꢀoneꢀstackꢀisꢀleftꢀandꢀtheꢀinterruptꢀisꢀnotꢀwellꢀcontrolled,ꢀtheꢀoriginalꢀcontrolꢀsequenceꢀwillꢀbeꢀ
damagedꢀonceꢀaꢀCALLꢀsubroutineꢀisꢀexecutedꢀinꢀtheꢀinterruptꢀsubroutine.
EveryꢀinterruptꢀhasꢀtheꢀcapabilityꢀofꢀwakingꢀupꢀtheꢀmicrocontrollerꢀwhenꢀitꢀisꢀinꢀSLEEPꢀorꢀIDLEꢀ
Mode,ꢀtheꢀwakeꢀupꢀbeingꢀgeneratedꢀwhenꢀtheꢀinterruptꢀrequestꢀflagꢀchangesꢀfromꢀlowꢀtoꢀhigh.ꢀIfꢀitꢀisꢀ
requiredꢀtoꢀpreventꢀaꢀcertainꢀinterruptꢀfromꢀwakingꢀupꢀtheꢀmicrocontrollerꢀthenꢀitsꢀrespectiveꢀrequestꢀ
flagꢀshouldꢀbeꢀfirstꢀsetꢀhighꢀbeforeꢀenterꢀSLEEPꢀorꢀIDLEꢀMode.
AsꢀonlyꢀtheꢀProgramꢀCounterꢀisꢀpushedꢀontoꢀtheꢀstack,ꢀthenꢀwhenꢀtheꢀinterruptꢀisꢀserviced,ꢀifꢀtheꢀ
contentsꢀofꢀtheꢀaccumulator,ꢀstatusꢀregisterꢀorꢀotherꢀregistersꢀareꢀalteredꢀbyꢀtheꢀinterruptꢀserviceꢀ
program,ꢀtheirꢀcontentsꢀshouldꢀbeꢀsavedꢀtoꢀtheꢀmemoryꢀatꢀtheꢀbeginningꢀofꢀtheꢀinterruptꢀserviceꢀ
routine.ꢀToꢀreturnꢀfromꢀanꢀinterruptꢀsubroutine,ꢀeitherꢀaꢀRETꢀorꢀRETIꢀinstructionꢀmayꢀbeꢀexecuted.ꢀ
TheꢀRETIꢀinstructionꢀinꢀadditionꢀtoꢀexecutingꢀaꢀreturnꢀtoꢀtheꢀmainꢀprogramꢀalsoꢀautomaticallyꢀsetsꢀ
theꢀEMIꢀbitꢀhighꢀtoꢀallowꢀfurtherꢀinterrupts.ꢀTheꢀRETꢀinstructionꢀhoweverꢀonlyꢀexecutesꢀaꢀreturnꢀtoꢀ
theꢀmainꢀprogramꢀleavingꢀtheꢀEMIꢀbitꢀinꢀitsꢀpresentꢀzeroꢀstateꢀandꢀthereforeꢀdisablingꢀtheꢀexecutionꢀ
ofꢀfurtherꢀinterrupts.
Rev. 1.10
191
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Low Voltage Detector – LVD
EachꢀdeviceꢀcontainsꢀaꢀLowꢀVoltageꢀDetectorꢀfunction,ꢀalsoꢀknownꢀasꢀLVD.ꢀThisꢀenabledꢀtheꢀdeviceꢀ
toꢀmonitorꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀVDD,ꢀorꢀLVDINꢀpinꢀinputꢀvoltage,ꢀandꢀprovideꢀaꢀwarningꢀsignalꢀ
shouldꢀitꢀfallꢀbelowꢀaꢀcertainꢀlevel.ꢀThisꢀfunctionꢀmayꢀbeꢀespeciallyꢀusefulꢀinꢀbatteryꢀapplicationsꢀ
whereꢀtheꢀsupplyꢀvoltageꢀwillꢀgraduallyꢀreduceꢀasꢀtheꢀbatteryꢀages,ꢀasꢀitꢀallowsꢀanꢀearlyꢀwarningꢀ
batteryꢀlowꢀsignalꢀtoꢀbeꢀgenerated.ꢀTheꢀLowꢀVoltageꢀDetectorꢀalsoꢀhasꢀtheꢀcapabilityꢀofꢀgeneratingꢀ
anꢀinterruptꢀsignal.
LVD Register
TheꢀLowꢀVoltageꢀDetectorꢀfunctionꢀisꢀcontrolledꢀusingꢀaꢀsingleꢀregisterꢀwithꢀtheꢀnameꢀLVDC.ꢀThreeꢀ
bitsꢀinꢀthisꢀregister,ꢀVLVD2~VLVD0,ꢀareꢀusedꢀtoꢀselectꢀoneꢀofꢀeightꢀfixedꢀvoltagesꢀbelowꢀwhichꢀaꢀ
lowꢀvoltageꢀconditionꢀwillꢀbeꢀdetermined.ꢀAꢀlowꢀvoltageꢀconditionꢀisꢀindicatedꢀwhenꢀtheꢀLVDOꢀbitꢀ
isꢀset.ꢀIfꢀtheꢀLVDOꢀbitꢀisꢀlow,ꢀthisꢀindicatesꢀthatꢀtheꢀVDDꢀorꢀLVDINꢀpinꢀinputꢀvoltageꢀisꢀaboveꢀtheꢀ
presetꢀlowꢀvoltageꢀvalue.ꢀTheꢀLVDENꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀlowꢀ
voltageꢀdetector.ꢀSettingꢀtheꢀbitꢀhighꢀwillꢀenableꢀtheꢀlowꢀvoltageꢀdetector.ꢀClearingꢀtheꢀbitꢀtoꢀ“0”ꢀ
willꢀswitchꢀoffꢀtheꢀinternalꢀlowꢀvoltageꢀdetectorꢀcircuits.ꢀAsꢀtheꢀlowꢀvoltageꢀdetectorꢀwillꢀconsumeꢀaꢀ
certainꢀamountꢀofꢀpower,ꢀitꢀmayꢀbeꢀdesirableꢀtoꢀswitchꢀoffꢀtheꢀcircuitꢀwhenꢀnotꢀinꢀuse,ꢀanꢀimportantꢀ
considerationꢀinꢀpowerꢀsensitiveꢀbatteryꢀpoweredꢀapplications.
LVDC Register
Bit
7
6
5
LVDO
R
4
LVDEN
R/W
0
3
VBGEN
R/W
0
2
VLVDꢅ
R/W
0
1
VLVD1
R/W
0
0
VLVD0
R/W
0
Name
R/W
—
—
—
—
—
—
POR
0
Bitꢀ7~6ꢀ
Bitꢀ5
Unimplemented,ꢀreadꢀasꢀ“0”
LVDO:ꢀLVDꢀOutputꢀFlag
0:ꢀNoꢀLowꢀVoltageꢀDetect
1:ꢀLowꢀVoltageꢀDetect
Bitꢀ4
LVDEN:ꢀLowꢀVoltageꢀDetectorꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ3
VBGEN:ꢀBandgapꢀBufferꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ2~0
VLVD2~VLVD0:ꢀSelectꢀLVDꢀVoltage
000:ꢀVLVDINꢀ ꢀ1.04V
≤
001:ꢀ2.2V
010:ꢀ2.4V
011:ꢀ2.7V
100:ꢀ3.0V
101:ꢀ3.3V
110:ꢀ3.6V
111:ꢀ4.0V
Note:ꢀWhenꢀtheꢀVLVDꢀbitꢀfieldꢀisꢀsetꢀtoꢀ000B,ꢀtheꢀLVDꢀfunctionꢀwillꢀbeꢀimplementedꢀ
byꢀcomparingꢀtheꢀLVDꢀreferenceꢀvoltageꢀwithꢀaꢀvoltageꢀvalueꢀofꢀ1.04Vꢀwhichꢀ
isꢀderivedꢀfromꢀtheꢀLVDINꢀpin.ꢀOtherwise,ꢀtheꢀLVDꢀfunctionꢀwillꢀoperateꢀbyꢀ
comparingꢀtheꢀLVDꢀreferenceꢀvoltageꢀwithꢀaꢀspecificꢀvoltageꢀvalueꢀwhichꢀisꢀ
generatedꢀbyꢀtheꢀinternalꢀLVDꢀcircuitꢀwhenꢀtheꢀVLVDꢀbitꢀfieldꢀisꢀsetꢀtoꢀanyꢀotherꢀ
valueꢀexceptꢀ000B.
Rev. 1.10
19ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
LVD Operation
TheꢀLowꢀVoltageꢀDetectorꢀfunctionꢀoperatesꢀbyꢀcomparingꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀVDDꢀorꢀLVDINꢀ
pinꢀinputꢀvoltageꢀwithꢀaꢀpre-specifiedꢀvoltageꢀlevelꢀstoredꢀinꢀtheꢀLVDCꢀregister.ꢀWhenꢀtheꢀpowerꢀ
supplyꢀvoltage,ꢀVDDꢀorꢀLVDINꢀpinꢀinputꢀvoltageꢀfallꢀbelowꢀthisꢀpre-determinedꢀvalue,ꢀtheꢀLVDOꢀbitꢀ
willꢀbeꢀsetꢀhighꢀindicatingꢀaꢀlowꢀpowerꢀsupplyꢀvoltageꢀcondition.ꢀTheꢀLowꢀVoltageꢀDetectorꢀfunctionꢀ
isꢀsuppliedꢀbyꢀaꢀreferenceꢀvoltageꢀwhichꢀwillꢀbeꢀautomaticallyꢀenabled.ꢀWhenꢀtheꢀdeviceꢀisꢀinꢀtheꢀ
SLEEPꢀmode,ꢀtheꢀlowꢀvoltageꢀdetectorꢀwillꢀbeꢀdisabledꢀevenꢀifꢀtheꢀLVDENꢀbitꢀisꢀhigh.ꢀAfterꢀenablingꢀ
theꢀLowꢀVoltageꢀDetector,ꢀaꢀtimeꢀdelayꢀtLVDSꢀshouldꢀbeꢀallowedꢀforꢀtheꢀcircuitryꢀtoꢀstabiliseꢀbeforeꢀ
readingꢀtheꢀLVDOꢀbit.ꢀNoteꢀalsoꢀthatꢀasꢀtheꢀVDDꢀvoltageꢀorꢀLVDINꢀpinꢀpinputꢀvoltageꢀmayꢀriseꢀandꢀ
fallꢀratherꢀslowly,ꢀatꢀtheꢀvoltageꢀnearsꢀthatꢀofꢀVLVD,ꢀthereꢀmayꢀbeꢀmultipleꢀbitꢀLVDOꢀtransitions.
VLVDIN oꢁ VDD
VLVD
LVDEN
LVDO
tLVDS
LVDIN
tLVD
LVD Operation
TheꢀLowꢀVoltageꢀDetectorꢀinterruptꢀisꢀcontainedꢀwithinꢀtheꢀMulti-functionꢀinterrupt,ꢀprovidingꢀ
anꢀalternativeꢀmeansꢀofꢀlowꢀvoltageꢀdetection,ꢀinꢀadditionꢀtoꢀpollingꢀtheꢀLVDOꢀbit.ꢀTheꢀinterruptꢀ
willꢀonlyꢀbeꢀgeneratedꢀafterꢀaꢀdelayꢀofꢀtLVDꢀafterꢀtheꢀLVDOꢀbitꢀhasꢀbeenꢀsetꢀhighꢀbyꢀaꢀlowꢀvoltageꢀ
condition.ꢀWhenꢀtheꢀdeviceꢀisꢀpoweredꢀdownꢀtheꢀLowꢀVoltageꢀDetectorꢀwillꢀremainꢀactiveꢀifꢀtheꢀ
LVDENꢀbitꢀisꢀhigh.ꢀInꢀthisꢀcase,ꢀtheꢀLVFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀset,ꢀcausingꢀanꢀinterruptꢀtoꢀbeꢀ
generatedꢀifꢀVDDꢀorꢀLVDINꢀpinꢀinputꢀvoltageꢀfallsꢀbelowꢀtheꢀpresetꢀLVDꢀvoltage.ꢀThisꢀwillꢀcauseꢀtheꢀ
deviceꢀtoꢀwake-upꢀfromꢀtheꢀIDLEꢀMode,ꢀhoweverꢀifꢀtheꢀLowꢀVoltageꢀDetectorꢀwakeꢀupꢀfunctionꢀisꢀ
notꢀrequiredꢀthenꢀtheꢀLVFꢀflagꢀshouldꢀbeꢀfirstꢀsetꢀhighꢀbeforeꢀtheꢀdeviceꢀentersꢀtheꢀIDLEꢀMode.
WhenꢀLVDꢀfunctionꢀisꢀenabled,ꢀitꢀisꢀrecommencedꢀtoꢀclearꢀLVDꢀflagꢀfirst,ꢀandꢀthenꢀenablesꢀinterruptꢀ
functionꢀtoꢀavoidꢀmistakeꢀaction.
Rev. 1.10
193
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
16-bit Multiplication Division Unit – MDU
Eachꢀdeviceꢀcontainsꢀaꢀ16-bitꢀMultiplicationꢀDivisionꢀUnit,ꢀMDU,ꢀwhichꢀintegratesꢀaꢀ16-bitꢀ
unsignedꢀmultiplierꢀandꢀaꢀ32-bit/16-bitꢀdivider.ꢀTheꢀMDU,ꢀinꢀreplacingꢀtheꢀsoftwareꢀmultiplicationꢀ
andꢀdivisionꢀoperations,ꢀcanꢀthereforeꢀsaveꢀlargeꢀamountsꢀofꢀcomputingꢀtimeꢀasꢀwellꢀasꢀtheꢀProgramꢀ
andꢀDataꢀMemoryꢀspace.ꢀItꢀalsoꢀreducesꢀtheꢀoverallꢀmicrocontrollerꢀloadingꢀtheꢀresultsꢀinꢀtheꢀoverallꢀ
systemꢀperfofmanceꢀimprovements.
fSYS
MDUWR0
MDUWR1
MDUWRꢅ
MDUWR3
16/3ꢅ-bit Dividend
/
16-bit Mꢀltiplicand
MDWEF
+/-
MDWOV
Shift Contꢁol
16-bit Divisoꢁ
MDUWRꢃ
MDUWR5
/
16-bit Mꢀltiplieꢁ
16-bit MDU Block Diagram
MDU registers
Theꢀmultiplicationꢀandꢀdivisionꢀoperationsꢀareꢀimplementedꢀinꢀaꢀspecificꢀway,ꢀaꢀspecificꢀwriteꢀ
accessꢀsequenceꢀofꢀaꢀseriesꢀofꢀMDUꢀdataꢀregisters.ꢀTheꢀstatusꢀregister,ꢀMDUWCTRL,ꢀprovidesꢀtheꢀ
indicationsꢀforꢀtheꢀMDUꢀoperation.ꢀTheꢀdataꢀregisterꢀeachꢀisꢀusedꢀtoꢀstoreꢀtheꢀdataꢀregardedꢀasꢀtheꢀ
differentꢀoperandꢀcorrespondingꢀtoꢀdifferentꢀMDUꢀoperations.
Bit
Register
Name
7
6
5
4
3
2
1
0
MDUWR0
MDUWR1
MDUWRꢅ
MDUWR3
MDUWRꢃ
MDUWR5
D7
D7
D7
D7
D7
D7
D6
D6
D6
D6
D6
D6
D5
D5
D5
D5
D5
D5
–
Dꢃ
Dꢃ
Dꢃ
Dꢃ
Dꢃ
Dꢃ
–
D3
D3
D3
D3
D3
D3
–
Dꢅ
Dꢅ
Dꢅ
Dꢅ
Dꢅ
Dꢅ
–
D1
D1
D1
D1
D1
D1
–
D0
D0
D0
D0
D0
D0
–
MDUWCTRL MDWEF MDWOV
MDU Registers List
MDUWRn Register (n=0~5)
Bit
Name
R/W
7
D7
R/W
x
6
D6
R/W
x
5
4
3
2
1
D1
R/W
x
0
D5
R/W
x
Dꢃ
R/W
x
D3
R/W
x
Dꢅ
R/W
x
D0
R/W
POR
x
“x” ꢀnknown
Bitꢀ7~0
D7~D0:ꢀ16-bitꢀMDUꢀdataꢀregisterꢀn
Rev. 1.10
19ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
MDUWCTRL Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
MDWEF MDWOV
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R
0
R
0
POR
Bitꢀ7
MDWEF:ꢀ16-bitꢀMDUꢀErrorꢀFlag
0:ꢀNormal
1:ꢀAbnormal
Thisꢀbitꢀwillꢀbeꢀsetꢀtoꢀ1ꢀifꢀtheꢀdataꢀregisterꢀMDUWRnꢀisꢀwrittenꢀorꢀreadꢀasꢀtheꢀMDUꢀ
operationꢀisꢀexecuting.ꢀThisꢀbitꢀshouldꢀbeꢀclearedꢀtoꢀ0ꢀbyꢀreadingꢀtheꢀMDUWCTRLꢀ
registerꢀifꢀitꢀisꢀequalꢀtoꢀ1ꢀandꢀtheꢀMDUꢀoperationꢀisꢀcompleted.
Bitꢀ6
MDWOV:ꢀ16-bitꢀMDUꢀOverflowꢀFlag
0:ꢀNoꢀoverflowꢀoccurs
1:ꢀMultiplicationꢀproductꢀ>ꢀFFFFHꢀorꢀDivisorꢀ=ꢀ0
Whenꢀanꢀoperationꢀisꢀcompleted,ꢀthisꢀbitꢀwillꢀbeꢀupdatedꢀbyꢀhardwareꢀtoꢀaꢀnewꢀvalueꢀ
correspondingꢀtoꢀtheꢀcurrentꢀoperationꢀsituation.
Bitꢀ5~0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Multiplication Division Unit Operation
ForꢀthisꢀMDUꢀtheꢀmultiplicationꢀorꢀdivisionꢀoperationꢀisꢀcarriedꢀoutꢀinꢀaꢀspecificꢀwayꢀandꢀisꢀ
determinedꢀbyꢀtheꢀwriteꢀaccessꢀsequenceꢀofꢀtheꢀsixꢀMDUꢀdataꢀregisters,ꢀMDUWR0~MDUWR5.ꢀTheꢀ
lowꢀbyteꢀdata,ꢀregardlessꢀofꢀtheꢀdividend,ꢀmultiplicand,ꢀdivisorꢀorꢀmultiplier,ꢀmustꢀfirstꢀbeꢀwrittenꢀ
intoꢀtheꢀcorrespondingꢀMDUꢀdataꢀregisterꢀfollowedꢀbyꢀtheꢀhighꢀbyteꢀdata.ꢀAllꢀMDUꢀoperationsꢀ
willꢀbeꢀexecutedꢀafterꢀtheꢀMDUWR5ꢀregisterꢀisꢀwrite-accessedꢀtogetherꢀwithꢀtheꢀcorrectꢀspecificꢀ
writeꢀaccessꢀsequenceꢀofꢀtheꢀMDUWRn.ꢀNoteꢀthatꢀitꢀisꢀnotꢀnecessaryꢀtoꢀconsecutivelyꢀwriteꢀdataꢀ
intoꢀtheꢀMDUꢀdataꢀregistersꢀbutꢀmustꢀbeꢀinꢀaꢀcorrectꢀwriteꢀaccessꢀsequence.ꢀTherefore,ꢀaꢀnon-writeꢀ
MDUWRnꢀinstructionꢀorꢀanꢀinterrupt,ꢀetc.,ꢀcanꢀbeꢀinsertedꢀintoꢀtheꢀcorrectꢀwriteꢀaccessꢀsequenceꢀ
withoutꢀdestroyingꢀtheꢀwriteꢀoperation.ꢀTheꢀrelationshipꢀbetweenꢀtheꢀwriteꢀaccessꢀsequenceꢀandꢀtheꢀ
MDUꢀoperationꢀisꢀshownꢀinꢀtheꢀfollowing.
•ꢀ 32-bit/16-bitꢀDivisionꢀOperation:ꢀWriteꢀdataꢀsequentiallyꢀintoꢀtheꢀsixꢀMDUꢀdataꢀregistersꢀfromꢀ
MDUWR0ꢀtoꢀMDUWR5.
•ꢀ 16-bit/16-bitꢀDivisionꢀOperation:ꢀWriteꢀdataꢀsequentiallyꢀintoꢀtheꢀspecificꢀfourꢀMDUꢀdataꢀ
registersꢀinꢀaꢀsequenceꢀofꢀMDUWR0,ꢀMDUWR1,ꢀMDUWR4ꢀandꢀMDUWR5ꢀwithꢀnoꢀwriteꢀ
accessꢀtoꢀMDUWR2ꢀandꢀMDUWR3.
•ꢀ 16-bit/16-bitꢀMultiplicationꢀOperation:ꢀWriteꢀdataꢀsequentiallyꢀintoꢀtheꢀspecificꢀfourꢀMDUꢀdataꢀ
registerꢀinꢀaꢀsequenceꢀofꢀMDUWR0,ꢀMDUWR4,ꢀMDUWR1ꢀandꢀMDUWR5ꢀwithꢀnoꢀwriteꢀaccessꢀ
toꢀMDUWR2ꢀandꢀMDUWR3.
Afterꢀtheꢀspecificꢀwriteꢀaccessꢀsequenceꢀisꢀdetermined,ꢀtheꢀMDUꢀwillꢀstartꢀtoꢀperformꢀtheꢀ
correspondingꢀoperation.ꢀTheꢀcalculationꢀtimeꢀnecessaryꢀforꢀtheseꢀMDUꢀoperationsꢀareꢀdifferent.ꢀ
Duringꢀtheꢀcalculationꢀtimeꢀanyꢀread/writeꢀaccessꢀtoꢀtheꢀsixꢀMDUꢀdataꢀregistersꢀisꢀforbidden.ꢀAfterꢀ
theꢀcompletionꢀofꢀeachꢀoperation,ꢀitꢀisꢀnecessaryꢀtoꢀcheckꢀtheꢀoperationꢀstatusꢀinꢀtheꢀMDUWCTRLꢀ
registerꢀtoꢀmakeꢀsureꢀthatꢀwhetherꢀtheꢀoperationꢀisꢀcorrectꢀorꢀnot.ꢀThenꢀtheꢀoperationꢀresultꢀcanꢀ
beꢀreadꢀoutꢀfromꢀtheꢀcorrespondingꢀMDUꢀdataꢀregistersꢀinꢀaꢀspecificꢀreadꢀaccessꢀsequenceꢀifꢀtheꢀ
operationꢀisꢀcorrectlyꢀfinished.ꢀTheꢀnecessaryꢀcalculationꢀtimeꢀforꢀdifferentꢀMDUꢀoperationsꢀisꢀlistedꢀ
inꢀtheꢀfollowing.
•ꢀ 32-bit/16-bitꢀdivisionꢀoperation:ꢀ17ꢀ×ꢀtSYS
•ꢀ 16-bit/16-bitꢀdivisionꢀoperation:ꢀ9ꢀ×ꢀtSYS
.
.
•ꢀ 16-bit/16-bitꢀmultiplicationꢀoperation:ꢀ11ꢀ×ꢀtSYS
.
Rev. 1.10
195
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
TheꢀoperationꢀresultsꢀwillꢀbeꢀstoredꢀinꢀtheꢀcorrespondingꢀMDUꢀdataꢀregistersꢀandꢀshouldꢀbeꢀreadꢀ
outꢀfromꢀtheꢀMDUꢀdataꢀregistersꢀinꢀaꢀspecificꢀreadꢀaccessꢀsequenceꢀafterꢀtheꢀoperationꢀisꢀcompleted.ꢀ
NoeꢀthatꢀitꢀisꢀnotꢀnecessaryꢀtoꢀconsecutivelyꢀreadꢀdataꢀoutꢀfromꢀtheꢀMDUꢀdataꢀregistersꢀbutꢀmustꢀbeꢀ
inꢀaꢀcorrectꢀreadꢀaccessꢀsequence.ꢀTherefore,ꢀaꢀnon-readꢀMDUWRnꢀinstructionꢀorꢀanꢀinterrupt,ꢀetc.,ꢀ
canꢀbeꢀinsertedꢀintoꢀtheꢀcorrectꢀreadꢀaccessꢀsequenceꢀwithoutꢀdestroyingꢀtheꢀreadꢀoperation.ꢀTheꢀ
relationshipꢀbetweenꢀtheꢀoperationꢀresultꢀreadꢀaccessꢀsequenceꢀandꢀtheꢀMDUꢀoperationꢀisꢀshownꢀinꢀ
theꢀfollowing.
•ꢀ 32-bit/16-bitꢀdivisionꢀoperation:ꢀReadꢀtheꢀquotientꢀfromꢀMDUWR0ꢀtoꢀMDUWR3ꢀandꢀremainderꢀ
fromꢀMDUWR4ꢀandꢀMDUWR5ꢀsequentially.
•ꢀ 16-bit/16-bitꢀdivisionꢀoperation:ꢀReadꢀtheꢀquotientꢀfromꢀMDUWR0ꢀandꢀMDUWR1ꢀandꢀ
remainderꢀfromꢀMDUWR4ꢀandꢀMDUWR5ꢀsequentially.
•ꢀ 16-bit/16-bitꢀmultiplicationꢀoperation:ꢀReadꢀtheꢀproductꢀsequentiallyꢀfromꢀMDUWR0ꢀtoꢀ
MDUWR3.
TheꢀoverallꢀimportantꢀpointsꢀforꢀtheꢀMDUꢀread/writeꢀaccessꢀsequenceꢀandꢀcalculationꢀtimeꢀareꢀ
summarizedꢀinꢀtheꢀfollowingꢀtable.
Operations
32-bit / 16-bit Division
16-bit / 16-bit Division
16-bit × 16-bit Multiplication
Items
Write Sequence
Dividend Bꢂte 0 wꢁitten to MDUWR0
Dividend Bꢂte 1 wꢁitten to MDUWR1
Dividend Bꢂte ꢅ wꢁitten to MDUWRꢅ
Dividend Bꢂte 3 wꢁitten to MDUWR3
Divisoꢁ Bꢂte 0 wꢁitten to MDUWRꢃ
Divisoꢁ Bꢂte 1 wꢁitten to MDUWR5
Fiꢁst wꢁite
Dividend Bꢂte 0 wꢁitten to MDUWR0
Dividend Bꢂte 1 wꢁitten to MDUWR1
Divisoꢁ Bꢂte 0 wꢁitten to MDUWRꢃ
Divisoꢁ Bꢂte 1 wꢁitten to MDUWR5
Mꢀltiplicand Bꢂte 0 wꢁitten to MDUWR0
Mꢀltiplieꢁ Bꢂte 0 wꢁitten to MDUWRꢃ
Mꢀltiplicand Bꢂte 1 wꢁitten to MDUWR1
Mꢀltiplieꢁ Bꢂte 1 wꢁitten to MDUWR5
↓
↓
↓
↓
Last wꢁite
Calculation Time
17 × tSYS
9 × tSYS
11 × tSYS
Read Sequence
Qꢀotient Bꢂte 0 ꢁead fꢁom MDUWR0
Qꢀotient Bꢂte 1 ꢁead fꢁom MDUWR1
Qꢀotient Bꢂte ꢅ ꢁead fꢁom MDUWRꢅ
Qꢀotient Bꢂte 3 ꢁead fꢁom MDUWR3
Remaindeꢁ Bꢂte 0 ꢁead fꢁom MDUWRꢃ Remaindeꢁ Bꢂte 1 ꢁead fꢁom MDUWR5 Pꢁodꢀct Bꢂte 3 wꢁitten to MDUWR3
Remaindeꢁ Bꢂte 1 ꢁead fꢁom MDUWR5
Fiꢁst ꢁead
Qꢀotient Bꢂte 0 ꢁead fꢁom MDUWR0
Qꢀotient Bꢂte 1 ꢁead fꢁom MDUWR1
Remaindeꢁ Bꢂte 0 ꢁead fꢁom MDUWRꢃ Pꢁodꢀct Bꢂte ꢅ wꢁitten to MDUWRꢅ
Pꢁodꢀct Bꢂte 0 wꢁitten to MDUWR0
Pꢁodꢀct Bꢂte 1 wꢁitten to MDUWR1
↓
↓
↓
↓
Last ꢁead
MDU Operations Summary
Rev. 1.10
196
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Application Circuits
8-electrode
VOREG
VDD
VOREG/VREFP
VDD/VIN
VSS
1μF
1μF
10μF
0.1μF
AVSS/VREFN
VCM
1K
1K
1K
AN0
AN1
AN2
AN3
0.1μF
1K
RFC
VOREG
0.1μF
RF IC
100kΩ
100kΩ
SPI/UART
CP0N
33kΩ
0.1μF
TO
HVR
HVL
FVR
FVL
RF2
RF1
1kΩ
200Ω
I/O
LED Panel
FIR
FIL
HIR
HIL
RF
BH66F2660-8
BH66F2650-8
SIN
2.7kΩ
0.1μF
Rev. 1.10
197
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
4-electrode
VOREG
VDD
VOREG/VREFP
VDD/VIN
1μF
10μF
0.1μF
AVSS/VREFN
VCM
VSS
1μF
1K
1K
1K
AN0
AN1
AN2
AN3
0.1μF
1K
RFC
VOREG
0.1μF
RF IC
100kΩ
100kΩ
SPI/UART
CP0N
TO
33kΩ
0.1μF
FVR
FVL
RF2
RF1
1kΩ
200Ω
I/O
LED Panel
FIR
FIL
RF
BH66F2660
BH66F2650
SIN
2.7kΩ
0.1μF
Rev. 1.10
19ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Instruction Set
Introduction
Centralꢀtoꢀtheꢀsuccessfulꢀoperationꢀofꢀanyꢀmicrocontrollerꢀisꢀitsꢀinstructionꢀset,ꢀwhichꢀisꢀaꢀsetꢀofꢀ
programꢀinstructionꢀcodesꢀthatꢀdirectsꢀtheꢀmicrocontrollerꢀtoꢀperformꢀcertainꢀoperations.ꢀInꢀtheꢀcaseꢀ
ofꢀHoltekꢀmicrocontroller,ꢀaꢀcomprehensiveꢀandꢀflexibleꢀsetꢀofꢀoverꢀ60ꢀinstructionsꢀisꢀprovidedꢀtoꢀ
enableꢀprogrammersꢀtoꢀimplementꢀtheirꢀapplicationꢀwithꢀtheꢀminimumꢀofꢀprogrammingꢀoverheads.ꢀ
Forꢀeasierꢀunderstandingꢀofꢀtheꢀvariousꢀinstructionꢀcodes,ꢀtheyꢀhaveꢀbeenꢀsubdividedꢀintoꢀseveralꢀ
functionalꢀgroupings.
Instruction Timing
Mostꢀinstructionsꢀareꢀimplementedꢀwithinꢀoneꢀinstructionꢀcycle.ꢀTheꢀexceptionsꢀtoꢀthisꢀareꢀbranch,ꢀ
call,ꢀorꢀtableꢀreadꢀinstructionsꢀwhereꢀtwoꢀinstructionꢀcyclesꢀareꢀrequired.ꢀOneꢀinstructionꢀcycleꢀisꢀ
equalꢀtoꢀ4ꢀsystemꢀclockꢀcycles,ꢀthereforeꢀinꢀtheꢀcaseꢀofꢀanꢀ8MHzꢀsystemꢀoscillator,ꢀmostꢀinstructionsꢀ
wouldꢀbeꢀimplementedꢀwithinꢀ0.5μsꢀandꢀbranchꢀorꢀcallꢀinstructionsꢀwouldꢀbeꢀimplementedꢀwithinꢀ
1μs.ꢀAlthoughꢀinstructionsꢀwhichꢀrequireꢀoneꢀmoreꢀcycleꢀtoꢀimplementꢀareꢀgenerallyꢀlimitedꢀtoꢀ
theꢀJMP,ꢀCALL,ꢀRET,ꢀRETIꢀandꢀtableꢀreadꢀinstructions,ꢀitꢀisꢀimportantꢀtoꢀrealizeꢀthatꢀanyꢀotherꢀ
instructionsꢀwhichꢀinvolveꢀmanipulationꢀofꢀtheꢀProgramꢀCounterꢀLowꢀregisterꢀorꢀPCLꢀwillꢀalsoꢀtakeꢀ
oneꢀmoreꢀcycleꢀtoꢀimplement.ꢀAsꢀinstructionsꢀwhichꢀchangeꢀtheꢀcontentsꢀofꢀtheꢀPCLꢀwillꢀimplyꢀaꢀ
directꢀjumpꢀtoꢀthatꢀnewꢀaddress,ꢀoneꢀmoreꢀcycleꢀwillꢀbeꢀrequired.ꢀExamplesꢀofꢀsuchꢀinstructionsꢀ
wouldꢀbeꢀ“CLRꢀPCL”ꢀorꢀ“MOVꢀPCL,ꢀA”.ꢀForꢀtheꢀcaseꢀofꢀskipꢀinstructions,ꢀitꢀmustꢀbeꢀnotedꢀthatꢀifꢀ
theꢀresultꢀofꢀtheꢀcomparisonꢀinvolvesꢀaꢀskipꢀoperationꢀthenꢀthisꢀwillꢀalsoꢀtakeꢀoneꢀmoreꢀcycle,ꢀifꢀnoꢀ
skipꢀisꢀinvolvedꢀthenꢀonlyꢀoneꢀcycleꢀisꢀrequired.
Moving and Transferring Data
Theꢀtransferꢀofꢀdataꢀwithinꢀtheꢀmicrocontrollerꢀprogramꢀisꢀoneꢀofꢀtheꢀmostꢀfrequentlyꢀusedꢀ
operations.ꢀMakingꢀuseꢀofꢀthreeꢀkindsꢀofꢀMOVꢀinstructions,ꢀdataꢀcanꢀbeꢀtransferredꢀfromꢀregistersꢀtoꢀ
theꢀAccumulatorꢀandꢀvice-versaꢀasꢀwellꢀasꢀbeingꢀableꢀtoꢀmoveꢀspecificꢀimmediateꢀdataꢀdirectlyꢀintoꢀ
theꢀAccumulator.ꢀOneꢀofꢀtheꢀmostꢀimportantꢀdataꢀtransferꢀapplicationsꢀisꢀtoꢀreceiveꢀdataꢀfromꢀtheꢀ
inputꢀportsꢀandꢀtransferꢀdataꢀtoꢀtheꢀoutputꢀports.
Arithmetic Operations
Theꢀabilityꢀtoꢀperformꢀcertainꢀarithmeticꢀoperationsꢀandꢀdataꢀmanipulationꢀisꢀaꢀnecessaryꢀfeatureꢀofꢀ
mostꢀmicrocontrollerꢀapplications.ꢀWithinꢀtheꢀHoltekꢀmicrocontrollerꢀinstructionꢀsetꢀareꢀaꢀrangeꢀofꢀ
addꢀandꢀsubtractꢀinstructionꢀmnemonicsꢀtoꢀenableꢀtheꢀnecessaryꢀarithmeticꢀtoꢀbeꢀcarriedꢀout.ꢀCareꢀ
mustꢀbeꢀtakenꢀtoꢀensureꢀcorrectꢀhandlingꢀofꢀcarryꢀandꢀborrowꢀdataꢀwhenꢀresultsꢀexceedꢀ255ꢀforꢀ
additionꢀandꢀlessꢀthanꢀ0ꢀforꢀsubtraction.ꢀTheꢀincrementꢀandꢀdecrementꢀinstructionsꢀINC,ꢀINCA,ꢀDECꢀ
andꢀDECAꢀprovideꢀaꢀsimpleꢀmeansꢀofꢀincreasingꢀorꢀdecreasingꢀbyꢀaꢀvalueꢀofꢀoneꢀofꢀtheꢀvaluesꢀinꢀtheꢀ
destinationꢀspecified.
Rev. 1.10
199
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Logical and Rotate Operation
TheꢀstandardꢀlogicalꢀoperationsꢀsuchꢀasꢀAND,ꢀOR,ꢀXORꢀandꢀCPLꢀallꢀhaveꢀtheirꢀownꢀinstructionꢀ
withinꢀtheꢀHoltekꢀmicrocontrollerꢀinstructionꢀset.ꢀAsꢀwithꢀtheꢀcaseꢀofꢀmostꢀinstructionsꢀinvolvingꢀ
dataꢀmanipulation,ꢀdataꢀmustꢀpassꢀthroughꢀtheꢀAccumulatorꢀwhichꢀmayꢀinvolveꢀadditionalꢀ
programmingꢀsteps.ꢀInꢀallꢀlogicalꢀdataꢀoperations,ꢀtheꢀzeroꢀflagꢀmayꢀbeꢀsetꢀifꢀtheꢀresultꢀofꢀtheꢀ
operationꢀisꢀzero.ꢀAnotherꢀformꢀofꢀlogicalꢀdataꢀmanipulationꢀcomesꢀfromꢀtheꢀrotateꢀinstructionsꢀsuchꢀ
asꢀRR,ꢀRL,ꢀRRCꢀandꢀRLCꢀwhichꢀprovideꢀaꢀsimpleꢀmeansꢀofꢀrotatingꢀoneꢀbitꢀrightꢀorꢀleft.ꢀDifferentꢀ
rotateꢀinstructionsꢀexistꢀdependingꢀonꢀprogramꢀrequirements.ꢀRotateꢀinstructionsꢀareꢀusefulꢀforꢀserialꢀ
portꢀprogrammingꢀapplicationsꢀwhereꢀdataꢀcanꢀbeꢀrotatedꢀfromꢀanꢀinternalꢀregisterꢀintoꢀtheꢀCarryꢀ
bitꢀfromꢀwhereꢀitꢀcanꢀbeꢀexaminedꢀandꢀtheꢀnecessaryꢀserialꢀbitꢀsetꢀhighꢀorꢀlow.ꢀAnotherꢀapplicationꢀ
whichꢀrotateꢀdataꢀoperationsꢀareꢀusedꢀisꢀtoꢀimplementꢀmultiplicationꢀandꢀdivisionꢀcalculations.
Branches and Control Transfer
ProgramꢀbranchingꢀtakesꢀtheꢀformꢀofꢀeitherꢀjumpsꢀtoꢀspecifiedꢀlocationsꢀusingꢀtheꢀJMPꢀinstructionꢀ
orꢀtoꢀaꢀsubroutineꢀusingꢀtheꢀCALLꢀinstruction.ꢀTheyꢀdifferꢀinꢀtheꢀsenseꢀthatꢀinꢀtheꢀcaseꢀofꢀaꢀ
subroutineꢀcall,ꢀtheꢀprogramꢀmustꢀreturnꢀtoꢀtheꢀinstructionꢀimmediatelyꢀwhenꢀtheꢀsubroutineꢀhasꢀ
beenꢀcarriedꢀout.ꢀThisꢀisꢀdoneꢀbyꢀplacingꢀaꢀreturnꢀinstructionꢀ“RET”ꢀinꢀtheꢀsubroutineꢀwhichꢀwillꢀ
causeꢀtheꢀprogramꢀtoꢀjumpꢀbackꢀtoꢀtheꢀaddressꢀrightꢀafterꢀtheꢀCALLꢀinstruction.ꢀInꢀtheꢀcaseꢀofꢀaꢀJMPꢀ
instruction,ꢀtheꢀprogramꢀsimplyꢀjumpsꢀtoꢀtheꢀdesiredꢀlocation.ꢀThereꢀisꢀnoꢀrequirementꢀtoꢀjumpꢀbackꢀ
toꢀtheꢀoriginalꢀjumpingꢀoffꢀpointꢀasꢀinꢀtheꢀcaseꢀofꢀtheꢀCALLꢀinstruction.ꢀOneꢀspecialꢀandꢀextremelyꢀ
usefulꢀsetꢀofꢀbranchꢀinstructionsꢀareꢀtheꢀconditionalꢀbranches.ꢀHereꢀaꢀdecisionꢀisꢀfirstꢀmadeꢀregardingꢀ
theꢀconditionꢀofꢀaꢀcertainꢀdataꢀmemoryꢀorꢀindividualꢀbits.ꢀDependingꢀuponꢀtheꢀconditions,ꢀtheꢀ
programꢀwillꢀcontinueꢀwithꢀtheꢀnextꢀinstructionꢀorꢀskipꢀoverꢀitꢀandꢀjumpꢀtoꢀtheꢀfollowingꢀinstruction.ꢀ
Theseꢀinstructionsꢀareꢀtheꢀkeyꢀtoꢀdecisionꢀmakingꢀandꢀbranchingꢀwithinꢀtheꢀprogramꢀperhapsꢀ
determinedꢀbyꢀtheꢀconditionꢀofꢀcertainꢀinputꢀswitchesꢀorꢀbyꢀtheꢀconditionꢀofꢀinternalꢀdataꢀbits.
Bit Operations
TheꢀabilityꢀtoꢀprovideꢀsingleꢀbitꢀoperationsꢀonꢀDataꢀMemoryꢀisꢀanꢀextremelyꢀflexibleꢀfeatureꢀofꢀallꢀ
Holtekꢀmicrocontrollers.ꢀThisꢀfeatureꢀisꢀespeciallyꢀusefulꢀforꢀoutputꢀportꢀbitꢀprogrammingꢀwhereꢀ
individualꢀbitsꢀorꢀportꢀpinsꢀcanꢀbeꢀdirectlyꢀsetꢀhighꢀorꢀlowꢀusingꢀeitherꢀtheꢀ“SETꢀ[m].i”ꢀorꢀ“CLRꢀ[m].i”ꢀ
instructionsꢀrespectively.ꢀTheꢀfeatureꢀremovesꢀtheꢀneedꢀforꢀprogrammersꢀtoꢀfirstꢀreadꢀtheꢀ8-bitꢀoutputꢀ
port,ꢀmanipulateꢀtheꢀinputꢀdataꢀtoꢀensureꢀthatꢀotherꢀbitsꢀareꢀnotꢀchangedꢀandꢀthenꢀoutputꢀtheꢀportꢀwithꢀ
theꢀcorrectꢀnewꢀdata.ꢀThisꢀread-modify-writeꢀprocessꢀisꢀtakenꢀcareꢀofꢀautomaticallyꢀwhenꢀtheseꢀbitꢀ
operationꢀinstructionsꢀareꢀused.
Table Read Operations
Dataꢀstorageꢀisꢀnormallyꢀimplementedꢀbyꢀusingꢀregisters.ꢀHowever,ꢀwhenꢀworkingꢀwithꢀlargeꢀ
amountsꢀofꢀfixedꢀdata,ꢀtheꢀvolumeꢀinvolvedꢀoftenꢀmakesꢀitꢀinconvenientꢀtoꢀstoreꢀtheꢀfixedꢀdataꢀinꢀ
theꢀDataꢀMemory.ꢀToꢀovercomeꢀthisꢀproblem,ꢀHoltekꢀmicrocontrollersꢀallowꢀanꢀareaꢀofꢀProgramꢀ
Memoryꢀtoꢀbeꢀsetꢀasꢀaꢀtableꢀwhereꢀdataꢀcanꢀbeꢀdirectlyꢀstored.ꢀAꢀsetꢀofꢀeasyꢀtoꢀuseꢀinstructionsꢀ
providesꢀtheꢀmeansꢀbyꢀwhichꢀthisꢀfixedꢀdataꢀcanꢀbeꢀreferencedꢀandꢀretrievedꢀfromꢀtheꢀProgramꢀ
Memory.
Other Operations
Inꢀadditionꢀtoꢀtheꢀaboveꢀfunctionalꢀinstructions,ꢀaꢀrangeꢀofꢀotherꢀinstructionsꢀalsoꢀexistꢀsuchꢀasꢀ
theꢀ“HALT”ꢀinstructionꢀforꢀPower-downꢀoperationsꢀandꢀinstructionsꢀtoꢀcontrolꢀtheꢀoperationꢀofꢀ
theꢀWatchdogꢀTimerꢀforꢀreliableꢀprogramꢀoperationsꢀunderꢀextremeꢀelectricꢀorꢀelectromagneticꢀ
environments.ꢀForꢀtheirꢀrelevantꢀoperations,ꢀreferꢀtoꢀtheꢀfunctionalꢀrelatedꢀsections.
Rev. 1.10
ꢅ00
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Instruction Set Summary
Theꢀinstructionsꢀrelatedꢀtoꢀtheꢀdataꢀmemoryꢀaccessꢀinꢀtheꢀfollowingꢀtableꢀcanꢀbeꢀusedꢀwhenꢀtheꢀ
desiredꢀdataꢀmemoryꢀisꢀlocatedꢀinꢀDataꢀMemoryꢀsectorꢀ0.
Table Conventions
x:ꢀBitsꢀimmediateꢀdataꢀ
m:ꢀDataꢀMemoryꢀaddressꢀ
A:ꢀAccumulatorꢀ
i:ꢀ0~7ꢀnumberꢀofꢀbitsꢀ
addr:ꢀProgramꢀmemoryꢀaddress
Mnemonic
Description
Cycles
Flag Affected
Arithmetic
ADD Aꢄ[m]
ADDM Aꢄ[m]
ADD Aꢄx
Add Data Memoꢁꢂ to ACC
1
1Note
1
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
Add ACC to Data Memoꢁꢂ
Add immediate data to ACC
ADC Aꢄ[m]
ADCM Aꢄ[m]
SUB Aꢄx
Add Data Memoꢁꢂ to ACC with Caꢁꢁꢂ
Add ACC to Data memoꢁꢂ with Caꢁꢁꢂ
Sꢀbtꢁact immediate data fꢁom the ACC
Sꢀbtꢁact Data Memoꢁꢂ fꢁom ACC
1
1Note
1
SUB Aꢄ[m]
SUBM Aꢄ[m]
SBC Aꢄx
1
Sꢀbtꢁact Data Memoꢁꢂ fꢁom ACC with ꢁesꢀlt in Data Memoꢁꢂ
Sꢀbtꢁact immediate data fꢁom ACC with Caꢁꢁꢂ
Sꢀbtꢁact Data Memoꢁꢂ fꢁom ACC with Caꢁꢁꢂ
1Note Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
1
1
Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
SBC Aꢄ[m]
SBCM Aꢄ[m]
DAA [m]
Sꢀbtꢁact Data Memoꢁꢂ fꢁom ACC with Caꢁꢁꢂꢄ ꢁesꢀlt in Data Memoꢁꢂ 1Note Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
Decimal adjꢀst ACC foꢁ Addition with ꢁesꢀlt in Data Memoꢁꢂ
1Note
C
Logic Operation
AND Aꢄ[m]
OR Aꢄ[m]
Logical AND Data Memoꢁꢂ to ACC
Logical OR Data Memoꢁꢂ to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memoꢁꢂ
Logical OR ACC to Data Memoꢁꢂ
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memoꢁꢂ
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
XOR A,[m]
ANDM Aꢄ[m]
ORM Aꢄ[m]
XORM A,[m]
AND Aꢄx
1
1Note
1Note
1Note
1
OR Aꢄx
1
XOR A,x
1
1Note
CPL [m]
CPLA [m]
Complement Data Memoꢁꢂ with ꢁesꢀlt in ACC
1
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
Incꢁement Data Memoꢁꢂ with ꢁesꢀlt in ACC
1
Z
Z
Z
Z
Incꢁement Data Memoꢁꢂ
1Note
Decꢁement Data Memoꢁꢂ with ꢁesꢀlt in ACC
Decꢁement Data Memoꢁꢂ
1
1Note
RRA [m]
RR [m]
Rotate Data Memoꢁꢂ ꢁight with ꢁesꢀlt in ACC
Rotate Data Memoꢁꢂ ꢁight
1
1Note
1
None
None
C
RRCA [m]
RRC [m]
RLA [m]
RL [m]
Rotate Data Memoꢁꢂ ꢁight thꢁoꢀgh Caꢁꢁꢂ with ꢁesꢀlt in ACC
Rotate Data Memoꢁꢂ ꢁight thꢁoꢀgh Caꢁꢁꢂ
Rotate Data Memoꢁꢂ left with ꢁesꢀlt in ACC
Rotate Data Memoꢁꢂ left
1Note
C
1
None
None
C
1Note
1
RLCA [m]
RLC [m]
Rotate Data Memoꢁꢂ left thꢁoꢀgh Caꢁꢁꢂ with ꢁesꢀlt in ACC
Rotate Data Memoꢁꢂ left thꢁoꢀgh Caꢁꢁꢂ
1Note
C
Rev. 1.10
ꢅ01
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Mnemonic
Data Move
MOV Aꢄ[m]
Description
Cycles Flag Affected
Move Data Memoꢁꢂ to ACC
1
1Note
1
None
None
None
MOV [m]ꢄA Move ACC to Data Memoꢁꢂ
MOV Aꢄx
Move immediate data to ACC
Bit Operation
CLR [m].i
Cleaꢁ bit of Data Memoꢁꢂ
Set bit of Data Memoꢁꢂ
1Note
1Note
None
None
SET [m].i
Branch Operation
�MP addꢁ
SZ [m]
�ꢀmp ꢀnconditionallꢂ
Skip if Data Memoꢁꢂ is zeꢁo
ꢅ
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
ꢅ
SZA [m]
SZ [m].i
SNZ [m]
SNZ [m].i
SIZ [m]
Skip if Data Memoꢁꢂ is zeꢁo with data movement to ACC
Skip if bit i of Data Memoꢁꢂ is zeꢁo
Skip if Data Memoꢁꢂ is not zeꢁo
Skip if bit i of Data Memoꢁꢂ is not zeꢁo
Skip if incꢁement Data Memoꢁꢂ is zeꢁo
Skip if decꢁement Data Memoꢁꢂ is zeꢁo
Skip if incꢁement Data Memoꢁꢂ is zeꢁo with ꢁesꢀlt in ACC
Skip if decꢁement Data Memoꢁꢂ is zeꢁo with ꢁesꢀlt in ACC
Sꢀbꢁoꢀtine call
SDZ [m]
SIZA [m]
SDZA [m]
CALL addꢁ
RET
Retꢀꢁn fꢁom sꢀbꢁoꢀtine
ꢅ
RET Aꢄx
RETI
Retꢀꢁn fꢁom sꢀbꢁoꢀtine and load immediate data to ACC
Retꢀꢁn fꢁom inteꢁꢁꢀpt
ꢅ
ꢅ
Table Read Operation
TABRD [m] Read table (specific page) to TBLH and Data Memory
TABRDL [m] Read table (last page) to TBLH and Data Memoꢁꢂ
ꢅNote
ꢅNote
None
None
None
ITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory ꢅNote
Increment table pointer TBLP first and Read table (last page) to TBLH and
Data Memoꢁꢂ
ITABRDL [m]
ꢅNote
None
Miscellaneous
NOP
No opeꢁation
1
1Note
1Note
1
None
None
CLR [m]
SET [m]
CLR WDT
SWAP [m]
Cleaꢁ Data Memoꢁꢂ
Set Data Memoꢁꢂ
None
Cleaꢁ Watchdog Timeꢁ
Swap nibbles of Data Memoꢁꢂ
TOꢄ PDF
None
1Note
SWAPA [m] Swap nibbles of Data Memoꢁꢂ with ꢁesꢀlt in ACC
HALT Enteꢁ poweꢁ down mode
1
None
1
TOꢄ PDF
Note:ꢀ1.ꢀForꢀskipꢀinstructions,ꢀifꢀtheꢀresultꢀofꢀtheꢀcomparisonꢀinvolvesꢀaꢀskipꢀthenꢀupꢀtoꢀthreeꢀcyclesꢀareꢀrequired,ꢀifꢀ
noꢀskipꢀtakesꢀplaceꢀonlyꢀoneꢀcycleꢀisꢀrequired.
2.ꢀAnyꢀinstructionꢀwhichꢀchangesꢀtheꢀcontentsꢀofꢀtheꢀPCLꢀwillꢀalsoꢀrequireꢀ2ꢀcyclesꢀforꢀexecution.
3.ꢀForꢀtheꢀ“CLRꢀWDT”ꢀinstructionꢀtheꢀTOꢀandꢀPDFꢀflagsꢀmayꢀbeꢀaffectedꢀbyꢀtheꢀexecutionꢀstatus.ꢀTheꢀTOꢀ
andꢀPDFꢀflagsꢀareꢀclearedꢀafterꢀtheꢀ“CLRꢀWDT”ꢀinstructionsꢀisꢀexecuted.ꢀOtherwiseꢀtheꢀTOꢀandꢀPDFꢀ
flagsꢀremainꢀunchanged.
Rev. 1.10
ꢅ0ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Extended Instruction Set
Theꢀextendedꢀinstructionsꢀareꢀusedꢀtoꢀsupportꢀtheꢀfullꢀrangeꢀaddressꢀaccessꢀforꢀtheꢀdataꢀmemory.ꢀ
Whenꢀtheꢀaccessedꢀdataꢀmemoryꢀisꢀlocatedꢀinꢀanyꢀdataꢀmemoryꢀsectionsꢀexceptꢀsectorꢀ0,ꢀtheꢀ
extendedꢀinstructionꢀcanꢀbeꢀusedꢀtoꢀaccessꢀtheꢀdataꢀmemoryꢀinsteadꢀofꢀusingꢀtheꢀindirectꢀaddressingꢀ
accessꢀtoꢀimproveꢀtheꢀCPUꢀfirmwareꢀperformance.
Mnemonic
Arithmetic
LADD Aꢄ[m]
Description
Cycles
Flag Affected
Add Data Memoꢁꢂ to ACC
ꢅ
ꢅNote
ꢅ
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
LADDM Aꢄ[m] Add ACC to Data Memoꢁꢂ
LADC Aꢄ[m] Add Data Memoꢁꢂ to ACC with Caꢁꢁꢂ
LADCM Aꢄ[m] Add ACC to Data memoꢁꢂ with Caꢁꢁꢂ
LSUB Aꢄ[m] Sꢀbtꢁact Data Memoꢁꢂ fꢁom ACC
LSUBM Aꢄ[m] Sꢀbtꢁact Data Memoꢁꢂ fꢁom ACC with ꢁesꢀlt in Data Memoꢁꢂ
LSBC Aꢄ[m] Sꢀbtꢁact Data Memoꢁꢂ fꢁom ACC with Caꢁꢁꢂ
ꢅNote
ꢅ
ꢅNote Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
ꢅ
Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
LSBCM Aꢄ[m] Sꢀbtꢁact Data Memoꢁꢂ fꢁom ACC with Caꢁꢁꢂꢄ ꢁesꢀlt in Data Memoꢁꢂ ꢅNote Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
LDAA [m]
Decimal adjꢀst ACC foꢁ Addition with ꢁesꢀlt in Data Memoꢁꢂ
ꢅNote
C
Logic Operation
LAND Aꢄ[m]
LOR Aꢄ[m]
Logical AND Data Memoꢁꢂ to ACC
Logical OR Data Memoꢁꢂ to ACC
Logical XOR Data Memory to ACC
ꢅ
ꢅ
Z
Z
Z
Z
Z
Z
Z
Z
LXOR A,[m]
ꢅ
LANDM Aꢄ[m] Logical AND ACC to Data Memoꢁꢂ
LORM Aꢄ[m] Logical OR ACC to Data Memoꢁꢂ
LXORM A,[m] Logical XOR ACC to Data Memory
ꢅNote
ꢅNote
ꢅNote
ꢅNote
ꢅ
LCPL [m]
Complement Data Memoꢁꢂ
LCPLA [m]
Complement Data Memoꢁꢂ with ꢁesꢀlt in ACC
Increment & Decrement
LINCA [m]
LINC [m]
Incꢁement Data Memoꢁꢂ with ꢁesꢀlt in ACC
ꢅ
Z
Z
Z
Z
Incꢁement Data Memoꢁꢂ
ꢅNote
LDECA [m]
LDEC [m]
Rotate
Decꢁement Data Memoꢁꢂ with ꢁesꢀlt in ACC
Decꢁement Data Memoꢁꢂ
ꢅ
ꢅNote
LRRA [m]
LRR [m]
Rotate Data Memoꢁꢂ ꢁight with ꢁesꢀlt in ACC
Rotate Data Memoꢁꢂ ꢁight
ꢅ
ꢅNote
ꢅ
None
None
C
LRRCA [m]
LRRC [m]
LRLA [m]
Rotate Data Memoꢁꢂ ꢁight thꢁoꢀgh Caꢁꢁꢂ with ꢁesꢀlt in ACC
Rotate Data Memoꢁꢂ ꢁight thꢁoꢀgh Caꢁꢁꢂ
Rotate Data Memoꢁꢂ left with ꢁesꢀlt in ACC
Rotate Data Memoꢁꢂ left
ꢅNote
C
ꢅ
None
None
C
LRL [m]
ꢅNote
ꢅ
LRLCA [m]
LRLC [m]
Data Move
LMOV Aꢄ[m]
LMOV [m]ꢄA
Bit Operation
LCLR [m].i
LSET [m].i
Rotate Data Memoꢁꢂ left thꢁoꢀgh Caꢁꢁꢂ with ꢁesꢀlt in ACC
Rotate Data Memoꢁꢂ left thꢁoꢀgh Caꢁꢁꢂ
ꢅNote
C
Move Data Memoꢁꢂ to ACC
Move ACC to Data Memoꢁꢂ
ꢅ
ꢅNote
None
None
Cleaꢁ bit of Data Memoꢁꢂ
Set bit of Data Memoꢁꢂ
ꢅNote
ꢅNote
None
None
Rev. 1.10
ꢅ03
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Mnemonic
Description
Cycles Flag Affected
Branch
LSZ [m]
Skip if Data Memoꢁꢂ is zeꢁo
ꢅNote
ꢅNote
ꢅNote
ꢅNote
ꢅNote
ꢅNote
ꢅNote
ꢅNote
ꢅNote
None
None
None
None
None
None
None
None
None
LSZA [m]
LSNZ [m]
LSZ [m].i
LSNZ [m].i
LSIZ [m]
Skip if Data Memoꢁꢂ is zeꢁo with data movement to ACC
Skip if Data Memoꢁꢂ is not zeꢁo
Skip if bit i of Data Memoꢁꢂ is zeꢁo
Skip if bit i of Data Memoꢁꢂ is not zeꢁo
Skip if incꢁement Data Memoꢁꢂ is zeꢁo
LSDZ [m]
LSIZA [m]
LSDZA [m]
Table Read
Skip if decꢁement Data Memoꢁꢂ is zeꢁo
Skip if incꢁement Data Memoꢁꢂ is zeꢁo with ꢁesꢀlt in ACC
Skip if decꢁement Data Memoꢁꢂ is zeꢁo with ꢁesꢀlt in ACC
LTABRD [m] Read table to TBLH and Data Memoꢁꢂ
3Note
3Note
None
None
None
LTABRDL [m] Read table (last page) to TBLH and Data Memoꢁꢂ
LITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory 3Note
Increment table pointer TBLP first and Read table (last page) to TBLH and
Data Memoꢁꢂ
LITABRDL [m]
3Note
None
Miscellaneous
LCLR [m]
Cleaꢁ Data Memoꢁꢂ
ꢅNote
ꢅNote
ꢅNote
ꢅ
None
None
None
None
LSET [m]
Set Data Memoꢁꢂ
LSWAP [m]
Swap nibbles of Data Memoꢁꢂ
LSWAPA [m] Swap nibbles of Data Memoꢁꢂ with ꢁesꢀlt in ACC
Note:ꢀ1.ꢀForꢀtheseꢀextendedꢀskipꢀinstructions,ꢀifꢀtheꢀresultꢀofꢀtheꢀcomparisonꢀinvolvesꢀaꢀskipꢀthenꢀupꢀtoꢀfourꢀcyclesꢀ
areꢀrequired,ꢀifꢀnoꢀskipꢀtakesꢀplaceꢀtwoꢀcyclesꢀisꢀrequired.
2.ꢀAnyꢀextendedꢀinstructionꢀwhichꢀchangesꢀtheꢀcontentsꢀofꢀtheꢀPCLꢀregisterꢀwillꢀalsoꢀrequireꢀthreeꢀcyclesꢀforꢀ
execution.
Rev. 1.10
ꢅ0ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Instruction Definition
ꢀ
AddꢀDataꢀMemoryꢀtoꢀACCꢀwithꢀCarry
ADC A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemory,ꢀAccumulatorꢀandꢀtheꢀcarryꢀflagꢀareꢀadded.ꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ+ꢀ[m]ꢀ+ꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
ꢀ
AddꢀACCꢀtoꢀDataꢀMemoryꢀwithꢀCarry
ADCM A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemory,ꢀAccumulatorꢀandꢀtheꢀcarryꢀflagꢀareꢀadded.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀspecifiedꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ[m]ꢀ+ꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
ꢀ
AddꢀDataꢀMemoryꢀtoꢀACC
ADD A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀareꢀadded.ꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ+ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
AddꢀimmediateꢀdataꢀtoꢀACC
ADD A,x
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀimmediateꢀdataꢀareꢀadded.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ+ꢀx
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
ꢀ
AddꢀACCꢀtoꢀDataꢀMemory
ADDM A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀareꢀadded.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀspecifiedꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀANDꢀDataꢀMemoryꢀtoꢀACC
AND A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀlogicalꢀANDꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″AND″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
LogicalꢀANDꢀimmediateꢀdataꢀtoꢀACC
AND A,x
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀimmediateꢀdataꢀperformꢀaꢀbitꢀwiseꢀlogicalꢀANDꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″AND″ꢀx
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀANDꢀACCꢀtoꢀDataꢀMemory
ANDM A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀANDꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ″AND″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
Rev. 1.10
ꢅ05
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
ꢀ
Subroutineꢀcall
CALL addr
Descriptionꢀ
Unconditionallyꢀcallsꢀaꢀsubroutineꢀatꢀtheꢀspecifiedꢀaddress.ꢀTheꢀProgramꢀCounterꢀthenꢀ
incrementsꢀbyꢀ1ꢀtoꢀobtainꢀtheꢀaddressꢀofꢀtheꢀnextꢀinstructionꢀwhichꢀisꢀthenꢀpushedꢀontoꢀtheꢀ
stack.ꢀTheꢀspecifiedꢀaddressꢀisꢀthenꢀloadedꢀandꢀtheꢀprogramꢀcontinuesꢀexecutionꢀfromꢀthisꢀ
newꢀaddress.ꢀAsꢀthisꢀinstructionꢀrequiresꢀanꢀadditionalꢀoperation,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
Stackꢀ←ꢀProgramꢀCounterꢀ+ꢀ1ꢀ
ProgramꢀCounterꢀ←ꢀaddr
Affectedꢀflag(s)ꢀ
None
ꢀ
ClearꢀDataꢀMemory
CLR [m]
Descriptionꢀ
Operationꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀclearedꢀtoꢀ0.
[m]ꢀ←ꢀ00H
None
Affectedꢀflag(s)ꢀ
ClearꢀbitꢀofꢀDataꢀMemory
CLR [m].i
Descriptionꢀ
Operationꢀ
BitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀclearedꢀtoꢀ0.
[m].iꢀ←ꢀ0
None
Affectedꢀflag(s)ꢀ
ꢀ
ClearꢀWatchdogꢀTimer
CLR WDT
Descriptionꢀ
TheꢀTO,ꢀPDFꢀflagsꢀandꢀtheꢀWDTꢀareꢀallꢀcleared.ꢀ
Operationꢀ
ꢀ
ꢀ
WDTꢀclearedꢀ
TOꢀ←ꢀ0ꢀ
PDFꢀ←ꢀ0
Affectedꢀflag(s)ꢀ
TO,ꢀPDF
ComplementꢀDataꢀMemory
CPL [m]
Descriptionꢀ
ꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀlogicallyꢀcomplementedꢀ(1′sꢀcomplement).ꢀBitsꢀwhichꢀ
previouslyꢀcontainedꢀaꢀ1ꢀareꢀchangedꢀtoꢀ0ꢀandꢀviceꢀversa.
Operationꢀ
[m]ꢀ←ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
ComplementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
CPLA [m]
Descriptionꢀ
ꢀ
ꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀlogicallyꢀcomplementedꢀ(1′sꢀcomplement).ꢀBitsꢀwhichꢀ
previouslyꢀcontainedꢀaꢀ1ꢀareꢀchangedꢀtoꢀ0ꢀandꢀviceꢀversa.ꢀTheꢀcomplementedꢀresultꢀisꢀstoredꢀinꢀ
theꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ACCꢀ←ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
Decimal-AdjustꢀACCꢀforꢀadditionꢀwithꢀresultꢀinꢀDataꢀMemory
DAA [m]
Descriptionꢀ
ConvertꢀtheꢀcontentsꢀofꢀtheꢀAccumulatorꢀvalueꢀtoꢀaꢀBCDꢀ(BinaryꢀCodedꢀDecimal)ꢀvalueꢀ
resultingꢀfromꢀtheꢀpreviousꢀadditionꢀofꢀtwoꢀBCDꢀvariables.ꢀIfꢀtheꢀlowꢀnibbleꢀisꢀgreaterꢀthanꢀ9ꢀ
orꢀifꢀACꢀflagꢀisꢀset,ꢀthenꢀaꢀvalueꢀofꢀ6ꢀwillꢀbeꢀaddedꢀtoꢀtheꢀlowꢀnibble.ꢀOtherwiseꢀtheꢀlowꢀnibbleꢀ
remainsꢀunchanged.ꢀIfꢀtheꢀhighꢀnibbleꢀisꢀgreaterꢀthanꢀ9ꢀorꢀifꢀtheꢀCꢀflagꢀisꢀset,ꢀthenꢀaꢀvalueꢀofꢀ6ꢀ
willꢀbeꢀaddedꢀtoꢀtheꢀhighꢀnibble.ꢀEssentially,ꢀtheꢀdecimalꢀconversionꢀisꢀperformedꢀbyꢀaddingꢀ
00H,ꢀ06H,ꢀ60Hꢀorꢀ66HꢀdependingꢀonꢀtheꢀAccumulatorꢀandꢀflagꢀconditions.ꢀOnlyꢀtheꢀCꢀflagꢀ
mayꢀbeꢀaffectedꢀbyꢀthisꢀinstructionꢀwhichꢀindicatesꢀthatꢀifꢀtheꢀoriginalꢀBCDꢀsumꢀisꢀgreaterꢀthanꢀ
100,ꢀitꢀallowsꢀmultipleꢀprecisionꢀdecimalꢀaddition.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Operationꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ00Hꢀorꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ06Hꢀorꢀꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ60Hꢀorꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ66H
ꢀ
ꢀ
ꢀ
Affectedꢀflag(s)ꢀ
C
Rev. 1.10
ꢅ06
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
ꢀ
DecrementꢀDataꢀMemory
DEC [m]
Descriptionꢀ
Operationꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀdecrementedꢀbyꢀ1.
[m]ꢀ←ꢀ[m]ꢀ−ꢀ1
Z
Affectedꢀflag(s)ꢀ
ꢀ
DecrementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
DECA [m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀdecrementedꢀbyꢀ1.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀ
Accumulator.ꢀTheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ACCꢀ←ꢀ[m]ꢀ−ꢀ1
Z
Affectedꢀflag(s)ꢀ
ꢀ
Enterꢀpowerꢀdownꢀmode
HALT
Descriptionꢀ
ꢀ
ꢀ
Thisꢀinstructionꢀstopsꢀtheꢀprogramꢀexecutionꢀandꢀturnsꢀoffꢀtheꢀsystemꢀclock.ꢀTheꢀcontentsꢀofꢀꢀ
theꢀDataꢀMemoryꢀandꢀregistersꢀareꢀretained.ꢀTheꢀWDTꢀandꢀprescalerꢀareꢀcleared.ꢀTheꢀpowerꢀ
downꢀflagꢀPDFꢀisꢀsetꢀandꢀtheꢀWDTꢀtime-outꢀflagꢀTOꢀisꢀcleared.
Operationꢀ
ꢀ
TOꢀ←ꢀ0ꢀ
PDFꢀ←ꢀ1
Affectedꢀflag(s)ꢀ
TO,ꢀPDF
ꢀ
IncrementꢀDataꢀMemoryꢀ
INC [m]
Descriptionꢀ
Operationꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀincrementedꢀbyꢀ1.
[m]ꢀ←ꢀ[m]ꢀ+ꢀ1
Z
Affectedꢀflag(s)ꢀ
IncrementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
INCA [m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀincrementedꢀbyꢀ1.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀ
TheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ACCꢀ←ꢀ[m]ꢀ+ꢀ1
Z
Affectedꢀflag(s)ꢀ
Jumpꢀunconditionally
JMP addr
Descriptionꢀ
ꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀProgramꢀCounterꢀareꢀreplacedꢀwithꢀtheꢀspecifiedꢀaddress.ꢀProgramꢀ
executionꢀthenꢀcontinuesꢀfromꢀthisꢀnewꢀaddress.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ
instructionꢀwhileꢀtheꢀnewꢀaddressꢀisꢀloaded,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.
Operationꢀ
ProgramꢀCounterꢀ←ꢀaddr
None
Affectedꢀflag(s)ꢀ
ꢀ
MoveꢀDataꢀMemoryꢀtoꢀACC
MOV A,[m]
Descriptionꢀ
Operationꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀcopiedꢀtoꢀtheꢀAccumulator.
ACCꢀ←ꢀ[m]
None
Affectedꢀflag(s)ꢀ
MoveꢀimmediateꢀdataꢀtoꢀACC
MOV A,x
Descriptionꢀ
Operationꢀ
TheꢀimmediateꢀdataꢀspecifiedꢀisꢀloadedꢀintoꢀtheꢀAccumulator.
ACCꢀ←ꢀx
None
Affectedꢀflag(s)ꢀ
ꢀ
MoveꢀACCꢀtoꢀDataꢀMemoryꢀ
MOV [m],A
Descriptionꢀ
Operationꢀ
TheꢀcontentsꢀofꢀtheꢀAccumulatorꢀareꢀcopiedꢀtoꢀtheꢀspecifiedꢀDataꢀMemory.
[m]ꢀ←ꢀACC
None
Affectedꢀflag(s)ꢀ
Rev. 1.10
ꢅ07
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
ꢀ
Noꢀoperation
NOP
Descriptionꢀ
Operationꢀ
Noꢀoperationꢀisꢀperformed.ꢀExecutionꢀcontinuesꢀwithꢀtheꢀnextꢀinstruction.
Noꢀoperation
None
Affectedꢀflag(s)ꢀ
LogicalꢀORꢀDataꢀMemoryꢀtoꢀACC
OR A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀ
logicalꢀORꢀoperation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″OR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀORꢀimmediateꢀdataꢀtoꢀACC
OR A,x
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀimmediateꢀdataꢀperformꢀaꢀbitwiseꢀlogicalꢀORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″OR″ꢀx
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀORꢀACCꢀtoꢀDataꢀMemory
ORM A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ″OR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
Returnꢀfromꢀsubroutine
RET
Descriptionꢀ
ꢀ
TheꢀProgramꢀCounterꢀisꢀrestoredꢀfromꢀtheꢀstack.ꢀProgramꢀexecutionꢀcontinuesꢀatꢀtheꢀrestoredꢀ
address.
Operationꢀ
ProgramꢀCounterꢀ←ꢀStack
None
Affectedꢀflag(s)ꢀ
ꢀ
ReturnꢀfromꢀsubroutineꢀandꢀloadꢀimmediateꢀdataꢀtoꢀACC
RET A,x
Descriptionꢀ
ꢀ
TheꢀProgramꢀCounterꢀisꢀrestoredꢀfromꢀtheꢀstackꢀandꢀtheꢀAccumulatorꢀloadedꢀwithꢀtheꢀspecifiedꢀ
immediateꢀdata.ꢀProgramꢀexecutionꢀcontinuesꢀatꢀtheꢀrestoredꢀaddress.
Operationꢀ
ꢀ
ProgramꢀCounterꢀ←ꢀStackꢀ
ACCꢀ←ꢀx
Affectedꢀflag(s)ꢀ
None
ꢀ
Returnꢀfromꢀinterrupt
RETI
Descriptionꢀ
TheꢀProgramꢀCounterꢀisꢀrestoredꢀfromꢀtheꢀstackꢀandꢀtheꢀinterruptsꢀareꢀre-enabledꢀbyꢀsettingꢀtheꢀ
EMIꢀbit.ꢀEMIꢀisꢀtheꢀmasterꢀinterruptꢀglobalꢀenableꢀbit.ꢀIfꢀanꢀinterruptꢀwasꢀpendingꢀwhenꢀtheꢀꢀ
RETIꢀinstructionꢀisꢀexecuted,ꢀtheꢀpendingꢀInterruptꢀroutineꢀwillꢀbeꢀprocessedꢀbeforeꢀreturningꢀꢀ
toꢀtheꢀmainꢀprogram.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ProgramꢀCounterꢀ←ꢀStackꢀ
EMIꢀ←ꢀ1
Affectedꢀflag(s)ꢀ
None
ꢀ
RotateꢀDataꢀMemoryꢀleft
RL [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ7ꢀrotatedꢀintoꢀbitꢀ0.
Operationꢀ
ꢀ
[m].(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
[m].0ꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
None
Rev. 1.10
ꢅ0ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
RotateꢀDataꢀMemoryꢀleftꢀwithꢀresultꢀinꢀACC
RLA [m]
Descriptionꢀ
ꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ7ꢀrotatedꢀintoꢀbitꢀ0.ꢀ
TheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀ
unchanged.
Operationꢀ
ꢀ
ACC.(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
ACC.0ꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀleftꢀthroughꢀCarry
RLC [m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbit.ꢀBitꢀ7ꢀ
replacesꢀtheꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀbitꢀ0.
Operationꢀ
ꢀ
ꢀ
[m].(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
[m].0ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
C
ꢀ
RotateꢀDataꢀMemoryꢀleftꢀthroughꢀCarryꢀwithꢀresultꢀinꢀACC
RLCA [m]
Descriptionꢀ
ꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbit.ꢀBitꢀ7ꢀreplacesꢀtheꢀ
Carryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀtheꢀbitꢀ0.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀ
AccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ꢀ
ACC.(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
ACC.0ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
C
RotateꢀDataꢀMemoryꢀright
RR [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ0ꢀrotatedꢀintoꢀbitꢀ7.
Operationꢀ
ꢀ
[m].iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
[m].7ꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀrightꢀwithꢀresultꢀinꢀACC
RRA [m]
Descriptionꢀ
ꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀrotatedꢀrightꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ0ꢀ
rotatedꢀintoꢀbitꢀ7.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀ
DataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ACC.iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
ACC.7ꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀrightꢀthroughꢀCarry
RRC [m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbit.ꢀBitꢀ0ꢀ
replacesꢀtheꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀbitꢀ7.
Operationꢀ
ꢀ
ꢀ
[m].iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
[m].7ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
C
Rev. 1.10
ꢅ09
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
ꢀ
RotateꢀDataꢀMemoryꢀrightꢀthroughꢀCarryꢀwithꢀresultꢀinꢀACC
RRCA [m]
Descriptionꢀ
ꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbit.ꢀBitꢀ0ꢀreplacesꢀꢀ
theꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀbitꢀ7.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀꢀ
AccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ꢀ
ACC.iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
ACC.7ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
C
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀCarry
SBC A,[m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcomplementꢀofꢀtheꢀcarryꢀflagꢀareꢀ
subtractedꢀfromꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀꢀ
resultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀ
positiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
ꢀ
ꢀ
ꢀ
Operationꢀ
ACCꢀ←ꢀACCꢀ−ꢀ[m]ꢀ−ꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
Affectedꢀflag(s)ꢀ
ꢀ
SubtractꢀimmediateꢀdataꢀfromꢀACCꢀwithꢀCarry
SBC A, x
Descriptionꢀ
Theꢀimmediateꢀdataꢀandꢀtheꢀcomplementꢀofꢀtheꢀcarryꢀflagꢀareꢀsubtractedꢀfromꢀtheꢀꢀ
Accumulator.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀꢀ
negative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀꢀ
willꢀbeꢀsetꢀtoꢀ1.
ꢀ
ꢀ
ꢀ
Operationꢀ
ACCꢀ←ꢀACCꢀ−ꢀ[m]ꢀ−ꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
Affectedꢀflag(s)ꢀ
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀCarryꢀandꢀresultꢀinꢀDataꢀMemory
SBCM A,[m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcomplementꢀofꢀtheꢀcarryꢀflagꢀareꢀꢀ
subtractedꢀfromꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.ꢀNoteꢀthatꢀifꢀtheꢀꢀ
resultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀꢀ
positiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
ꢀ
ꢀ
ꢀ
Operationꢀ
[m]ꢀ←ꢀACCꢀ−ꢀ[m]ꢀ−ꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
Affectedꢀflag(s)ꢀ
SkipꢀifꢀdecrementꢀDataꢀMemoryꢀisꢀ0
SDZ [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀdecrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀꢀ
followingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀꢀ
theꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀꢀ
proceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
[m]ꢀ←ꢀ[m]ꢀ−ꢀ1ꢀ
Skipꢀifꢀ[m]=0
Affectedꢀflag(s)ꢀ
None
ꢀ
SkipꢀifꢀdecrementꢀDataꢀMemoryꢀisꢀzeroꢀwithꢀresultꢀinꢀACC
SDZA [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀdecrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀꢀ
followingꢀinstructionꢀisꢀskipped.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀbutꢀtheꢀspecifiedꢀꢀ
DataꢀMemoryꢀcontentsꢀremainꢀunchanged.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ
instructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0,ꢀ
theꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ACCꢀ←ꢀ[m]ꢀ−ꢀ1ꢀ
SkipꢀifꢀACC=0
Affectedꢀflag(s)ꢀ
None
Rev. 1.10
ꢅ10
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
ꢀ
SetꢀDataꢀMemory
SET [m]
Descriptionꢀ
Operationꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀsetꢀtoꢀ1.
[m]ꢀ←ꢀFFH
None
Affectedꢀflag(s)ꢀ
SetꢀbitꢀofꢀDataꢀMemory
SET [m].i
Descriptionꢀ
Operationꢀ
BitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀsetꢀtoꢀ1.
[m].iꢀ←ꢀ1
None
Affectedꢀflag(s)ꢀ
SkipꢀifꢀincrementꢀDataꢀMemoryꢀisꢀ0
SIZ [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀincrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀ
followingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀꢀ
theꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀ
proceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
[m]ꢀ←ꢀ[m]ꢀ+ꢀ1ꢀ
Skipꢀifꢀ[m]=0ꢀ
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀincrementꢀDataꢀMemoryꢀisꢀzeroꢀwithꢀresultꢀinꢀACC
SIZA [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀincrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀꢀ
followingꢀinstructionꢀisꢀskipped.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀbutꢀtheꢀspecifiedꢀ
DataꢀMemoryꢀcontentsꢀremainꢀunchanged.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ
instructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ
0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ACCꢀ←ꢀ[m]ꢀ+ꢀ1ꢀ
SkipꢀifꢀACC=0
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀDataꢀMemoryꢀisꢀnotꢀ0
SNZ [m].i
Descriptionꢀ
ꢀ
ꢀ
IfꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀnotꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀ
insertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀꢀ
instruction.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m].iꢀ≠ꢀ0
None
Affectedꢀflag(s)ꢀ
SkipꢀifꢀDataꢀMemoryꢀisꢀnotꢀ0
SNZ [m]
Descriptionꢀ
ꢀ
ꢀ
IfꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀnotꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀ
insertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀꢀ
instruction.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m]≠ꢀ0
None
Affectedꢀflag(s)ꢀ
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACC
SUB A,[m]
Descriptionꢀ
ꢀ
ꢀ
TheꢀspecifiedꢀDataꢀMemoryꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀꢀ
storedꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀꢀ
clearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
Operationꢀ
ACCꢀ←ꢀACCꢀ−ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
Affectedꢀflag(s)ꢀ
Rev. 1.10
ꢅ11
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀresultꢀinꢀDataꢀMemory
SUBM A,[m]
Descriptionꢀ
ꢀ
ꢀ
TheꢀspecifiedꢀDataꢀMemoryꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀꢀ
storedꢀinꢀtheꢀDataꢀMemory.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀꢀ
clearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
Operationꢀ
[m]ꢀ←ꢀACCꢀ−ꢀ[m]
Affectedꢀflag(s)ꢀ
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
SubtractꢀimmediateꢀdataꢀfromꢀACC
SUB A,x
Descriptionꢀ
ꢀ
ꢀ
TheꢀimmediateꢀdataꢀspecifiedꢀbyꢀtheꢀcodeꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀꢀ
flagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
Operationꢀ
ACCꢀ←ꢀACCꢀ−ꢀx
Affectedꢀflag(s)ꢀ
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
SwapꢀnibblesꢀofꢀDataꢀMemory
SWAP [m]
Descriptionꢀ
Operationꢀ
Theꢀlow-orderꢀandꢀhigh-orderꢀnibblesꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀinterchanged.
[m].3~[m].0ꢀ↔ꢀ[m].7~[m].4
None
Affectedꢀflag(s)ꢀ
ꢀ
SwapꢀnibblesꢀofꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
SWAPA [m]
Descriptionꢀ
ꢀ
Theꢀlow-orderꢀandꢀhigh-orderꢀnibblesꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀinterchanged.ꢀTheꢀꢀ
resultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀTheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ACC.3~ACC.0ꢀ←ꢀ[m].7~[m].4ꢀ
ACC.7~ACC.4ꢀ←ꢀ[m].3~[m].0
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀDataꢀMemoryꢀisꢀ0
SZ [m]
Descriptionꢀ
ꢀ
ꢀ
IfꢀtheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀꢀ
requiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀꢀ
cycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m]=0
None
Affectedꢀflag(s)ꢀ
SkipꢀifꢀDataꢀMemoryꢀisꢀ0ꢀwithꢀdataꢀmovementꢀtoꢀACC
SZA [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀcopiedꢀtoꢀtheꢀAccumulator.ꢀIfꢀtheꢀvalueꢀisꢀzero,ꢀꢀ
theꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀꢀ
whileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀꢀ
programꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ACCꢀ←ꢀ[m]ꢀ
Skipꢀifꢀ[m]=0
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀbitꢀiꢀofꢀDataꢀMemoryꢀisꢀ0
SZ [m].i
Descriptionꢀ
ꢀ
ꢀ
IfꢀbitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀ
theꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀ
instruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0,ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m].i=0
None
Affectedꢀflag(s)ꢀ
Rev. 1.10
ꢅ1ꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
ꢀ
Readꢀtableꢀ(specificꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory
TABRD [m]
Descriptionꢀ
ꢀ
Theꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀ(specificꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀpairꢀꢀ
(TBLPꢀandꢀTBHP)ꢀisꢀmovedꢀtoꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.
Operationꢀ
ꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)ꢀ
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
Affectedꢀflag(s)ꢀ
None
Readꢀtableꢀ(lastꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory
TABRDL [m]
Descriptionꢀ
ꢀ
Theꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀ(lastꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀ(TBLP)ꢀisꢀmovedꢀꢀ
toꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.
Operationꢀ
ꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)ꢀ
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
Affectedꢀflag(s)ꢀ
None
ꢀ
IncrementꢀtableꢀpointerꢀlowꢀbyteꢀfirstꢀandꢀreadꢀtableꢀtoꢀTBLHꢀandꢀDataꢀMemory
ITABRD [m]
Descriptionꢀ
ꢀ
ꢀ
Incrementꢀtableꢀpointerꢀlowꢀbyte,ꢀTBLP,ꢀfirstꢀandꢀthenꢀtheꢀprogramꢀcodeꢀaddressedꢀbyꢀtheꢀꢀ
tableꢀpointerꢀ(TBHPꢀandꢀTBLP)ꢀisꢀmovedꢀtoꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀꢀ
movedꢀtoꢀTBLH.
Operationꢀ
ꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
None
Affectedꢀflag(s)ꢀ
ꢀ
Incrementꢀtableꢀpointerꢀlowꢀbyteꢀfirstꢀandꢀreadꢀtableꢀ(lastꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory
ITABRDL [m]
Descriptionꢀ
ꢀ
ꢀ
Incrementꢀtableꢀpointerꢀlowꢀbyte,ꢀTBLP,ꢀfirstꢀandꢀthenꢀtheꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀꢀ
(lastꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀ(TBLP)ꢀisꢀmovedꢀtoꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀꢀ
theꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.
Operationꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
None
ꢀ
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀXORꢀDataꢀMemoryꢀtoꢀACC
XOR A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″XOR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀXORꢀACCꢀtoꢀDataꢀMemory
XORM A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ″XOR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
LogicalꢀXORꢀimmediateꢀdataꢀtoꢀACC
XOR A,x
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀimmediateꢀdataꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″XOR″ꢀx
Z
Affectedꢀflag(s)ꢀ
Rev. 1.10
ꢅ13
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Extended Instruction Definition
Theꢀextendedꢀinstructionsꢀareꢀusedꢀtoꢀdirectlyꢀaccessꢀtheꢀdataꢀstoredꢀinꢀanyꢀdataꢀmemoryꢀsections.
ꢀ
AddꢀDataꢀMemoryꢀtoꢀACCꢀwithꢀCarry
LADC A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemory,ꢀAccumulatorꢀandꢀtheꢀcarryꢀflagꢀareꢀadded.ꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ+ꢀ[m]ꢀ+ꢀC
Affectedꢀflag(s)ꢀ
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
ꢀ
AddꢀACCꢀtoꢀDataꢀMemoryꢀwithꢀCarry
LADCM A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemory,ꢀAccumulatorꢀandꢀtheꢀcarryꢀflagꢀareꢀadded.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀspecifiedꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ[m]ꢀ+ꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
ꢀ
AddꢀDataꢀMemoryꢀtoꢀACC
LADD A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀareꢀadded.ꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ+ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
ꢀ
AddꢀACCꢀtoꢀDataꢀMemory
LADDM A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀareꢀadded.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀspecifiedꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀANDꢀDataꢀMemoryꢀtoꢀACC
LAND A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀlogicalꢀANDꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″AND″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀANDꢀACCꢀtoꢀDataꢀMemory
LANDM A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀANDꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ″AND″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
ClearꢀDataꢀMemory
LCLR [m]
Descriptionꢀ
Operationꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀclearedꢀtoꢀ0.
[m]ꢀ←ꢀ00H
None
Affectedꢀflag(s)ꢀ
ClearꢀbitꢀofꢀDataꢀMemory
LCLR [m].i
Descriptionꢀ
Operationꢀ
BitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀclearedꢀtoꢀ0.
[m].iꢀ←ꢀ0
None
Affectedꢀflag(s)ꢀ
Rev. 1.10
ꢅ1ꢃ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
ComplementꢀDataꢀMemory
LCPL [m]
Descriptionꢀ
ꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀlogicallyꢀcomplementedꢀ(1′sꢀcomplement).ꢀBitsꢀwhichꢀ
previouslyꢀcontainedꢀaꢀ1ꢀareꢀchangedꢀtoꢀ0ꢀandꢀviceꢀversa.
Operationꢀ
[m]ꢀ←ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
ComplementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
LCPLA [m]
Descriptionꢀ
ꢀ
ꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀlogicallyꢀcomplementedꢀ(1′sꢀcomplement).ꢀBitsꢀwhichꢀ
previouslyꢀcontainedꢀaꢀ1ꢀareꢀchangedꢀtoꢀ0ꢀandꢀviceꢀversa.ꢀTheꢀcomplementedꢀresultꢀisꢀstoredꢀinꢀ
theꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ACCꢀ←ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
Decimal-AdjustꢀACCꢀforꢀadditionꢀwithꢀresultꢀinꢀDataꢀMemory
LDAA [m]
Descriptionꢀ
ConvertꢀtheꢀcontentsꢀofꢀtheꢀAccumulatorꢀvalueꢀtoꢀaꢀBCDꢀ(BinaryꢀCodedꢀDecimal)ꢀvalueꢀ
resultingꢀfromꢀtheꢀpreviousꢀadditionꢀofꢀtwoꢀBCDꢀvariables.ꢀIfꢀtheꢀlowꢀnibbleꢀisꢀgreaterꢀthanꢀ9ꢀ
orꢀifꢀACꢀflagꢀisꢀset,ꢀthenꢀaꢀvalueꢀofꢀ6ꢀwillꢀbeꢀaddedꢀtoꢀtheꢀlowꢀnibble.ꢀOtherwiseꢀtheꢀlowꢀnibbleꢀ
remainsꢀunchanged.ꢀIfꢀtheꢀhighꢀnibbleꢀisꢀgreaterꢀthanꢀ9ꢀorꢀifꢀtheꢀCꢀflagꢀisꢀset,ꢀthenꢀaꢀvalueꢀofꢀ6ꢀ
willꢀbeꢀaddedꢀtoꢀtheꢀhighꢀnibble.ꢀEssentially,ꢀtheꢀdecimalꢀconversionꢀisꢀperformedꢀbyꢀaddingꢀ
00H,ꢀ06H,ꢀ60Hꢀorꢀ66HꢀdependingꢀonꢀtheꢀAccumulatorꢀandꢀflagꢀconditions.ꢀOnlyꢀtheꢀCꢀflagꢀ
mayꢀbeꢀaffectedꢀbyꢀthisꢀinstructionꢀwhichꢀindicatesꢀthatꢀifꢀtheꢀoriginalꢀBCDꢀsumꢀisꢀgreaterꢀthanꢀ
100,ꢀitꢀallowsꢀmultipleꢀprecisionꢀdecimalꢀaddition.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Operationꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ00Hꢀorꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ06Hꢀorꢀꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ60Hꢀorꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ66H
ꢀ
ꢀ
ꢀ
Affectedꢀflag(s)ꢀ
C
ꢀ
DecrementꢀDataꢀMemory
LDEC [m]
Descriptionꢀ
Operationꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀdecrementedꢀbyꢀ1.
[m]ꢀ←ꢀ[m]ꢀ−ꢀ1
Z
Affectedꢀflag(s)ꢀ
ꢀ
DecrementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
LDECA [m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀdecrementedꢀbyꢀ1.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀ
Accumulator.ꢀTheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ACCꢀ←ꢀ[m]ꢀ−ꢀ1
Z
Affectedꢀflag(s)ꢀ
ꢀ
IncrementꢀDataꢀMemoryꢀ
LINC [m]
Descriptionꢀ
Operationꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀincrementedꢀbyꢀ1.
[m]ꢀ←ꢀ[m]ꢀ+ꢀ1
Z
Affectedꢀflag(s)ꢀ
IncrementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
LINCA [m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀincrementedꢀbyꢀ1.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀ
TheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ACCꢀ←ꢀ[m]ꢀ+ꢀ1
Z
Affectedꢀflag(s)ꢀ
Rev. 1.10
ꢅ15
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
ꢀ
MoveꢀDataꢀMemoryꢀtoꢀACC
LMOV A,[m]
Descriptionꢀ
Operationꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀcopiedꢀtoꢀtheꢀAccumulator.
ACCꢀ←ꢀ[m]
None
Affectedꢀflag(s)ꢀ
ꢀ
MoveꢀACCꢀtoꢀDataꢀMemoryꢀ
LMOV [m],A
Descriptionꢀ
Operationꢀ
TheꢀcontentsꢀofꢀtheꢀAccumulatorꢀareꢀcopiedꢀtoꢀtheꢀspecifiedꢀDataꢀMemory.
[m]ꢀ←ꢀACC
None
Affectedꢀflag(s)ꢀ
LogicalꢀORꢀDataꢀMemoryꢀtoꢀACC
LOR A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀ
logicalꢀORꢀoperation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″OR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀORꢀACCꢀtoꢀDataꢀMemory
LORM A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ″OR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
RotateꢀDataꢀMemoryꢀleft
LRL [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ7ꢀrotatedꢀintoꢀbitꢀ0.
Operationꢀ
ꢀ
[m].(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
[m].0ꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀleftꢀwithꢀresultꢀinꢀACC
LRLA [m]
Descriptionꢀ
ꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ7ꢀrotatedꢀintoꢀbitꢀ0.ꢀ
TheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀ
unchanged.
Operationꢀ
ꢀ
ACC.(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
ACC.0ꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀleftꢀthroughꢀCarry
LRLC [m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbit.ꢀBitꢀ7ꢀ
replacesꢀtheꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀbitꢀ0.
Operationꢀ
ꢀ
ꢀ
[m].(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
[m].0ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
C
ꢀ
RotateꢀDataꢀMemoryꢀleftꢀthroughꢀCarryꢀwithꢀresultꢀinꢀACC
LRLCA [m]
Descriptionꢀ
ꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbit.ꢀBitꢀ7ꢀreplacesꢀtheꢀ
Carryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀtheꢀbitꢀ0.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀ
AccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ꢀ
ACC.(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
ACC.0ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
C
Rev. 1.10
ꢅ16
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
RotateꢀDataꢀMemoryꢀright
LRR [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ0ꢀrotatedꢀintoꢀbitꢀ7.
Operationꢀ
ꢀ
[m].iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
[m].7ꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀrightꢀwithꢀresultꢀinꢀACC
LRRA [m]
Descriptionꢀ
ꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀrotatedꢀrightꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ0ꢀ
rotatedꢀintoꢀbitꢀ7.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀ
DataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ACC.iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
ACC.7ꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀrightꢀthroughꢀCarry
LRRC [m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbit.ꢀBitꢀ0ꢀ
replacesꢀtheꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀbitꢀ7.
Operationꢀ
ꢀ
ꢀ
[m].iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
[m].7ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
C
ꢀ
RotateꢀDataꢀMemoryꢀrightꢀthroughꢀCarryꢀwithꢀresultꢀinꢀACC
LRRCA [m]
Descriptionꢀ
ꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbit.ꢀBitꢀ0ꢀreplacesꢀꢀ
theꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀbitꢀ7.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀꢀ
AccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ꢀ
ACC.iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
ACC.7ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
C
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀCarry
LSBC A,[m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcomplementꢀofꢀtheꢀcarryꢀflagꢀareꢀ
subtractedꢀfromꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀꢀ
resultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀ
positiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
ꢀ
ꢀ
ꢀ
Operationꢀ
ACCꢀ←ꢀACCꢀ−ꢀ[m]ꢀ−ꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
Affectedꢀflag(s)ꢀ
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀCarryꢀandꢀresultꢀinꢀDataꢀMemory
LSBCM A,[m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcomplementꢀofꢀtheꢀcarryꢀflagꢀareꢀꢀ
subtractedꢀfromꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.ꢀNoteꢀthatꢀifꢀtheꢀꢀ
resultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀꢀ
positiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
ꢀ
ꢀ
ꢀ
Operationꢀ
[m]ꢀ←ꢀACCꢀ−ꢀ[m]ꢀ−ꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
Affectedꢀflag(s)ꢀ
Rev. 1.10
ꢅ17
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
SkipꢀifꢀdecrementꢀDataꢀMemoryꢀisꢀ0
LSDZ [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀdecrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀꢀ
followingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀꢀ
theꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀꢀ
proceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
[m]ꢀ←ꢀ[m]ꢀ−ꢀ1ꢀ
Skipꢀifꢀ[m]=0
Affectedꢀflag(s)ꢀ
None
ꢀ
SkipꢀifꢀdecrementꢀDataꢀMemoryꢀisꢀzeroꢀwithꢀresultꢀinꢀACC
LSDZA [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀdecrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀꢀ
followingꢀinstructionꢀisꢀskipped.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀbutꢀtheꢀspecifiedꢀꢀ
DataꢀMemoryꢀcontentsꢀremainꢀunchanged.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ
instructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0,ꢀ
theꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ACCꢀ←ꢀ[m]ꢀ−ꢀ1ꢀ
SkipꢀifꢀACC=0
Affectedꢀflag(s)ꢀ
None
ꢀ
SetꢀDataꢀMemory
LSET [m]
Descriptionꢀ
Operationꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀsetꢀtoꢀ1.
[m]ꢀ←ꢀFFH
None
Affectedꢀflag(s)ꢀ
SetꢀbitꢀofꢀDataꢀMemory
LSET [m].i
Descriptionꢀ
Operationꢀ
BitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀsetꢀtoꢀ1.
[m].iꢀ←ꢀ1
None
Affectedꢀflag(s)ꢀ
SkipꢀifꢀincrementꢀDataꢀMemoryꢀisꢀ0
LSIZ [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀincrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀ
followingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀꢀ
theꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀ
proceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
[m]ꢀ←ꢀ[m]ꢀ+ꢀ1ꢀ
Skipꢀifꢀ[m]=0ꢀ
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀincrementꢀDataꢀMemoryꢀisꢀzeroꢀwithꢀresultꢀinꢀACC
LSIZA [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀincrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀꢀ
followingꢀinstructionꢀisꢀskipped.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀbutꢀtheꢀspecifiedꢀ
DataꢀMemoryꢀcontentsꢀremainꢀunchanged.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ
instructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ
0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ACCꢀ←ꢀ[m]ꢀ+ꢀ1ꢀ
SkipꢀifꢀACC=0
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀDataꢀMemoryꢀisꢀnotꢀ0
LSNZ [m].i
Descriptionꢀ
ꢀ
ꢀ
IfꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀnotꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀ
insertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀꢀ
instruction.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m].iꢀ≠ꢀ0
None
Affectedꢀflag(s)ꢀ
Rev. 1.10
ꢅ1ꢆ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
SkipꢀifꢀDataꢀMemoryꢀisꢀnotꢀ0
LSNZ [m]
Descriptionꢀ
ꢀ
ꢀ
IfꢀꢀtheꢀcontentꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀnotꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀꢀ
thisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀꢀ
twoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m]ꢀ≠ꢀ0
None
Affectedꢀflag(s)ꢀ
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACC
LSUB A,[m]
Descriptionꢀ
ꢀ
ꢀ
TheꢀspecifiedꢀDataꢀMemoryꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀꢀ
storedꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀꢀ
clearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
Operationꢀ
ACCꢀ←ꢀACCꢀ−ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
Affectedꢀflag(s)ꢀ
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀresultꢀinꢀDataꢀMemory
LSUBM A,[m]
Descriptionꢀ
ꢀ
ꢀ
TheꢀspecifiedꢀDataꢀMemoryꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀꢀ
storedꢀinꢀtheꢀDataꢀMemory.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀꢀ
clearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
Operationꢀ
[m]ꢀ←ꢀACCꢀ−ꢀ[m]
Affectedꢀflag(s)ꢀ
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
SwapꢀnibblesꢀofꢀDataꢀMemory
LSWAP [m]
Descriptionꢀ
Operationꢀ
Theꢀlow-orderꢀandꢀhigh-orderꢀnibblesꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀinterchanged.
[m].3~[m].0ꢀ↔ꢀ[m].7~[m].4
None
Affectedꢀflag(s)ꢀ
ꢀ
SwapꢀnibblesꢀofꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
LSWAPA [m]
Descriptionꢀ
ꢀ
Theꢀlow-orderꢀandꢀhigh-orderꢀnibblesꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀinterchanged.ꢀTheꢀꢀ
resultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀTheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ACC.3~ACC.0ꢀ←ꢀ[m].7~[m].4ꢀ
ACC.7~ACC.4ꢀ←ꢀ[m].3~[m].0
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀDataꢀMemoryꢀisꢀ0
LSZ [m]
Descriptionꢀ
ꢀ
ꢀ
IfꢀtheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀꢀ
requiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀꢀ
cycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m]=0
None
Affectedꢀflag(s)ꢀ
SkipꢀifꢀDataꢀMemoryꢀisꢀ0ꢀwithꢀdataꢀmovementꢀtoꢀACC
LSZA [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀcopiedꢀtoꢀtheꢀAccumulator.ꢀIfꢀtheꢀvalueꢀisꢀzero,ꢀꢀ
theꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀꢀ
whileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀꢀ
programꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ACCꢀ←ꢀ[m]ꢀ
Skipꢀifꢀ[m]=0
Affectedꢀflag(s)ꢀ
None
Rev. 1.10
ꢅ19
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
SkipꢀifꢀbitꢀiꢀofꢀDataꢀMemoryꢀisꢀ0
LSZ [m].i
Descriptionꢀ
ꢀ
ꢀ
IfꢀbitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀ
theꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀ
instruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0,ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m].i=0
None
Affectedꢀflag(s)ꢀ
ꢀ
Readꢀtableꢀ(currentꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory
LTABRD [m]
Descriptionꢀ
ꢀ
Theꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀ(currentꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀ(TBLP)ꢀisꢀꢀ
movedꢀtoꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.
Operationꢀ
ꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)ꢀ
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
Affectedꢀflag(s)ꢀ
None
Readꢀtableꢀ(lastꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory
LTABRDL [m]
Descriptionꢀ
ꢀ
Theꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀ(lastꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀ(TBLP)ꢀisꢀmovedꢀꢀ
toꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.
Operationꢀ
ꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)ꢀ
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
Affectedꢀflag(s)ꢀ
None
ꢀ
IncrementꢀtableꢀpointerꢀlowꢀbyteꢀfirstꢀandꢀreadꢀtableꢀtoꢀTBLHꢀandꢀDataꢀMemory
LITABRD [m]
Descriptionꢀ
ꢀ
ꢀ
Incrementꢀtableꢀpointerꢀlowꢀbyte,ꢀTBLP,ꢀfirstꢀandꢀthenꢀtheꢀprogramꢀcodeꢀaddressedꢀbyꢀtheꢀꢀ
tableꢀpointerꢀ(TBHPꢀandꢀTBLP)ꢀisꢀmovedꢀtoꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀꢀ
movedꢀtoꢀTBLH.
Operationꢀ
ꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
Affectedꢀflag(s)ꢀ
None
ꢀ
Incrementꢀtableꢀpointerꢀlowꢀbyteꢀfirstꢀandꢀreadꢀtableꢀ(lastꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory
LITABRDL [m]
Descriptionꢀ
ꢀ
ꢀ
Incrementꢀtableꢀpointerꢀlowꢀbyte,ꢀTBLP,ꢀfirstꢀandꢀthenꢀtheꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀꢀ
(lastꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀ(TBLP)ꢀisꢀmovedꢀtoꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀꢀ
theꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.
Operationꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
None
ꢀ
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀXORꢀDataꢀMemoryꢀtoꢀACC
LXOR A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″XOR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀXORꢀACCꢀtoꢀDataꢀMemory
LXORM A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ″XOR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
Rev. 1.10
ꢅꢅ0
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Package Information
Noteꢀthatꢀtheꢀpackageꢀinformationꢀprovidedꢀhereꢀisꢀforꢀconsultationꢀpurposesꢀonly.ꢀAsꢀthisꢀ
informationꢀmayꢀbeꢀupdatedꢀatꢀregularꢀintervalsꢀusersꢀareꢀremindedꢀtoꢀconsultꢀtheꢀHoltekꢀwebsiteꢀforꢀ
theꢀlatestꢀversionꢀofꢀtheꢀPackage/CartonꢀInformation.
Additionalꢀsupplementaryꢀinformationꢀwithꢀregardꢀtoꢀpackagingꢀisꢀlistedꢀbelow.ꢀClickꢀonꢀtheꢀrelevantꢀ
sectionꢀtoꢀbeꢀtransferredꢀtoꢀtheꢀrelevantꢀwebsiteꢀpage.
•ꢀ FurtherꢀPackageꢀInformationꢀ(includeꢀOutlineꢀDimensions,ꢀProductꢀTapeꢀandꢀReelꢀSpecifications)
•ꢀ PackingꢀMeterialsꢀInformation
•ꢀ Cartonꢀinformation
Rev. 1.10
ꢅꢅ1
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
48-pin LQFP (7mm×7mm) Outline Dimensions
C
H
D
G
3
6
2
5
I
3
7
2
4
F
A
B
E
4
8
1
3
=
K
J
1
1
2
Dimensions in inch
Symbol
Min.
—
Nom.
0.35ꢃ BSC
0.ꢅ76 BSC
0.35ꢃ BSC
0.ꢅ76 BSC
0.0ꢅ0 BSC
0.009
Max.
—
A
B
C
D
E
F
G
H
I
—
—
—
—
—
—
—
—
0.007
0.053
—
0.011
0.057
0.063
0.006
0.030
0.00ꢆ
7°
0.055
—
0.00ꢅ
0.01ꢆ
0.00ꢃ
0°
—
�
0.0ꢅꢃ
K
α
—
―
Dimensions in mm
Symbol
Min.
—
Nom.
9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
0.50 BSC
0.ꢅꢅ
Max.
—
A
B
C
D
E
F
G
H
I
—
—
—
—
—
—
—
—
0.17
1.35
—
0.ꢅ7
1.ꢃ5
1.60
0.15
0.75
0.ꢅ0
7°
1.ꢃ0
—
0.05
0.ꢃ5
0.09
0°
—
�
0.60
K
α
—
―
Rev. 1.10
ꢅꢅꢅ
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
BH66F2650/BH66F2660
Body Fat Measurment Flash MCU
Copꢂꢁight© ꢅ01ꢆ bꢂ HOLTEK SEMICONDUCTOR INC.
The infoꢁmation appeaꢁing in this Data Sheet is believed to be accꢀꢁate at the time
of pꢀblication. Howeveꢁꢄ Holtek assꢀmes no ꢁesponsibilitꢂ aꢁising fꢁom the ꢀse of
the specifications described. The applications mentioned herein are used solely
foꢁ the pꢀꢁpose of illꢀstꢁation and Holtek makes no waꢁꢁantꢂ oꢁ ꢁepꢁesentation that
sꢀch applications will be sꢀitable withoꢀt fꢀꢁtheꢁ modificationꢄ noꢁ ꢁecommends
the ꢀse of its pꢁodꢀcts foꢁ application that maꢂ pꢁesent a ꢁisk to hꢀman life dꢀe to
malfꢀnction oꢁ otheꢁwise. Holtek's pꢁodꢀcts aꢁe not aꢀthoꢁized foꢁ ꢀse as cꢁitical
components in life sꢀppoꢁt devices oꢁ sꢂstems. Holtek ꢁeseꢁves the ꢁight to alteꢁ
its products without prior notification. For the most up-to-date information, please
visit oꢀꢁ web site at http://www.holtek.com.tw/en/home.
Rev. 1.10
ꢅꢅ3
�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ
相关型号:
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