HT48R062(16NSOP-A) [HOLTEK]
Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PDSO16;
| 型号： | HT48R062(16NSOP-A) |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PDSO16 可编程只读存储器 微控制器 光电二极管 |
| 文件： | 总31页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HT48R062/HT48C062
Cost-Effective I/O Type 8-Bit MCU
Technical Document
·
·
·
Tools Information
FAQs
Application Note
-
-
-
-
-
HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
HA0013E HT48 & HT46 LCM Interface Design
HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series
HA0075E MCU Reset and Oscillator Circuits Application Note
HA0126E Nickel Cadmium and Nickel Hydride Battery Charging Applications Using the HT48R062
Features
·
·
·
·
·
·
·
·
·
Operating voltage:
SYS=4MHz: 2.2V~5.5V
SYS=8MHz: 3.3V~5.5V
63 powerful instructions
f
Up to 0.5ms instruction cycle with 8MHz system clock
All instructions in 1 or 2 machine cycles
14-bit table read instructions
f
·
·
·
·
·
·
11 bidirectional I/O lines
On-chip crystal and RC oscillator
Watchdog Timer
One-level subroutine nesting
Bit manipulation instructions
1K´14 program memory
32´8 data RAM
Low voltage reset function
16-pin DIP/NSOP package
HALT function and wake-up feature reduce power
consumption
General Description
The HT48R062/HT48C062 are 8-bit high performance,
RISC architecture microcontroller devices specifically
designed for cost-effective multiple I/O control product
applications. The mask version HT48C062 is fully pin
and functionally compatible with the OTP version
HT48R062 devices.
The advantages of low power consumption, I/O flexibil-
ity, oscillator options, HALT and wake-up functions,
watchdog timer, as well as low cost, enhance the versa-
tility of these devices to suit a wide range of application
possibilities such as industrial control, consumer prod-
ucts, subsystem controllers, etc.
Block Diagram
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P
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P
B
0
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2
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Rev. 1.21
1
December 30, 2008
HT48R062/HT48C062
Pin Assignment
P
A
3
P
A
4
1
2
3
4
5
6
7
8
1
1
1
1
1
1
1
6
5
4
3
2
1
0
9
P
A
2
P
A
5
P
A
1
P
A
A
6
7
P
P
A
B
0
0
P
O
O
S
S
C
C
2
1
V
S
S
P
P
B
B
1
2
V
D
D
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H
T
4
8
R
0
6
2
/
H
T
4
8
C
0
6
2
1
6
D
I
P
-
A
/
N
S
O
P
-
A
Pin Description
Code
Pin Name
I/O
Description
Option
Bidirectional 8-bit input/output port. A configuration option determines if all of
the pins on this port are configured as wake-up inputs. Software instructions
Pull-high
PA0~PA7
I/O
Wake-up determine the CMOS output or Schmitt trigger input with a pull-high resistor
(determined by pull-high options).
Bidirectional 3-bit input/output port. Software instructions determine the
PB0~PB2
I/O
Pull-high
CMOS output or Schmitt trigger input with a pull-high resistor (determined by
pull-high options).
VDD
VSS
Positive power supply
¾
¾
¾
¾
Negative power supply, ground
OSC1, OSC2 are connected to an RC network or a crystal (determined by
code option) for the internal system clock. In the case of RC operation, OSC2
is the output terminal for 1/4 system clock (NMOS open drain output).
OSC2
OSC1
O
I
Crystal
or RC
RES
I
Schmitt trigger reset input. Active low.
¾
Note: The Port A wake-up configuration option applies to all pins on Port A. Individual pins on this port cannot be setup
to have a wake-up function.
Absolute Maximum Ratings
Supply Voltage...........................VSS-0.3V to VSS+6.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total .............................................................150mA
Total Power Dissipation .....................................500mW
Storage Temperature............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
IOH Total ..........................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.21
2
December 30, 2008
HT48R062/HT48C062
D.C. Characteristics
Ta=25°C
Test Conditions
Conditions
SYS=4MHz
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
f
f
2.2
3.3
¾
5.5
5.5
1.5
4
V
¾
¾
VDD
Operating Voltage
SYS=8MHz
V
¾
3V
5V
3V
5V
0.6
2
mA
mA
mA
mA
IDD1
No load, fSYS=4MHz
Operating Current (Crystal OSC)
Operating Current (RC OSC)
¾
0.8
2.5
1.5
4
¾
IDD2
IDD3
ISTB1
No load, fSYS=4MHz
No load, fSYS=8MHz
No load, system HALT
¾
Operating Current
5V
4
8
mA
¾
(Crystal OSC, RC OSC)
3V
5V
3V
5V
¾
5
10
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
3
mA
mA
mA
mA
V
Standby Current (WDT Enabled)
Standby Current (WDT Disabled)
1
¾
ISTB2
No load, system HALT
2
¾
VIL1
VIH1
VIL2
VIH2
VLVR
0.3VDD
VDD
0.4VDD
VDD
3.3
¾
Input Low Voltage for I/O Port
Input High Voltage for I/O Port
Input Low Voltage (RES)
Input High Voltage (RES)
Low Voltage Reset
0
¾
0.7VDD
0
V
¾
¾
V
¾
¾
¾
0.9VDD
2.7
4
V
¾
LVRenabled
V
¾
3V
5V
3V
5V
3V
5V
8
mA
mA
mA
mA
kW
kW
IOL
VOL=0.1VDD
VOH=0.9VDD
¾
I/O Port Sink Current
I/O Port Source Current
Pull-high Resistance
10
20
-4
-10
60
30
¾
-2
¾
IOH
-5
¾
20
100
50
RPH
10
A.C. Characteristics
Ta=25°C
Test Conditions
Conditions
2.2V~5.5V
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
400
400
400
400
22
4000
8000
4000
8000
90
kHz
kHz
kHz
kHz
ms
¾
¾
¾
¾
45
32
¾
fSYS1
System Clock (Crystal OSC)
System Clock (RC OSC)
Watchdog Oscillator Period
3.3V~5.5V
¾
2.2V~5.5V
¾
fSYS2
3.3V~5.5V
¾
3V
5V
¾
tWDTOSC
¾
¾
16
64
ms
tRES
tSST
tLVR
External Reset Low Pulse Width
System Start-up Timer Period
Low Voltage Width to Reset
1
¾
ms
Power-up or wake-up
from HALT
tSYS
ms
1024
1
¾
¾
¾
¾
0.25
2
¾
Note: tSYS=1/fSYS
Rev. 1.21
3
December 30, 2008
HT48R062/HT48C062
Functional Description
Execution Flow
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The HT48R062/HT48C062 system clock can be derived
from a crystal/ceramic resonator oscillator or an RC. It is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set or return from subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to get the proper instruction. Otherwise
proceed with the next instruction.
Program Counter - PC
The 10-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex-
ecuted and its contents specify a maximum of 1024 ad-
dresses.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
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P
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P
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1
P
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2
P
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(
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(
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-
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(
P
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(
P
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(
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+
2
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(
P
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+
1
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Execution Flow
Program Counter
Mode
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
Skip
0
0
0
0
0
0
0
0
0
0
Program Counter+2
Loading PCL
*9
*8
@7
#7
@6
#6
@5
#5
@4
#4
@3
#3
@2
#2
@1
#1
@0
#0
Jump, Call Branch
Return from Subroutine
#9
S9
#8
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *9~*0: Program counter bits
#9~#0: Instruction code bits
S9~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.21
4
December 30, 2008
HT48R062/HT48C062
Program Memory - ROM
Stack Register - STACK
The program memory is used to store the program in-
structions which are to be executed. It also contains
data and table and is organized into 1024´14 bits, ad-
dressed by the program counter and table pointer.
This is a special part of the memory used to save the
contents of the Program Counter only. The stack is orga-
nized into one level and is neither part of the data nor
part of the program space, and is neither readable nor
writeable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call the contents of the program counter are
pushed onto the stack. At the end of a subroutine sig-
naled by a return instruction (RET), the program counter
is restored to its previous value from the stack. After a
chip reset, the SP will point to the top of the stack.
Certain locations in the program memory are reserved
for special usage:
·
Location 000H
This area is reserved for the initialization program. Af-
ter chip reset, the program always begins execution at
location 000H.
·
Table location
Any location in the EPROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, one page=256 words) and ²TABRDL
[m]² (the last page) transfer the contents of the
lower-order byte to the specified data memory, and
the higher-order byte to TBLH (08H). Only the desti-
nation of the lower-order byte in the table is
well-defined, the other bits of the table word are trans-
ferred to the lower portion of TBLH, the remaining 2
bits are read as ²0². The Table Higher-order byte reg-
ister (TBLH) is read only. The table pointer (TBLP) is a
read/write register (07H), where P indicates the table
location. Before accessing the table, the location must
be placed in TBLP. The TBLH is read only and cannot
be restored. All table related instructions need 2 cy-
cles to complete the operation. These areas may
function as normal program memory depending upon
the requirements.
If the stack is full and a ²CALL² is subsequently exe-
cuted, stack overflow occurs and the first entry will be
lost (only the most recent return address is stored).
Data Memory - RAM
The data memory is designed with 44´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(32´8). Most of them are read/write, but some are read
only.
The special function registers include the Indirect Ad-
dressing Register (00H), the Memory Pointer register
(MP;01H), the Accumulator (ACC;05H) the Program
Counter Lower-order byte register (PCL;06H), the Table
Pointer (TBLP;07H), the table higher-order byte register
(TBLH;08H), the Watchdog Timer option setting register
(WDTS;09H), the STATUS register (STATUS;0AH), the
I/O registers (PA;12H, PB;14H) and I/O control registers
(PAC;13H, PBC;15H). The remaining space before the
20H is reserved for future expanded usage and reading
these locations will return the result 00H. The general
purpose data memory, addressed from 20H to 3FH, is
used for data and control information under instruction
command.
0
0
0
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6
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n
F
F
H
All data memory areas can handle arithmetic, logic, in-
crement, decrement and rotate operations directly. Ex-
cept for some dedicated bits, each bit in the data
memory can be set and reset by the ²SET [m].i² and
²CLR [m].i² instructions, respectively. They are also indi-
rectly accessible through memory pointer register
(MP;01H).
L
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-
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p
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a
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(
2
5
6
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3
F
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1
4
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3
Program Memory
Table Location
Instruction(s)
*9
P9
1
*8
P8
1
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
TABRDL [m]
@7
@7
@6
@6
@5
@5
@4
@4
@3
@3
@2
@2
@1
@1
@0
@0
Table Location
@7~@0: Table pointer bits
Note: *9~*0: Table location bits
P9~P8: Current program counter bits
Rev. 1.21
5
December 30, 2008
HT48R062/HT48C062
result ²1². Any writing operation to MP will only transfer
the lower 7-bit data to MP.
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
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M
P
Accumulator
The accumulator closely relates to ALU operations. It is
also mapped to location 05H of the data memory and is
capable of carrying out immediate data operations. Data
movement between two data memory locations has to
pass through the accumulator.
A
C
C
P
C
L
T
B
L
P
T
B
L
H
W
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T
S
0
0
A
B
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Arithmetic and Logic Unit - ALU
D
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This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions.
0
0
C
D
H
H
·
·
·
·
·
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
0
E
H
0
F
H
1
1
1
1
1
0
1
2
3
4
H
H
H
H
H
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
P
A
P
A
C
The ALU not only saves the results of a data operation but
also changes the contents of the status register.
P
B
1
1
5
6
H
H
P
B
C
:
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,
Status Register - STATUS
r
e
a
d
a
s
"
0
0
"
1
F
H
H
2
0
This 8-bit status register (0AH) contains the zero flag
(Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF) and watchdog time-out
flag (TO). It also records the status information and con-
trols the operation sequence.
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2
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3
F
H
RAM Mapping
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other register. Any data written into the status register
will not change the TO or PDF flags. In addition it should
be noted that operations related to the status register
may give different results from those intended. The TO
and PDF flags can only be changed by the Watchdog
Timer overflow, chip power-up, clearing the Watchdog
Timer and executing the ²HALT² instruction.
Indirect Addressing Register
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation of
[00H] accesses data memory pointed to by MP (01H).
Reading location 00H itself indirectly will return the re-
sult 00H. Writing indirectly results in no operation.
The memory pointer register MP (01H) is a 7-bit register.
The bit 7 of MP is undefined and reading will return the
Bit No.
Label
Function
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
0
C
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
1
2
3
AC
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
OV
PDF is cleared when either a system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
4
PDF
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
5
TO
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
Rev. 1.21
6
December 30, 2008
HT48R062/HT48C062
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4), decided by options. This timer is
designed to prevent a software malfunction or sequence
from jumping to an unknown location with unpredictable
results. The Watchdog Timer can be disabled by an op-
tion. If the Watchdog Timer is disabled, all the execu-
tions related to the WDT result in no operation.
In addition, on executing the subroutine call, the status
register will not be automatically pushed onto the stack.
If the contents of the status are important and if the sub-
routine can corrupt the status register, precautions must
be taken to save it properly.
Once the internal WDT oscillator (RC oscillator with a
period of 32ms at 5V normally) is selected, it is first di-
vided by 512 (9-stage) to get the nominal time-out pe-
riod of approximately 17ms at 5V. This time-out period
may vary with temperatures, VDD and process varia-
tions. By invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2, WS1,
WS0 (bit 2,1,0 of the WDTS) can give different time-out
periods. If WS2, WS1, and WS0 are all equal to 1, the di-
vision ratio is up to 1:128, and the maximum time-out
period is 2.1s at 5V seconds. If the WDT oscillator is dis-
abled, the WDT clock may still come from the instruction
clock and operate in the same manner except that in the
HALT state the WDT may stop counting and lose its pro-
tecting purpose. In this situation the logic can only be re-
started by external logic. The high nibble and bit 3 of the
WDTS are reserved for user¢s defined flags, which can
be used to indicate some specified status.
Oscillator Configuration
There are two oscillator circuits implemented in the
microcontroller.
V
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System Oscillator
Both are designed for system clocks; the RC oscillator
and the Crystal oscillator, which are determined by code
options. No matter what oscillator type is selected, the
signal provides the system clock. The HALT mode stops
the system oscillator and ignores the external signal to
conserve power.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
If an RC oscillator is used, an external resistor between
OSC1 and VSS in needed and the resistance must
range from 24kW to 1MW. The system clock, divided by
4, is available on OSC2, which can be used to synchro-
nize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency of the
oscillation may vary with VDD, temperature and the chip
itself due to process variations. It is, therefore, not suit-
able for timing sensitive operations where accurate os-
cillator frequency is desired.
WS2
WS1
WS0
Division Ratio
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift for the oscillator. No other external components are
needed. Instead of a crystal, the resonator can also be
connected between OSC1 and OSC2 to get a frequency
reference, but two external capacitors in OSC1 and
OSC2 are required.
WDTS (09H) Register
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit ²TO². But in the HALT
mode, the overflow will initialize a ²warm reset², and
only the Program Counter and SP are reset to zero. To
clear the contents of WDT (including the WDT
prescaler), three methods are adopted; external reset (a
Watchdog Timer - WDT
The clock source of WDT is implemented by a dedicated
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Watchdog Timer
Rev. 1.21
7
December 30, 2008
HT48R062/HT48C062
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
Reset
low level to RES), software instruction and a ²HALT² in-
struction. The software instruction include ²CLR WDT²
and the other set - ²CLR WDT1² and ²CLR WDT2². Of
these two types of instruction, only one can be active de-
pending on the option - ²CLR WDT times selection op-
tion². If the ²CLR WDT² is selected (i.e. CLRWDT times
equal one), any execution of the ²CLR WDT² instruction
will clear the WDT. In the case that ²CLR WDT1² and
²CLR WDT2² are chosen (i.e. CLRWDT times equal
two), these two instructions must be executed to clear
the WDT; otherwise, the WDT may reset the chip as a
result of time-out.
There are three ways in which a reset can occur:
·
·
·
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
Some registers remain unchanged during reset condi-
tions. Most registers are reset to the ²initial condition²
when the reset conditions are met. By examining the
PDF and TO flags, the program can distinguish between
different ²chip resets².
Power Down Operation - HALT
TO PDF
RESET Conditions
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
0
u
0
1
1
0
u
1
u
1
·
·
The system oscillator turns off and the WDT stops.
The contents of the on-chip RAM and registers remain
unchanged.
WDT time-out during normal operation
WDT wake-up HALT
·
·
·
WDT prescaler are cleared.
All I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
Note: ²u² means unchanged.
The system can quit the HALT mode by means of an ex-
ternal reset or an external falling edge signal on Port A.
An external reset causes a device initialization. Exam-
ining the TO and PDF flags, the reason for chip reset
can be determined. The PDF flag is cleared when the
system powers up or execute the ²CLR WDT² instruc-
tion and is set when the ²HALT² instruction is executed.
The TO flag is set if the WDT time-out occurs, and
causes a wake-up that only resets the program counter
and SP, the others keep their original status.
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem powers up or when the system awakes from a HALT
state.
When a system power up occurs, an SST delay is added
during the reset period. But when the reset comes from
the RES pin, the SST delay is disabled. Any wake-up
from HALT will enable the SST delay.
The functional unit chip reset status is shown below.
APort Awake-up can be considered as a continuation of
normal execution. A configuration option determines if
all of the pins on Port A are configured as wake-up pins.
Individual Port A pins cannot be setup as wake-up
inputs. Awakening from an I/O port stimulus, the pro-
gram will resume execution of the next instruction.
Program Counter
WDT Prescaler
Input/Output ports
Stack Pointer
000H
Clear
Input mode
Points to the top of the stack
Once a wake-up event(s) occurs, it takes 1024 tSYS
(system clock period) to resume normal operation. In
other words, a dummy cycle period will be inserted after
the wake-up.
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Reset Timing Chart
Rev. 1.21
8
December 30, 2008
HT48R062/HT48C062
V
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Reset Circuit
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Note: Most applications can use the Basic Reset Cir-
cuit as shown, however for applications with ex-
tensive noise, it is recommended to use the
Hi-noise Reset Circuit.
Reset Configuration
The chip reset status of the registers is summarized in the following table:
Reset
WDT Time-out
RES Reset
RES Reset
WDT Time-out
(HALT)*
Register
(Power-on) (Normal Operation) (Normal Operation)
(HALT)
Program Counter
MP
000H
000H
000H
000H
000H
-xxx xxxx
xxxx xxxx
xxxx xxxx
--xx xxxx
0000 0111
--00 xxxx
1111 1111
1111 1111
---- -111
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0111
--1u uuuu
1111 1111
1111 1111
---- -111
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0111
--uu uuuu
1111 1111
1111 1111
---- -111
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0111
--01 uuuu
1111 1111
1111 1111
---- -111
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
--11 uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
ACC
TBLP
TBLH
WDTS
STATUS
PA
PAC
PB
PBC
---- -111
---- -111
---- -111
---- -111
---- -uuu
Note:
²*² means ²warm reset²
²u² means ²unchanged²
²x² means ²unknown²
Rev. 1.21
9
December 30, 2008
HT48R062/HT48C062
Input/Output Ports
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H or 14H)
instructions.
There are up to 11 bidirectional input/output lines in the
microcontroller labeled with port names PA and PB,
which are mapped to the data memory of [12H] and
[14H] respectively. All of these I/O ports can be used for
input and output operations. For input operation, these
ports are non-latching, that is, the inputs must be ready
at the T2 rising edge of instruction ²MOV A,[m]² (m=12H
or 14H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each I/O line has its own control register (PAC, PBC) to
control the input/output configuration. With this control
register, CMOS output or Schmitt trigger input with or
without pull-high resistor structures can be reconfigured
dynamically (i.e. on-the-fly) under software control. To
function as an input, the corresponding latch of the con-
trol register must write ²1². The input source also de-
pends on the control register. If the control register bit is
²1², the input will read the pad state. If the control regis-
ter bit is ²0², the contents of the latches will move to the
internal bus. The latter is possible in the ²read-modify-
write² instruction.
Each line of Port A has the capability of waking-up the
device. The highest 5-bit of Port B are not physically im-
plemented; on reading them a ²0² is returned whereas
writing then results in a no-operation. See Application
note.
There are pull-high options available for PA and PB.
Once the pull-high option is selected, I/O lines have
pull-high resistors. Otherwise, the pull-high resistors are
absent. It should be noted that a non-pull-high I/O line
operating in input mode will cause a floating state.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H
and 15H.
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Input/Output Ports
Rev. 1.21
10
December 30, 2008
HT48R062/HT48C062
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will au-
tomatically reset the device internally.
V
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5
.
5
V
5
.
5
V
V
L
V
R
The LVR includes the following specifications:
3
.
0
V
·
The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
2
.
2
V
0
.
9
V
·
The LVR uses the ²OR² function with the external
RES signal to perform chip reset.
Note:
V
OPR is the voltage range for proper chip opera-
tion at 4MHz system clock.
V
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5
.
5
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*
1
*
2
Low Voltage Reset
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters
the reset mode.
Options
The following table shows eight kinds of code option in the HT48R062/HT48C062. All the code options must be defined
to ensure proper system functioning.
No.
1
Options
WDT clock source: WDTOSC or fSYS/4
WDT function: enable or disable
LVR function: enable or disable
2
3
4
CLRWDT instruction(s): one or two clear WDT instruction(s)
System oscillator: RC or crystal
5
6
PA and PB pull-high resistors: none or pull-high
PA0~PA7 wake-up: enable or disable
7
Rev. 1.21
11
December 30, 2008
HT48R062/HT48C062
Application Circuits
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Note: 1. Crystal/resonator system oscillators
For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For
resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is
not necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator
when VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2
should be selected in consultation with the crystal/resonator manufacturer specifications.
2. Reset circuit
The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and re-
mains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of
the wiring connected to the RES pin is kept as short as possible, to avoid noise interference.
3. For applications where noise may interfere with the reset circuit and for details on the oscillator external
components, refer to Application Note HA0075E for more information.
Rev. 1.21
12
December 30, 2008
HT48R062/HT48C062
Instruction Set
Introduction
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to en-
sure correct handling of carry and borrow data when re-
sults exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Central to the successful operation of any
microcontroller is its instruction set, which is a set of pro-
gram instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of pro-
gramming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several func-
tional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on pro-
gram requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruc-
tion cycle. The exceptions to this are branch, call, or ta-
ble read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be im-
plemented within 1ms. Although instructions which re-
quire one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instruc-
tions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to imple-
ment. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instruc-
tions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the re-
sult of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a sub-
routine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the sub-
routine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made re-
garding the condition of a certain data memory or indi-
vidual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the pro-
gram perhaps determined by the condition of certain in-
put switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific imme-
diate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
Rev. 1.21
13
December 30, 2008
HT48R062/HT48C062
Bit Operations
Other Operations
The ability to provide single bit operations on Data Mem-
ory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The fea-
ture removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write pro-
cess is taken care of automatically when these bit oper-
ation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² in-
struction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electro-
magnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be con-
sulted as a basic instruction reference using the follow-
ing listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using regis-
ters. However, when working with large amounts of
fixed data, the volume involved often makes it inconve-
nient to store the fixed data in the Data Memory. To over-
come this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instruc-
tions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Arithmetic
Description
Cycles Flag Affected
ADD A,[m]
ADDM A,[m]
ADD A,x
Add Data Memory to ACC
1
1Note
1
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
Add ACC to Data Memory
Add immediate data to ACC
ADC A,[m]
ADCM A,[m]
SUB A,x
Add Data Memory to ACC with Carry
1
1Note
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
1
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
1
1Note
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1Note
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1Note
1Note
1
OR A,x
1
XOR A,x
1
1Note
CPL [m]
CPLA [m]
Complement Data Memory with result in ACC
1
Increment & Decrement
INCA [m]
INC [m]
Increment Data Memory with result in ACC
1
Z
Z
Z
Z
Increment Data Memory
1Note
DECA [m]
DEC [m]
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
Rev. 1.21
14
December 30, 2008
HT48R062/HT48C062
Mnemonic
Rotate
Description
Cycles Flag Affected
RRA [m]
RR [m]
Rotate Data Memory right with result in ACC
Rotate Data Memory right
1
1Note
1
1Note
1
1Note
None
None
C
RRCA [m]
RRC [m]
RLA [m]
RL [m]
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
C
None
None
C
RLCA [m]
RLC [m]
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
C
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Bit Operation
CLR [m].i
SET [m].i
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Branch
JMP addr
SZ [m]
Jump unconditionally
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Skip if Data Memory is zero
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
Return from subroutine
2
RET A,x
RETI
Return from subroutine and load immediate data to ACC
Return from interrupt
2
2
Table Read
TABRDC [m]
TABRDL [m]
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
Miscellaneous
NOP
No operation
1
1Note
1Note
1
None
None
CLR [m]
Clear Data Memory
SET [m]
Set Data Memory
None
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Clear Watchdog Timer
TO, PDF
TO, PDF
TO, PDF
None
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1
1Note
1
None
1
TO, PDF
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
Rev. 1.21
15
December 30, 2008
HT48R062/HT48C062
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-
eration. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
Rev. 1.21
16
December 30, 2008
HT48R062/HT48C062
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then in-
crements by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruc-
tion.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Operation
Each bit of the specified Data Memory is cleared to 0.
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Operation
Bit i of the specified Data Memory is cleared to 0.
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Description
Operation
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev. 1.21
17
December 30, 2008
HT48R062/HT48C062
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-
sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-
ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Operation
Data in the specified Data Memory is decremented by 1.
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-
mulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 1.21
18
December 30, 2008
HT48R062/HT48C062
INC [m]
Increment Data Memory
Description
Operation
Data in the specified Data Memory is incremented by 1.
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-
lator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Description
Operation
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
Operation
The immediate data specified is loaded into the Accumulator.
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Description
Operation
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
Operation
Affected flag(s)
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-
ation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 1.21
19
December 30, 2008
HT48R062/HT48C062
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-
ation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the re-
stored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by set-
ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed be-
fore returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-
main unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.21
20
December 30, 2008
HT48R062/HT48C062
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-
tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-
places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.21
21
December 30, 2008
HT48R062/HT48C062
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-
sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Operation
Each bit of the specified Data Memory is set to 1.
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Operation
Bit i of the specified Data Memory is set to 1.
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.21
22
December 30, 2008
HT48R062/HT48C062
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumu-
lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-
tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.21
23
December 30, 2008
HT48R062/HT48C062
SWAP [m]
Description
Operation
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruc-
tion.
Operation
Skip if [m] = 0
None
Affected flag(s)
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-
tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
None
Affected flag(s)
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.21
24
December 30, 2008
HT48R062/HT48C062
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-
eration. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.21
25
December 30, 2008
HT48R062/HT48C062
Package Information
16-pin DIP (300mil) Outline Dimensions
A
A
9
8
1
6
9
8
1
6
B
B
1
1
H
H
C
D
C
D
G
G
E
E
I
I
F
F
Fig1. Full Lead Packages
Fig2. 1/2 Lead Packages
·
MS-001d (see fig1)
Dimensions in mil
Symbol
Min.
780
240
115
115
14
Nom.
¾
Max.
880
280
195
150
22
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
45
70
¾
100
¾
¾
300
¾
325
430
¾
¾
·
MS-001d (see fig2)
Dimensions in mil
Symbol
Min.
735
240
115
115
14
Nom.
¾
Max.
775
280
195
150
22
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
45
70
¾
100
¾
¾
300
¾
325
430
¾
¾
Rev. 1.21
26
December 30, 2008
HT48R062/HT48C062
·
MO-095a (see fig2)
Dimensions in mil
Symbol
Min.
745
275
120
110
14
Nom.
¾
Max.
785
295
150
150
22
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
45
60
¾
100
¾
¾
300
¾
325
430
¾
¾
Rev. 1.21
27
December 30, 2008
HT48R062/HT48C062
16-pin NSOP (150mil) Outline Dimensions
1
6
9
8
A
B
1
C
C
'
G
H
D
a
F
E
·
MS-012
Dimensions in mil
Symbol
Min.
228
150
12
386
¾
Nom.
¾
Max.
244
157
20
A
B
C
C¢
D
E
F
¾
¾
394
69
¾
¾
50
¾
¾
4
10
¾
¾
¾
¾
G
H
a
16
7
50
10
0°
8°
Rev. 1.21
28
December 30, 2008
HT48R062/HT48C062
Product Tape and Reel Specifications
Reel Dimensions
D
T
2
C
A
B
T
1
SOP 16N (150mil)
Symbol
Description
Dimensions in mm
A
B
Reel Outer Diameter
Reel Inner Diameter
Spindle Hole Diameter
Key Slit Width
330.0±1.0
100.0±1.5
13.0+0.5/-0.2
C
D
2.0±0.5
16.8+0.3/-0.2
T1
T2
Space Between Flange
Reel Thickness
22.2±0.2
Rev. 1.21
29
December 30, 2008
HT48R062/HT48C062
Carrier Tape Dimensions
P
0
P
1
t
D
E
F
W
B
0
C
D
1
P
K
0
A
0
R
e
e
l
H
o
l
e
I
C
p
a
c
k
a
g
e
p
i
n
1
a
n
d
t
h
e
r
e
e
l
h
o
l
e
s
a
r
e
l
o
c
a
t
e
d
o
n
t
h
e
s
a
m
e
s
i
d
e
.
SOP 16N (150mil)
Symbol
Description
Dimensions in mm
16.0±0.3
8.0±0.1
W
P
Carrier Tape Width
Cavity Pitch
E
Perforation Position
1.75±0.1
7.5±0.1
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
D
1.55+0.1/-0.0
1.50+0.25/-0.0
4.0±0.1
D1
P0
P1
A0
B0
K0
t
Cavity to Perforation (Length Direction)
Cavity Length
2.0±0.1
6.5±0.1
Cavity Width
10.3±0.1
2.1±0.1
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
0.30±0.05
13.3±0.1
C
Rev. 1.21
30
December 30, 2008
HT48R062/HT48C062
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
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Fax: 886-2-2655-7373
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Holtek Semiconductor Inc. (Shanghai Sales Office)
G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103
Tel: 86-21-5422-4590
Fax: 86-21-5422-4705
http://www.holtek.com.cn
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5F, Unit A, Productivity Building, Gaoxin M 2nd, Middle Zone Of High-Tech Industrial Park, ShenZhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
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Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125
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Tel: 86-28-6653-6590
Fax: 86-28-6653-6591
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Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2008 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.21
31
December 30, 2008
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