HXNV0100ASF [HONEYWELL]
Memory Circuit, 64KX16, CMOS, CQFP64, QFP-64;
| 型号： | HXNV0100ASF |
| 厂家： | 
Honeywell |
| 描述： | Memory Circuit, 64KX16, CMOS, CQFP64, QFP-64 内存集成电路 |
| 文件： | 总14页 (文件大小：539K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HXNV0100
64K x 16 Non-Volatile
Magnetic RAM
Advanced Information
The 64K x 16 radiation hardened low power nonvolatile
Magnetic RAM (MRAM) is a high performance 65,536
word x 16-bit magnetic random access memory with
industry-standard functionality.
Integrated Power Up and Power Down circuitry controls
the condition of the device during power transitions.
It is fabricated with Honeywell’s radiation hardened
Silicon On Insulator (SOI) technology, and is designed
for use in low-voltage systems operating in radiation
environments. The MRAM operates over the full military
temperature range and is operated with 3.3 ± 0.3V and
1.8 ± 0.15 V power supplies.
The MRAM is designed for very high reliability.
Redundant write control lines, error correction coding
and low-voltage write protection ensure the correct
operation of the memory and that it is protected from
inadvertent writes.
FEATURES
ꢀRead Cycle Time ≤60 ns
ꢀFabricated on S150 Silicon On
Insulator (SOI) CMOS
ꢀDual Power Supplies
ꢀWrite Cycle Time ≤100ns
•
1.8 V ± 0.15V, 3.3 V ±0.3V
Underlayer Technology
ꢀTypical Operating Power ≤500 mW
•
3.3V CMOS Compatible I/O
ꢀ150 nm Process (Leff = 130 nm)
ꢀUnlimited Read/Write (>1E15
ꢀTotal Dose Hardness ≥ 3x105
ꢀOperating Range is -55°C to
+125°C
Cycles)
rad (SiO2)
ꢀ>10 years Power-Off Data
ꢀPackage: 64 Lead Shielded
ꢀDose Rate Upset Hardness ≥
Retention
1x1010 rad(Si)/s
ceramic Quad Flat Pack
ꢀSynchronous Operation
ꢀDose Rate Survivability ≥1x1012
ꢀSingle-Bit Error Detection &
rad(Si)/s
Correction (ECC)
ꢀSoft Error Rate ≤1x10-10
upsets/bit-day
ꢀNeutron Hardness ≥1x1013 cm-2
ꢀNo Latchup
HMXNV0100
FUNCTIONAL BLOCK DIAGRAM
Bit Line Current Drivers
A(7:15)
CS
D
C
Q
Q
ECC Array
65,536 x 5
Memory Array
65,536 x 16
WE
D
C
WE_AS
OE
ECC Logic
NWI
Digit Line Current
Drivers
ECC_DISABLE
ERROR
A(0:6)
D
C
Q
Column Decoder
Data Input/Output
Read Circuits
DQ(0:15)
SIGNAL DESCRIPTION
Signal
Definition
A(0:6)
Column Select Address Input. Signals which select a column within the
memory array.
A–(7:15)
DQ(0:15)
Row Select Address Input. Signals which select a row within the
memory array.
Data Input/Output Signals. Bi-directional data pins which serve as data
outputs during a read operation and as data inputs during a write
operation.
CS
Chip select. The rising edge of CS will clock in the address and WE
signals
WE
WE_AS
Write Enable. This signal is latched to enable a write.
Write Enable Asynchronous – This signal can be used to delay the
beginning of the write cycle
OE
NWI_0
NWI_1
Output Enable.
Not Write Inhibit – When set low, these signals inhibit writes to the
memory. A high level allows the memory to be written.
NWI(0) controls address locations A(15:0) = 0x0000 to 0x7FFF.
NWI(1) controls address locations A(15:0) = 0x1000 to 0xFFFF.
ECC_Disable Error Correction Disable – Disables the error correction function.
ERROR
Test_1
Test_2
VDD1
ECC Error flag
These signals are for Honeywell test purposes only. These should be
grounded in normal operation.
DC Power Source Input: 1.8V
VDD2
DC Power Source Input: 3.3V
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HMXNV0100
TRUTH TABLE
NWI
L
WE & WE_ASY
OE
L
MODE
Deselected
Disabled
Read
DQ
X
L
High Z
High Z
Data Out
Data In
H
L
H
H
L
H
H
X
Write
X: VI = VIH or VIL
PACKAGE PINOUT
VDD1
GND
DQ(1)
DQ(0)
CS
NWI(0)
VDD2
VDD1
GND
1
2
3
4
5
6
7
8
9
48 GND
47 VDD2
46 ADR(6)
45 ADR(15)
44 WE
43 WE_ASY
42 OE
HMXNV1000
41 VDD2
40 VDD1
NWI(1) 10
ECCDISABLE 11
ERROR 12
DQ(8) 13
39 GND
38 ADDR(14)
37 ADDR(13)
36 ADDR(12)
35 ADDR(11)
34 GND
DQ(9) 14
VDD2 15
GND 16
33 VDD1
RAM and ROM Functional Capability
This MRAM incorporates two write control
signals allowing the two sections of the
memory to be controlled independently.
The two NOT WRITE INHIBIT signals,
NWI(0) and NWI(1), allow one section of the
devices to operate as a RAM and the other
to operate as a ROM at the full control of the
user.
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HMXNV0100
SOI AND MAGNETIC MEMORY TECHNOLOGY
two orthogonal currents of the desired
Honeywell’s S150 Silicon On Insulator
(SOI) is radiation hardened through the use
of advanced and proprietary design, layout
and process hardening techniques. The 150
nm process is a technology with a 32Å gate
oxide for 1.8 V transistors and 70Å gate
oxide for 3.3 V transistors. The memory
element is a magnetic tunnel junction (MTJ)
that is composed of a magnetic storage
layer structure and a magnetic pinned layer
structure separated by an insulating tunnel
barrier interlayer. During a write cycle, the
storage layer is written by the application of
polarity using row-and-column addressing.
The resistance of the MTJ depends on the
magnetic state of the storage layer, which
uses the pinned layer structure as a
reference, and which enables sensing,
signal amplification, and readback. The
resistance change is a consequence of the
change in tunneling magnetoresistance
(TMR) between the storage and pinned
layers that depends on the magnetic state of
the storage layer. With read and write cycles
in excess of 1015, there is no wear-out.
ERROR CORRECTION CODE (ECC)
Hamming 5-Bit ECC
from memory and corrected, if necessary,
before being placed on the output data bus.
There is no change made to the actual data
in the memory cells based on the ECC
results. Actual data in memory is changed
only upon writing new values.
A 5-bit Hamming ECC is generated for all
data written into memory. This code allows
for the correction of all single-bit errors per
address. On a read cycle, the data is read
RADIATION CHARACTERISTIC
Transient Pulse Ionizing Radiation
Total Ionizing Radiation Dose
The MRAM is capable of writing, reading,
and retaining stored data during and after
exposure to a transient ionizing radiation
pulse, up to the specified transient dose rate
upset specification, when applied under
recommended operating conditions. To
ensure validity of all specified performance
parameters before, during, and after
The MRAM will meet all stated functional
and electrical specifications over the entire
operating temperature range after the
specified total ionizing radiation dose. All
electrical and timing performance
parameters will remain within specifications
after rebound at typical VDD and T =125°C
extrapolated to ten years of operation. Total
dose hardness is assured by wafer level
testing of process monitor transistors and
RAM product using 10 KeV X-ray and Co60
radiation sources. Transistor gate threshold
shift correlations have been made between
10 KeV X-rays applied at a dose rate of
1x105 rad(SiO2)/min at T = 25°C and gamma
rays (Cobalt 60 source) to ensure that wafer
level X-ray testing is consistent with
standard military radiation test
radiation (timing degradation during
transient pulse radiation is ±10%), it is
suggested that stiffening capacitance be
placed near the package VDD2 and ground
(GND).
It is recommended that the inductance
between the MRAM package leads and the
stiffening capacitance be less that 1.0 nH. If
there are no operate through or valid stored-
data requirements, typical circuit board
mounted de-coupling capacitors are
recommended. The MRAM will meet any
functional or electrical specification after
exposure to a radiation pulse up to the
transient dose rate survivability
environments.
specification, when applied under
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HMXNV0100
recommended operating conditions. Note
that the current conducted during the pulse
by the RAM inputs, outputs, and power
supply may significantly exceed the normal
operating levels. The application design
must accommodate these effects.
recommended operating conditions. This
hardness level is defined by the Adams 90%
worst case cosmic ray environment for
geosynchronous orbits.
Latchup
Neutron Radiation
The MRAM will not latch up under any of the
above radiation exposure conditions when
applied under recommended operating
conditions. Fabrication with the SIMOX
substrate material provides oxide isolation
between adjacent PMOS and NMOS
The MRAM will meet any functional or timing
specification after exposure to the specified
neutron fluence under recommended
operating or storage conditions. This
assumes equivalent neutron energy of 1
MeV.
transistors and eliminates any potential
SCR-type latchup structures. Sufficient
transistor body tie connections to the p-
channel and n-channel substrates are made
to ensure no source/drain snapback occurs.
Soft Error Rate
The MRAM is capable of meeting the
specified Soft Error Rate (SER) under
Radiation-Hardness Ratings
Parameter
Total Dose:
R-Level
Limits
Units
Test Conditions
5
5
6
Rads(SiO2)
VDD1= 1.95 Volts, VDD2= 3.6 Volts
T = 25C, X-Ray or Co
A
≥ 1 x 10
≥ 3 x 10
≥ 1 x 10
F-Level
60
H-Level
Soft Error Rate:
-
Upsets/bit-day VDD1= 1.8 Volts, VDD2= 3.3 Volts
= -55 to 125°C
10
≤ 1 x 10
T
C
Transient Dose
Rate Upset
10
Rads(Si)/s
Rads(Si)/s
N/cm-2
VDD1= 1.65 Volts, VDD2= 3.0 Volts
≥ 1 x 10
T
= 125°C Pulse Width = 1µsec, X-
C
Ray
Transient Dose
12
VDD1= 1.95 Volts, VDD2= 3.6 Volts
≥ 1 x 10
Rate Survivability
T = 25°C
A
Pulse Width = 50 nsec, X-Ray
Neutron Fluence
1x1013
1MeV equivalent energy
MAGNETIC FIELD CHARACTERISTICS
The MRAM will meet all stated functional
and electrical specifications over the entire
operating temperature range when exposed
to the specified magnetic fields. The
magnetic field hardening is achieved
through a combination of SOI technology
characteristics, circuit design and
specialized packaging.
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HMXNV0100
MAGNETIC FIELD RATING
Parameter
Magnetic Field
Limits
50
Units
Oe
Test Conditions
VDD1= 1.8 Volts, VDD2= 3.3 Volts
T
C
= -55 to 125°C
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (1)
Ratings
Symbol
Parameter
Min
-0.5
-0.5
-0.5
-65
Max
2.5
Units
Volts
Volts
VDD
Positive Supply Voltage (2)
Positive Supply Voltage (2)
Voltage on Any Pin (2)
Storage Temperature
Soldering Temperature
1
VDD
4.5
2
VPIN
VDD2 + 0.5 Volts
150
TSTORE
TSOLDER
PD
°C
225°C
°C*sec (5)
Package Power Dissipation (3)
2.5
W
PJC
Package Thermal Resistance (Junction
2.0
°C/W
to Case)
VPROT
TJ
Electrostatic Discharge Protection
Voltage (4)
2000
V
Junction Temperature
175
°C
Stresses in excess of those listed above may result in immediate permanent damage
to the device. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect
device reliability.
1.
Voltage referenced to GND
2.
3. RAM power dissipation due to IDDS, IDDOP, and IDDSEI, plus RAM output driver power
dissipation due to external loading must not exceed this specification
4. Class 2 electrostatic discharge (ESD) input protection voltage per MIL-STD-883,
Method 3015
5. Maximum soldering temp of 225°C can be maintained for no more than 5 seconds.
RECOMMENDED OPERATING CONDITIONS (1)
Limits
Symbol
DD1
DD2
Parameter
Min
1.65
3.0
Typical
Max
1.95
3.6
Units
Volts
Volts
V
V
T
Positive Supply Voltage
Positive Supply Voltage
1.8
3.3
25
External Package Temperature -55
Voltage On Any Pin
125
°C
C
V
PIN
-0.3
V
DD2
+0.3 Volts
(1) Voltages referenced to GND
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HMXNV0100
DC ELECTRICAL CHARACTERISTICS
Limits
Symbol
Parameter
Low Level Input
Voltage
Min
Typical
Max
Units
Test Conditions
VIL
0.3VDD
V
VIH
High-level Input Voltage 0.7VDD
Low-level Output
V
V
VOL
0.35
0.5
VDD = 3.0 volts
Voltage
VOH
IOZ
High-level Output
Voltage
VDD-0.5
2.66
(2.95)
TBD
V
VDD = 3.0 volts
(VDD = 3.3 volts)
Output Leakage
Current
µA
IL
Input Leakage Current
Output Drive Current
Standby Current
VDD1 (1.8V)
TBD
6
µA
IO
mA
mA
IDDSB
3
3
VDD2 (3.3V)
AC ELECTRICAL CHARACTERISTICS
Limits
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions
Continuous write
cycle at 10 MHz (1)
IDDWR
Average Write Current
VDD1 (1.8V)
mA
15
VDD2 (3.3V)
260
IDDRD
Average Read Current
VDD1 (1.8V)
mA
Continuous read
15
3
cycle at 10 MHz (1)
VDD2 (3.3V)
1. Current consumption is reduced with lower duty cycle. The scale is linear with respect to
duty cycle with 3 mA minimum values of on each VDD signal.
CAPACITANCE (1)
Limits
Max
6
Test Conditions
TBD
Symbol
Parameter
Min
Units
Ca and CC
Address and Control line
Capacitance
pF
CD
Data Line Capacitance
Not Write Inhibit
Capacitance
9
pF
pF
Value is I/O buffer only.
CNWI
100
Note: 1. These values are tested at characterization only.
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HMXNV0100
RISE/FALL TIMES
Value
Min
Test Conditions
Symbol
Rt
Rt
Parameter
Rise Time
Rise Time
Max
1.4
2.9
Units
ns
ns
Cload = 5 pF
Cload = 25 pF
Ft
Ft
Fall Time
Fall Time
1.4
2.9
ns
ns
Cload = 5 pF
Cload = 25 pF
DATA ENDURANCE
Ratings
Test Conditions
Test Conditions
Parameter
Min
Max
Max
Units
Data Endurance
1x1015
Cycles
DATA RETENTION
Ratings
Min
>10
Parameter
Data Retention
Units
years
Tester Equivalent Load Circuit
Valid High
3.3V
Output
V1
V2
249
Valid Low
Output
DUT
Output
CL > 50 pf
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HMXNV0100
READ CYCLE
The RAM is synchronous in operation
relative to the rising edge of the Chip Select
(CS) signal. With the initiation of a CS
signal, the address and the Write Enable
(WE) signal are latched into the device and
the read operation begins. The memory
locations are read and compared with the
ECC values. Any single bit errors are
detected and corrected.
If WE was low when latched in, the data is
sent to the output drivers. In addition to WE
low being latched, Output Enable (OE) must
be set to a high value to enable the DQ
output buffers. OE is not latched, and may
be set high before or after the rising edge of
CS.
READ CYCLE AC TIMING CHARACTERISTICS
READ CYCLE
Trdc
CS
Tcspw
ADDR[0:15]
ADDR VALID
Tadsu Tadhd
Tcsdv
WE
OE
Twesu Twehd
Toedv
HIGH Z
DQ[0:15]
OUTPUT DATA VALID
Min
Typ
------
Max
------
Tcspw
Tcspi
CS pulse width (for valid read)
10ns
CS ignored pulse width (glitch tolerance)
------
3ns
------
------
------
------
------
------
------
------
1ns
------
------
------
------
60ns
10ns
------
Twesu
Twehd
Tadsu
Tadhd
Tcsdv
Toedv
Trdc
WE setup time with respect to rising edge of CS
WE hold time with respect to rising edge of CS
Address setup time with respect to rising edge of CS
Address hold time with respect to rising edge of CS
Output data valid with respect to rising edge of CS
Output data valid with respect to rising edge of OE
CS rising edge to next CS rising edge (read cycle time)
2ns
8ns
2ns
------
------
60ns
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HMXNV0100
WRITE CYCLE
The RAM is synchronous in operation
relative to the rising edge of the Chip Select
(CS) signal. With the initiation of a CS
signal, the address and the Write Enable
(WE) signal are latched into the device.
The WRITE CYCLE begins by reading the
current value in memory. The current
memory data is compared to the data to be
written. If the location needs to change
value, the data is then written.
If WE was high when latched in, the Write
Asynchronous (WE_AS) signal is checked.
If WE_AS is high, the WRITE CYCLE will
begin. If WE_AS is low, the WRITE CYCLE
will be delayed until WE_AS is set high. This
allows control by the host processor of the
actual time the data is written to memory.
The bit cell construction of this device does
not provide a method of simply writing a “1”
or a “0” to match the data. The “write” to a
bit can only change its state, thus the need
to read the bit locations first. Only the bits
which need to “change state” are actually
written.
WRITE CYCLE AC TIMING CHARACTERISTICS
NON-DELAYED
W RITE CYCLE - non delayed (W E_ASYN < 40ns after CS)
Twrc
CS
Tcspw
ADDR[0:15]
ADDR VALID
Tadsu Tadhd
W E
Twesu Twehd
Tcswa
W E_ASYN
DQ[0:15]
DATA VALID
DATA W RITTEN
Tdqsu
Tdqhd
NW I
Tcsdw, Tcshd
Min
10ns
Typ
------
Max
Tcspw
Tcspi
CS pulse width (for valid write)
CS ignored pulse width (glitch tolerance)
------
1ns
------
3ns
2ns
8ns
2ns
------
------
------
------
------
Twesu
Twehd
Tadsu
Tadhd
Tcswa
Tdqsu
Tdqhd
Tcsdw
Tcshd
Twrc
W E setup tim e with respect to rising edge of CS
W E hold tim e with respect to rising edge of CS
Address setup tim e with respect to rising edge of CS
Address hold tim e with respect to rising edge of CS
W E_ASYN delay from rising edge of CS
------
------
------
------
40ns
20ns
------
100ns
------
------
DQ setup tim e after rising edge of CS
------
60ns
------
------
------
------
------
DQ hold tim e with respect to rising edge of CS
W RT
Valid data write tim e
rising edge of CS
------
NW I,W E_ASYNC hold tim e W RT rising edge of CS
CS rising edge to next CS rising edge (write cycle tim e)
100ns
100ns
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HMXNV0100
DELAYED
WRITE CYCLE - delayed (WE_ASYN > 40ns after CS)
Twrdc
CS
Tcspw
ADDR VALID
Tadsu Tadhd
ADDR[0:15]
WE
Twesu Twehd
Tcswa
WE_ASYN
DQ[0:15]
DATA VALID
DATA WRITTEN
Tdqsu
Tdqhd
NWI
Twahd
Min
10ns
------
3ns
Typ
Max
------
Tcspw
Tcspi
CS pulse width (for valid write)
CS ignored pulse width (glitch tolerance)
------
------
------
------
------
------
------
------
------
------
------
------
1ns
------
------
------
------
------
------
------
60ns
------
------
Twesu
Twehd
Tadsu
Tadhd
Tcswa
Tdqsu
Tdqhd
Twadw
Twahd
Twrdc
WE setup time with respect to rising edge of CS
WE hold time with respect to rising edge of CS
2ns
8ns
2ns
40ns
4ns
20ns
------
60ns
Address setup time with respect to rising edge of CS
Address hold time with respect to rising edge of CS
WE_ASYN delay from rising edge of CS
DQ setup time to rising edge of WE_ASYN
DQ hold time
WRT
NWI,WE_ASYN, hold time
rising edge of WE_ASYN
WRT
Valid data write time
rising edge of WE_ASYNC
WRT
rising edge of WE_ASYN
Tcswa + 60ns
CS rising edge to next CS rising edge (write cycle time)
POWER UP TIMING
During power-up there are no restrictions on
which supply comes up first provided NWI is
asserted (low). NWI is de-asserted within
1us of both supplies reaching their 90%
values.
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HMXNV0100
POWER-UP SEQUENCE
VDD1
VDD2
NWI
1us
POWER DOWN TIMING
POWER-DOWN SEQUENCE
VDD1
VDD2
NWI
100ns
QUALITY AND RADIATION HARDNESS ASSURANCE
Honeywell maintains a high level of product
integrity through process control, utilizing
statistical process and six sigma controls. It
is part of a “Total Quality Assurance
Program”, the computer-based process
performance tracking system and a radiation
hardness assurance stategy.
SCREENING LEVELS
Honeywell offers several levels of device
screeing to meet your needs. “Engineering
Devices” are available with limited
perfomrance and screening for prototype
development and evaluation testing. Hi-Rel
Level B and S devices undergo additional
screening per the requirements of MIL-STD-
883.
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HMXNV0100
RELIABILITY
Honeywell understands the stringent
reliability requirements that space and
defense systems require. Honeywell has
extensive experience in reliability testing on
programs of this nature. Reliability attributes
of the SOI process were characterized by
testing specially designed structures to
evaluate failure mechanisms including hot
carriers, electro migration, and time-
dependent dielectric breakdown. The
results are feedback to improve the process
to ensure the highest reliability products.
In addition, our products are subjected to
dynamic, accelerated life tests. The
packages used are qualified through MIL-
STD-883, TM 5005 Class S. The product
screening flow can be modified to meet the
specific requirements. Quality conformance
testing is performed as an option on all
production lots to ensure on-going reliability.
PACKAGE OUTLINE
The 64 Lead Shielded Ceramic QFP Package shown is preliminary and is subject to change,
including external capacitors. The outline is for reference only.
.900
39
47
VDD2
VS S
VDD2
VS S
38
48
210
205
200
195
190
185
180
175
170
165
160
155
150
145
140
135
215
220
225
130
125
230
120
235
240
115
110
245
105
100
VS S
250
255
VDD1
95
260
265
90
85
VDD2
.900
270
80
75
275
280
H
o n e yw el
l
5
10
15
20
25
30
35
40
45
50
55
60
65
70
D
SES
11
75
2202xxxx
VS S
VDD2
VS S
VDD2
1
10
.050
.018
.150
.075
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HMXNV0100
ORDERING INFORMATION (1)
H
X
NV
0100
A
S
H
Screen Level
V = QML Class V
Q = QML Class Q
S = Level S
Part Number
Process
0100 = 1 Meg
X = SOI
Total Dose Hardness
R = 1x105 rad (SiO2)
F = 3x105 rad (SiO2)
H = 1x106 rad (SiO2)
N = No Level Guaranteed
Part Type
Package Designation
B = Level B
NV = Non Volatile
A = 64 Lead QFP
Source
E = Eng. Model (2)
H = Honeywell
(1) To order parts or obtain technical assistance, call 1-800-323-8295
(2) Engineering Model Description: Parameters are tested from-55 to 1250C, 24-hour burn-in, no radiation
guarantee.
For more information about Honeywell’s MRAM product and our family of memory and ASIC
products and services, visit www.myspaceparts.com.
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its
patent rights nor the rights of others.
Honeywell International Inc.
Aerospace Electronics Systems
Defense & Space Electronics Systems
12001 Highway 55
Form #900232
Plymouth, MN 55441
1-800-323-8295
May 2005
©2005 Honeywell International Inc.
www.honeywell.com
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