H5TC2G83GFR-PBI_技术文档

2Gb DDR3L SDRAM

Lead-Free&Halogen-Free

(RoHS Compliant)

H5TC2G83GFR-xxA

H5TC2G83GFR-xxI

H5TC2G83GFR-xxL

H5TC2G83GFR-xxJ

H5TC2G63GFR-xxA

H5TC2G63GFR-xxI

H5TC2G63GFR-xxL

H5TC2G63GFR-xxJ

* SK Hynix reserves the right to change products or specifications without notice.

Rev. 1.3 / Nov. 2015

1

Revision History

Revision No.

History

Draft Date

Mar. 2015

June. 2015

July. 2015

Oct. 2015

Nov. 2015

Remark

Preliminary

Page 25

0.1

1.0

1.1

1.2

1.3

Preliminary version release

IDD update

Operating NOTE update

IDD update

Page 4

Page 25 - IDD3N x16

Page 4

Typo Correct

Rev. 1.3 / Nov. 2015

2

Description

The H5TC2G83GFR-xxA(I,L,J) and H5TC2G63GFR-xxA(I,L,J) are a 2Gb low power Double Data Rate III

(DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large mem-

ory density, high bandwidth and low power operation at 1.35V. SK Hynix DDR3L SDRAM provides back-

ward compatibility with the 1.5V DDR3 based environment without any changes. SK Hynix 2Gb DDR3L

SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While

all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock),

data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data

paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.

Device Features and Ordering Information

FEATURES

• VDD=VDDQ=1.35V + 0.100 / - 0.067V

• Fully differential clock inputs (CK, CK) operation

• Differential Data Strobe (DQS, DQS)

• BL switch on the fly

• 8banks

• AverageRefreshCycle (Tcaseof0 ^oC~95^oC)

- 7.8 µs at 0^oC ~ 85 ^oC

- 3.9 µs at 85^oC ~ 95 ^oC

• On chip DLL align DQ, DQS and DQS transition with CK

transition

Commerical Temperature (0^oC ~ 95 ^oC)

Industrial Temperature(-40^oC ~ 95 ^oC)

• DM masks write data-in at the both rising and falling

edges of the data strobe

• All addresses and control inputs except data,

data strobes and data masks latched on the

rising edges of the clock

• JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)

• Driver strength selected by EMRS

• Dynamic On Die Termination supported

• Asynchronous RESET pin supported

• ZQ calibration supported

• Programmable CAS latency 6, 7, 8, 9, 10, 11, 12 and

13

supported

• Programmable additive latency 0, CL-1, and CL-2

supported

• TDQS (Termination Data Strobe) supported (x8 only)

• Write Levelization supported

• Programmable CAS Write latency (CWL) = 5, 6, 7, 8

and 9

• 8 bit pre-fetch

• Programmable burst length 4/8 with both nibble

sequential and interleave mode

* This product in compliance with the RoHS directive.

Rev. 1.3 / Nov. 2015

3

ORDERING INFORMATION

Part No.

Configuration

Power Consumption

Temperature

Package

H5TC2G83GFR-*xxA

H5TC2G83GFR-*xxI

H5TC2G83GFR-*xxL

H5TC2G83GFR-*xxJ

H5TC2G63GFR-*xxA

H5TC2G63GFR-*xxI

H5TC2G63GFR-*xxL

H5TC2G63GFR-*xxJ

Commercial

Industrial

Normal Consumption

256M x 8

78ball FBGA

Commercial

Industrial

Low Power Consumption

(IDD6 Only)

Commercial

Industrial

Normal Consumption

128M x 16

96ball FBGA

Commercial

Industrial

Low Power Consumption

(IDD6 Only)

* xx means Speed Bin Grade

OPERATING FREQUENCY

Frequency [Mbps]

CL5 CL6 CL7 CL8 CL9 CL10 CL11 CL12 CL13 CL14

Speed

Grade

(Marking)

Remark

(CL-tRCD-tRP)

-G7*

-H9*

-PB*

-RD

667

800 1066 1066

DDR3L-1066 7-7-7

800 1066 1066 1333 1333

DDR3L-1333 9-9-9

1600

DDR3L-1600 11-11-11

DDR3L-1866 13-13-13

1866

*Note1: -RD covers lower speed of -PB and -H9 and -G7.

Rev. 1.3 / Nov. 2015

4

x8 Package Ball out (Top view): 78ball FBGA Package

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

VSS

VDD

VSSQ

DQ2

DQ6

VDDQ

VSS

VDD

CS

NC

DQ0

DQS

DQ4

RAS

CAS

WE

NU/TDQS

DM/TDQS

DQ1

VSS

VSSQ

DQ3

VSS

DQ5

VSS

VDD

ZQ

VDD

VDDQ

VSSQ

VDDQ

NC

A

B

C

D

E

F

VDDQ

VSSQ

VREFDQ

NC

VDD

DQ7

CK

G

H

J

ODT

NC

CK

CKE

NC

G

H

J

A10/AP

NC

VSS

BA0

A3

BA2

A0

VREFCA

BA1

A4

VSS

K

L

VDD

VSS

A12/BC

A1

VDD

VSS

K

L

A5

A2

M

N

VDD

VSS

A7

A9

A11

A6

VDD

VSS

M

N

RESET

A13

A14

A8

1

2

3

4

5

6

7

8

9

1

2

3

7

8

9

A

B

C

D

E

(Top View: See the balls through the Package)

F

Populated ball

Ball not populated

G

H

J

K

L

M

N

Rev. 1.3 / Nov. 2015

5

x16 Package Ball out (Top view): 96ball FBGA Package

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

VDDQ

VSSQ

VDDQ

VSSQ

VSS

DQU5

VDD

DQU3

VDDQ

VSSQ

DQL2

DQL6

VDDQ

VSS

DQU7

VSS

DQU1

DMU

DQL0

DQSL

DQL4

RAS

CAS

WE

DQU4

DQSU

DQU0

DML

DQL1

VDD

VDDQ

DQU6

DQU2

VSSQ

DQL3

VSS

VSSQ

VDDQ

VDD

VDDQ

VSSQ

VDDQ

NC

A

B

C

D

E

F

VDDQ

VSSQ

VREFDQ

NC

G

H

J

G

H

J

DQL7

CK

DQL5

VSS

K

L

ODT

VDD

CS

CK

VDD

CKE

NC

K

L

NC

A10/AP

NC

ZQ

M

N

P

R

T

VSS

BA0

BA2

A0

VREFCA

BA1

VSS

M

N

P

R

T

VDD

A3

A12/BC

A1

VDD

VSS

A5

A2

A4

VDD

A7

A9

A11

A6

VDD

VSS

RESET

A13

NC

A8

1

2

3

4

5

6

7

8

9

Rev. 1.3 / Nov. 2015

6

1

2 3

7

8 9

A

B

C

D

E

F

G

H

J

(Top View: See the balls through the Package)

Populated ball

Ball not populated

K

L

M

N

P

R

T

Pin Functional Description

Symbol

Type

Function

Clock: CK and CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of CK.

CK, CK

Input

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and

device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down

and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any

bank).

CKE, (CKE0),

(CKE1)

Input CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable

during the power on and initialization sequence, they must be maintained during all

operations (including Self-Refresh). CKE must be maintained high throughout read and

write accesses. Input buffers, excluding CK, CK, ODT and CKE, are disabled during power-

down. Input buffers, excluding CKE, are disabled during Self-Refresh.

Chip Select: All commands are masked when CS is registered HIGH.

CS provides for external Rank selection on systems with multiple Ranks.

CS is considered part of the command code.

CS, (CS0),

(CS1), (CS2),

(CS3)

Input

Rev. 1.3 / Nov. 2015

7

Symbol

Type

Function

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the

DDR3L SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS,

NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x4/x8

configurations. For x16 configuration, ODT is applied to each DQ, DQSU, DQSU, DQSL,

DQSL, DMU, and DML signal. The ODT pin will be ignored if MR1 is programmed to disable

ODT.

ODT, (ODT0),

(ODT1)

Input

Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

RAS.

CAS. WE

Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH coincident with that input data during a Write access. DM is sampled

on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by

Mode Register A11 setting in MR1.

DM, (DMU),

(DML)

Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge

BA0 - BA2

A0 - A15

Input command is being applied. Bank address also determines if the mode register or extended

mode register is to be accessed during a MRS cycle.

Address Inputs: Provide the row address for Active commands and the column address for

Read/Write commands to select one location out of the memory array in the respective

bank. (A10/AP and A12/BC have additional functions, see below).

Input

The address inputs also provide the op-code during Mode Register Set commands.

Auto-precharge: A10 is sampled during Read/Write commands to determine whether

Autoprecharge should be performed to the accessed bank after the Read/Write operation.

(HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge

command to determine whether the Precharge applies to one bank (A10 LOW) or all

banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank

addresses.

A10 / AP

A12 / BC

Input

Burst Chop: A12 / BC is sampled during Read and Write commands to determine if burst

Input chop (on-the-fly) will be performed.

(HIGH, no burst chop; LOW: burst chopped). See command truth table for details.

Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when

RESET is HIGH. RESET must be HIGH during normal operation.

RESET is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of V_DD, i.e.

1.20V for DC high and 0.30V for DC low.

RESET

DQ

Input

Input /

Data Input/ Output: Bi-directional data bus.

Output

Data Strobe: output with read data, input with write data. Edge-aligned with read data,

centered in write data. The data strobe DQS, DQSL, and DQSU are paired with differential

signals DQS, DQSL, and DQSU, respectively, to provide differential pair signaling to the

system during reads and writes. DDR3L SDRAM supports differential data strobe only and

does not support single-ended.

DQU, DQL,

DQS, DQS,

DQSU, DQSU, Output

DQSL, DQSL

Input /

Rev. 1.3 / Nov. 2015

8

Symbol

Type

Function

Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. When enabled via

Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance

TDQS, TDQS Output function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11

= 0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4

DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.

NC

NF

No Connect: No internal electrical connection is present.

No Function

V_DDQ

V_SSQ

V_DD

Supply DQ Power Supply: 1.35 V +0.100/-0.067V

Supply

DQ Ground

Power Supply: 1.35 V +0.100/-0.067V

Ground

V_SS

Reference voltage for DQ

Reference voltage for CA

Reference Pin for ZQ calibration

V_REFDQ

V_REFCA

ZQ

Note:

Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination.

ROW AND COLUMN ADDRESS TABLE

2Gb

Configuration

# of Banks

256Mb x 8

128Mb x 16

8

Bank Address

Auto precharge

BL switch on the fly

Row Address

Column Address

Page size ¹

BA0 - BA2

A10/AP

A12/BC

A0 - A14

A0 - A9

1 KB

BA0 - BA2

A10/AP

A12/BC

A0 - A13

A0 - A9

2 KB

Rev. 1.3 / Nov. 2015

9

Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers

when an ACTIVE command is registered. Page size is per bank, calculated as follows:

page size = 2 ^COLBITS* ORG  8

where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits

Absolute Maximum Ratings

Absolute Maximum DC Ratings

Symbol

Parameter

Voltage on VDD pin relative to Vss

Voltage on VDDQ pin relative to Vss

Voltage on any pin relative to Vss

Storage Temperature

Rating

Units

Notes

VDD

- 0.4 V ~ 1.80 V

V

1,3

VDDQ

V_IN, V_OUT

T_STG

- 0.4 V ~ 1.80 V

-55 to +100

V

1,3

1

V

^oC

1, 2

Rev. 1.3 / Nov. 2015

10

Absolute Maximum DC Ratings

Notes:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these or any other conditions above

those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-

ing conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement

conditions, please refer to JESD51-2 standard.

3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than

0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.

DRAM Component Operating Temperature Range

Temperature Range

Symbol

Parameter

Normal Operating Temperature Range

Extended Temperature Range

Rating

0 to 85

85 to 95

Units

^oC

Notes

1,2

1,4

T_OPER

-40 to 95

^oC

1,3,4

Industrial Temperature Range

Notes:

1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea-

surement conditions, please refer to the JEDEC document JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-

ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.

3. The Industrial Temperature Range specifies the temperatures where all DRAM specifications will be supported.

During operation, the DRAM case temperature must be maintained between -40 - 85oC under all operating condi-

tions.

4. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC

case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:

a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs.

b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the Man-

ual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b).

AC & DC Operating Conditions

Recommended DC Operating Conditions

Recommended DC Operating Conditions - DDR3L (1.35V) operation

Rating

Symbol

Parameter

Units

Notes

Min.

Typ.

Max.

VDD

1.283

1.35

1.45

V

1,2,3,4

Supply Voltage

Rev. 1.3 / Nov. 2015

11

VDDQ

Notes:

1.283

1.35

1.45

V

1,2,3,4

Supply Voltage for Output

1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a

very long period of time (e.g., 1 sec).

2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.

3. Under these supply voltages, the device operates to this DDR3L specification.

4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and

VDDQ are changed for DDR3 operation (see Figure 0).

Recommended DC Operating Conditions - DDR3 (1.5V) operation

Rating

Symbol

Parameter

Units

Notes

Min.

Typ.

Max.

VDD

1.425

1.5

1.575

V

1,2,3

Supply Voltage

Supply Voltage for Output

VDDQ

1.425

1.5

1.575

Notes:

1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.

2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as

defined for this device.

3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and

VDDQ are changed for DDR3L operation (see Figure 0).

Rev. 1.3 / Nov. 2015

12

Ta

Tb

Tc

Td

Te

Tf

Tg

Th

Ti

Tj

Tk

CK,CK#

tCKSRX

Tmin = 10ns

VDD, VDDQ (DDR3)

VDD, VDDQ (DDR3L)

Tmin = 10ns

Tmin = 200us

T = 500us

RESET#

Tmin = 10ns

CKE

VALID

tDLLK

tIS

tXPR

tMRD

tMOD

tZQinit

1)

COMMAND

BA

READ

1)

MRS

MR2

MRS

MR3

MRS

MR1

MRS

MR0

ZQCL

VALID

tIS

ODT

RTT

READ

Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW

VALID

NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied

between MRS and ZQCL commands.

DON’T CARE

TIME BREAK

Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3L

Rev. 1.3 / Nov. 2015

13

IDD and IDDQ Specification Parameters and Test Conditions

IDD and IDDQ Measurement Conditions

In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure

1. shows the setup and test load for IDD and IDDQ measurements.

•

IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,

IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls

of the DDR3L SDRAM under test tied together. Any IDDQ current is not included in IDD currents.

•

IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all

VDDQ balls of the DDR3L SDRAM under test tied together. Any IDD current is not included in IDDQ

currents.

Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3L SDRAM. They can

be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In

DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one

merged-power layer in Module PCB.

For IDD and IDDQ measurements, the following definitions apply:

•

”0” and “LOW” is defined as VIN <= V

ILAC(max).

”1” and “HIGH” is defined as VIN >= V

IHAC(max).

•

“MID_LEVEL” is defined as inputs are VREF = VDD/2.

Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.

Basic IDD and IDDQ Measurement Conditions are described in Table 2.

Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.

IDD Measurements are done after properly initializing the DDR3L SDRAM. This includes but is not lim-

ited to setting

RON = RZQ/7 (34 Ohm in MR1);

Qoff = 0 (Output Buffer enabled in MR1);

B

RTT_Nom = RZQ/6 (40 Ohm in MR1);

RTT_Wr = RZQ/2 (120 Ohm in MR2);

TDQS Feature disabled in MR1

•

Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time

before actual IDD or IDDQ measurement is started.

•

Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}

Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}

Rev. 1.3 / Nov. 2015

14

IDDQ (optional)

IDD

VDD

RESET

CK/CK

VDDQ

DDR3L

SDRAM

RTT = 25 Ohm

CKE

CS

DQS, DQS

DQ, DM,

VDDQ/2

RAS, CAS, WE

TDQS, TDQS

A, BA

ODT

ZQ

VSS

VSSQ

Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements

[Note: DIMM level Output test load condition may be different from above]

Application specific

memory channel

environment

IDDQ

Test Load

Channel

IO Power

Simulation

IDDQ

Simulation

IDDQ

Simulation

Correction

Channel IO Power

Number

Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported

by IDDQ Measurement

Rev. 1.3 / Nov. 2015

15

Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns

DDR3L-1066

DDR3L-1333

DDR3L-1600

DDR3L-1866

Symbol

Unit

7-7-7

9-9-9

1.5

9

11-11-11

13-13-13

t_CK

1.875

1.25

11

1.07

13

ns

CL

7

nCK

n_RCD

n_RC

n_RAS

n_RP

9

11

13

27

20

7

33

24

9

39

45

28

32

11

13

1KB page

20

27

4

20

30

4

24

32

5

26

33

5

nCK

size

n_FAW

2KB page

size

1KB page

size

n_RRD

2KB page

size

6

5

6

n_RFC-512Mb

n_RFC-1 Gb

n_RFC- 2 Gb

n_RFC- 4 Gb

n_RFC- 8 Gb

48

59

60

74

72

88

85

nCK

103

150

243

328

86

107

174

234

128

208

280

139

187

Table 2 -Basic IDD and IDDQ Measurement Conditions

Symbol

Description

Operating One Bank Active-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8^a); AL: 0; CS: High between ACT

and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO:

MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see

I_DD0

Table 3); Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details:

see Table 3.

Rev. 1.3 / Nov. 2015

16

Symbol

Description

Operating One Bank Active-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8^a); AL: 0; CS: High between

ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to

Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table

I_DD1

4); Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details: see

Table 4.

Precharge Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0;

I_DD2N

I_DD2NT

I_DD2P0

Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable

at 0; Pattern Details: see Table 5.

Precharge Standby ODT Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0;

Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: tog-

gling according to Table 6; Pattern Details: see Table 6.

Precharge Power-Down Current Slow Exit

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Precharge Power Down

Mode: Slow Exit^c)

Precharge Power-Down Current Fast Exit

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;

I_DD2P1

Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Precharge Power Down

Mode: Fast Exit^c)

Precharge Quiet Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;

I_DD2Q

Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0

Rev. 1.3 / Nov. 2015

17

Symbol

Description

Active Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0;

I_DD3N

Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable

at 0; Pattern Details: see Table 5.

Active Power-Down Current

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open;

I_DD3P

Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0

Operating Burst Read Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: High between RD; Command,

Address, Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst

with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank

Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer

I_DD4R

and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details: see Table 7.

Operating Burst Write Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: High between WR; Command,

Address, Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst

with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank

Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buf-

I_DD4W

fer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at HIGH; Pattern Details: see Table 8.

Burst Refresh Current

CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8^a); AL: 0; CS: High between REF; Com-

mand, Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM:

stable at 0; Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in

I_DD5B

Mode Registers^b); ODT Signal: stable at 0; Pattern Details: see Table 9.

Self-Refresh Current: Normal Temperature Range

T_CASE: 0 - 85 ^oC; Auto Self-Refresh (ASR): Disabled^d);Self-Refresh Temperature Range (SRT): Normal^e);

I_DD6

CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8^a); AL: 0; CS, Command, Address,

Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Out-

put Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: MID_LEVEL

Rev. 1.3 / Nov. 2015

18

Symbol

Description

Self-Refresh Current: Extended Temperature Range

T_CASE: 0 - 95 ^oC; Auto Self-Refresh (ASR): Disabled^d);Self-Refresh Temperature Range (SRT): Extend-

ed^e); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8^a); AL: 0; CS, Command,

Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Tempera-

I_DD6ET

ture Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal:

MID_LEVEL

Operating Bank Interleave Read Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8^{a), f)}; AL: CL-

1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling accord-

ing to Table 10; Data IO: read data burst with different data between one burst and the next one

according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0,

I_DD7

1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registers^b);

ODT Signal: stable at 0; Pattern Details: see Table 10.

a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;

RTT_Wr enable: set MR2 A[10,9] = 10B

c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit

d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature

e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range

f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B

Rev. 1.3 / Nov. 2015

19

Table 3 - IDD0 Measurement-Loop Pattern^a)

Data^b)

0

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

-

0

1,2

3,4

...

repeat pattern 1...4 until nRAS - 1, truncate if necessary

nRAS

PRE

0

1

0

00

0

-

...

repeat pattern 1...4 until nRC - 1, truncate if necessary

1*nRC+0

1*nRC+1, 2

1*nRC+3, 4

...

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

F

0

-

repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary

PRE 00

1*nRC+nRAS

...

0

1

0

F

0

-

repeat pattern 1...4 until 2*nRC - 1, truncate if necessary

repeat Sub-Loop 0, use BA[2:0] = 1 instead

repeat Sub-Loop 0, use BA[2:0] = 2 instead

repeat Sub-Loop 0, use BA[2:0] = 3 instead

repeat Sub-Loop 0, use BA[2:0] = 4 instead

repeat Sub-Loop 0, use BA[2:0] = 5 instead

repeat Sub-Loop 0, use BA[2:0] = 6 instead

repeat Sub-Loop 0, use BA[2:0] = 7 instead

1

2

3

4

5

6

7

2*nRC

4*nRC

6*nRC

8*nRC

10*nRC

12*nRC

14*nRC

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.

b) DQ signals are MID-LEVEL.

Rev. 1.3 / Nov. 2015

20

Table 4 - IDD1 Measurement-Loop Pattern^a)

Data^b)

0

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

-

0

1,2

3,4

...

repeat pattern 1...4 until nRCD - 1, truncate if necessary

RD 00

repeat pattern 1...4 until nRAS - 1, truncate if necessary

nRCD

...

0

1

0

1

0

00000000

-

nRAS

PRE

0

1

0

00

0

...

repeat pattern 1...4 until nRC - 1, truncate if necessary

1*nRC+0

1*nRC+1,2

1*nRC+3,4

...

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

F

0

-

repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary

RD 00

repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary

PRE 00

1*nRC+nRCD

...

0

1

0

1

0

F

0

00110011

-

1*nRC+nRAS

...

0

1

0

F

0

repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary

repeat Sub-Loop 0, use BA[2:0] = 1 instead

repeat Sub-Loop 0, use BA[2:0] = 2 instead

repeat Sub-Loop 0, use BA[2:0] = 3 instead

repeat Sub-Loop 0, use BA[2:0] = 4 instead

repeat Sub-Loop 0, use BA[2:0] = 5 instead

repeat Sub-Loop 0, use BA[2:0] = 6 instead

repeat Sub-Loop 0, use BA[2:0] = 7 instead

1

2

3

4

5

6

7

2*nRC

4*nRC

6*nRC

8*nRC

10*nRC

12*nRC

14*nRC

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.

b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.

Rev. 1.3 / Nov. 2015

21

Table 5 - IDD2N and IDD3N Measurement-Loop Pattern^a)

Data^b)

0

D

1

0

1

0

1

0

1

0

F

0

-

0

1

2

3

1

2

3

4

5

6

7

4-7

repeat Sub-Loop 0, use BA[2:0] = 1 instead

repeat Sub-Loop 0, use BA[2:0] = 2 instead

repeat Sub-Loop 0, use BA[2:0] = 3 instead

repeat Sub-Loop 0, use BA[2:0] = 4 instead

repeat Sub-Loop 0, use BA[2:0] = 5 instead

repeat Sub-Loop 0, use BA[2:0] = 6 instead

repeat Sub-Loop 0, use BA[2:0] = 7 instead

8-11

12-15

16-19

20-23

24-17

28-31

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.

b) DQ signals are MID-LEVEL.

Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern^a)

Data^b)

0

D

1

0

1

0

1

0

1

0

-

0

1

0

F

0

2

3

1

2

3

4

5

6

7

4-7

repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3

repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4

repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7

8-11

12-15

16-19

20-23

24-17

28-31

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.

b) DQ signals are MID-LEVEL.

Rev. 1.3 / Nov. 2015

22

Table 7 - IDD4R and IDDQ4R Measurement-Loop Pattern^a)

Data^b)

0

RD

D

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00

0

F

0

00000000

0

1

-

2,3

D,D

RD

D

-

4

00110011

5

-

6,7

D,D

1

2

3

4

5

6

7

8-15

16-23

24-31

32-39

40-47

48-55

56-63

repeat Sub-Loop 0, but BA[2:0] = 1

repeat Sub-Loop 0, but BA[2:0] = 2

repeat Sub-Loop 0, but BA[2:0] = 3

repeat Sub-Loop 0, but BA[2:0] = 4

repeat Sub-Loop 0, but BA[2:0] = 5

repeat Sub-Loop 0, but BA[2:0] = 6

repeat Sub-Loop 0, but BA[2:0] = 7

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.

b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

Rev. 1.3 / Nov. 2015

23

Table 8 - IDD4W Measurement-Loop Pattern^a)

Data^b)

0

WR

D

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00

0

F

0

00000000

0

1

-

2,3

D,D

WR

D

-

4

00110011

5

-

6,7

D,D

1

2

3

4

5

6

7

8-15

16-23

24-31

32-39

40-47

48-55

56-63

repeat Sub-Loop 0, but BA[2:0] = 1

repeat Sub-Loop 0, but BA[2:0] = 2

repeat Sub-Loop 0, but BA[2:0] = 3

repeat Sub-Loop 0, but BA[2:0] = 4

repeat Sub-Loop 0, but BA[2:0] = 5

repeat Sub-Loop 0, but BA[2:0] = 6

repeat Sub-Loop 0, but BA[2:0] = 7

a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.

b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.

Table 9 - IDD5B Measurement-Loop Pattern^a)

Data^b)

0

1

0

REF

D, D

0

1

0

1

0

1

0

1

0

F

0

-

1.2

00

3,4

5...8

repeat cycles 1...4, but BA[2:0] = 1

repeat cycles 1...4, but BA[2:0] = 2

repeat cycles 1...4, but BA[2:0] = 3

repeat cycles 1...4, but BA[2:0] = 4

repeat cycles 1...4, but BA[2:0] = 5

repeat cycles 1...4, but BA[2:0] = 6

repeat cycles 1...4, but BA[2:0] = 7

9...12

13...16

17...20

21...24

25...28

29...32

33...nRFC-1

2

repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.

b) DQ signals are MID-LEVEL.

Rev. 1.3 / Nov. 2015

24

Table 10 - IDD7 Measurement-Loop Pattern^a)

ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9

Data^b)

0

1

0

1

2

...

ACT

RDA

D

0

1

0

1

0

1

0

1

0

00

0

1

0

-

00000000

-

repeat above D Command until nRRD - 1

nRRD

nRRD+1

nRRD+2

...

2*nRRD

3*nRRD

4*nRRD

ACT

RDA

D

0

1

0

1

0

1

0

1

0

1

00

0

1

0

F

0

-

00110011

-

repeat above D Command until 2* nRRD - 1

repeat Sub-Loop 0, but BA[2:0] = 2

repeat Sub-Loop 1, but BA[2:0] = 3

2

3

D

1

0

3

00

0

F

0

-

4

Assert and repeat above D Command until nFAW - 1, if necessary

repeat Sub-Loop 0, but BA[2:0] = 4

repeat Sub-Loop 1, but BA[2:0] = 5

repeat Sub-Loop 0, but BA[2:0] = 6

repeat Sub-Loop 1, but BA[2:0] = 7

5

6

7

8

nFAW

nFAW+nRRD

nFAW+2*nRRD

nFAW+3*nRRD

nFAW+4*nRRD

D

1

0

7

00

0

F

0

9

Assert and repeat above D Command until 2* nFAW - 1, if necessary

2*nFAW+0

2*nFAW+1

ACT

RDA

D

0

1

0

1

0

1

0

1

0

00

0

1

0

F

0

-

00110011

-

10

2&nFAW+2

Repeat above D Command until 2* nFAW + nRRD - 1

2*nFAW+nRRD

2*nFAW+nRRD+1 RDA

ACT

0

1

0

1

0

1

0

1

0

1

00

0

1

0

-

00000000

-

11

D

2&nFAW+nRRD+

2

Repeat above D Command until 2* nFAW + 2* nRRD - 1

12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2

13 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3

D

1

0

3

00

0

-

14 2*nFAW+4*nRRD

Assert and repeat above D Command until 3* nFAW - 1, if necessary

repeat Sub-Loop 10, but BA[2:0] = 4

15 3*nFAW

16 3*nFAW+nRRD

repeat Sub-Loop 11, but BA[2:0] = 5

17 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6

18 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7

D

1

0

7

00

0

-

19 3*nFAW+4*nRRD

Assert and repeat above D Command until 4* nFAW - 1, if necessary

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.

b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

Rev. 1.3 / Nov. 2015

25

IDD Specifications

IDD values are for full operating range of voltage and temperature unless otherwise noted.

I_DDSpecification

Speed Grade

Bin

DDR3L - 1066 DDR3 L- 1333 DDR3L - 1600 DDR3L - 1866

7-7-7

Max.

28

33

32

41

11

14

13

14

15

16

14

16

19

23

29

50

90

54

95

143

150

9

9-9-9

Max.

28

11-11-11

Max.

28

13-13-13

Max.

32

Unit

Notes

Symbol

mA

x8

x16

x8

I

DD0

33

35

36

32

36

I

DD01

41

45

x16

x8

11

I

DD2P0

11

x16

x8

11

DD2P1

14

x16

x8

14

16

I

DD2N

14

16

x16

x8

16

18

19

I

DD2NT

16

18

19

x16

x8

14

16

I

DD2Q

16

x16

x8

19

20

I

DD3P

DD3N

DD4R

DD4w

24

25

x16

x8

24

25

26

I

31

32

33

x16

x8

63

69

82

I

100

68

110

74

125

87

x16

x8

I

105

143

150

9

115

146

155

9

130

146

155

9

x16

x8

I

DD5

x16

x8

DD6

9

x16

x8/16

x8

I

Low Power)

6

DD6 (

11

104

180

11

I

DD6ET

11

x16

x8

114

180

115

185

130

189

I

DD7

x16

Notes:

1. Applicable for MR2 settings A6=0 and A7=0. Temperature range for IDD6 is 0 - 85^oC.

2. Applicable for MR2 settings A6=0 and A7=1. Temperature range for IDD6ET is 0 - 95^oC.

Rev. 1.3 / Nov. 2015

26

Input/Output Capacitance

DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866

Parameter

Symbol

Units Notes

Min

Max Min Max Min Max Min Max

Input/output capacitance

(DQ, DM, DQS, DQS, TDQS,

TDQS)

C_IO

1.4

2.7

1.4

2.5

1.4

2.3

1.4

2.2

pF

1,2,3

Input capacitance, CK and

CK

Input capacitance delta

CK and CK

Input capacitance delta,

DQS and DQS

Input capacitance

(All other input-only pins)

Input capacitance delta

(All CTRL input-only pins)

Input capacitance delta

(All ADD/CMD input-only

pins)

C_CK

C_DCK

C_DDQS

C_I

0.8

0

1.6

0.8

0

1.4

0.15

1.3

0.8

0

1.4

0.15

1.3

0.8

0

1.3

0.15

1.2

pF

2,3

2,3,4

2,3,5

2,3,6

2,3,7,8

0.15

0.20

0

0.75

-0.5

1.35 0.75

0.75

-0.4

0.75

-0.4

C_{DI_CTRL}

0.3

0.5

-0.4

0.2

C_{DI_ADD_}

-0.5

0.4

-0.4

0.4

-0.4

0.4

pF 2,3,9,10

CMD

Input/output capacitance

delta

(DQ, DM, DQS, DQS)

Input/output capacitance of

ZQ pin

C_DIO

-0.5

-

0.3

3

-0.5

-

0.3

3

-0.5

-

0.3

3

-0.5

-

0.3

3

pF

2,3,11

2,3,12

C_ZQ

Notes:

1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS.

2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is

measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK

ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE,

RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.

3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

4. Absolute value of C_CK-C_CK.

5. Absolute value of C_IO(DQS)-C_IO(DQS).

6. C_Iapplies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.

7. C_{DI_CTR}applies to ODT, CS and CKE.

8. C_{DI_CTRL}=C_I(CNTL) - 0.5 * C_I(CLK) + C_I(CLK))

9. C_{DI_ADD_CMD}applies to A0-A15, BA0-BA2, RAS, CAS and WE.

10. C_{DI_ADD_CMD}=C_I(ADD_CMD) - 0.5*(C_I(CLK)+C_I(CLK))

11. C_DIO=C_IO(DQ) - 0.5*(C_IO(DQS)+C_IO(DQS))

12. Maximum external load capacitance an ZQ pin: 5 pF.

Rev. 1.3 / Nov. 2015

27

Standard Speed Bins

DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.

DDR3L-1066 Speed Bins

For specific Notes see “Speed Bin Table Notes” on page 31.

Speed Bin

DDR3L-1066

7-7-7

Unit

Note

CL - nRCD - nRP

Parameter

Symbol

min

max

Internal read command to

first data

t_AA

13.125

20

ns

ACT to internal read or

write delay time

t_RCD

13.125

50.625

—

t_RP

PRE command period

ACT to ACT or REF

command period

t_RC

ACT to PRE command

period

t_RAS

37.5

3.0

9 * tREFI

3.3

ns

1, 2, 3, 4, 6,

12,13

t_CK(AVG)

CWL = 5

CL = 5

t_CK(AVG)

CWL = 6

Reserved

ns

4

1, 2, 3, 6

1, 2, 3, 4

4

CWL = 5

CL = 6

2.5

3.3

CWL = 6

Reserved

ns

CWL = 5

CL = 7

ns

CWL = 6

1.875

< 2.5

ns

1, 2, 3, 4

4

CWL = 5

CL = 8

Reserved

ns

CWL = 6

ns

1, 2, 3

13

n_CK

Supported CL Settings

Supported CWL Settings

5, 6, 7, 8

5, 6

Rev. 1.3 / Nov. 2015

28

DDR3L-1333 Speed Bins

For specific Notes see “Speed Bin Table Notes” on page 31.

Speed Bin

DDR3L-1333

9-9-9

Unit

Note

CL - nRCD - nRP

Parameter

Symbol

min

13.5

max

Internal read

command to first data

t_AA

t_RCD

t_RP

20

ns

(13.125)^5,11

13.5

(13.125)^5,11

ACT to internal read or

write delay time

—

13.5

(13.125)^5,11

PRE command period

49.5

(49.125)^5,11

ACT to ACT or REF

command period

t_RC

ACT to PRE command

period

t_RAS

36

9 * tREFI

3.3

ns

1, 2, 3, 4,

7, 12,13

t_CK(AVG)

CWL = 5

CL = 5

3.0

t_CK(AVG)

CWL = 6, 7

Reserved

ns

4

CWL = 5

2.5

3.3

1, 2, 3, 7

CL = 6

CL = 7

CL = 8

CWL = 6

CWL = 7

CWL = 5

Reserved

1, 2, 3, 4, 7

4

1.875

< 2.5

t_CK(AVG)

CWL = 6

ns

1, 2, 3, 4, 7

(Optional)⁵

Reserved

t_CK(AVG)

CWL = 7

CWL = 5

ns

1, 2, 3, 4

4

CWL = 6

1, 2, 3, 7

1, 2, 3, 4

4

CWL = 7

Reserved

CWL = 5, 6

CWL = 7

CL = 9

1.5

<1.875

1, 2, 3, 4

4

CWL = 5, 6

Reserved

(Optional)

CL = 10

ns

1, 2, 3

5

t_CK(AVG)

CWL = 7

n_CK

Supported CL Settings

Supported CWL Settings

5, 6, 8, (7), 9, (10)

5, 6, 7

n_CK

Rev. 1.3 / Nov. 2015

29

DDR3L-1600 Speed Bins

For specific Notes see “Speed Bin Table Notes” on page 31.

Speed Bin

DDR3L-1600

11-11-11

Unit

Note

CL - nRCD - nRP

Parameter

Symbol

min

13.75

max

Internal read

command to first data

t_AA

t_RCD

t_RP

20

ns

(13.125)^5,11

13.75

(13.125)^5,11

ACT to internal read or

write delay time

—

13.75

(13.125)^5,11

PRE command period

48.75

(48.125)^5,11

ACT to ACT or REF

command period

t_RC

ACT to PRE command

period

t_RAS

35

9 * tREFI

3.3

ns

1, 2, 3, 4,

8, 12,13

4

t_CK(AVG)

CWL = 5

CL = 5

3.0

t_CK(AVG)

CWL = 6, 7

Reserved

ns

CWL = 5

2.5

3.3

1, 2, 3, 8

CL = 6

CL = 7

CWL = 6

CWL = 7

CWL = 5

Reserved

1, 2, 3, 4, 8

4

1.875

< 2.5

t_CK(AVG)

CWL = 6

ns

1, 2, 3, 4, 8

(Optional)⁵

Reserved

t_CK(AVG)

CWL = 7

CWL = 8

CWL = 5

CWL = 6

CWL = 7

CWL = 8

CWL = 5, 6

ns

1, 2, 3, 4, 8

4

1.875

1.5

< 2.5

1, 2, 3, 8

1, 2, 3, 4, 8

1, 2, 3, 4

4

CL = 8

CL = 9

Reserved

<1.875

t_CK(AVG)

CWL = 7

ns

1, 2, 3, 4, 8

(Optional)⁵

Reserved

t_CK(AVG)

CWL = 8

ns

1, 2, 3, 4

4

CWL = 5, 6

CL = 10 CWL = 7

CWL = 8

1.5

<1.875

<1.5

ns

1, 2, 3, 8

1, 2, 3, 4

4

Reserved

ns

CWL = 5, 6,7

CL = 11

ns

CWL = 8

1.25

ns

1, 2, 3

n_CK

Supported CL Settings

Supported CWL Settings

5, 6, (7), 8, (9), 10, 11

5, 6, 7, 8

Rev. 1.3 / Nov. 2015

30

DDR3L-1866 Speed Bins

For specific Notes see “Speed Bin Table Notes” on page 31.

Speed Bin

DDR3L-1866

13-13-13

Unit

Note

CL - nRCD - nRP

Parameter

Symbol

min

max

13.91

(13.125)^5,14

13.91

(13.125)^5,14

13.91

(13.125)^5,14

Internal read command

to first data

t_AA

t_RCD

t_RP

20

ns

ACT to internal read or

write delay time

—

PRE command period

ACT to PRE command

period

t_RAS

t_RC

34

9 * tREFI

47.91

(47.125)^5,14

3.0

ACT to ACT or PRE

command period

-

t_CK(AVG)

CWL = 5

CL = 5

3.3

ns

n_CK

1, 2, 3, 4, 9

CWL = 6,7,8,9

Reserved

4

CWL = 5

2.5

3.3

1, 2, 3, 9

CL = 6

CL = 7

CWL = 6

CWL = 7,8,9

CWL = 5

Reserved

1, 2, 3, 4, 9

4

CWL = 6

1.875

< 2.5

1, 2, 3, 4, 9

CWL = 7,8,9

CWL = 5

Reserved

4

CWL = 6

1, 2, 3, 9

CL = 8

CL = 9

CWL = 7

Reserved

1, 2, 3, 4, 9

CWL = 8,9

CWL = 5, 6

CWL = 7

4

1.5

<1.875

1, 2, 3, 4, 9

CWL = 8

Reserved

1, 2, 3, 4, 9

CWL = 9

4

CWL = 5, 6

CWL = 7

4

1, 2, 3, 9

1, 2, 3, 4, 9

4

CL = 10

CL = 11

1.5

<1.875

<1.5

CWL = 8

Reserved

CWL = 5,6,7

CWL = 8

1.25

1, 2, 3, 4, 9

1, 2, 3, 4

4

CWL = 9

Reserved

CWL = 5,6,7,8

CWL = 9

CL = 12

CL = 13

1,2,3,4

4

CWL = 5,6,7,8

CWL = 9

1.07

<1.25

1, 2, 3

Supported CL Settings

Supported CWL Settings

6, 8, 10, 13, (7), (9), (11)

5, 6, 7, 8, 9

Rev. 1.3 / Nov. 2015

31

Speed Bin Table Notes

Absolute Specification (T_OPER; V_DDQ= V_DD= 1.5V +/- 0.075 V);

1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making

a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements

from CWL setting.

2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized

by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the

next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK]

= tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) = 3.0 ns should

only be used for CL = 5 calculation.

3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)

down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX

corresponding to CL SELECTED.

4. ‘Reserved’ settings are not allowed. User must program a different value.

5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a man-

datory feature. Refer to SK Hynix DIMM data sheet and/or the DIMM SPD information if and how this

setting is supported.

6. Any DDR3L-1066 speed bin also supports functional operation at lower frequencies as shown in the table