HY57V561620CTP-8 [HYNIX]
4 Banks x 4M x 16Bit Synchronous DRAM; 4银行x 4米X 16Bit的同步DRAM型号: | HY57V561620CTP-8 |
厂家: | HYNIX SEMICONDUCTOR |
描述: | 4 Banks x 4M x 16Bit Synchronous DRAM |
文件: | 总12页 (文件大小:214K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HY57V561620C(L)T(P)
4 Banks x 4M x 16Bit Synchronous DRAM
DESCRIPTION
The HY57V561620C(L)T(P) Series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications
which require large memory density and high bandwidth. HY57V561620C(L)T(P) Series is organized as 4banks of 4,194,304x16.
HY57V561620C(L)T(P) Series is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input
and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or
write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
•
•
Single 3.3±0.3V power supply
•
•
•
Auto refresh and self refresh
All device pins are compatible with LVTTL interface
8192 refresh cycles / 64ms
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch (Leaded Package or Lead Free Package)
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
All inputs and outputs referenced to positive edge of system
clock
•
•
Data mask function by UDQM, LDQM
Internal four banks operation
•
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
400mil 54pin TSOP II
HY57V561620C(L)T(P)-6
HY57V561620C(L)T(P)-7
HY57V561620C(L)T(P)-K
HY57V561620C(L)T(P)-H
HY57V561620C(L)T(P)-8
HY57V561620C(L)T(P)-P
HY57V561620C(L)T(P)-S
166MHz
143MHz
133MHz
133MHz
125MHz
100MHz
100MHz
(Normal)
/
Low Power
(Leaded)
/
Lead Free
4Banks x 4Mbits x16
LVTTL
Note :
1. HY57V561620CT Series
: Nomal power & Leaded 54Pin TSOP II
2. HY57V561620CLT Series : Low power & Leaded 54Pin TSOP II
3. HY57V561620CTP Series : Nomal power & Lead Free 54Pin TSOP II
4. HY57V561620CLTP Series : Low power & Lead Free 54Pin TSOP II
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.5 / June 2004
1
HY57V561620C(L)T(P)
PIN CONFIGURATION
V
DQ0
DD
1
2
3
4
5
6
7
8
9
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
VDDQ
DQ5 10
DQ6 11
VSSQ 12
DQ7 13
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
VDD 14
LDQM 15
/WE 16
/CAS 17
/RAS 18
/CS 19
BA0 20
BA1 21
A10/AP 22
A0 23
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A1 24
A2 25
A3 26
A4
VSS
VDD 27
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CLK
Clock
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CKE
CS
Clock Enable
Chip Select
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
BA0, BA1
A0 ~ A12
Bank Address
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
RAS, CAS, WE
UDQM, LDQM
DQ0 ~ DQ15
VDD/VSS
Data Input/Output Mask
Data Input/Output
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power Supply/Ground
Power supply for internal circuits and input buffers
Power supply for output buffers
VDDQ/VSSQ
NC
Data Output Power/Ground
No Connection
No connection
Rev. 0.5 / June 2004
2
HY57V561620C(L)T(P)
FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x 16 I/O Synchronous DRAM
CLK
Row Active
CKE
CS
DQ0
DQ1
RAS
CAS
WE
Column
Active
UDQM
LDQM
DQ14
DQ15
Bank Select
A0
A1
A12
BA0
BA1
CAS Latency
Pipe Line Control
Rev. 0.5 / June 2004
3
HY57V561620C(L)T(P)
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
°C
Storage Temperature
TSTG
°C
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
VIN, VOUT
VDD, VDDQ
IOS
V
V
mA
PD
1
W
Soldering Temperature ⋅ Time
TSOLDER
260 ⋅ 10
°C ⋅ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Symbol
VDD, VDDQ
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Input High Voltage
Input Low Voltage
3.0
2.0
3.3
3.0
0
3.6
VDDQ + 0.3
0.8
V
V
V
1
VIH
VIL
1,2
1,3
- 0.3
Note :
1.All voltages are referenced to VSS = 0V
2.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration
3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration
AC OPERATING CONDITION (TA=0 to 70°C, VDD=3.3 ± 0.3V, VSS=0V)
Parameter
AC Input High / Low Level Voltage
Symbol
Value
Unit
Note
VIH / VIL
Vtrip
2.4/0.4
1.4
1
V
V
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
tR / tF
Voutref
CL
ns
V
Output Timing Measurement Reference Level
Output Load Capacitance for Access Time Measurement
1.4
50
pF
1
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
Rev. 0.5 / June 2004
4
HY57V561620C(L)T(P)
CAPACITANCE (TA=25°C, f=1MHz)
-6/7/K/H
-8/P/S
Parameter
Pin
Symbol
Unit
Min
Max
Min
Max
Input capacitance
CLK
CI1
CI2
2.5
2.5
3.5
3.8
2.5
2.5
4.0
5.0
pF
pF
A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS,
WE, UDQM, LDQM
Data input / output capacitance
DQ0 ~ DQ15
CI/O
4.0
6.5
4.0
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250 Ω
Output
Output
50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
ILI
-1
-1
2.4
-
1
1
uA
uA
V
1
2
ILO
VOH
VOL
-
IOH = -4mA
IOL = +4mA
0.4
V
Note :
1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2.DOUT is disabled, VOUT=0 to 3.6V
Rev. 0.5 / June 2004
5
HY57V561620C(L)T(P)
DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Speed
Parameter
Symbol
Test Condition
Unit Note
-6
-7
-K
-H
-8
-P
-S
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
Operating Current
IDD1
130
110
110
110
100
100
100
mA
mA
1
IDD2P
CKE ≤ VIL(max), tCK = 15ns
CKE ≤ VIL(max), tCK = ∞
2
1
Precharge Standby Current
in Power Down Mode
IDD2PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD2N
20
10
Precharge Standby Current
in Non Power Down Mode
mA
mA
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
IDD2NS
IDD3P
CKE ≤ VIL(max), tCK = 15ns
CKE ≤ VIL(max), tCK = ∞
3
3
Active Standby Current
in Power Down Mode
IDD3PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD3N
30
Active Standby Current
in Non Power Down Mode
mA
mA
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
IDD3NS
25
Burst Mode Operating
Current
tCK ≥ tCK(min), IOL=0mA
All banks active
IDD4
IDD5
150
220
130
220
130
220
130
130
200
110
200
110
200
1
Auto Refresh Current
Self Refresh Current
tRRC ≥ tRRC(min), All banks active
CKE ≤ 0.2V
220
3
mA
mA
mA
2
3
4
IDD6
1.5
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V561620CT(P)-6/7/K/H/8/P/S
4.HY57V561620CLT(P)-6/7/K/H/8/P/S
Rev. 0.5 / June 2004
6
HY57V561620C(L)T(P)
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-6
-7
-K
-H
-8
-P
-S
Parameter
Symbol
Unit Note
Min
6
Max
Min
7
Max
Min
7.5
7.5
2.5
2.5
-
Max
Min
7.5
10
2.5
2.5
-
Max
Min
8
Max
Min
10
10
3
Max
Min
10
12
3
Max
CAS Latency = 3 tCK3
CAS Latency = 2 tCK2
ns
ns
System Clock
Cycle Time
1000
1000
1000
1000
1000
1000
1000
7.5
2.5
2.5
-
10
2.5
2.5
-
10
3
Clock High Pulse Width
Clock Low Pulse Width
tCHW
tCLW
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
-
-
-
-
3
3
3
CAS Latency = 3 tAC3
CAS Latency = 2 tAC2
tOH
5.4
5.4
5.4
5.4
-
6
6
-
-
6
6
-
-
6
6
-
Access Time
From Clock
2
-
6
-
6
-
5.4
-
6
-
-
-
Data-Out Hold Time
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
-
3
3
3
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
tDS
-
-
-
-
2
-
2
-
2
-
1
1
1
1
1
1
1
1
tDH
tAS
-
-
-
-
1
-
1
-
1
-
-
-
-
-
2
-
2
-
2
-
tAH
-
-
-
-
-
1
-
1
-
1
-
CKE Setup Time
tCKS
tCKH
tCS
-
-
-
2
-
2
-
2
-
CKE Hold Time
-
-
-
-
-
-
-
1
-
1
-
1
-
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
-
2
-
2
-
2
-
tCH
tOLZ
-
-
-
-
1
-
1
-
1
-
-
-
-
-
1
-
1
-
1
-
CAS Latency = 3 tOHZ3
CAS Latency = 2 tOHZ2
2.7
2.7
5.4
5.4
2.7
2.7
5.4
5.4
2.7
2.7
5.4
5.4
2.7
3
5.4
6
3
6
6
3
6
6
3
6
6
CLK to Data
Output in High-Z
Time
3
3
3
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 0.5 / June 2004
7
HY57V561620C(L)T(P)
AC CHARACTERISTICS II
-6
-7
-K
-H
-8
-P
-S
Parameter
Symbol
Unit Note
Min
60
60
18
42
18
12
1
Max
Min
60
60
18
42
18
14
1
Max
Min
60
60
15
45
15
15
1
Max
Min
65
65
20
45
20
15
1
Max
Min
68
68
20
48
20
16
1
Max
Min
70
70
20
50
20
20
1
Max
Min
70
70
20
50
20
20
1
Max
Operation
Auto Refresh
tRC
-
-
-
-
-
-
-
ns
ns
RAS Cycle Time
tRRC
tRCD
tRAS
tRP
-
-
-
-
-
-
-
RAS to CAS Delay
RAS Active Time
-
-
-
-
-
-
-
ns
100K
100K
100K
100K
100K
100K
100K
ns
RAS Precharge Time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
RAS to RAS Bank Active Delay
CAS to CAS Delay
tRRD
tCCD
tWTL
tWR
ns
-
-
-
-
-
-
-
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Write Command to Data-In Delay
Write Recovery Time
0
-
0
-
0
-
0
-
0
-
0
-
0
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
Data-In to Active Command
DQM to Data-Out Hi-Z
DQM to Data-In Mask
tDAL
tDQZ
tDQM
tMRD
5
-
5
-
5
-
5
-
5
-
5
-
5
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
MRS to New Command
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CAS Latency = 3 tPROZ3
CAS Latency = 2 tPROZ2
3
-
3
-
3
-
3
-
3
-
3
-
3
-
Precharge to Data
Output Hi-Z
2
-
2
-
2
-
2
-
2
-
2
-
2
-
Power Down Exit Time
Self Refresh Exit Time
Refresh Time
tPDE
tSRE
tREF
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
ms
1
-
64
-
64
-
64
-
64
-
64
-
64
-
64
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.5 / June 2004
8
HY57V561620C(L)T(P)
IBIS SPECIFICATION
IOH Characteristics (Pull-up)
66MHz and 100MHz Pull-up
100MHz
(Min)
100MHz
(Max)
66MHz
(Min)
Voltage
0
0.5
1
1.5
2
2.5
3
3.5
(V)
3.45
3.3
3.0
2.6
2.4
2.0
1.8
1.65
1.5
1.4
1.0
0
I(mA)
I(mA)
-2.4
I(mA)
0
-100
-200
-300
-400
-500
-600
-27.3
0
-74.1
-0.7
-7.5
-21.1
-34.1
-58.7
-67.3
-73
-129.2
-153.3
-197
-13.3
-27.5
-35.5
-41.1
-47.9
-52.4
-72.5
-93
-226.2
-248
Voltage (V)
-77.9
-80.8
-88.6
-93
-269.7
-284.3
-344.5
-502.4
I
OH Min (100MHz)
I
OH Min (66MHz)
I
OH Max (66 /100MHz)
IOL Characteristics (Pull-down)
66MHz and 100MHz Pull-down
100MHz
(Min)
100MHz
(Max)
66MHz
(Min)
Voltage
250
200
150
100
50
(V)
0
I(mA)
0
I(mA)
0
I(mA)
0
0.4
27.5
41.8
51.6
58.0
70.7
72.9
75.4
77.0
77.6
80.3
81.4
70.2
17.7
26.9
33.3
37.6
46.6
48.0
49.5
50.7
51.5
54.2
54.9
0.65
0.85
1.0
107.5
133.8
151.2
187.7
194.4
202.5
208.6
212.0
219.6
222.6
1.4
1.5
0
1.65
1.8
0
0.5
1
1.5
2
2.5
3
3.5
Voltage (V)
1.95
3.0
I
OL Min (100MHz)
OL Min (66MHz)
I
IOL Max (100MHz)
3.45
Rev. 0.5 / June 2004
9
HY57V561620C(L)T(P)
DEVICE OPERATING OPTION TABLE
HY57V561620C(L)T(P)-6
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
166MHz(6ns)
143MHz(7ns)
133MHz(7.5ns)
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
3CLKs
7CLKs
6CLKs
6CLKs
10CLKs
9CLKs
9CLKs
3CLKs
3CLKs
3CLKs
5.4ns
5.4ns
5.4ns
2.7ns
2.7ns
2.7ns
HY57V561620C(L)T(P)-7
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
143MHz(7ns)
133MHz(7.5ns)
125MHz(8ns)
3CLKs
2CLKs
3CLKs
3CLKs
3CLKs
3CLKs
6CLKs
6CLKs
6CLKs
9CLKs
9CLKs
9CLKs
3CLKs
3CLKs
3CLKs
5.4ns
5.4ns
6ns
2.7ns
2.7ns
3ns
HY57V561620C(L)T(P)-K
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
125MHz(8ns)
100MHz(10ns)
2CLKs
3CLKs
2CLKs
2CLKs
3CLKs
2CLKs
6CLKs
6CLKs
5CLKs
8CLKs
9CLKs
7CLKs
2CLKs
3CLKs
2CLKs
5.4ns
6ns
6ns
2.7ns
3ns
3ns
HY57V561620C(L)T(P)-H
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
125MHz(8ns)
100MHz(10ns)
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
2CLKs
6CLKs
6CLKs
5CLKs
9CLKs
9CLKs
7CLKs
3CLKs
3CLKs
2CLKs
5.4ns
6ns
6ns
2.7ns
3ns
3ns
HY57V561620C(L)T-8
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
125MHz(8ns)
100MHz(10ns)
83MHz(12ns)
3CLKs
2CLKs
2CLKs
3CLKs
2CLKs
2CLKs
6CLKs
5CLKs
4CLKs
9CLKs
7CLKs
6CLKs
3CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
HY57V561620C(L)T(P)-P
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
83MHz(12ns)
66MHz(15ns)
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
HY57V561620C(L)T(P)-S
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
83MHz(12ns)
66MHz(15ns)
3CLKs
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
Rev. 0.5 / June 2004
10
HY57V561620C(L)T(P)
COMMAND TRUTH TABLE
A10/
AP
ADDR
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
Note
Mode Register Set
H
X
L
H
L
L
X
H
L
L
X
H
H
L
X
H
H
X
OP code
No Operation
H
H
H
X
X
X
X
X
X
X
Bank Active
L
RA
V
V
Read
L
L
L
H
H
L
L
L
H
L
CA
CA
X
Read with Autoprecharge
Write
H
L
H
H
X
X
X
V
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Burst Stop
H
H
X
V
X
X
L
L
H
H
L
L
L
H
H
H
H
X
L
X
V
X
X
DQM
X
X
Auto Refresh
H
X
L
L
L
L
L
H
H
A9 Pin High
(Other Pins OP code)
Burst-Read-Single-WRITE
H
H
L
X
X
Entry
L
H
L
L
X
H
X
H
X
H
X
V
L
X
H
X
H
X
H
X
V
H
X
H
X
H
X
H
X
V
Self Refresh1
Exit
X
L
H
L
H
L
X
X
X
H
L
Entry
Precharge
power down
X
X
H
L
Exit
H
H
L
Entry
Clock
Suspend
H
L
L
X
X
Exit
H
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Rev. 0.5 / June 2004
11
HY57V561620C(L)T(P)
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
UNIT : mm(inch)
11.938(0.4700)
11.735(0.4620)
22.327(0.8790)
22.149(0.8720)
10.262(0.4040)
10.058(0.3960)
0.150(0.0059)
0.050(0.0020)
1.194(0.0470)
0.991(0.0390)
5deg
0deg
0.210(0.0083)
0.120(0.0047)
0.597(0.0235)
0.406(0.0160)
0.400(0.016)
0.80(0.0315)BSC
0.300(0.012)
Rev. 0.5 / June 2004
12
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