HY5PS121621CFLP-S6 [HYNIX]
DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, ROHS COMPLIANT, FBGA-84;
| 型号： | HY5PS121621CFLP-S6 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, ROHS COMPLIANT, FBGA-84 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总38页 (文件大小：613K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY5PS12421C(L)FP
HY5PS12821C(L)FP
HY5PS121621C(L)FP
512Mb DDR2 SDRAM
HY5PS12421C(L)FP
HY5PS12821C(L)FP
HY5PS121621C(L)FP
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.8 / Oct. 2007
1
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
Revision History
Rev.
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
History
Preliminary
Draft Date
May 2006
July 2006
July 2006
Aug. 2006
Feb. 2007
July 2007
Sep. 2007
Oct. 2007
IDD Spec. Changed
Removed improper note in ODT spec.
Updated IDD3P-S value/OCD Default Characteristics
Updated IDD spec for x8 org. on page 16
Removed Y4 Speed bin
Updated Timing Patterns (DDR2-800 5/5/5 and 6/6/6)
Corrected Typo
Rev. 0.8 / Oct. 2007
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1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Key Features
1.1.2 Ordering Information
1.1.3 Ordering Frequency
1.2 Pin configuration
1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings
2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions
5.1.1 Recommended DC Operating Conditions(SSTL_1.8)
5.1.2 ODT DC Electrical Characteristics
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
3.2.4 Differential Input AC Logic Level
3.2.5 Differential AC output parameters
3.3 Output Buffer Levels
3.3.1 Output AC Test Conditions
3.3.2 Output DC Current Drive
3.3.3 OCD default characteristics
3.4 IDD Specifications & Measurement Conditions
3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
Rev. 0.8 / Oct. 2007
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1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
• VDD ,VDDQ =1.8 +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 3, 4, 5 and 6 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4 / 8 with both nibble sequential and interleave mode
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 60ball FBGA(x4/x8) & 84ball FBGA(x16)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe supported (x8 only)
• Self-Refresh High Temperature Entry
• Partial Array Self Refresh support
Operating Frequency
Ordering Information
Speed Bin tCK(ns) CL tRCD tRP Unit
Part No.
Organization
Package
E3
C4
Y5
S5
S6
Clk
Clk
Clk
Clk
Clk
5
3.75
3
3
4
5
5
6
3
4
5
5
6
3
4
5
5
6
HY5PS12421C(L)FP-X*
128Mx4
64Mx8
HY5PS12821C(L)FP-X*
Lead free**
HY5PS121621C(L)FP-X*
32Mx16
2.5
2.5
Note:
1. -X* is the speed bin, refer to the Operation Frequency table for
complete Part No.
2. Hynix Lead-free products are compliant to RoHS.
Rev. 0.8 / Oct. 2007
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1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
1.2 Pin Configuration & Address Table
128Mx4 DDR2 Pin Configuration(Top view: see balls through package)
7
8
3
9
1
2
VSSQ
DQS
VSS
VDDQ
VDD
NC
NC
A
B
C
D
DQS
VDDQ
DQ2
VSSQ
DQ0
VSSQ
CK
DM
VDDQ
DQ3
VSS
NC
VDDQ
NC
VSSQ
DQ1
VDDQ
NC
VSSQ
VREF
CKE
VSSDL
RAS
VDD
ODT
VDDL
E
F
CK
WE
CAS
A2
CS
A0
BA1
A1
G
H
J
NC
VSS
VDD
BA0
A10
A3
VDD
VSS
A6
A4
A5
A11
NC
A8
A9
K
L
A7
A13
NC
A12
ROW AND COLUMN ADDRESS TABLE
ITEMS
# of Bank
128Mx4
4
Bank Address
Auto Precharge Flag
Row Address
BA0, BA1
A10/AP
A0 - A13
A0-A9, A11
1 KB
Column Address
Page size
Rev. 0.8 / Oct. 2007
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1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
64Mx8 DDR2 PIN CONFIGURATION(Top view: see balls through package)
7
8
3
9
1
2
VSSQ
DQS
VSS
VDDQ
VDD
DQ6
VDDQ
DQ4
VDDL
NU, RDQS
A
B
C
D
DQS
VDDQ
DQ2
VSSQ
DQ0
VSSQ
CK
DM, RDQS
VDDQ
DQ3
DQ7
VDDQ
DQ5
VSSQ
DQ1
VSSQ
VREF
CKE
VSSDL
RAS
VSS
VDD
E
F
CK
WE
ODT
CAS
A2
CS
A0
BA1
A1
G
H
J
NC
VSS
VDD
BA0
A10
A3
VDD
VSS
A6
A4
A5
A11
NC
A8
A9
K
L
A7
A13
NC
A12
ROW AND COLUMN ADDRESS TABLE
ITEMS
# of Bank
64Mx8
4
Bank Address
Auto Precharge Flag
Row Address
BA0, BA1
A10/AP
A0 - A13
A0-A9
Column Address
Page size
1 KB
Rev. 0.8 / Oct. 2007
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1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
32Mx16 DDR2 PIN CONFIGURATION(Top view: see balls through package)
7
8
3
9
1
2
VSSQ
UDQS
VSS
VDDQ
VDD
NC
A
B
C
D
E
F
UDQS
VDDQ
DQ10
VSSQ
LDQS
VDDQ
DQ2
VSSQ
DQ8
UDM
VDDQ
DQ11
VSS
DQ15
VDDQ
DQ13
VDDQ
DQ7
DQ14
VDDQ
DQ12
VDD
VSSQ
DQ9
VSSQ
NC
VSSQ
LDQS
VSSQ
DQ0
LDM
DQ6
VSSQ
DQ1
VSSQ
VDDQ
DQ3
VDDQ
DQ5
VDDQ
DQ4
G
H
VSSQ
VSSDL
RAS
CK
CK
VSS
WE
VDD
ODT
VDDL
VREF
CKE
J
K
CAS
A2
CS
A0
A4
A8
NC
BA1
A1
L
M
N
P
NC
VSS
VDD
BA0
A10
A3
VDD
VSS
A6
A5
A11
NC
A9
A7
NC
R
A12
ROW AND COLUMN ADDRESS TABLE
ITEMS
# of Bank
32Mx16
4
Bank Address
Auto Precharge Flag
Row Address
BA0, BA1
A10/AP
A0 - A12
A0-A9
Column Address
Page size
2 KB
Rev. 0.8 / Oct. 2007
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1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
1.3 PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
Clock: CK and CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK. Output
(read) data is referenced to the crossings of CK and CK (both directions of crossing).
CK, CK
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for
SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. After VREF has
become stable during the power on and initialization sequence, it must be maintained
for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF
must be maintained to this input. CKE must be maintained high throughout READ and
WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled during POWER
DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH.
CKE
Input
Input
Chip Select : All commands are masked when CS is registered HIGH. CS provides for
external bank selection on systems with multiple banks. CS is considered part of the
command code.
CS
On Die Termination Control : ODT(registered HIGH) enables on die termination resis-
tance internal to the DDR2 SDRAM. When enabled, ODT is only applied to DQ, DQS,
DQS, RDQS, RDQS, and DM signal for x4,x8 configurations. For x16 configuration ODT
is applied to each DQ, UDQS/UDQS.LDQS/LDQS, UDM and LDM signal. The ODT pin
will be ignored if the Extended Mode Register(EMRS(1)) is programmed to disable ODT.
ODT
Input
Input
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being
entered.
RAS, CAS, WE
Input Data Mask : DM is an input mask signal for write data. Input Data is masked
when DM is sampled High coincident with that input data during a WRITE access. DM
is sampled on both edges of DQS, Although DM pins are input only, the DM loading
matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/ RDQS is
enabled by EMRS command.
DM
(LDM, UDM)
Bank Address Inputs: BA0 - BA2 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied(For 256Mb and 512Mb, BA2 is not applied). Bank
address also determines if the mode register or extended mode register is to be
accessed during a MRS or EMRS cycle.
BA0 - BA2
A0 -A15
Input
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE commands to select one location
out of the memory array in the respective bank. A10 is sampled during a precharge
command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0-
BA2. The address inputs also provide the op code during MODE REGISTER SET com-
mands.
Input/
Output
DQ
Data input / output : Bi-directional data bus
Rev. 0.8 / Oct. 2007
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1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
-Continue-
PIN
TYPE
DESCRIPTION
Data Strobe : Output with read data, input with write data. Edge aligned with read data,
centered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS
corresponds to the data on DQ8~DQ15. For the x8, an RDQS option using DM pin can
be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS,
UDQS, and RDQS may be used in single ended mode or paired with optional comple-
mentary signals DQS, LDQS,UDQS and RDQS to provide differential pair signaling to the
system during both reads and wirtes. An EMRS(1) control bit enables or disables all
complementary data strobe signals.
DQS, (DQS)
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0
(UDQS),(UDQS) Input/
(LDQS),(LDQS) Output
(RDQS),(RDQS)
of EMRS(1)
x4 DQS/DQS
x8 DQS/DQS
x8 DQS/DQS, RDQS/RDQS,
if EMRS(1)[A11] = 0
if EMRS(1)[A11] = 1
x16 LDQS/LDQS and UDQS/UDQS
"single-ended DQS signals" refers to any of the following with A10 = 1
of EMRS(1)
x4 DQS
x8 DQS
if EMRS(1)[A11] = 0
x8 DQS, RDQS, if EMRS(1)[A11] = 1
x16 LDQS and UDQS
NC
No Connect : No internal electrical connection is present.
VDDQ
VSSQ
VDDL
VSSDL
VDD
Supply DQ Power Supply: 1.8V +/- 0.1V
Supply DQ Ground
Supply DLL Power Supply : 1.8V +/- 0.1V
Supply DLL Ground
Supply Power Supply : 1.8V +/- 0.1V
Supply Ground
VSS
VREF
Supply Reference voltage for inputs for SSTL interface.
Rev. 0.8 / Oct. 2007
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1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
2. Maximum DC Ratings
2.1 Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
Notes
VDD
- 1.0 V ~ 2.3 V
V
1
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on VDDL pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
VDDQ
VDDL
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
V
V
1
1
V
IN, VOUT
V
1
TSTG
1, 2
℃
Input leakage current; any input 0V VIN VDD;
all other balls not under test = 0V)
II
-2 uA ~ 2 uA
-5 uA ~ 5 uA
uA
uA
Output leakage current; 0V VOUT VDDQ; DQ
and ODT disabled
IOZ
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions. Please refer to JESD51-2 standard.
2.2 Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
tOPER
0 to 95
°C
1,2
Operating Temperature
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the mea-
surement conditions, please refer to JESD51-2 standard.
2. At tOPER 85~95℃, Double refresh rate(tREFI: 3.9us) is required, and to enter the self refresh mode at this
temperature range it must be required an EMRS command to change itself refresh rate.
Rev. 0.8 / Oct. 2007
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1HY5PS121621C(L)FP
3. AC & DC Operating Conditons
3.1 DC Operating Conditions
3.1.1 Recommended DC Operating Conditions (SSTL_1.8)
Rating
Symbol
Parameter
Supply Voltage
Units
Notes
Min.
Typ.
Max.
VDD
VDDL
VDDQ
VREF
VTT
1.7
1.8
1.9
V
V
1
1.7
1.8
1.8
1.9
1,2
1,2
3,4
5
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.9
V
0.49*VDDQ
VREF-0.04
0.50*VDDQ
VREF
0.51*VDDQ
VREF+0.04
mV
V
1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option.
2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD.
3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the
value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track vari-
ations in VDDQ
4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).
5. VTT of transmitting device must track VREF of receiving device.
3.1.2 ODT DC electrical characteristics
PARAMETER/CONDITION
SYMBOL MIN NOM MAX UNITS NOTES
Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm
Rtt1(eff)
60
120
40
75
150
50
90
180
60
ohm
ohm
ohm
%
1
1
1
1
Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm Rtt2(eff)
Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm
Deviation of VM with respect to VDDQ/2
Rtt3(eff)
delta VM
-6
+6
Note:
1. Test condition for Rtt measurements
Measurement Definition for Rtt(eff): Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH
(ac)) and I(VIL(ac)) respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18
VIH (ac) - VIL (ac)
Rtt(eff) =
I(VIH (ac)) - I(VIL (ac))
Measurement Definition for VM : Measurement Voltage at test pin(mid point) with no load.
2 x Vm
delta VM =
- 1 x 100%
VDDQ
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1HY5PS121621C(L)FP
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
Symbol
Parameter
Min.
Max.
Units
Notes
Notes
VIH(dc)
VREF + 0.125
VDDQ + 0.3
V
dc input logic high
dc input logic low
VIL(dc)
- 0.3
VREF - 0.125
V
3.2.2 Input AC Logic Level
DDR2 400,533
DDR2 667,800
Symbol
Parameter
Units
Min.
Max.
Min.
Max.
VREF +
0.250
VREF +
0.200
VIH (ac)
VIL (ac)
-
-
V
V
ac input logic high
ac input logic low
-
VREF - 0.250
-
VREF - 0.200
3.2.3 AC Input Test Conditions
Symbol
Condition
Value
Units
Notes
VREF
VSWING(MAX)
SLEW
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
0.5 * VDDQ
1.0
V
V
1
1
1.0
V/ns
2, 3
Note:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising
edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VSWING(MAX)
V
IL(dc) max
VIL(ac) max
VSS
delta TF
delta TR
VREF - VIL(ac) max
delta TF
VIH(ac) min - VREF
Falling Slew =
Rising Slew =
delta TR
< Figure : AC Input Test Signal Waveform>
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1HY5PS121621C(L)FP
3.2.4 Differential Input AC logic Level
Symbol
Parameter
Min.
Max.
Units
Notes
VID (ac)
0.5
VDDQ + 0.6
V
1
ac differential input voltage
ac differential cross point voltage
VIX (ac)
0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175
V
2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS,
LDQS, LDQS, UDQS and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input
(such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS
or UDQS) level. The minimum value is equal to VIH(DC) - V IL(DC).
V
DDQ
V
TR
Crossing point
V
ID
V
V
IX or OX
V
CP
V
SSQ
< Differential signal levels >
Note:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input
signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS
or UDQS). The minimum value is equal to V IH(AC) - V IL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is
expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must
cross.
3.2.5 Differential AC output parameters
Symbol
OX (ac)
Note:
Parameter
Min.
Max.
Units Notes
V
0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125
V
1
ac differential cross point voltage
1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is
expected to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals
must cross.
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3.3 Output Buffer Characteristics
3.3.1 Output AC Test Conditions
Symbol
Parameter
SSTL_18 Class II
Units
Notes
VOTR
Output Timing Measurement Reference Level
0.5 * VDDQ
V
1
1. The VDDQ of the device under test is referenced.
3.3.2 Output DC Current Drive
Symbol
IOH(dc)
IOL(dc)
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
SSTl_18
- 13.4
Units
mA
Notes
1, 3, 4
2, 3, 4
13.4
mA
1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ
and VDDQ - 280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280
mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test
device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are
delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating
point (see Section 3.3) along a 21 ohm load line to define a convenient driver current for measurement.
Rev. 0.8 / Oct. 2007
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3.3.3 OCD default characteristics
Description
Parameter
Min
Nom
Max
Unit
Notes
See full strength default
driver characteristics
Output impedance
ohms
1
Output impedance step size for OCD calibration
Pull-up and pull-down mismatch
Output slew rate
0
0
1.5
4
ohms
ohms
V/ns
6
1,2,3
Sout
1.5
-
5
1,4,5,6,7,8
Note
1. Absolute Specifications ( Toper; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V). DRAM I/O specifications for
timing,voltage, and
slew rate are no longer applicable if OCD is changed from default settings. Please refer to the Device Operation &
Timing Diagram
of DDR2 for the Full Strength Default Driver Characteristics.
2. Impedance measurement condition for output source dc current: VDDQ=1.7V; VOUT=1420mV; (VOUT-VDDQ)/Ioh
must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement
condition for output sink
dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V
and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from vil(ac) to vih(ac).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as
measured from AC to AC. This is guaranteed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process corners/
variations and represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved if the
OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions.
Output Slew rate load:
VTT
25 ohms
Reference
point
Output
(Vout)
7. DRAM output slew rate specification applies to 400 , 533 and 667 MT/s speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in
tDQSQ and tQHS specification.
Rev. 0.8 / Oct. 2007
15
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
3.4 IDD Specifications & Test Conditions
IDD Specifications(max)
DDR2 800
DDR2 667
DDR2 533
DDR2 400
Units
Symbol
x4/x8
x16
x4/x8
x16
x4/x8
x16
x4/x8
x16
IDD0
IDD1
100
100
8
120
90
90
110
80
90
100
110
8
80
100
mA
130
8
120
8
80
8
110
8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
8
8
40
40
40
40
30
30
30
30
30
12
40
90
80
150
30
50
50
40
40
40
40
30
F
S
35
35
30
30
30
30
30
IDD3P
12
12
12
12
12
12
12
IDD3N
IDD4W
IDD4R
IDD5B
60
60
50
50
50
50
40
160
140
160
240
200
165
140
120
160
200
170
160
120
100
150
170
150
150
130
110
150
Normal
Power
8
8
8
8
8
8
8
8
mA
IDD6
Low Power*
4
4
4
4
4
4
4
4
mA
mA
IDD7
230
340
220
320
210
320
210
320
Note:
1. Low power parts have an extra suffix ‘L’ in part number ; ex) HY5PS1216CLFP-C4
Rev. 0.8 / Oct. 2007
16
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
IDD Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)
Symbol
IDD0
Conditions
Units
t
t
t
t
t
Operating one bank active-precharge current; CK = CK(IDD), RC = RC(IDD), RAS =
t
mA
RAS min(IDD) ; CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are
SWITCHING;Data bus inputs are SWITCHING
Operating one bank active-read-precharge current ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL
t
t
t
t
t
t
t
t
= 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD = RCD(IDD) ; CKE is HIGH,
CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same
as IDD4W
IDD1
mA
t
t
Precharge power-down current ; All banks idle ; CK = CK(IDD) ; CKE is LOW ; Other control
IDD2P
IDD2Q
IDD2N
mA
mA
mA
and address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge quiet standby current ; All banks idle; CK = CK(IDD);CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge standby current; All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH; Other
control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
mA
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
t
t
Active power-down current; All banks open; CK = CK(IDD);
CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
IDD3P
t
t
t
t
t
Active standby current; All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP
IDD3N
IDD4W
t
mA
mA
= RP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD),
AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
t
t
t
t
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4,
t
t
t
t
t
t
CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS
is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as
IDD4W
IDD4R
mA
mA
t
t
t
Burst refresh current; CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCH-
ING; Data bus inputs are SWITCHING
IDD5B
IDD6
Self refresh current; CK and CK at 0V; CKE £ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
mA
Rev. 0.8 / Oct. 2007
17
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL
t
t
t
t
t
t
t
t
= CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD),
IDD7
Note:
t
t
mA
RCD = 1* CK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are
STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for
detailed timing conditions
1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V
(exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed grade)
2. IDD specifications are tested after the device is properly initialized
3. Input slew rate is specified by AC Parametric Test Condition
4. IDD parameters are specified with ODT disabled.
5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met
with all combinations of EMRS bits 10 and 11.
6. Definitions for IDD
LOW is defined as Vin £ VILAC(max)
HIGH is defined as Vin Š VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks)
for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals not including masks or strobes.
Rev. 0.8 / Oct. 2007
18
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
For purposes of IDD testing, the following parameters are to be utilized
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Speed Bin
Units
(CL-tRCD-tRP)
5-5-5
6-6-6
6
5-5-5
5
4-4-4
4
3-3-3
3
CL(IDD)
5
tCK
t
12.5
15
15
15
15
RCD(IDD)
ns
ns
t
57.25
7.5
60
60
60
55
RC(IDD)
t
ns
ns
RRD(IDD)-x4/x8
7.5
7.5
7.5
7.5
t
RRD(IDD)-x16
10
10
10
3
10
10
5
t
2.5
2.5
3.75
CK(IDD)
ns
ns
t
45
70000
12.5
75
45
70000
15
45
70000
15
45
70000
15
40
70000
15
RASmin(IDD)
t
ns
ns
ns
ns
ns
RASmax(IDD)
t
RP(IDD)
t
t
75
75
75
75
RFC(IDD)-256Mb
RFC(IDD)-512Mb
105
105
105
105
105
t
127.5
127.5
127.5
127.5
127.5
RFC(IDD)-1Gb
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the
specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
t
t
All banks are being interleaved at minimum RC(IDD) without violating RRD(IDD) using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)
-DDR2-533 3/3/3: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)
-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D (16 clocks)
-DDR2-667 4/4/4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)
-DDR2-667 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)
-DDR2-800 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D (23 clocks)
-DDR2-800 6/6/6: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D (24 clocks)
Rev. 0.8 / Oct. 2007
19
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
3.5. Input/Output Capacitance
DDR2- 400
DDR2- 533
DDR2 667
DDR2 800
Parameter
Symbol
Units
Min Max Min Max Min Max
Input capacitance, CK and CK
CCK
CDCK
CI
1.0
x
2.0
0.25
2.0
1.0
x
2.0
0.25
2.0
1.0
x
2.0
0.25
1.75
0.25
3.5
pF
pF
pF
pF
pF
pF
Input capacitance delta, CK and CK
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance, DQ, DM, DQS, DQS
Input/output capacitance delta, DQ, DM, DQS, DQS
1.0
x
1.0
x
1.0
x
CDI
0.25
4.0
0.25
3.5
CIO
2.5
x
2.5
x
2.5
x
CDIO
0.5
0.5
0.5
4. Electrical Characteristics & AC Timing Specification
( 0 ℃ ≤ TCASE ≤ 95℃; VDDQ = 1.8 V +/- 0.1V; VDD = 1.8V +/- 0.1V)
Refresh Parameters by Device Density
Parameter
Symbol
256Mb 512Mb 1Gb
2Gb
4Gb Units
Refresh to Active
/Refresh command time
tRFC
75
105
127.5
195
327.5
ns
0 ℃≤ TCASE ≤ 85℃
85℃ < TCASE ≤ 95℃
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
us
us
Average periodic refresh interval
tREFI
DDR2 SDRAM speed bins and tRCD, tRP and tRC for corresponding bin
Speed
DDR2-800D
DDR2-800E
DDR2-667D
DDR2-533C
DDR2-400B Units
Bin(CL-tRCD-tRP)
5-5-5
min
5
6-6-6
min
6
5-5-5
min
5
4-4-4
min
4
3-3-3
min
Parameter
CAS Latency
tRCD
5
tCK
ns
12.5
12.5
45
15
15
15
15
15
40
55
tRP
15
15
15
ns
tRAS
45
45
45
ns
tRC
57.25
60
60
60
ns
Rev. 0.8 / Oct. 2007
20
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
Timing Parameters by Speed Grade
(Refer to notes for information related to this table at the following pages of this table)
DDR2-400
DDR2-533
Symbol
Unit Note
Parameter
min
max
+600
+500
0.55
min
max
+500
+450
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
-600
-500
-500
-450
ps
ps
tDQSCK
tCH
0.45
0.45
tCK
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
min
(tCL,tCH)
5000
min
(tCL,tCH)
3750
CK half period
tHP
-
8000
-
-
8000
-
ps
ps
ps
11,12
Clock cycle time, CL=x
DQ and DM input setup time
(differential strobe)
tCK
15
6,7,8,
20
tDS
(base)
tDH
150
275
25
100
225
-25
-25
0.6
DQ and DM input hold time
(differential strobe)
6,7,8,
21
-
-
-
-
-
-
-
-
-
-
ps
ps
(base)
DQ and DM input setup time
(single ended strobe)
6,7,8,
20
tDS
DQ and DM input hold time
(single ended strobe)
6,7,8,
21
tDH
25
ps
Control & Address input pulse width for
each input
tIPW
tDIPW
0.6
0.35
tCK
tCK
DQ and DM input pulse width for each
input
0.35
Data-out high-impedance time from CK/CK tHZ
-
tAC max
tAC max
-
tAC max
tAC max
ps
ps
ps
18
18
18
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ
signals
tLZ(DQS)
tAC min
tAC min
tLZ(DQ)
2*tAC min tAC max 2*tAC min tAC max
tDQSQ
-
350
-
300
ps
13
12
DQ hold skew factor
tQHS
tQH
-
450
-
-
400
-
ps
ps
DQ/DQS output hold time from DQS
First DQS latching transition to associated
clock edge
tHP - tQHS
tHP - tQHS
tDQSS
-0.25
+ 0.25
-0.25
+ 0.25
tCK
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
-
-
0.35
0.35;;
0.2
-
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
-
-
tDSH
-
0.2
-
tMRD
tWPST
tWPRE
-
2
-
0.4
0.35
0.6
-
0.4
0.6
-
10
Write preamble
0.35
5,7,9,
23
Address and control input setup time
Address and control input hold time
tIS(base)
tIH(base)
350
475
-
-
250
375
-
-
ps
ps
5,7,9,
23
Rev. 0.8 / Oct. 2007
21
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
-Continue-
(Refer to notes for information related to this table at the following pages of this table)
DDR2-400
DDR2-533
Symbol
Unit Note
Parameter
min
max
1.1
min
max
1.1
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.4
0.9
0.4
tCK
tCK
0.6
0.6
Active to active command period for 1KB
page size products
tRRD
tRRD
tFAW
tFAW
7.5
10
-
-
-
-
7.5
10
-
-
-
-
ns
ns
ns
ns
4
4
Active to active command period for 2KB
page size products
Four Active Window for 1KB page size
products
37.5
50
37.5
50
Four Active Window for 2KB page size
products
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
2
tCK
ns
15
-
-
-
15
-
-
-
Auto precharge write recovery + precharge
time
tDAL
WR+tRP
WR+tRP
tCK
14
Internal write to read command delay
tWTR
10
7.5
7.5
7.5
ns
ns
24
3
Internal read to precharge command delay tRTP
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-
read command
tXSNR
tRFC + 10
200
tRFC + 10
200
ns
tXSRD
-
-
-
-
tCK
tXP
2
2
2
2
tCK
tCK
tCK
Exit active power down to read command tXARD
1
Exit active power down to read command
tXARDS
6 - AL
6 - AL
1, 2
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
tCKE
3
2
3
2
tCK
tCK
ns
27
tAOND
tAON
ODT turn-on delay
2
2
tAC(max)
+1
tAC(max)
+1
ODT turn-on
tAC(min)
tAC(min)
16
2tCK+
tAC(max)
+1
2tCK+
tAC(max)
+1
tAC(min)+
2
tAC(min)+
2
tAONPD
ODT turn-on(Power-Down mode)
ns
tAOFD
tAOF
ODT turn-off delay
ODT turn-off
2.5
2.5
2.5
2.5
tCK
ns
tAC(max)
+ 0.6
tAC(max)
+ 0.6
tAC(min)
tAC(min)
17
15
2.5tCK+
tAC(max)
+1
2.5tCK+
tAC(max)
+1
tAC(min)+
2
tAC(min)+
2
tAOFPD
ODT turn-off (Power-Down mode)
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tANPD
tAXPD
tOIT
3
8
3
8
tCK
tCK
ns
0
tIS+tCK+t
IH
12
0
tIS+tCK+t
IH
12
tDelay
ns
Rev. 0.8 / Oct. 2007
22
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
DDR2-667
DDR2-800
Unit Note
Symbol
tAC
Parameter
min
max
+450
+400
0.55
min
max
+400
+350
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
-450
-400
-400
-350
ps
ps
tDQSCK
tCH
0.45
0.45
tCK
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
min(tCL,
tCH)
min(tCL,
tCH)
CK half period
tHP
-
8000
-
-
ps
ps
ps
11,12
Clock cycle time, CL=x
DQ and DM input setup time
tCK
3000
2500
15
6,7,8,2
0
tDS(base)
100
175
0.6
50
-
-
-
-
tDH
(base)
6,7,8,2
1
DQ and DM input hold time
-
-
-
125
0.6
ps
tCK
tCK
ps
Control & Address input pulse width for
each input
tIPW
tDIPW
tHZ
DQ and DM input pulse width for each
input
0.35
0.35
Data-out high-impedance time from CK/
CK
-
tAC max
tAC max
-
tAC max
tAC max
18
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated
DQ signals
tLZ(DQS)
tLZ(DQ)
tAC min
tAC min
ps
ps
18
18
2*tAC min tAC max
2*tAC min tAC max
tDQSQ
-
240
-
200
ps
13
12
DQ hold skew factor
tQHS
tQH
-
340
-
-
300
-
ps
ps
DQ/DQS output hold time from DQS
First DQS latching transition to
associated clock edge
tHP - tQHS
tHP - tQHS
tDQSS
- 0.25
+ 0.25
- 0.25
+ 0.25
tCK
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
-
-
0.35
0.35
0.2
0.2
2
-
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
-
-
tDSH
-
-
Mode register set command cycle time tMRD
-
-
Write postamble
Write preamble
tWPST
tWPRE
0.4
0.35
0.6
-
0.4
0.35
0.6
-
10
5,7,9,2
Address and control input setup time
Address and control input hold time
tIS(base)
tIH(base)
200
275
-
-
175
250
-
-
ps
ps
2
5,7,9,2
3
Read preamble
tRPRE
tRPST
tRAS
0.9
0.4
45
1.1
0.6
0.9
0.4
45
1.1
0.6
tCK
tCK
ns
19
Read postamble
19
Activate to precharge command
Active to active command period for 1KB
page size products
70000
70000
3
tRRD
tRRD
7.5
10
-
-
7.5
10
-
-
ns
ns
4
4
Active to active command period for 2KB
page size products
Rev. 0.8 / Oct. 2007
23
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
-Continue-
DDR2-667
DDR2-800
Symbol
Unit Note
Parameter
min
max
min
max
Four Active Window for 1KB page size
products
tFAW
37.5
-
ns
37.5
50
-
Four Active Window for 2KB page size
products
tFAW
50
-
-
ns
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
2
tCK
ns
15
-
-
-
15
-
-
-
Auto precharge write recovery +
precharge time
tDAL
tWTR
tRTP
WR+tRP
7.5
WR+tRP
7.5
tCK
ns
14
3
Internal write to read command delay
Internal read to precharge command
delay
7.5
7.5
ns
tRFC +
10
Exit self refresh to a non-read command tXSNR
tRFC + 10
ns
Exit self refresh to a read command
Exit precharge power down to any non-
read command
tXSRD
tXP
200
2
-
-
200
-
-
tCK
tCK
tCK
tCK
2
2
Exit active power down to read command tXARD
2
1
Exit active power down to read command
tXARDS
7 - AL
8 - AL
1, 2
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
tCKE
3
2
3
2
tCK
tCK
ns
tAOND
tAON
ODT turn-on delay
2
2
tAC(max)
+0.7
tAC(max)
+0.7
ODT turn-on
tAC(min)
tAC(min)
6,16
17
2tCK+
tAC(max)+1
tAC(min)
+2
2tCK+
tAC(max)+1
tAONPD
tAOFD
tAOF
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAC(min)+2
2.5
ns
tCK
ns
2.5
2.5
2.5
tAC(max)+
0.6
tAC(max)
+0.6
ODT turn-off
tAC(min)
tAC(min)
tAC(min)
2.5tCK+
tAC(max)+1
tAC(min)
2.5tCK+
tAC(max)+1
tAOFPD
ODT turn-off (Power-Down mode)
ns
+2
+2
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after
CKE asynchronously drops LOW
tANPD
tAXPD
tOIT
3
8
3
8
0
tCK
tCK
ns
0
tIS+tCK+tI
H
12
12
tIS+tCK
+tIH
tDelay
ns
15
Rev. 0.8 / Oct. 2007
24
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended
signals.
For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS
- DQS = +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VIL(dc) to VIH(ac) for
rising edges and from
VIH(dc) and VIL(ac) for falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK =
+500 mV(250mV to -500 mV for falling egdes).
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between
DQS and DQS for differential strobe.
2. DDR2 SDRAM AC timing reference load
The following figure represents the timing reference load used in defining the relevant timing parameters of the part.
It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual
load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing
reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a
coaxial transmission line terminated at the tester electronics).
VDDQ
DQ
DQS
DQS
Output
DUT
VTT = VDDQ/2
RDQS
RDQS
Timing
reference
point
25Ω
AC Timing Reference Load
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing refer-
ence voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS)
signal.
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown below.
VDDQ
DUT
DQ
Output
DQS, DQS
VTT = VDDQ/2
RDQS, RDQS
25Ω
Test point
Slew Rate Test Load
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of
the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method
by which the DDR2 SDRAM pin timings are measured is mode dependent. In single
Rev. 0.8 / Oct. 2007
25
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its comple-
ment, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differen-
tial data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a
20 ohm to 10 K ohm resistor to insure proper operation.
t
t
DQSL
DQSH
DQS
DQS
DQS/
DQS
t
t
WPST
WPRE
V
(dc)
V
(ac)
IH
IH
DQ
DM
D
D
D
t
D
t
V
(ac)
V
(dc)
IL
IL
t
t
DH
DH
DS
DS
V
(dc)
V
(ac)
IH
IH
DMin
DMin
DMin
(ac)
DMin
V
IL
V
(dc)
IL
Figure -- Data input (write) timing
t
t
CL
CH
CK
CK
CK/CK
DQS
DQS
DQS/DQS
DQ
t
t
RPRE
RPST
Q
Q
Q
Q
t
DQSQmax
t
DQSQmax
t
QH
t
QH
Figure -- Data output (read) timing
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
7. All voltages referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/
supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage
range specified.
Rev. 0.8 / Oct. 2007
26
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
Specific Notes for dedicated AC parameters
1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast
active power down exit timing. tXARDS is expected to be used for slow active power down exit timing where a lower
power value is defined by each vendor data sheet.
2. AL = Additive Latency
3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min)
have been satisfied.
4. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency
5. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for other slew rate
values.
6. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns.
See System Derating for other slew rate values.
tDS, tDH Derating Values(ALL units in 'ps', Note 1 applies to entire Table)
DQS, DQS Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
tD
△
△
△
△
△
△
△
△
△
△
△
△
△
△
△
△
△
△
S
H
S
H
S
H
S
H
S
H
S
H
S
H
S
H
S
H
125 45 125 45 +125 +45
-
-
-
-
-
-
-
-
-
-
-
-
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
83
0
-
21
0
-
83
0
21 +83 +21 95
33
12
-2
-
-
-
-
-
-
-
-
-
-
-
0
0
0
12
1
24
13
-1
24
10
-7
-
-
-
-
-
-
-
DQ
Slew
rate
V/ns
-11 -14 -11 -14
25
11
-7
22
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-25 -31 -13 -19
23
5
17
-6
-
-
-
-
-
-
-
-
-
-
-
-
-
-31 -42 -42 -19
-8
17
-7
6
-
-
-
-
-
-
-
-
-
-
-43 -59 -31 -47 -19 -35
-23
5
-11
-
-
-
-
-
-
-74 -89 -62 -77 -50 -65 -38 -53
-127 -140 -115 -128 -103 -116
-
-
-
-
7. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a
differen tial slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single ended mode. See System
Derating for other slew rate values.
8. tDS and tDH derating table (for DDR2- 400 / 533)
1) For all input signals the total tDS(setup time) and tDH(hold time) required is calculated by adding the datasheet value
to the derating value listed in above Table.
Setup(tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the
first crossing of Vih(ac)min. Setup(tDS) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate
line between shaded ‘ VREF(dc) to ac region’, use nominal slew rate for derating value(see Fig a.) If the actual signal is
later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to
the actual signal from the ac level to dc level is used for derating value(see Fig b.)
Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate rate between the last crossing of Vil(dc) max and
the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of Vih(dc) min and the first crossing of VREF(dc). If the actual signal is earlier than the nominal slew rate line
anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to
VREF(dc) level is used for derating value(see Fig d.)
Rev. 0.8 / Oct. 2007
27
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/
IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach
VIH/IL(ac).
For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate rate between the last crossing of Vil(dc) max
and the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of Vih(dc) min and the first crossing of VREF(dc). If the actual signal is earlier than the nominal slew
rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the
dc level to VREF(dc) level is used for derating value(see Fig d.)
Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/
IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach
VIH/IL(ac).
For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Rev. 0.8 / Oct. 2007
28
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
Fig. a Illustration of nominal slew rate for tIS,tDS
CK,DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
VIH(ac)min
VIH(dc)min
nominal
slew rate
VREF(dc)
nominal
slew rate
VIL(dc)max
VREF to ac
region
VIL(ac)max
Vss
Delta TF
Delta TR
Setup Slew Rate
Falling Signal
VREF(dc)-VIL(ac)max
Delta TF
Setup Slew Rate
Rising Signal
VIH(ac)min-VREF(dc)
Delta TR
=
=
Rev. 0.8 / Oct. 2007
29
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
Fig. -b Illustration of tangent line for tIS,tDS
CK, DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
nominal
line
VIH(ac)min
VIH(dc)min
tangent
line
VREF(dc)
VIL(dc)max
VIL(ac)max
Tangent
line
V
REF to ac
region
Nomial
line
Vss
Delta TR
Setup Slew Rate
Rising Signal
Tangent line[VIH(ac)min-VREF(dc)]
Delta TR
=
Delta TF
Tangent line[VREF(dc)-VIL(ac)max]
Delta TF
Setup Slew Rate
Falling Signal
=
Rev. 0.8 / Oct. 2007
30
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
Fig. -c Illustration of nominal line for tIH, tDH
CK, DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
VIH(ac)min
VIH(dc)min
dc to VREF
region
nominal
slew rate
VREF(dc)
nominal
slew rate
VIL(dc)max
VIL(ac)max
Vss
Delta TR
Hold Slew Rate
Delta TF
VIH(dc)min - VREF(dc)
Delta TF
Hold Slew Rate
Rising Signal
VREF(dc)-VIL(dc)max
Delta TR
=
=
Falling Signal
Rev. 0.8 / Oct. 2007
31
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
Fig. -d Illustration of tangent line for tIH , tDH
CK, DQS
CK, DQS
tIS,
tDS
tIS,
tDS
tIH,
tDH
tIH,
tDH
VDDQ
VIH(ac)min
nominal
line
VIH(dc)min
tangent
line
VREF(dc)
dc to VREF
region
Tangent
line
nominal
line
VIL(dc)max
VIL(ac)max
Vss
Delta TR
Delta TF
Hold Slew Rate Tangent line[VREF(dc)-VIL(ac)max]
=
Rising Signal
Delta TR
Tangent line[VIH(ac)min-VREF(dc)]
Delta TF
Hold Slew Rate
Falling Signal
=
Rev. 0.8 / Oct. 2007
32
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
9. tIS and tIH (input setup and hold) derating
tIS, tIH Derating Values for DDR2 400, DDR2 533
CK, CK Differential Slew Rate
1.5 V/ns
2.0 V/ns
△tIS
1.0 V/ns
△tIH
+94
+89
+83
+75
+45
+21
0
△tIS
+217
+209
+197
+180
+155
+113
+30
△tIH
+124
+119
+113
+105
+75
△tIS
+247
+239
+227
+210
+185
+143
+60
△tIH
+124
+149
+143
+135
+105
+81
Units Notes
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
+187
+179
+167
+150
+125
+83
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+51
+0
+30
60
-11
-14
+19
+16
+49
+46
Command /
Address Slew
rate(V/ns)
-25
-31
+5
-1
+35
+29
-43
-54
-37
-53
-7
+6
-67
-83
-37
-53
-7
-23
-100
-150
-223
-250
-500
-750
-1250
-125
-188
-292
-375
-500
-708
-1125
-80
-95
-50
-65
-145
-255
-320
-495
-770
-1420
-158
-262
-345
-470
-678
-1095
-115
-225
-290
-465
-740
-1065
-128
-232
-315
-440
-648
TBD
tIS, tIH Derating Values for DDR2 667, DDR2 800
CK, CK Differential Slew Rate
2.0 V/ns
△tIS
1.5 V/ns
△tIS
1.0 V/ns
△tIH
+94
+89
+83
+75
+45
+21
0
△tIH
+124
+119
+113
+105
+75
△tIS
+210
+203
+193
+180
+160
+127
+60
△tIH
+154
+149
+143
+135
+105
+81
Units Notes
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
+150
+143
+133
+120
+100
+67
0
+180
+173
+163
+150
+130
+97
+30
+25
+17
+8
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+51
+30
60
-5
-14
+16
+55
+46
Command /
Address Slew
rate(V/ns)
-13
-31
-1
+47
+29
-22
-54
-24
+38
+6
-34
-83
-4
-53
-26
-23
-60
-125
-188
-292
-375
-500
-708
-1125
-30
-95
0
-65
-100
-168
-200
-325
-517
-1000
-70
-158
-262
-345
-470
-678
-1095
-40
-128
-232
-315
-440
-648
-1065
-138
-170
-295
-487
-970
-108
-140
-265
-457
-940
Rev. 0.8 / Oct. 2007
33
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the datasheet value to
the derating value listed in above Table.
Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first
crossing of VIH(ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate for line
between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value(see fig a.) If the actual signal is later than
the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual
signal from the ac level to dc level is used for derating value(see Fig b.)
Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the
first crossing of VREF(dc). Hold(tIH) nominal slew rate for a falling signal is defined as the slew rate between the last cross-
ing of VREF(dc). If the actual signal signal is always later than the nominal slew rate line between shaded ‘dc to VREF(dc)
region’, use nominal slew rate for derating value(see Fig.c) If the actual signal is earlier than the nominal slew rate line any-
where between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to
V
REF(dc) level is used for derating value(see Fig d.)
Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the
time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in table, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
11. MIN ( t CL, t CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the
device (i.e. this value can be greater than the minimum specification limits for t CL and t CH). For example, t CL and t CH
are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock source, and less the half period jitter due to
crosstalk (tJIT(crosstalk)) into the clock traces.
12. t QH = t HP – t QHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock
low ( tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition,
both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel
variation of the output drivers.
13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers
as well as output slew rate mismatch between DQS/ DQS and associated DQ in any given cycle.
14. DAL = WR + RU{tRP(ns)/tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS.
For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the
application clock period.
Example: For DDR533 at tCK = 3.75ns with tWR programmed to 4 clocks.
tDAL = 4 + (15ns/3.75ns) clocks = 4+(4) clocks = 8 clocks.
15. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock
frequency change during precharge power-down, a specific procedure is required as described in section 2.9.
16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
Rev. 0.8 / Oct. 2007
34
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
17. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
18. tHZ and tLZ transitions occur in the same access time as valid data transitions. Thesed parameters are referenced
to a specific voltage level which specifies when the device output is no longer driving(tHZ), or begins driving (tLZ).
Below figure shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ)
by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as
the calculation is consistenet.
19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device
output is no longer driving (tRPST), or begins driving (tRPRE). Below figure shows a method to calculate these
points when the device is no longer driving (tRPST), or begins driving (tRPRE). Below Figure shows a method to
calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the
signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is
consistent.
VOH + xmV
VTT + 2xmV
VTT + xmV
VOH + 2xmV
tHZ
tHZ
tRPST end point
tRPRE begin point
VOL + 1xmV
VOL + 2xmV
VTT -xmV
VTT - 2xmV
tHZ , tRPST end point = 2*T1-T2
tLZ , tRPRE begin point = 2*T1-T2
20. Input waveform timing with differential data strobe enabled MR[bit10] =0, is referenced from the input signal
crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal
crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under
test.
21. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal
crossing at the VIH(dc) level to the differential data strobe crosspoint for a rising signal and VIL(dc) to the
differential data strobe crosspoint for a falling signal applied to the device under test.
Differential Input waveform timing
DQS
DQS
tDS tDH
tDS tDH
VDDQ
VIH(ac)min
VIH(dc)min
VREF(dc)
VIL(dc)max
VIL(ac)max
VSS
Rev. 0.8 / Oct. 2007
35
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
DQS
DQS
tIS
tIH
tIS
tIH
VDDQ
VIH(ac)min
VIH(dc)min
VREF(dc)
VIL(dc)max
VIL(ac)max
VSS
24. tWTR is at least two clocks (2*tCK) independent of operation frequency.
25. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal
crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a
rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing
VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between VIL(dc)max and VIH(dc) min.
26. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal
crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a
rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing
VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between VIL(dc) max and VIH(dc) min.
27. tCKE min of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at
the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition,
CKE may not transition from its valid level during the time period of tIS + 2*tCK + tIH.
Rev. 0.8 / Oct. 2007
36
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
5. Package Dimensions
Package Dimension(x4,x8)
60Ball Fine Pitch Ball Grid Array Outline
10.50 +/- 0.10
A1 Ball Mark
<Top View>
1.20 Max.
0.34 +/- 0.05
A1 Ball Mark
60 - φ0.45 ± 0.05
1
2
3
7
8
9
0.80
0.80 x 8 = 6.40
<Bottom View>
note: all dimension units are Millimeters.
Rev. 0.8 / Oct. 2007
37
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
Package Dimension(x16)
84Ball Fine Pitch Ball Grid Array Outline
10.50 +/- 0.10
A1 Ball Mark
1.20 Max.
0.34 +/- 0.05
A1 Ball Mark
1
2
3
7
8
9
84 - φ0.45 ± 0.05
0.80
0.80 x 8 = 6.40
<Bottom View>
note: all dimension units are Millimeters.
Rev. 0.8 / Oct. 2007
38
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