HYM7V72A831TFG-10 [HYNIX]
Synchronous DRAM Module, 8MX72, 8ns, CMOS, DIMM-168;
| 型号： | HYM7V72A831TFG-10 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Synchronous DRAM Module, 8MX72, 8ns, CMOS, DIMM-168 动态存储器 |
| 文件： | 总15页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8Mx72 bit SDRAM Unbuffered DIMM F-Series
based on 8Mx8 SDRAM, LVTTL, 2/4-Banks & 4K/8K-Refresh
HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831
DESCRIPTION
The HYM7V72A800/ 72A801/ 72A830/ 72A831 F-Series are high speed 3.3-Volt synchronous dynamic
RAM Modules composed of nine 8Mx8 bit Synchronous DRAMs in 54-pin TSOPII and 8-pin TSSOP 2K bit
E2PROM on a 168-pin glass-epoxy printed circuit board. Two 0.22mF and two 0.0022mF decoupling capa-
citors per each SDRAM are mounted on the module.
The HYM7V72A800/ 72A801/ 72A830/ 72A831 F-Series are gold plated socket type Dual In-line Memory
Modules suitable for easy interchange and addition of 64M bytes memory. All addresses, data and control
inputs are latched on the rising edge of the master clock input. The data paths are internally pipelined to
achieve very high bandwidths.
FEATURES
· 168-Pin Unbuffered DIMM with ECC
· Serial Presence Detect with Serial E2PROM
· Meets all the other JEDEC specifications
· Single 3.3V±0.3V power supply
· All device pins are LVTTL compatible
· 4096 refresh cycles every 64ms or 8192 refresh
cycles every 128ms
· Interleaved auto refresh mode
· Programmable burst lengths and sequences
- 1,2,4,8,full page for Sequential type
- 1,2,4,8 for Interleave type
· Programmable /CAS latency ; 1,2,3 clocks
· Support clock suspend/power down mode by
CKE0
· Fully synchronous ; all inputs referenced to
positive edge of system clock
· Data mask function by DQM
· Mode register set programming
· Burst termination command
· Dual or Quad internal banks with single pulsed
/RAS
· Self refresh provides minimum power, full
internal refresh control
· Auto precharge/precharge all banks by A10 flag
· Possible to assert random column address
every clock cycle
ORDERING INFORMATION
Part No.
Max. Frequency SDRAM Bank Refresh Package Plating
HYM7V72A800TFG - 10/12/15
HYM7V72A801TFG - 10/12/15
HYM7V72A830TFG - 10/12/15
HYM7V72A831TFG - 10/12/15
100/ 83/ 66 MHz
100/ 83/ 66 MHz
100/ 83/ 66 MHz
100/ 83/ 66 MHz
2 Banks
4 Banks
2 Banks
4 Banks
4K
4K
8K
8K
TSOP
TSOP
TSOP
TSOP
Gold
Gold
Gold
Gold
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Sep. 1998
Rev 4.1
HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831 F-Series
PIN DESCRIPTION
Pin Name
Pin Type
Description
System Clock Input; All other inputs except CKE are registered
to the SDRAM on the rising edge of CLK.
CK0-CK3
CKE0
INPUT
Clock Enable; Controls internal clock signal and when deactiva-
ted, the SDRAM will be either one of the states among power
down, suspend, or self refresh.
INPUT
/S0, /S2
/RAS
INPUT
INPUT
Chip select; Functions command mask(NOP).
Row address strobe; See functional truth table in 8Mx8 Data
Sheets for details.
Column address strobe; See functional truth table in 8Mx8 Data
Sheets for details.
/CAS
INPUT
Write Enable; See functional truth table in 8Mx8 Data Sheets
for details.
/WE
INPUT
INPUT
DQM0-7
DQ0-DQ63
Data Input / Output Mask
INPUT/
OUTPUT
Data Input / Output; Include inputs, outputs, or Hi-z state.
INPUT/
OUTPUT
Check Bit Input / Output; Include inputs, outputs, or Hi-z state.
CB0-CB7
VCC
VSS
SUPPLY
SUPPLY
Power Supplies; 3.3V±0.3V
Ground
INPUT/
SDA
Serial Address and Data Input / Output.
OUTPUT
SCL
INPUT
INPUT
Serial Clock
SA0-SA2
Addresses in Serial E2PROM for Socket Presence.
HYM7V72A800/HYM7V72A830 F-Series ( 2Bank 8Mx8 SDRAM Based )
Pin Name
Pin Type
Description
Bank select address inputs; Select one of dual banks during
both /RAS and /CAS activity.
BA0
INPUT
Address Inputs;
A0-A8; X&Y addresses, A0-A13; Opcode for mode register set,
A10; Precharge flag, A9-A12; X addresses only.
A0-A12
INPUT
HYM7V72A801/HYM7V72A831 F-Series ( 4Bank 8Mx8 SDRAM Based )
Pin Name
Pin Type
Description
Bank address inputs; Select one of quad banks during both
/RAS and /CAS activity.
BA0, BA1
INPUT
Address Inputs;
A0-A8; X&Y addresses, A0-A13; Opcode for mode register set,
A10; Precharge flag, A9-A11; X addresses only.
A0-A11
INPUT
Rev 4.1
2
HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831 F-Series
PIN NAME
#
NAME
#
NAME
#
NAME
#
NAME
1
2
3
4
5
6
7
8
9
Vss
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Vss
85
86
Vss
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DU
DQ32
DQ33
DQ34
DQ35
Vcc
CKE0
NC
/S2
87
DQM2
DQM3
DU
88
DQM6
DQM7
NC
89
90
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
Vcc
91
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
Vcc
NC
92
NC
NC
93
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CB2
94
CB6
CB3
95
CB7
Vss
96
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ16
DQ17
DQ18
DQ19
Vcc
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ48
DQ49
DQ50
DQ51
Vcc
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
DQ20
NC
DQ52
NC
DQ14
DQ15
CB0
CB1
Vss
DQ46
DQ47
CB4
CB5
Vss
VREF, NC
NC
VREF, NC
NC
Vss
Vss
DQ21
DQ22
DQ23
Vss
DQ53
DQ54
DQ55
Vss
NC
NC
NC
NC
Vcc
Vcc
/WE
DQM0
DQM1
/S0
DQ24
DQ25
DQ26
DQ27
Vcc
/CAS
DQM4
DQM5
NC
DQ56
DQ57
DQ58
DQ59
Vcc
DU
/RAS
Vss
Vss
DQ28
DQ29
DQ30
DQ31
Vss
DQ60
DQ61
DQ62
DQ63
Vss
A0
A1
A2
A3
A4
A5
A6
A7
A8
*CK2
NC
A9
*CK3
NC
A10(AP)
* BA1
Vcc
BA0
NC
A11
SA0
SDA
SCL
Vcc
SA1
Vcc
CK1
* A12
SA2
CK0
Vcc
Vcc
Note : 1. BA1 is used for HYM7V72A801/HYM7V72A831 F-Series ( 4 Bank 8Mx8 Based )
2. A12 is used for HYM7V72A800/HYM7V72A830 F-Series ( 2 Bank 8Mx8 Based )
3. CK2 and CK3 are connected with termination R/C ( Refer to the block diagram )
3
Rev 4.1
HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831 F-Series
BLOCK DIAGRAM
Note : 1. The serial resistor values of DQs are 10 Ohms.
2. The padding capacitance of termination R/C for CK2/3 is 10pF.
Rev 4.1
4
HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831 F-Series
I-1 SERIAL PRESENCE DETECT
[ HYM7V72A800/HYM7V72A830 F-Series; 2 Banks ]
BYTE NUMBER
FUNCTION DESCRIBED
FUNCTION
VALUE
NOTE
BYTE0
# of Bytes Written into Serial Memory
at Module Manufacturer
128 Bytes
80h
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
256 Bytes
SDRAM
2 Banks; 13
9
08h
04h
0Dh
09h
01h
48h
00h
01h
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
1
1 Bank
72 Bits
-
Data Width of This Assembly(Continued)
Voltage Interface Standard of This Assembly
LVTTL
tCLK
(A) 10ns
(B) 12ns
(C) 15ns
tAC
(A) 8ns
(B) 9ns
(C) 10ns
ECC
SDRAM Cycle Time
@ /CAS Latency=3
3
3
(A) A0h
(B) C0h
(C) F0h
BYTE10
SDRAM Access Time from Clock
@ /CAS Latency=3, @Cycle Time=10ns
@ /CAS Latency=3, @Cycle Time=12ns
@ /CAS Latency=3, @Cycle Time=15ns
(A) 80h
(B) 90h
(C) A0h
02h
BYTE11
BYTE12
DIMM Configuration Type
Refresh Rate/Type
80h
15.625ms
/ Self Refresh Supported
BYTE13
BYTE14
BYTE15
Primary SDRAM Width
Error Checking SDRAM Width
Minimum Clock Delay Back to Back
Random Column Address
Burst Lengths Supported
# of Banks on SDRAM Device
2 Bank 8Mx8 Based
x8
x8
08h
08h
01h
tCCD=1 Latency
BYTE16
BYTE17
1,2,4,8,Full Page
2 Banks
8Fh
2
02h
07h
BYTE18
CAS # Latency
/CAS
Latency=1,2,3
BYTE19
BYTE20
BYTE21
CS # Latency
Write Latency
/CS Latency=0
01h
01h
00h
/WE Latency=0
-
SDRAM Module Attributes
( Neither Buffered nor Registered )
SDRAM Module Attributes General
( Burst read, Precharge All, Auto Precharge )
BYTE22
BYTE23
-
06h
SDRAM Cycle Time
@ /CAS Latency=2
tCLK
3
(A) 12ns
(B) 15ns
(C) 15ns
(A) C0h
(B) F0h
(C) F0h
5
Rev 4.1
HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831 F-Series
I-2 SERIAL PRESENCE DETECT
[ HYM7V72A800/HYM7V72A830 F-Series; 2 Banks: Continued ]
BYTE NUMBER
FUNCTION DESCRIBED
FUNCTION
VALUE
NOTE
BYTE24
SDRAM Access Time from Clock
@ /CAS Latency=2, @Cycle Time=12ns
@ /CAS Latency=2, @Cycle Time=15ns
@ /CAS Latency=2, @Cycle Time=15ns
tAC
3
(A) 9ns
(B) 9ns
(C) 10ns
tCLK
(A) 30ns
(B) 30ns
(C) 30ns
tAC
(A) 24ns
(B) 24ns
(C) 24ns
tRP
(A) 30ns
(B) 36ns
(C) 45ns
tRRD
(A) 30ns
(B) 24ns
(C) 30ns
tRCD
(A) 30ns
(B) 36ns
(C) 45ns
tRAS
(A) 90h
(B) 90h
(C) A0h
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
SDRAM Cycle Time
@ /CAS Latency=1
3
3
3
3
3
3
(A) 78h
(B) 78h
(C) 78h
SDRAM Access Time from Clock
@ /CAS Latency=1, @Cycle Time=30ns
@ /CAS Latency=1, @Cycle Time=30ns
@ /CAS Latency=1, @Cycle Time=30ns
(A) 60h
(B) 60h
(C) 60h
Minimum Row Pre-charge Time
@/CAS Latency=3, @Cycle Time=10ns
@/CAS Latency=3, @Cycle Time=12ns
@/CAS Latency=3, @Cycle Time=15ns
(A) 1Eh
(B) 24h
(C) 2Dh
Minimum Row Active to Row Active Delay
@/CAS Latency=3, @Cycle Time=10ns
@/CAS Latency=3, @Cycle Time=12ns
@/CAS Latency=3, @Cycle Time=15ns
(A) 1Eh
(B) 18h
(C) 1Eh
Minimum /RAS to /CAS Delay
@/CAS Latency=3, @Cycle Time=10ns
@/CAS Latency=3, @Cycle Time=12ns
@/CAS Latency=3, @Cycle Time=15ns
(A) 1Eh
(B) 24h
(C) 2Dh
Minimum /RAS Pulse width
@/CAS Latency=3, @Cycle Time=10ns
@/CAS Latency=3, @Cycle Time=12ns
@/CAS Latency=3, @Cycle Time=15ns
(A) 50ns
(B) 48ns
(C) 45ns
64MB
(A) 32h
(B) 30h
(C) 2Dh
10h
BYTE31
Module Bank Density
Superset Information
(May Be Used in the Future)
SPD Revision
BYTE32-61
-
00h
BYTE62
BYTE63
-
01h
Checksum for Byte 0-62
3
@/CAS Latency=3, @Cycle Time=10ns
@/CAS Latency=3, @Cycle Time=12ns
@/CAS Latency=3, @Cycle Time=15ns
(A) Decimal 4
(B) Decimal 104
(C) Decimal 205
-
(A) 04h
(B) 68h
(C) CDh
-
BYTE64-127
BYTE128-255
Manufacturer Information
Unused Storage Locations
Undefined
Undefined
Note : 1. The bank address is excluded.
2. In interleaved type. the burst lengths supported is 1,2,4,8.
3. In case of (A): 10ns, (B): 12ns, and (C): 15ns part.
* All above data can be changed, if the JEDEC standard is modified.
Rev 4.1
6
HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831 F-Series
II-1 SERIAL PRESENCE DETECT
[ HYM7V72A801/HYM7V72A831 F-Series; 4 Banks ]
BYTE NUMBER
FUNCTION DESCRIBED
FUNCTION
VALUE
NOTE
BYTE0
# of Bytes Written into Serial Memory
at Module Manufacturer
128 Bytes
80h
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
256 Bytes
SDRAM
4 Banks; 12
9
08h
04h
0Ch
09h
01h
48h
00h
01h
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
1
1 Bank
72 Bits
-
Data Width of This Assembly(Continued)
Voltage Interface Standard of This Assembly
LVTTL
tCLK
(A) 10ns
(B) 12ns
(C) 15ns
tAC
(A) 8ns
(B) 9ns
(C) 10ns
ECC
SDRAM Cycle Time
@ /CAS Latency=3
3
3
(A) A0h
(B) C0h
(C) F0h
BYTE10
SDRAM Access Time from Clock
@ /CAS Latency=3, @Cycle Time=10ns
@ /CAS Latency=3, @Cycle Time=12ns
@ /CAS Latency=3, @Cycle Time=15ns
(A) 80h
(B) 90h
(C) A0h
02h
BYTE11
BYTE12
DIMM Configuration Type
Refresh Rate/Type
80h
15.625ms
/ Self Refresh Supported
BYTE13
BYTE14
BYTE15
Primary SDRAM Width
Error Checking SDRAM Width
Minimum Clock Delay Back to Back
Random Column Address
Burst Lengths Supported
# of Banks on SDRAM Device
4 Bank 8Mx8 Based
x8
x8
08h
08h
01h
tCCD=1 Latency
BYTE16
BYTE17
1,2,4,8,Full Page
4 Banks
8Fh
2
04h
07h
BYTE18
CAS # Latency
/CAS
Latency=1,2,3
BYTE19
BYTE20
BYTE21
CS # Latency
Write Latency
/CS Latency=0
01h
01h
00h
/WE Latency=0
-
SDRAM Module Attributes
( Neither Buffered nor Registered )
SDRAM Module Attributes General
( Burst read, Precharge All, Auto Precharge )
BYTE22
BYTE23
-
06h
SDRAM Cycle Time
@ /CAS Latency=2
tCLK
3
(A) 12ns
(B) 15ns
(C) 15ns
(A) C0h
(B) F0h
(C) F0h
7
Rev 4.1
HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831 F-Series
II-2 SERIAL PRESENCE DETECT
[ HYM7V72A801/HYM7V72A831 F-Series; 4 Banks: Continued ]
BYTE NUMBER
FUNCTION DESCRIBED
FUNCTION
VALUE
NOTE
BYTE24
SDRAM Access Time from Clock
@ /CAS Latency=2, @Cycle Time=12ns
@ /CAS Latency=2, @Cycle Time=15ns
@ /CAS Latency=2, @Cycle Time=15ns
tAC
3
(A) 9ns
(B) 9ns
(C) 10ns
tCLK
(A) 30ns
(B) 30ns
(C) 30ns
tAC
(A) 24ns
(B) 24ns
(C) 24ns
tRP
(A) 30ns
(B) 36ns
(C) 45ns
tRRD
(A) 30ns
(B) 24ns
(C) 30ns
tRCD
(A) 30ns
(B) 36ns
(C) 45ns
tRAS
(A) 90h
(B) 90h
(C) A0h
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
SDRAM Cycle Time
@ /CAS Latency=1
3
3
3
3
3
3
(A) 78h
(B) 78h
(C) 78h
SDRAM Access Time from Clock
@ /CAS Latency=1, @Cycle Time=30ns
@ /CAS Latency=1, @Cycle Time=30ns
@ /CAS Latency=1, @Cycle Time=30ns
(A) 60h
(B) 60h
(C) 60h
Minimum Row Pre-charge Time
@/CAS Latency=3, @Cycle Time=10ns
@/CAS Latency=3, @Cycle Time=12ns
@/CAS Latency=3, @Cycle Time=15ns
(A) 1Eh
(B) 24h
(C) 2Dh
Minimum Row Active to Row Active Delay
@/CAS Latency=3, @Cycle Time=10ns
@/CAS Latency=3, @Cycle Time=12ns
@/CAS Latency=3, @Cycle Time=15ns
(A) 1Eh
(B) 18h
(C) 1Eh
Minimum /RAS to /CAS Delay
@/CAS Latency=3, @Cycle Time=10ns
@/CAS Latency=3, @Cycle Time=12ns
@/CAS Latency=3, @Cycle Time=15ns
(A) 1Eh
(B) 24h
(C) 2Dh
Minimum /RAS Pulse width
@/CAS Latency=3, @Cycle Time=10ns
@/CAS Latency=3, @Cycle Time=12ns
@/CAS Latency=3, @Cycle Time=15ns
(A) 50ns
(B) 48ns
(C) 45ns
64MB
(A) 32h
(B) 30h
(C) 2Dh
10h
BYTE31
Module Bank Density
Superset Information
BYTE32-61
-
00h
(May Be Used in the Future)
SPD Revision
BYTE62
BYTE63
-
01h
Checksum for Byte 0-62
3
@/CAS Latency=3, @Cycle Time=10ns
@/CAS Latency=3, @Cycle Time=12ns
@/CAS Latency=3, @Cycle Time=15ns
Manufacturer Information
(A) Decimal
5
(A) 05h
(B) 69h
(C) CEh
-
(B) Decimal 105
(C) Decimal 206
-
BYTE64-127
BYTE128-255
Unused Storage Locations
Undefined
Undefined
Note : 1. The bank address is excluded.
2. In interleaved type. the burst lengths supported is 1,2,4,8.
3. In case of (A): 10ns, (B): 12ns, and (C): 15ns part.
* All above data can be changed, if the JEDEC standard is modified.
Rev 4.1
8
HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831 F-Series
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rating
0 to 70
-55 to 125
-1.0 to 4.6
-1.0 to 4.6
50
Unit
TA
Ambient Temperature
°C
°C
TSTG
Storage Temperature
VIN, VOUT
VCC
Voltage on Any Pin relative to VSS
Voltage on VCC relative to VSS
Short Circuit Output Current
Power Dissipation
V
V
IOS
mA
W
PD
9
TSOLDER
Soldering Temperature×Time
260×10
°C×sec
Note : Operation at above Absolute Maximum Ratings can adversely affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS*
(TA=0°C to 70°C)
Symbol
Parameter
Min.
3.0
0
Typ.
Max.
3.6
Unit
V
Note
VCC
Vss
VIH
VIL
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
3.3
0
-
0
V
2.0
-0.3
VCC + 0.4
0.8
V
LVTTL
LVTTL
-
V
RECOMMENDED AC OPERATING CONDITIONS* (TA=0°C to 70°C, VCC=3.3V±10%, VSS=0V)
Symbol
VIH / VIL
Vtrip
Parameter
AC Input High/Low Level Voltage
Value
2.4/0.4
1.4
Unit
V
Note
LVTTL
LVTTL
Input Timing Measurement Reference Level Voltage
Input Rise/Fall Time
V
tr / tf
1
ns
V
Voutref
CL
Output Reference Voltage
1.4
LVTTL
Output Load Capacitance for Access Time Measurement
Note
pF
Note : Output load to measure access times is equivalent to two TTL gates and one capacitance(50pF).
Note : *
DC Output Load Circuit
AC Output Load Circuit
50W
Rt=500W
Output
Vtt=1.4V
Vtt=1.4V
Z0=50W
Output
50pF
50pF
9
Rev 4.1
HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831 F-Series
DC CHARACTERISTICS(I)
(TA=0°C to 70°C, VCC=3.3V±10%, VSS=0V)
Symbol
Parameter
Test Condition
Min.
-9
Max.
9
Unit
Note
VI=0 to 3.6V, All other
pins not undertest=0V
ILI
Input Leakage Current
mA
DOUT is disabled,
VO=0 to 3.6V
IO=2.0mA
ILO
Output Leakage Current
-1
1
mA
VOL
VOH
Output Low Voltage
Output High Voltage
-
0.4
-
V
V
LVTTL
LVTTL
IO=-2.0mA
2.4
DC CHARACTERISTICS(II)
(TA=0°C to 70°C, VCC=3.3V±10%, VSS=0V)
Test Condition Max. Unit Note
10ns 765
Symbol
Parameter
Burst Length=1, One bank active
tRAS³ tRAS(min),
ICC1
Operating current
12ns 630 mA Note 2
15ns 540
tRP³ tRP(min), IO=0mA
Precharge Standby Current
in Power Down Mode
ICC2P
ICC2N
18
mA
CKE£VIL(max)
Precharge Standby Current
in Non Power Down Mode
108 mA LVTTL1
CKE³ VIH(min), All other pins³ VCC-0.2V or
£0.2V
Active Standby Current
in Power Down Mode
ICC3P
ICC3N
27
mA
CKE£VIL(max), All banks active
Active Standby Current
in Non Power Down Mode
Operating Current
315 mA LVTTL1
CKE³ VIH(min), All other pins³ VCC-0.2V
or £0.2V All banks active
10ns 1350
tCLK³ tCLK(min),
ICC4
ICC5
(Burst Mode)
12ns 1080 mA Note 2
15ns 900
tRAS³ tRAS(min),
IO=0mA, /CAS Latency=3
tRC³ tRC(min), Two banks active
(8K/128ms)
10ns 990
12ns 810 mA Note 2
15ns 900
Refresh Current
10ns 1440
tRC³ tRC(min), Four banks active
(4K/64ms)
12ns 1170 mA Note 2
15ns 945
ICC6
Self Refresh Current
18
mA
CKE£0.2V
4.5
L-part
Note :
1. It depends on the number of each pin¢s transition. It is assumed there is no transition to measure this
current.
2. ICC1 depends on output loads and cycle rates. Specified values are obtained with the output open.
In addition this ICC1 is measured on condition that addresses are changed only one time during tCLK(Min.)
Rev 4.1
10
HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831 F-Series
AC CHARACTERISTICS
Synchronous Characteristics(I)
100MHz
(10ns)
83MHz
(12ns)
66MHz
(15ns)
Parameter
Unit
/CAS Latency
Frequency
3
2
1
3
2
1
3
2
1
Latency
MHz
100 83 33 83 66 33 66 66 33
Clock Cycle Time 10 12 30 12 15 30 15 15 30
ns
tRCD
3
5
3
8
3
1
4
1
2
4
3
7
2
1
3
1
1
1
2
1
3
1
1
2
1
3
4
3
7
2
1
3
1
2
4
2
6
2
1
3
1
1
1
2
1
3
2
1
2
1
3
3
3
-
2
4
2
6
2
1
3
1
1
2
1
3
2
1
2
1
CLK(s)
CLK(s)
CLK(s)
CLK(s)
CLK(s)
CLK(s)
CLK(s)
CLK(s)
ns
tRAS
tRP
tRC
tRRD
2
-
tDPL
tDAL
-
tSRE
-
tT
1
8K/128ms, 4K/64ms
Cycles
Refresh Cycle
Asynchronous
Characteristic
50ns Part
ns
Note : tRRD -Bank Active to Active Command
tDPL -DIN to Precharge Command
tDAL -DIN to Active(Ref.) Command (After Write with Autoprecharge)
tSRE -Self Refresh Exit Time
Synchronous Characteristics(II)
Symbol
Parameter
-10
-12
-15
Unit Note
Min. Max. Min. Max. Min. Max.
/CAS Lat.=3
/CAS Lat.=2
/CAS Lat.=1
-
-
8
9
24
-
-
-
9
9
24
-
-
-
10
10
24
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAC
Access Time from CLK
-
-
-
tCH
CLK High Level Width
CLK Low Level Width
Data-out Hold Time
3.5
3.5
3
3.5
3.5
3
3.5
3.5
3
tCL
-
-
-
tOH
tOLZ
tOHZ
tDS
-
-
-
Data-out Low-Impedance Time
Data-out High-Impedance Time
Data-in Set-up Time
3
-
3
-
3
-
0
8
-
0
9
-
0
10
-
3
3
3
tDH
Data-in Hold Time
1
-
1
-
1
-
tAS
Address Set-up Time
Address Hold Time
3
-
3
-
3
-
tAH
1
-
1
-
1
-
tCKS
tCKH
tCS
CKE Set-up Time
3
-
3
-
3
-
CKE Hold Time
1
-
1
-
1
-
Command Set-up Time
Command Hold Time
Power Down Exit Set-up Time
3
-
3
-
3
-
tCH
1
-
1
-
1
-
tPDE
3
-
3
-
3
-
11
Rev 4.1
HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831 F-Series
Latency
Symbol
Parameter
Latency
tCKED
tDQMOZ
tDQMIM
tWTL
CKE to CLK Suspend / Power Down Mode Entry
DQM to Data Output in Hi-z
1
2
0
0
1
2
3
1
1
1
DQM to Data Input Mask
Write Command to Data Input Valid
/CAS Latency=1
/CAS Latency=2
/CAS Latency=3
tPROZ
Precharge Command to Data Output in Hi-z
tMRD
tCCD
tPPD
Mode Register Set to New Command
Min. Column Address to Column Address Delay
Min. Precharge to Precharge Time
Note :
1. All voltages referenced VSS(Ground).
2. An initial pause of 100mS is required after power-on followed by Power On Sequence & Auto Refresh
before proper device operation is achieved.
3. AC measurements assume tT=1ns.
4. Reference level for measuring timing of input signals is 1.40V for LVTTL
Transition times are measured between VIH and VIL.
5. An access time is measured at 1.40V for LVTTL
CAPACITANCE
(TA=25°C, f=1MHz)
Symbol
Parameter
Pin
Typ. Max.
Unit
pF
pF
pF
pF
pF
pF
pF
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Output Capacitance
A0-A11/12, BA0/BA1
/RAS, /CAS, /WE
/S0, /S2
-
-
-
-
75
75
40
45
60
20
15
CK0, CK1
CKE0
DQM0-DQM7
DQ0-DQ63,CB0-CB7
-
-
Rev 4.1
12
HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831 F-Series
PROGRAMMABLE MODE REGISTER
MODE REGISTER SET(WRITE)
A13
0
A12
0
A11
0
A10
0
A9
0
A8
0
A7
0
A6
A5
A4
A3
BT
A2
A1
A0
/CAS Latency
Burst Length
A3
Burst Type
0
1
Sequential (Wrap round, Binary-up)
Interleave (Wrap round)
A2
0
A1
0
A0
0
Burst Length
A6
0
A5
0
A4
0
/CAS Latency
Reserved
1
1
0
0
1
2
0
0
1
0
1
0
4
0
1
0
2
0
1
1
8
0
1
1
3
1
0
0
Reserved
Reserved
Reserved
Full page1
1
0
0
Reserved
Reserved
Reserved
Reserved
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Note : 1. Full page burst supports only sequential type.
TEST MODE
A11 A10 A9
A8
0
A7 A6
A5
X
A4
X
A3
X
A2
X
A1
X
A0
X
Address
Refresh Counter Test
0
0
0
1
X
Note : Test Mode - Used to test the counter of Auto Refresh.
- Exit test mode using ¢Precharge All banks¢.
13
Rev 4.1
HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831 F-Series
BURST LENGTH AND SEQUENCE
Initial Address
Burst Type
Burst Length
2
A2 A1 A0
X X 0
X X 1
X 0 0
X 0 1
X 1 0
X 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Sequential
0,1
Interleave
0,1
1,0
1,0
4
0,1,2,3
0,1,2,3
1,2,3,0
1,0,3,2
2,3,0,1
2,3,0,1
3,0,1,2
3,2,1,0
8
0,1,2,3,4,5,6,7
1,2,3,4,5,6,7,0
2,3,4,5,6,7,0,1
3,4,5,6,7,0,1,2
4,5,6,7,0,1,2,3
5,6,7,0,1,2,3,4
6,7,0,1,2,3,4,5
7,0,1,2,3,4,5,6
0,1,2,3,4,......,m
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
1,2,3,4,5,......,0
Full page
Note
Not supported
.
.
.
m,0,1,2,3,......,m-1
Table 1. Address sequence for different burst lengths
Note : 4Mbit x 2banks x 8I/O - Initial addresses: A8-A0, Page length: 1024, m=1023
2Mbit x 4banks x 8I/O - Initial addresses: A8-A0, Page length: 1024, m=1023
Rev 4.1
14
HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831 F-Series
PACKAGE DIMENSION
15
Rev 4.1
相关型号：
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