HYMP351P72AMP4-C4 [HYNIX]
DDR DRAM Module, 512MX72, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240;
| 型号： | HYMP351P72AMP4-C4 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | DDR DRAM Module, 512MX72, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总24页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
240pin Registered DDR2 SDRAM DIMMs based on 1Gb A ver.
This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 1Gb 1st ver. DDR2 SDRAMs
in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb ver. based Reg-
istered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width form factor of
industry standard. It is suitable for easy interchange and addition.
FEATURES
•
JEDEC standard Double Data Rate2 Synchro-
nous DRAMs (DDR2 SDRAMs) with 1.8V +/-
0.1V Power Supply
•
•
Fully differential clock operations (CK & /CK)
Programmable Burst Length 4 / 8 with both
sequential and interleave mode
•
All inputs and outputs are compatible with
SSTL_1.8 interface
•
•
•
•
•
•
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
•
•
•
•
•
8 Bank architecture
Serial presence detect with EEPROM
DDR2 SDRAM Package: 60, 68ball FBGA
133.35 x 30.00 mm form factor
Posted CAS
Programmable CAS Latency 3 , 4 , 5
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
Lead-free Products are RoHS compliant
ORDERING INFORMATION
# of
DRAMs
# of
ranks
Parity
Support
Part Name
Density
Organization
HYMP112P72AP8-C4/Y5
HYMP125P72AP4-C4/Y5
HYMP351P72AMP4-C4/Y5
HYMP112R72AP8-E3
1GB
2GB
4GB
1GB
2GB
4GB
128Mx72
256Mx72
512Mx72
128Mx72
256Mx72
512Mx72
9
1
1
2
1
1
2
O
O
O
X
18
36
9
HYMP125R72AP4-E3
18
36
X
HYMP351R72AMP4-E3
X
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Jul. 2007
1
1240pin Registered DDR2 SDRAM DIMMs
SPEED GRADE & KEY PARAMETERS
E3 (DDR2-400)
C4 (DDR2-533)
Y5 (DDR2-667)
Unit
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
400
533
400
533
-
400
533
Mbps
Mbps
Mbps
tCK
667
667
3-3-3
4-4-4
5-5-5
ADDRESS TABLE
# of
DRAMs
Refresh
Method
Organization Ranks
SDRAMs
# of row/bank/column Address
1GB
2GB
4GB
128M x 72
256M x 72
512M x 72
1
1
2
128Mb x 8
256Mb x 4
256Mb x 4
9
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
8K / 64ms
18
36
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms
Rev. 0.2 / Jul. 2007
2
1240pin Registered DDR2 SDRAM DIMMs
Input/Output Functional Description
Symbol
Type
Polarity
Pin Description
Positive
Edge
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CK0
CK0
IN
Negative
Edge
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
IN
IN
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deacti-
vating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
CKE[1:0]
S[1:0]
Active High
Enables the associated DDR2 SDRAM command decoder when low and disables the command
IN
Active Low decoder when high. When the command decoder is disabled, new commands are ignored but previous
operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
ODT[1:0]
RAS, CAS, WE
Vref
IN
IN
Active High On-Die Termination signals.
When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define the
command being entered.
Active Low
Supply
Supply
IN
Reference voltage for SSTL18 inputs
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current
DDR2 unbuffered DIMM designs, V
V
DDQ
shares the same power plane as V pins.
DDQ
DD
BA[2:0]
-
-
Selects which DDR2 SDRAM internal bank of Eight is activated.
During a Bank Activate command cycle, Address input difines the row address(RA0~RA13)
During a Read or Write command cycle, Address input defines the column address when sampled at the
cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used
to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autopre-
charge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is dis-
abled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which
bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn
inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
A[9:0],A10/AP
A[13:11]
IN
DQ[63:0],
CB[7:0]
Data and Check Bit Input/Output pins.
IN
IN
-
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with
Active High that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input
only, the DM loading matches the DQ and DQS loading.
DM[8:0]
Power and ground for the DDR2 SDRAM input buffers, and core logic. V and V
pins are tied to
DDQ
DD
V
,V
Supply
DD SS
V
/V
planes on these modules.
DD DDQ
Positive
Edge
Positive line of the differential data strobe for input and output data
Negative line of the differential data strobe for input and output data
DQS[17:0]
DQS[17:0]
SA[2:0]
I/O
I/O
IN
Negative
Edge
These signals are tied at the system planar to either V or V
SS
to configure the serial SPD
DDSPD
-
-
-
EEPROM address range.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may be con-
nected from the SDA bus line to V on the system planar to act as a pull up.
SDA
I/O
IN
DDSPD
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from
SCL to V to act as a pull up on the system board.
SCL
DDSPD
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM
supply is operable from 1.7V to 3.6V.
VDDSPD
Supply
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all
register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low
level (the PLL will remain synchronized with the input clock)
RESET
IN
Par_In
Err_Out
TEST
IN
Parity bit for the Address and Control bus(“1”. Odd, “0”.Even)
Parity error found in the Address and Control bus
OUT
Used by memory bus analysis tools(unused on memory DIMMs)
Rev. 0.2 / Jul. 2007
3
1240pin Registered DDR2 SDRAM DIMMs
PIN DESCRIPTION
Pin
Pin Description
Clock Input,positive line
Clock input,negative line
Pin
Pin Description
On Die Termination Inputs
CK0
CK0
ODT[1:0]
VDDQ
DQs Power Supply
Data Input/Output
CKE0~CKE1
RAS
Clock Enable Input
Row Address Strobe
Column Address Strobe
Write Enable
DQ0~DQ63
CB0~CB7
DQS(0~8)
DQS(0~8)
Data check bits Input/Output
Data strobes
CAS
WE
Data strobes,negative line
S0,S1
Chip Select Input
DM(0~8),DQS(9~17) Data Maskes/Data strobes
A0~A9,A11~A13
A10/AP
Address input
DQS(9~17)
RFU
Data strobes,negative line
Reserved for Future Use
No Connect
Address input/Autoprecharge
SDRAM Bank Address
BA0, BA1, BA2
NC
Memory bus test tool(Not Connected and Not
Usable on DIMMs)
SCL
Serial Presence Detect(SPD) Clock Input
SPD Data Input/Output
TEST
SDA
VDD
VDDQ
VSS
Core Power
2
SA0~SA2
Par_In
I/O Power Supply
Ground
E PROM Address Inputs
Parity bit for the Address and Control bus
Parity error found on the Addre
Reset Enable
Err_Out
RESET
CB0~CB7
VREF
Reference Power Supply
Power Supply for SPD
VDDSPD
Data Strobe Inputs/Outputs
PIN LOCATION
Front Side
Back Side
1 pin
64 pin 65 pin
120 pin
184 pin
240 pin
185 pin
121 pin
Rev. 0.2 / Jul. 2007
4
1240pin Registered DDR2 SDRAM DIMMs
PIN ASSIGNMENT
Pin
Name
VREF
VSS
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Name
VSS
Pin
81
Name
DQ33
VSS
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Name
VSS
Pin
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Name
CB4
Pin
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Name
VSS
1
2
CB0
82
DQ4
CB5
DM4/DQS13
DQS13
VSS
3
DQ0
CB1
83
DQS4
DQS4
VSS
DQ5
VSS
4
DQ1
VSS
84
VSS
DM8,DQS17
DQS17
VSS
5
VSS
DQS8
DQS8
VSS
85
DM0/DQS9
DQS9
VSS
DQ38
6
DQS0
DQS0
VSS
86
DQ34
DQ35
VSS
DQ39
7
87
CB6
VSS
8
CB2
88
DQ6
CB7
DQ44
9
DQ2
CB3
89
DQ40
DQ41
VSS
DQ7
VSS
DQ45
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ3
VSS
90
VSS
VDDQ
NC,CKE1
VDD
VSS
VSS
VDDQ
CKE0
VDD
91
DQ12
DQ13
VSS
DM5/DQS14
DQS14
VSS
DQ8
92
DQS5
DQS5
VSS
DQ9
93
A15,NC
A14,NC
VDDQ
A12
VSS
BA2,NC
NC,Err_Out
VDDQ
A11
94
DM1/DQS10
DQS10
VSS
DQ46
DQS1
DQS1
VSS
95
DQ42
DQ43
VSS
DQ47
96
VSS
97
RFU
A9
DQ52
RESET
NC
A7
98
DQ48
DQ49
VSS
RFU
VDD
DQ53
VDD
99
VSS
A8
VSS
VSS
A5
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ14
DQ15
VSS
A6
RFU
DQ10
DQ11
VSS
A4
SA2
VDDQ
A3
RFU
VDDQ
A2
NC(TEST)
VSS
VSS
DQ20
DQ21
VSS
A1
DM6/DQS15
NC,DQS15
VSS
DQ16
DQ17
VSS
VDD
DQS6
DQS6
VSS
VDD
Key
Key
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VSS
VSS
DM2/DQS11
DQS11
VSS
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
CK0
CK0
DQ54
DQS2
DQS2
VSS
DQ50
DQ51
VSS
DQ55
VDD
VDD
A0
VSS
NC,Err_Out
VDD
DQ22
DQ23
VSS
DQ60
DQ18
DQ19
VSS
DQ56
DQ57
VSS
VDD
BA1
DQ61
A10/AP
BA0
VSS
DQ28
DQ29
VSS
VDDQ
RAS
DM7/DQS16
NC,DQS16
VSS
DQ24
DQ25
VSS
VDDQ
WE
DQS7
DQS7
VSS
S0
CAS
DM3/DQS12
DQS12
VSS
VDDQ
ODT0
A13,NC
VDD
VSS
DQ62
DQS3
DQS3
VSS
VDDQ
NC, S1
NC, ODT1
VDDQ
VSS
DQ58
DQ59
VSS
DQ63
VSS
DQ30
DQ31
VSS
VDDSPD
SA0
DQ26
DQ27
SDA
SCL
DQ36
DQ37
SA1
DQ32
NC= No Connect, RFU= Reserved for Future Use.
Notes:
1. RESET(Pin 18) is connected to both OE of PLL and Reset of register.
2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity.
3. The Test pin(Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(DIMMs)
Rev. 0.2 / Jul. 2007
5
1240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx72) : HYMP112[R,P]72AP8
/RS0
DQS4
/DQS4
DQS0
/DQS0
DM0,DQS9
/DQS9
DM4,DQS13
/DQS13
DM
RDQS /RDQS
I/O 0
NU
/CS
DQS /DQS
DQS /DQS
DQS /DQS
DM
RDQS /RDQS
I/O 0
NU
/CS
DQS /DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 1
I/O 2
D4
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DQS1
/DQS5
/DQS1
DM5,DQS14
DM1,DQS10
/DQS10
/DQS14
DM
RDQS /RDQS
I/O 0
NU
DM
RDQS /RDQS
I/O 0
NU
/CS
/CS
DQS /DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 1
I/O 2
I/O 1
I/O 2
D5
D1
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS6
/DQS6
DQS2
/DQS2
DM6,DQS15
/DQS15
DM2,DQS11
/DQS11
DM
RDQS /RDQS
I/O 0
NU
/CS
DM
RDQS /RDQS
I/O 0
NU
/CS
DQS /DQS
DQS /DQS
DQS /DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 1
I/O 2
I/O 1
I/O 2
D6
D2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS7
/DQS7
DQS0
/DQS0
DM7,DQS16
/DQS16
DM0,DQS9
/DQS12
DM
RDQS /RDQS
I/O 0
NU
DM
RDQS /RDQS
I/O 0
NU
/CS
/CS
DQS /DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 1
I/O 2
I/O 1
I/O 2
D3
D7
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS8
/DQS8
Serial PD
U0
DM8DQS17
/DQS17
VDD SPD
Serial PD
DO-D8
SDA
SCL
SCL
SDA
DM
RDQS /RDQS
I/O 0
NU
/CS
VDD
/
VDDQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
W
P
A0
A1
A2
I/O 1
I/O 2
VREF
DO-D8
DO-D8
SA0 SA1 SA2
D8
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
VSS
R
/CS0*
/RS0 to /CS ==> /CS: SDRAMs D0 to D8
E
G
I
PCK0 to PCK6, PCK8,PCK9 ==> CK: SDRAMs D0 toD8
/PCK0 to /PCK6, /PCK8, /PCK9 ==> /CK: SDRAMs D0 toD8
CK0
P
L
L
BA0 to BA2
A0 to A13
RBA0 to RBA2 ==> BA0 to BA2: SDRAMs D0 to D8
/RA0 to RA13 ==> A0 to A13: SDRAMs D0 to D8
/RRAS ==>/RAS: SDRAMs D0 to D8
/CK0
S
T
E
R
/RAS
PCK7 ==> CK: Register
/PCK7 ==> /CK: Register
/CAS
/RCAS ==>/CAS: SDRAMs D0 to D8
/RESET
OE
CKE0
RCKE0 ==> CKE: SDRAMs D0 to D8
/RWE ==> /WE: SDRAMs D0 to D8
/WE
ODT0
Notes :
1. Register values are 22 Ohms.
RODT0 ==> ODT0: SDRAMs D0 to D8
/RESET
PCK7
/RST
/PCK7
* : /S0 connects to D/CS and VDD connects to /CSR on register.
Rev. 0.2 / Jul. 2007
6
1240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
2GB(256Mbx72): HYMP125[R,P]72AP4
VSS
/RS0
/ DQS0
DQS0
/ DQS9
DQS9
Serial PD
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DQS / DQS /CS
I/O0
DQS / DQS /CS
I/O0
DQ0
DQ4
SDA
SCL
SCL
SDA
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
I/O1
D0
I/O2
I/O1
D9
I/O2
U0
W
P
A0
A1
A2
I/O3
I/O3
/ DQS1
/ DQS10
DQS10
SA0 SA1 SA2
DQS1
DQS / DQS /CS
I/O0
DQS / DQS /CS
I/O0
DQ8
DQ12
Serial
PD
VDD SPD
VDD /VDDQ
VREF
DQ9
DQ13
DQ14
DQ15
I/O1
D1
I/O2
I/O1
D10
I/O2
DQ10
DQ11
DO-D 17
I/O3
I/O3
/ DQS2
DQS2
/ DQS11
DO-D 17
DO-D 17
DQS11
DQS / DQS /CS
I/O0
I/O1
D2
I/O2
DQS / DQS /CS
I/O0
I/O1
D11
I/O2
VSS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
I/O3
I/O3
DQ23
/ DQS3
DQS3
/ DQS12
DQS12
DQS / DQS /CS
I/O0
DQS / DQS /CS
I/O0
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O1
D3
I/O2
I/O1
D12
I/O2
I/O3
I/O3
/ DQS0
DQS0
/ DQS13
DQS13
DQS / DQS /CS
I/O0
I/O1
D4
I/O2
DQS / DQS /CS
I/O0
I/O1
D13
I/O2
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O3
I/O3
/ DQS5
DQS5
/ DQS14
DQS14
DQS / DQS /CS
I/O0
I/O1
D5
I/O2
DQS / DQS /CS
I/O0
I/O1
D14
I/O2
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
I/O3
I/O3
DQ47
/ DQS6
DQS6
/ DQS15
DQS15
DQS / DQS /CS
I/O0
I/O1
D6
I/O2
DQS / DQS /CS
I/O0
I/O1
D15
I/O2
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
I/O3
I/O3
DQ51
/ DQS7
DQS7
/ DQS16
DQS16
DQS / DQS /CS
I/O0
I/O1
D7
I/O2
DQS / DQS /CS
I/O0
I/O1
D16
I/O2
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O3
I/O3
/ DQS8
DQS8
/ DQS17
DQS17
DQS / DQS /CS
I/O0
DQS / DQS /CS
I/O0
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O1
D8
I/O2
I/O1
D17
I/O2
I/O3
I/O3
CK0
PCK0 to PCK6, PCK8,PCK9
=
>
CK : SDRAMx D0-D17
P
L
L
R
E
G
I
S
T
E
R
/CS0*
/RS0 to /CS ==> /CS: SDRAMs D0 to D17
/CK0
/PCK0 to /PCK6, /PCK8,/PCK9
=
>
/CK : SDRAMx D0-D17
BA0 to BA2
A0 to A13
RBA0 to RBA2 ==> BA0 to BA2: SDRAMs D0 to D17
/RA0 to RA13 ==> A0 to A13: SDRAMs D0 to D17
/RRAS ==>/RAS: SDRAMs D0 to D17
PCK7
=
>
CK: Register
/RAS
/RESET
OE
/PCK7
= > /CK: Register
/CAS
/RCAS ==>/CAS: SDRAMs D0 to D17
CKE0
RCKE0 ==> CKE: SDRAMs D0 to D17
/RW E ==> /W E: SDRAMs D0 to D17
/W E
Notes:
1. Resistor values are 22 Ohms +/- 5%.
ODT0
RODT0 ==> ODT0: SDRAMs D0 to D17
/RESET
PCK7
/S0 connects to D/CS of Register1 and /CSR of Register2. /CSR of register and D/CS of register2 connects to VDD.
/RST
/PCK7
*
** /RESET,PCK7 connect to both Registers. Other signals connect to one of two Registers. /S1,CKE1 and ODT1 are NC.
Rev. 0.2 / Jul. 2007
7
1240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
4GB(512Mbx72) : HYMP351[R,P]72AMP4
VSS
/RS0
/RS1
Serial PD
U0
SDA
SCL
SCL
SDA
DQS9
/ DQS9
DQS0
/ DQS0
W
P
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
A0
A1
A2
I/O0
I/O1
I/O0
I/O1
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
D0,D18( DDP)
D9,D27( DDP)
I/O2
I/O3
I/O2
I/O3
SA0 SA1 SA2
DQS10
DQS1
/ DQS10
/ DQS1
DM /CS DQS / DQS
DM /CS DQS / DQS
Serial
PD
DM /CS DQS
DM /CS DQS
VDD SPD
VDD/VDDQ
VREF
I/O0
I/O1
I/O0
I/O1
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
D10,D28( DDP)
D1,D19( DDP)
I/O2
I/O3
I/O2
I/O3
DO to D35
DQ11
DO to D35
DO to D35
/RS0
/RS1
DQS11
/ DQS11
DQS2
VSS
/ DQS2
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
I/O0
I/O1
I/O0
I/O1
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
D11,D29( DDP)
D2,D20( DDP)
I/O2
I/O3
I/O2
I/O3
DQS12
DQS3
/ DQS12
/ DQS3
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS
DM /CS DQS
I/O0
I/O1
I/O0
I/O1
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
D12,D30( DDP)
D3,D21( DDP)
I/O2
I/O3
I/O2
I/O3
DQS17
DQS8
/ DQS17
/ DQS8
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS
DM /CS DQS
I/O0
I/O1
I/O0
I/O1
CB4
CB5
CB6
CB7
CB0
CB1
CB2
CB3
D17,D35( DDP)
D8,D26( DDP)
I/O2
I/O3
I/O2
I/O3
/RS0
/RS1
DQS13
DQS4
/ DQS13
/ DQS4
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
I/O0
I/O1
I/O0
I/O1
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
D13,D31( DDP)
D4,D2( DDP)
I/O2
I/O3
I/O2
I/O3
DQS14
DQS5
/ DQS14
/ DQS5
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS
DM /CS DQS
I/O0
I/O1
I/O0
I/O1
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
D14,D32( DDP)
D5,D23( DDP)
I/O2
I/O3
I/O2
I/O3
/RS0
/RS1
DQS15
DQS6
/ DQS15
/ DQS6
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS / DQS
I/O0
I/O1
I/O0
I/O1
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
D15,D33( DDP)
D6,D24( DDP)
I/O2
I/O3
I/O2
I/O3
DQS9
DQS7
/ DQS9
/ DQS7
DM /CS DQS / DQS
DM /CS DQS / DQS
DM /CS DQS
DM /CS DQS
I/O0
I/O1
I/O0
I/O1
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
D9,D34( DDP)
D7,D25( DDP)
I/O2
I/O3
I/O2
I/O3
1:2
R
E
G
I
S
T
E
R
/S0*
/S1*
/RS0 to /CS : SDRAMs D0 ? D17
/RS1 to /CS : SDRAMs D18 ? D35
CK0
PCK0 to PCK6, PCK8,PCK9 = > CK : SDRAMx D0-D35
P
L
L
BA0 ? BA2
/RBA0 ? RBA2 = > BA0 -BA2 : SDRAMs D0-D35
/RA0 ? RA12 = > A0 -A12 : SDRAMs D0-D35
/RRAS = > /RAS: SDRAMs D0-D35
/RCAS = > /CAS: SDRAMs D0-D35
/RWE = > /WE: SDRAMs D0-D35
/CK0
/PCK0 to /PCK6, /PCK8,/PCK9 = > /CK : SDRAMx D0-D35
A0?A13
/RAS
PCK7 = > CK: Register
/PCK7 = > /CK: Register
/CAS
/WE
/RESET
OE
CKE0
CKE1
ODT0
ODT1
RCKE0 = > CKE0: SDRAMs D0-D17
RCKE1 = > CKE1: SDRAMs D18-D35
RODT0 = > ODT0: SDRAMs D0-D17
RODT1 = > ODT1: SDRAMs D18-D35
Notes:
/ RST
/RESET**
1. Register values are 22 Ohms +/- 5%.
2. /RS0 and /RS1 alternate between the back and front sides of the DIMM
PCK7**
/PCK7**
*
/S0 connects to D/CS0 and /S1 connects to D/CS1 on both Registers.
** /RESET,PCK7 and /PCK7 connect to both Registers. Other signals connect to two Registers.
Rev. 0.2 / Jul. 2007
8
1240pin Registered DDR2 SDRAM DIMMs
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
V
Note
V
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-50 ~ +100
1
1
1
1
1
Voltage on V pin relative to Vss
DD
DD
V
V
Voltage on V
pin relative to Vss
DDQ
DDQ
V
V
V
IN, OUT
Voltage on any pin relative to Vss
Storage Temperature
o
T
C
STG
H
Storage Humidity(without condensation)
5 to 95
%
STG
Notes :
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device
functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con
ditions for extended periods may affect reliablility.
3. Up to 9850 ft.
OPERATING CONDITIONS
Parameter
Symbol
Rating
Units
Notes
o
T
0 ~ +55
C
OPR
DIMM Operating temperature(ambient)
DIMM Barometric Pressure(operating & storage)
BAR
105 to 69
0 ~+95
K Pascal
1
2
P
o
T
DRAM Component Case Temperature Range
C
CASE
Notes :
1. Up to 9850 ft.
2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to
tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.
DC OPERATING CONDITIONS (SSTL_1.8)
Parameter
Symbol
VDD
Min
1.7
Max
1.9
Unit
V
Note
Power Supply Voltage
VDDQ
VREF
VDDSPD
VTT
1.7
1.9
V
1
2
Input Reference Voltage
EEPROM Supply Voltage
0.49 x VDDQ
1.7
0.51 x VDDQ
3.6
V
V
VREF+0.04
V
3
VREF-0.04
Termination Voltage
Notes :
1. VDDQ must be less than or equal to VDD
.
2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc)
3. VTT of transmitting device must track VREF of receiving device.
Rev. 0.2 / Jul. 2007
9
1240pin Registered DDR2 SDRAM DIMMs
INPUT DC LOGIC LEVEL
Parameter
Input High Voltage
Input Low Voltage
Symbol
VIH(DC)
VIL(DC)
Min
VREF + 0.125
-0.30
Max
Unit
V
Note
VDDQ + 0.3
VREF - 0.125
V
INPUT AC LOGIC LEVEL
DDR2 400/533
DDR2 667/800
Notes
Parameter
Symbol
Unit
Min
Max
Min
Max
AC Input logic High
AC Input logic Low
VIH(AC)
VIL(AC)
V
V
VREF + 0.250
-
-
VREF + 0.200
-
-
V
REF - 0.250
VREF - 0.200
AC INPUT TEST CONDITIONS
Symbol
VREF
Condition
Input reference voltage
Value
Units
Notes
0.5 * VDDQ
V
1
1
VSWING(MAX)
SLEW
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
1.0
V
V/ns
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF max to VIH(ac) min for rising
edges and the range from VREF min to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and
VIH(ac) to VIL(ac) on the negative transitions.
Start of Rising Edge Input Timing
Start of Falling Edge Input Timing
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF
min
min
V
SWING(MAX)
max
max
IL(dc)
IL(ac)
SS
delta TF
delta TR
V
min - V
REF
V
-
V
max
IL(ac)
IH(ac)
REF
Falling Slew =
Rising Slew =
delta TR
delta TF
< Figure : AC Input Test Signal Waveform >
Rev. 0.2 / Jul. 2007
10
1240pin Registered DDR2 SDRAM DIMMs
Differential Input AC logic Level
Note
Symbol
Parameter
Min.
Max.
Units
1
VID (ac)
0.5
VDDQ + 0.6
V
ac differential input voltage
ac differential cross point voltage
2
VIX (ac)
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,
LDQS, UDQS and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as
CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The
minimum value is equal to VIH(DC) - VIL(DC).
V
DDQ
V
TR
Crossing point
V
ID
V
V
IX or OX
V
CP
V
SSQ
< Differential signal levels >
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal
(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).
The minimum value is equal to V IH(AC) - VIL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to
track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
DIFFERENTIAL AC OUTPUT PARAMETERS
Symbol
Parameter
Min.
Max.
Units
Note
VOX (ac)
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
ac differential cross point voltage
Notes:
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to
track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
Rev. 0.2 / Jul. 2007
11
1240pin Registered DDR2 SDRAM DIMMs
OUTPUT BUFFER LEVELS
OUTPUT AC TEST CONDITIONS
Symbol
Parameter
SSTL_18
Units
Notes
VOTR
Output Timing Measurement Reference Level
0.5 * VDDQ
V
1
Notes:
1. The VDDQ of the device under test is referenced.
OUTPUT DC CURRENT DRIVE
Symbol
IOH(dc)
IOL(dc)
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
SSTl_18
Units
Notes
- 13.4
13.4
mA
mA
1, 3, 4
2, 3, 4
Notes:
1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and
VDDQ - 280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device
drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an
SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point along a 21 ohm
load line to define a convenient driver current for measurement.
Rev. 0.2 / Jul. 2007
12
1240pin Registered DDR2 SDRAM DIMMs
PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz )
1GB : HYMP112[R,P]72AP8
Pin
Symbol
Min
Max
Unit
pF
pF
pF
pF
pF
CK0, CK0
CCK
CI1
7
8
8
8
6
11
12
12
12
9
CKE, ODT
CS
CI2
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
CI3
CIO
2GB : HYMP125[R,P]72AP4
Symbol
Min
Max
Unit
Pin
pF
pF
pF
pF
pF
CK0, CK0
CCK
CI1
7
8
11
12
15
12
9
CKE, ODT
CS
CI2
CI3
10
8
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
CIO
6
4GB : HYMP351[R,P]72AMP4
Symbol
Min
Max
Unit
Pin
pF
pF
pF
pF
pF
CK0, CK0
CCK
CI1
9.5
10.5
10.5
10.5
17
14
16
16
16
21
CKE, ODT
CS
CI2
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
CI3
CIO
Notes :
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
Rev. 0.2 / Jul. 2007
13
1240pin Registered DDR2 SDRAM DIMMs
IDD SPECIFICATIONS (TCASE : 0 to 95oC)
1GB, 128M x 72 Registered DIMM : HYMP112[R,P]72AP8
Symbol
IDD0
E3(DDR2 400@CL 3)
C4(DDR2 533@CL 4)
Y5(DDR2 667@CL 5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P(F)
IDD3P(S)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
1
IDD7
Notes : 1. IDD6 current alues are guaranted up to Tcase of 85℃ max.
2GB, 256M x 72 Registered DIMM : HYMP125[R,P]72AP4
Symbol
IDD0
E3(DDR2 400@CL 3)
C4(DDR2 533@CL 4)
Y5(DDR2 667@CL 5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P(F)
IDD3P(S)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
1
IDD7
Notes : 1. IDD6 current alues are guaranted up to Tcase of 85℃ max.
Rev. 0.2 / Jul. 2007
14
1240pin Registered DDR2 SDRAM DIMMs
4GB, 512M x 72 Registered DIMM : HYMP351[R,P]72AMP4
Symbol
IDD0
E3(DDR2 400@CL 3)
C4(DDR2 533@CL 4)
Y5(DDR2 667@CL 5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P(F)
IDD3P(S)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
1
IDD7
Notes : 1. IDD6 current values are guaranted up to Tcase of 85℃ max.
Rev. 0.2 / Jul. 2007
15
1240pin Registered DDR2 SDRAM DIMMs
IDD Measurement Conditions
Symbol
Conditions
Units
t
t
t
t
t
t
Operating one bank active-precharge current; CK = CK(IDD), RC = RC(IDD), RAS = RAS-
min(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus
inputs are SWITCHING
mA
IDD0
IDD1
Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;
t
t
t
t
t
t
t
t
CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD = RCD(IDD) ; CKE is HIGH, CS is HIGH
between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W
mA
t
t
Precharge power-down current ; All banks idle ; CK = CK(IDD) ; CKE is LOW ; Other control and address
mA
mA
mA
IDD2P
IDD2Q
IDD2N
bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge quiet standby current;All banks idle; CK = CK(IDD);CKE is HIGH, CS is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge standby current; All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
mA
mA
Active power-down current; All banks open; CK = CK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
IDD3P
IDD3N
IDD4W
IDD4R
t
t
t
t
t
t
Active standby current; All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
mA
mA
mA
t
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK =
t
t
t
t
t
CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
t
t
t
t
t
t
AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid
commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W
t
t
t
Burst refresh current; CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS is
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD5B
IDD6
mA
mA
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85℃ max.
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL
t
t
t
t
t
t
t
t
t
t
= RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD), RCD = 1* CK(IDD); CKE is
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pat-
tern is same as IDD4R; - Refer to the following page for detailed timing conditions
mA
IDD7
Notes:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combina-
tions of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
Rev. 0.2 / Jul. 2007
16
1240pin Registered DDR2 SDRAM DIMMs
Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed
Bin(CL-tRCD-tRP)
Parameter
CAS Latency
tRCD
DDR2-667 (Y5)
DDR2-533 (C4)
DDR2-400 (E3)
Unit
4-4-4
min
4
3-3-3
min
3
5-5-5
min
5
ns
ns
ns
ns
ns
15
15
15
tRP
15
15
15
tRC
60
55
60
tRAS
45
40
45
AC Timing Parameters by Speed Grade
DDR2-400
DDR2-533
Parameter
Symbol
Unit Note
Min
Max
600
Min
Max
500
450
0.55
0.55
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
Clock High Level Width
tAC
tDQSCK
tCH
-600
-500
0.45
0.45
-500
-500
0.45
0.45
ps
ns
500
0.55
0.55
CK
CK
Clock Low Level Width
tCL
min
(tCL,tCH)
min
(tCL,tCH)
Clock Half Period
tHP
-
-
ns
ps
System Clock Cycle Time
tCK
tDS
5000
275
150
0.6
8000
3750
225
100
0.6
8000
DQ and DM input setup time
-
-
-
-
-
-
ps
ps
1
1
DQ and DM input hold time
tDH
tIPW
Control & Address input Pulse Width for each input
tCK
DQ and DM input pulse witdth for each input pulse width for
each input
tDIPW
tHZ
0.35
-
-
0.35
-
-
tCK
ps
tAC max
tAC max
Data-out high-impedance window from CK, /CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC min
tAC max
tAC min
tAC max
ps
ps
2*tAC min
tAC max
2*tAC min
tAC max
-
350
-
300
ps
-
tHP - tQHS
WL - 0.25
0.35
450
-
tHP - tQHS
WL - 0.25
0.35
400
ps
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
DQS input high pulse width
tQH
-
-
ps
tDQSS
tDQSH
tDQSL
tDSS
WL + 0.25
WL + 0.25
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
-
-
DQS input low pulse width
0.35
-
0.35
-
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
0.2
-
0.2
-
tDSH
0.2
-
-
0.2
-
-
tMRD
2
2
tWPST
tWPRE
0.4
0.6
-
0.4
0.6
-
Write preamble
0.35
0.35
Rev. 0.2 / Jul. 2007
17
1240pin Registered DDR2 SDRAM DIMMs
- continued -
DDR2-400
DDR2-533
Parameter
Symbol
Unit Note
Min
Max
Min
Max
Address and control input setup time
Address and control input hold time
Read preamble
tIS
tIH
350
475
0.9
-
-
250
375
0.9
0.4
-
-
ps
ps
tRPRE
tRPST
tRFC
1.1
0.6
-
1.1
0.6
-
tCK
tCK
ns
Read postamble
0.4
Auto-Refresh to Active/Auto-Refresh command period
127.5
7.5
127.5
7.5
tRRD
tRRD
tFAW
tFAW
-
-
ns
Row Active to Row Active Delay for 1KB page size
Row Active to Row Active Delay for 2KB page size
Four Activate Window for 1KB page size
10
37.5
50
-
-
-
10
37.5
50
-
-
-
ns
ns
ns
Four Activate Window for 2KB page size
CAS to CAS command delay
tCCD
tWR
2
15
2
15
tCK
ns
Write recovery time
-
-
-
-
Auto Precharge Write Recovery + Precharge Time
tDAL
tWR+tRP
tWR+tRP
tCK
Write to Read Command Delay
tWTR
10
-
ns
7.5
-
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tRTP
tXSNR
tXSRD
tXP
7.5
7.5
ns
ns
tRFC + 10
tRFC + 10
200
2
-
-
200
2
-
-
tCK
tCK
tCK
Exit precharge power down to any non-read command
Exit active power down to read command
tXARD
2
2
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
6 - AL
3
6 - AL
3
tCK
tCK
CKE minimum pulse width
(high and low pulse width)
t
CKE
t
ODT turn-on delay
ODT turn-on
2
2
2
2
tCK
ns
AOND
t
tAC(min)
tAC(max)+1
tAC(min)
tAC(max)+1
AON
2tCK+tAC(m
ax)+1
2tCK+tAC(m
ax)+1
t
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAC(min)+2
2.5
tAC(min)+2
2.5
ns
tCK
ns
AONPD
t
2.5
2.5
AOFD
tAC(max)+
0.6
tAC(max)+
0.6
t
ODT turn-off
tAC(min)
tAC(min)
AOF
2.5tCK+tA
C(max)+1
2.5tCK+tA
C(max)+1
t
ODT turn-off (Power-Down mode)
tAC(min)+2
tAC(min)+2
ns
AOFPD
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
tCK
tCK
ns
3
8
0
3
8
0
12
12
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tDelay
ns
tIS+tCK+tIH
tIS+tCK+tIH
tREFI
tREFI
-
-
7.8
3.9
-
-
7.8
3.9
us
us
2
3
Average periodic Refresh Interval
Note :
1. For details and notes, please refer to the relevant HYNIX component datasheet HY5PS1G[4/8]31AFP.
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Rev. 0.2 / Jul. 2007
18
1240pin Registered DDR2 SDRAM DIMMs
DDR2-667
DDR2-800
Symbol
Unit
Note
Parameter
min
-450
-400
0.45
0.45
max
min
-400
-350
0.45
0.45
max
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
tDQSCK
tCH
+450
+400
0.55
+400
+350
0.55
ps
ps
tCK
tCK
CK low-level width
tCL
0.55
0.55
min(tCL,
tCH)
min(tCL,
tCH)
CK half period
tHP
tCK
tDS
-
8000
-
-
ps
ps
ps
Clock cycle time, CL=x
3000
2500
DQ and DM input setup time
(differential strobe)
100
50
-
-
-
1
1
DQ and DM input hold time
(differential strobe)
tDH
175
0.6
-
-
125
0.6
ps
Control & Address input pulse width for each
input
tIPW
tCK
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
tDIPW
tHZ
0.35
-
-
0.35
-
-
tCK
ps
tAC max
tAC max
tAC max
tAC max
tAC max
tAC max
tLZ(DQS)
tLZ(DQ)
tAC min
2*tAC min
tAC min
2*tAC min
ps
ps
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
-
240
-
200
ps
DQ hold skew factor
tQHS
tQH
-
340
-
-
300
-
ps
ps
DQ/DQS output hold time from DQS
tHP - tQHS
tHP - tQHS
First DQS latching transition to associated
clock edge
tDQSS
- 0.25
+ 0.25
- 0.25
+ 0.25
tCK
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
-
-
0.35
0.35
0.2
0.2
2
-
-
tCK
tCK
tCK
tCK
tCK
tCK
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
-
-
tDSH
-
-
tMRD
tWPST
-
-
0.4
0.6
0.4
0.6
Auto-Refresh to Active/Auto-Refresh command
period
tRFC
tRRD
127.5
7.5
-
-
127.5
7.5
-
-
ns
ns
Row Active to Row Active Delay for 1KB page size
Write preamble
tWPRE
tIS
0.35
200
275
0.9
0.4
45
-
-
0.35
175
250
0.9
0.4
45
-
-
tCK
ps
Address and control input setup time
Address and control input hold time
Read preamble
tIH
-
-
ps
tRPRE
tRPST
tRAS
1.1
0.6
70000
1.1
0.6
70000
tCK
tCK
ns
Read postamble
Activate to precharge command
Active to active command period for 1KB
page size products
tRRD
7.5
-
7.5
-
ns
tRRD
10
-
10
-
ns
Row Active to Row Active Delay for 2KB page size
Four Active Window for 1KB page size
products
tFAW
37.5
-
35
-
ns
Four Activate Window for 2KB page size
tFAW
50
-
50
-
ns
Rev. 0.2 / Jul. 2007
19
1240pin Registered DDR2 SDRAM DIMMs
- continued -
DDR2-667
DDR2-800
max
Symbol
Unit Note
Parameter
min
2
max
min
2
CAS to CAS command delay
Write recovery time
tCCD
tWR
tCK
ns
15
-
-
-
15
-
-
-
Auto precharge write recovery + precharge
time
tDAL
WR+tRP
WR+tRP
tCK
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tWTR
tRTP
7.5
7.5
7.5
7.5
ns
ns
tXSNR
tXSRD
tRFC + 10
200
tRFC + 10
200
ns
-
-
-
-
tCK
Exit precharge power down to any non-read
command
tXP
2
2
2
2
tCK
tCK
tCK
Exit active power down to read command
tXARD
tXARDS
Exit active power down to read command
(Slow exit, Lower power)
7 - AL
8 - AL
CKE minimum pulse width
(high and low pulse width)
tCKE
tAOND
tAON
3
2
3
2
tCK
tCK
ns
ODT turn-on delay
2
2
tAC(max)
+0.7
tAC(max)
+0.7
ODT turn-on
tAC(min)
tAC(min)
2tCK+
tAC(max)+1
tAC(min)
+2
2tCK+
tAC(max)+1
tAONPD
tAOFD
tAOF
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAC(min)+2
2.5
ns
tCK
ns
2.5
2.5
2.5
tAC(max)+
0.6
tAC(max)
+0.6
ODT turn-off
tAC(min)
tAC(min)
tAC(min)
+2
2.5tCK+
tAC(max)+1
tAC(min)
+2
2.5tCK+
tAC(max)+1
tAOFPD
ODT turn-off (Power-Down mode)
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
12
12
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tIS+tCK
+tIH
tDelay
tIS+tCK+tIH
ns
tREFI
tREFI
-
-
7.8
3.9
-
-
7.8
3.9
us
us
2
3
Average periodic Refresh Interval
Notes :
1. For details and notes, please refer to the relevant HYNIX component datasheet HY5PS1G[4/8]31AFP.
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Rev. 0.2 / Jul. 2007
20
1240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
128Mx72 (1 rank) - HYMP112[R,P]72AP8
Front
133.35
Side
2. 7 max
(Front)
4.0±0.1
30.0
PLL
Detail-A
Detail-B
1. 27 ±0.10
5.175
5.175
63.0
55.0
5.0
Back
3.0
3.0
Detail of Contacts A
Detail of Contacts B
2.50
1.0
±0.05
0.8
1.50 ±0.10
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.2 / Jul. 2007
21
1240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
256Mx72 (1 rank) - HYMP125[R,P]72AP4
Front
133.35
Side
4.0 max
4.0±0.1
30.0
PLL
Detail-A
Detail-B
5.175
1.27 ± 0.10
5.175
63.0
55.0
5.0
Back
3.0
3.0
Detail of Contacts A
Detail of Contacts B
2.50
1.0
±0.05
0.8
1.50 ±0.10
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.2 / Jul. 2007
22
1240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
512Mx72 (2 rank) - HYMP351[R,P]72AMP4
Front
133.35
Side
4. 0 max
4.0±0.1
30.0
PLL
Detail-A
Detail-B
5.175
5.175
1. 27 ±0.10
63.0
55.0
5.0
Back
3.0
3.0
Detail of Contacts A
Detail of Contacts B
2.50
1.0
±0.05
0.8
1.50 ±0.10
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.2 / Jul. 2007
23
1240pin Registered DDR2 SDRAM DIMMs
REVISION HISTORY
Revision
History
Date
Remark
0.1
Initial data sheet released
Mar. 2006
Jul. 2007
0.2
Discarded Speed C4 for Non-parity and corrected typos
Rev. 0.2 / Jul. 2007
24
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