IC-MH8_11_技术文档

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 1/25

FEATURES

APPLICATIONS

♦ Digital angular sensor

technology, 0–360°

♦ Incremental angular encoder

♦ Absolute angular encoder

♦ Brushless motors

♦ Real-time system for rotation speed up to 120,000 rpm

♦ Integrated Hall sensors with automatic offset compensation

♦ 4x sensor arrangement for fault-tolerant adjustment

♦ Amplitude control for optimum operating point

♦ Interpolator with 4096 angular increments/resolution better

than 0.1°

♦ Motor feedback

♦ Rotational speed control

♦ Programmable resolution, hysteresis, edge spacing, zero

position and rotating direction

♦ Incremental output of sensor position up to 8 MHz edge rate

♦ RS422-compatible AB encoder signals with index Z

♦ UVW commutation signals for eight pole EC motor applications

♦ Serial interface for data output and conﬁguration

♦ SSI-compatible output mode

PACKAGES

♦ Integrated ZAP diodes for module setup and OEM data,

programmable via serial interface

♦ Signal error (e.g. magnet loss) can also be read out via serial

interface

♦ Analogue sine and cosine differential signals

♦ Extended temperature range from -40 to +125 °C

QFN28 5 x 5 mm²

BLOCK DIAGRAM

Sine / cosine outputs

+ 5V

VPA

+ 5V

VPD

PCOUT NCOUT

PSOUT NSOUT

Binary interpolation factors

1, 2, 4, ... 256, 512, 1024

A

B

Z

A

B

Z

B

S

N

PTE

Test

CONVERSION

LOGIC

TEST

HALL SENSOR

SINE-TO-DIG

RS422

Two, four and eight pole

commutating signals

0°

U

2

U

V

SIN²+ COS

AMPLITUDE

120°

Loss of magnet,

frequency error

NERR

V

W

240°

PHASE

SHIFT

CORRECTION

W

ERROR MONITOR

AMPL CONTROL

SINE-TO-COM

INCR INTERFACE

Analog output signals

PSOUT

NSOUT

0x00

iC-MH8

MA

SLO

SLI

0x0F

0x10

16 Byte ZROM

0.5 V_pp

0x1F

0x77

0x7F

Programming

Voltage

ZAP CONTROL

ZAPROM

VNA2

VZAP

PCOUT

NCOUT

Data,

Programming

SERIAL

INTERFACE

RAM

BIAS/VREF

0°

180°

Angular position

360°

VNA1

VND

C061010-2

α

http://www.ichaus.com

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 2/25

DESCRIPTION

The iC-MH8 12-bit angular encoder is a position sen- The commutation interface with the signals U, V and

sor with integrated Hall sensors for scanning a per- W provides 120° phase-shifted signals for block com-

manent magnet. The signal conditioning unit gen- mutation of eight pole EC motors. The zero point of

erates constant-amplitude sine and cosine voltages the commutation signals is freely deﬁnable in incre-

that can be used for angle calculation. The resolu- ments of 5.625° over 360°.

tion can be programmed up to a maximum of 4,096

angular increments per rotation.

Sine and cosine signals are externally availabe to fa-

cilitate adjustement.

The integrated serial interface also enables the posi-

tion data to be read out to several networked sensors. The RS422-compatible outputs of the incremental

And the integrated memory can be written embedded interface and the commutation interface are pro-

in the data protocol.

grammable in the output current and the slew rate.

The incremental interface with the pins A, B and Z In conjunction with a rotating permanent magnet, the

supplies quadrature signals with an edge rate of up iC-MH8 module forms a one-chip encoder. The en-

to 8 MHz. Interpolation can be carried out with maxi- tire conﬁguration can be stored in the internal pa-

mum resolution at a speed of 120,000 rpm. The po- rameter ROM with zapping diodes. The integrated

sition of the index pulse Z is adjustable.

programming algorithm assumes writing of the ROM

structure.

PACKAGES QFN28 5 x5 mm² to JEDEC MO-220-VHHD-1

PIN CONFIGURATION QFN28 5 x 5mm²

PIN FUNCTIONS

No. Name Function

3 VPA

4 VNA1

5 SLI

6 MA

7 SLO

+5 V Supply Voltage (analog)

Ground (analog)

Serial Interface, Data Input

Serial Interface, Clock Input

Serial Interface, Data Output

not connected

PSOUT NSOUT

nc nc

W

28 27 26 25 24 23 22

8,9 nc

21

20

19

18

17

16

15

PTE

NERR

VPA

VNA1

SLI

1

2

3

4

5

6

7

V

10 PCOUT Positive Cosine Output

11 NCOUT Negative Cosine Output

12 VZAP

13 VNA2

14 nc

15 A

16 B

17 Z

18 VND

19 VPD

20 U

21 V

22 W

U

VPD

VND

Z

Zener Zapping Programming Voltage

Ground (analog)

not connected

Incremental A (+NU)

Incremental B (+NV)

Index Z (+NW)

MH8

MA

B

SLO

A

8

9

10 11 12 13 14

nc

C061010-1

Ground (digital)

nc nc

+5 V Supply Voltage (digital)

Commutation U (+NA)

Commutation V (+NB)

Commutation W (+NZ)

not connected

PCOUT VZAP

NCOUT

VNA2

23,24 nc

25 NSOUT Negative Sine Output

26 PSOUT Positive Sine Output

PIN FUNCTIONS

No. Name Function

27,28 nc

TP

not connected

Thermal-Pad

1 PTE Test Enable Pin

2 NERR Error output(active low)

The Thermal Pad is to be connected to common ground (VNA1, VNA2, VND) on the PCB. Orientation of the

logo ( MH8 CODE ...) is subject to alteration.

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 3/25

PACKAGE DIMENSIONS

RECOMMENDED PCB-FOOTPRINT

4.70

3.15

SIDE

0.50

0.30

TOP

5

BOTTOM

3.15

0.50

0.25

drb_qfn28-2_pack_1, 10:1

All dimensions given in mm.

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 4/25

ABSOLUTE MAXIMUM RATINGS

Beyond these values damage may occur; device operation is not guaranteed.

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Max.

G001 V()

Supply voltages at VPA, VPD

Zapping voltage

-0.3

6

8

6

V

G002 V(VZAP)

G003 V()

Voltages at A, B, Z, U, V, W, MA, SLO,

SLI, NERR, PTE

G004 I()

G005 I()

G006 I()

G007 I()

G008 Vd()

G009 Ts

G010 Tj

Current in VPA

-10

-20

20

200

100

10

mA

kV

Current in VPD

Current in A, B, Z, U, V, W

Current in MA, SLO, SLI, NERR, PTE

ESD-voltage, all pins

Storage temperature

Chip temperature

-100

-10

HBM 100 pF discharged over 1.5 kΩ

2

-40

150

135

°C

THERMAL DATA

Operating conditions: VPA, VPD = 5 V ±10 %

Item Symbol

No.

Parameter

Conditions

Unit

Min. Typ. Max.

-40 125

T01 Ta

Operating Ambient Temperature Range

Thermal Resistance Chip to Ambient

°C

T02 Rthja

surface mounted to PCB, thermal pad linked

40

K/W

to cooling area of approx. 2 cm²

All voltages are referenced to ground unless otherwise stated.

All currents ﬂowing into the device pins are positive; all currents ﬂowing out of the device pins are negative.

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 5/25

ELECTRICAL CHARACTERISTICS

Operating conditions:

VPA, VPD = 5 V ±10 %, VNA=VND, Tj = -40...125 °C, IBM adjusted to 200 µA , 4 mm NdFeB magnet, unless otherwise noted

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

General

001 V(VPA),

V(VPD)

Permissible Supply Voltage

4.5

5.5

V

002 I(VPA)

003 I(VPD)

004 I(VPD)

005 Vc()hi

Supply Current in VPA

Supply Current in VPD

3

5

12

27

20

1.5

mA

V

PRM = ’0’, without Load

PRM = ’1’, without Load

Vc()hi = V() − VPD, I() = 1 mA

2

Clamp Voltage hi at MA, SLI,

SLO, PTE, NERR

0.4

006 Vc()lo

Clamp Voltage lo at MA, SLI,

SLO, PTE, NERR

I() = -1 mA

-1.5

20

-0.3

V

Hall Sensors and Signal Conditioning

101 Hext

Operating Magnetic Field

Strength

at surface of chip

100

2

kA/m

kHz

102 fmag

Operating Magnetic Field

Frequency

120 000 rpm

Rotating Speed of Magnet

103 dsens

104 xdis

Diameter of Hall Sensor Array

2

mm

Max. Magnet Axis Displacement

vs. Center of Hall Sensor Array

0.2

+3

mm

105 xpac

Chip Placement Error vs. Pack- with QFN28

age

-0.2

-3

106 φpac

Chip Tilt Error vs. Package

with QFN28

Deg

mm

107 hpac

Sensor-to-Package-Surface Dis- with QFN28

tance

0.4

108 Vos

109 Vos

110 Vopt

Trimming range of output offset VOSS or VOSC = 0x7F

voltage

-55

mV

Vpp

Trimming range of output offset VOSS or VOSC = 0x3F

voltage

55

Optimal differential output voltage Vopt = Vpp(PSIN) − Vpp(NSIN), ENAC = ’0’,

4

see Fig. 6

111

112

Vratio

Amplitude Ratio

Vratio = Vpp(PSIN) / Vpp(PCOS), GCC = 0x3F

1.09

Vratio = Vpp(PSIN) / Vpp(PCOS), GCC = 0x40

0.92

4.8

Signal Level Control

201 Vpp

Differential Peak-to-Peak Output Vpp = Vpk(Px) − Vpk(Nx), ENAC = ’1’, see Fig.

3.2

Vpp

Amplitude

6

202 ton

Controller Settling Time

to ±10% of ﬁnal amplitude

300

2.8

µs

203 Vt()lo

MINERR Amplitude Error Thresh- see 201

old

1.0

4.8

Vpp

204 Vt()hi

MAXERR Amplitude Error

Threshold

see 201

5.8

Vpp

Bandgap Reference

401 Vbg

402 Vref

Bandgap Reference Voltage

1.18

45

1.25

50

1.32

55

V

Reference Voltage

Bias Current

%VPA

403

Iibm

CIBM = 0x0

CIBM = 0xF

Bias Current adjusted

-100

µA

-370

-220

-200

4.0

-180

4.3

404 VPDon

405 VPDoff

406 VPDhys

Turn-on Threshold VPD, System V(VPD) − V(VND), increasing voltage

3.65

V

on

Turn-off Threshold VPD, System V(VPD) − V(VND), decreasing voltage

3

3.5

3.8

reset

Hysteresis System on/reset

0.3

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 6/25

ELECTRICAL CHARACTERISTICS

Operating conditions:

VPA, VPD = 5 V ±10 %, VNA=VND, Tj = -40...125 °C, IBM adjusted to 200 µA , 4 mm NdFeB magnet, unless otherwise noted

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

407 Vosr

Reference voltage offset com-

pensation

475

500

525

mV

Clock Generation

501 f()sys

System Clock

Bias Current adjusted

0.85

13.5

1.0

16

1.2

18

MHz

502 f()sdc

Sinus/Digital-Converter Clock

Sin/Digital Converter

601 RESsdc

Sinus/Digital-Converter Resolu-

12

Bit

tion

602 AAabs

Absolute Angular Accuracy

Relative Angular Accuracy

Vpp() = 4 V, adjusted

-0.35

0.35

Deg

%

603

604

AArel

f()ab

with reference to an output periode at A, B.

CFGRES=0x2, ENF=1, PRM=0, HCLH=1,

GAING=0x0, Vpp(SIN/COS) = 4 Vpp.

see Fig. 17

± 10

Output frequency at A, B

CFGMTD = 0x0, CFGRES=0x0

CFGMTD = 0x7, CFGRES=0x0

2.0

0.25

MHz

Serial Interface, Digital Outputs MA, SLO, SLI

701 Vs(SLO)hi Saturation Voltage High

V(SLO) = V(VPD) − V(),

0.4

V

I(SLO) = 4 mA

702 Vs(SLO)lo Saturation Voltage Low

703 Isc(SLO)hi Short-Circuit Current High

704 Isc(SLO)lo Short-Circuit Current Low

I(SLO) = 4 mA to VND

V(SLO) = V(VND), 25°C

V(SLO) = V(VPD), 25°C

CL = 50 pF

V

mA

ns

-90

-50

50

80

60

2

705 tr(SLO)

706 tf(SLO)

707 Vt()hi

Rise Time SLO

Fall Time SLO

CL = 50 pF

ns

Threshold Voltage High: MA, SLI

Threshold Voltage Low: MA, SLI

Threshold Hysteresis: MA, SLI

Pull-Down Current: MA, SLI

V

708 Vt()lo

0.8

140

6

V

709 Vt()hys

710 Ipd()

250

30

mV

µA

MHz

V() = 0...VPD − 1 V

60

-6

711 Ipu(MA)

712 f(MA)

-60

-30

10

Zapping and Test

801 Vt()hi

Threshold Voltage High VZAP,

PTE

with reference to VND

Vt()hys = Vt()hi − Vt()lo

2

V

802 Vt()lo

Threshold Voltage Low VZAP,

PTE

0.8

803 Vt()hys

Hysteresis

140

0.7

250

7.0

mV

V

804 Vt()nozap Threshold Voltage Nozap VZAP V() = V(VZAP) − V(VPA), V(VPA) = 5 V ±5 %,

at chip temperature 27 °C

805 Vt()zap

Threshold Voltage Zap VZAP

V() = V(VZAP) − V(VPA), V(VPA) = 5 V ±5 %,

1.2

V

at chip temperature 27 °C

806 V()zap

807 V()zpd

808 V()uzpd

Zapping voltage

PROG = ’1’

6.9

7.1

2

V

Diode voltage, zapped

Diode voltage, unzapped

3

V

809 Rpd()VZAP Pull-Down Resistor at VZAP

30

55

kΩ

NERR Output

901 Vt()hi

902 Vs()lo

903 Vt()lo

904 Vt()hys

905 Ipu()

Input Threshold Voltage High

Saturation Voltage Low

Input Threshold Voltage Low

Input Hysteresis

with reference to VND

I() = 4 mA , with reference to VND

with reference to VND

Vt()hys = Vt()hi − Vt()lo

V(NERR) = 0...VPD − 1 V

V(NERR) = V(VPD), Tj = 25°C

CL = 50 pF

2

V

0.4

0.8

140

-800

V

250

-300

50

mV

µA

mA

ns

Pull-up Current Source

Short circuit current Lo

Decay time

-80

80

60

906 Isc()lo

907 tf()hilo

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 7/25

ELECTRICAL CHARACTERISTICS

Operating conditions:

VPA, VPD = 5 V ±10 %, VNA=VND, Tj = -40...125 °C, IBM adjusted to 200 µA , 4 mm NdFeB magnet, unless otherwise noted

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

Digital Line Driver Outputs

P01

Vs()hi

Saturation Voltage hi

Vs() = VPD − V();

CfgDR(1:0) = 00, I() = -4 mA

CfgDR(1:0) = 01, I() = -50 mA

CfgDR(1:0) = 10, I() = -50 mA

CfgDR(1:0) = 11, I() = -20 mA

200

700

400

mV

P02

P03

Vs()lo

Isc()hi

Saturation Voltage lo

CfgDR(1:0) = 00, I() = -4 mA

CfgDR(1:0) = 01, I() = -50 mA

CfgDR(1:0) = 10, I() = -50 mA

CfgDR(1:0) = 11, I() = -20 mA

200

700

400

mV

Short-Circuit Current hi

V() = 0 V;

CfgDR(1:0) = 00

CfgDR(1:0) = 01

CfgDR(1:0) = 10

CfgDR(1:0) = 11

-12

-125

-60

-4

mA

-50

-20

P04

Isc()lo

Short-Circuit Current lo

V() = VPD;

CfgDR(1:0) = 00

CfgDR(1:0) = 01

CfgDR(1:0) = 10

CfgDR(1:0) = 11

4

12

125

60

mA

50

20

P05 Ilk()tri

Leakage Current Tristate

Rise-Time lo to hi at Q

TRIHL(1:0) = 11

-100

100

µA

P06

tr()

RL = 100 Ω to VND;

CfgDR(1:0) = 00

CfgDR(1:0) = 01

CfgDR(1:0) = 10

CfgDR(1:0) = 11

5

50

5

20

350

40

ns

P07

tf()

Fall-Time hi to lo at Q

RL = 100 Ω to VND;

CfgDR(1:0) = 00

CfgDR(1:0) = 01

CfgDR(1:0) = 10

CfgDR(1:0) = 11

5

50

5

20

350

40

ns

Analog Outputs PSOUT, NSOUT, PCOUT, NCOUT

Q01 Vpk()

Q02 Vos()

Q03 fc()

Max. Output Signal Amplitude

Output Offset Voltage

Rl = 50 Ω vs. VPD / 2, see Fig.

200

300

50

mV

µV

±200

Output Cut-off Frequency

Output Short-circuit Current

Cl = 250 pF

10

kHz

mA

Q04 Isc()hi,lo

pin shorten to VPD or VND

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 8/25

OPERATING REQUIREMENTS: Serial Interface

Operating conditions: VPA, VPD = 5 V ±10 %, Ta = -40...125 °C, IBM calibrated to 200 µA;

Logic levels referenced to VND: lo = 0...0.45 V, hi = 2.4 V...VPD

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Max.

SSI Protocol (ENSSI = 1)

I001 T_MAS

I002 t_MASh

I003 t_MASl

Permissible Clock Period

t_outdetermined by CFGTOS

250

25

2x t_out

t_out

ns

Clock Signal Hi Level Duration

Clock Signal Lo Level Duration

25

t_out

Figure 1: I/O Interface timing with SSI protocol

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 9/25

Registers

OVERVIEW

Adr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Hall Signal Conditioning

0x00

0x01

0x02

0x03

0x04

z

GAING(1:0)

ENAC

GAINF(5:0)

GCC(6:0)

VOSS(6:0)

VOSC(6:0)

1

PRM

HCLH

DPU

DAO

CFGTOB

CIBM(3:0)

RS422 Driver

0x05 ENSSI

Sine/Digital Converter

z

CFGPROT

CFGO(1:0)

TRIHL(1:0)

CFGDR(1:0)

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

z

ENF

CFGMTD(2:0)

CFGDIR

CFGRES(3:0)

CFGZPOS(7:0)

CFGSU

CfgCOM(7:0)

CFGHYS(1:0)

CFGPOLE(1:0)

CFGAB(1:0)

-

Test settings

0x0E

0x0F

p

TEST(7:0)

ENHC

res.

PROGZAP

ZAP diodes (read only)

0x10

..

ZAP diodes for addresses 0x00..0x0C and 0x7D..0x7F

0x1F

not used

0x20

..

’invalid adresses’

0x41

Proﬁle identiﬁcation (read only)

0x42

Proﬁle - 0x2C

0x43

Proﬁle - 0x0

Data length DLEN

not used

0x44

..

’invalid adress’

0x75

Status messages (read only; messages will be set back during reading)

0x76

0x77

GAIN

PROGERR

ERRSDATA

ERRAMIN

ERRAMAX

ERREXT

res.

PROGOK

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 10/25

OVERVIEW

Adr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Identiﬁcation (0x78 bis 0x7B read-only)

0x78

0x79

0x7A

0x7B

0x7C

Device ID - 0x4D (’M’)

Device ID - 0x48 (’H’)

Revision - 0x38 (’8’)

Revision - 0x00 (”)

-

CFGTOS

0x7D

0x7E

0x7F

z

Manufacturer Revision - 0x00

Manufacturer ID - 0x00

z: Register value programmable by zapping

p: Register value write protected; can only be changed while V(VZAP)> Vt()hi

Table 5: Register layout

Hall signal processing . . . . . . . . . . . . . . . . . . . . Page 12 Sine/digital converter . . . . . . . . . . . . . . . . . . . . . Page 18

GAING:

GAINF:

Hall signal ampliﬁcation range

Hall signal ampliﬁcation (1–20, log.

scale)

Ampliﬁcation calibration cosine

Activation of amplitude control

Offset calibration sine

Offset calibration cosine

Energy-saving mode

Calibration of bias current

Deactivation of NERR pull-up

Activation of high Hall clock pulse

Activation of noise ﬁlter

CFGRES:

CFGZPOS:

CFGAB:

CFGPOLE:

CFGSU:

CFGMTD:

CFGDIR:

CFGHYS:

CFGCOM:

Resolution of sine digital converter

Zero point for position

Conﬁguration of incremental output

No. of poles for commutation signals

Behavior during start-up

GCC:

ENAC:

VOSS:

VOSC:

PRM:

CIBM:

DPU

HCLH

ENF

DAO:

Frequency at AB

Rotating direction reversal

Hysteresis sine/digital converter

Zero point for commutation

Test

TEST:

ENHC:

Test mode

Disable Analog Outputs

Enable High Current during ZAP-

Diode Read (iC-MH82 and later)

Activation of programming routine

RS422 driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 21

PROGZAP:

CFGDR:

TRIHL:

CFGO:

CFGPROT:

ENSSI:

Driver property

Tristate high-side/low-side driver

Conﬁguration of output mode

Write/read protection memory

Activation of SSI mode

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 11/25

Sensor principle

In conjunction with a rotating permanent magnet, the

iC-MH8 module can be used to create a complete en-

coder system. A diametrically magnetized, cylindri-

cal permanent magnet made of neodymium iron boron

(NdFeB) or samarium cobalt (SmCo) generates op-

timum sensor signals. The diameter of the magnet

should be in the range of 3 to 6 mm.

The iC-MH8 has four Hall sensors adapted for angle

determination and to convert the magnetic ﬁeld into

a measurable Hall voltage. Only the z-component of

the magnetic ﬁeld is evaluated, whereby the ﬁeld lines

pass through two opposing Hall sensors in the oppo-

site direction. Figure 2 shows an example of ﬁeld vec-

tors. The arrangement of the Hall sensors is selected

so that the mounting of the magnets relative to iC-MH8

is extremely tolerant. Two Hall sensors combined pro-

vide a differential Hall signal. When the magnet is ro-

tated around the longitudinal axis, sine and cosine out-

put voltages are produced which can be used to deter-

mine angles.

z

y

+B_z

B

x

-B_z

C151107-1

Figure 2: Sensor principle

Position of the Hall sensors and the analog sensor signal

The Hall sensors are placed in the center of the QFN28 In order to calculate the angle position of a diametri-

package at 90° to one another and arranged in a circle cally polarized magnet placed above the device a dif-

with a diameter of 2 mm as shown in Figure 3.

ference in signal is formed between opposite pairs of

Hall sensors, resulting in the sine being V_SIN= V_PSIN

-

V_NSINand the cosine V_COS= V_PCOS- V_NCOS. The zero

angle position of the magnet is marked by the resulting

cosine voltage value being at a maximum and the sine

voltage value at zero.

Pin 1 Mark

28 27 26 25 24 23 22

21

20

19

18

17

16

15

1

2

PSIN

PCOS

3

4

5

6

7

This is the case when the south pole of the magnet is

exactly above the PCOS sensor and the north pole is

above sensor NCOS, as shown in Figure 4. Sensors

PSIN and NSIN are placed along the pole boundary so

that neither generate a Hall signal.

NCOS

NSIN

(top view)

8

9

10 11 12 13 14

C040907-2

Figure 3: Position of the Hall sensors

When a magnetic south pole comes close to the sur-

face of the package the resulting magnetic ﬁeld has a When the magnet is rotated counterclockwise the

positive component in the +z direction (i.e. from the top poles then also cover the PSIN and NSIN sensors, re-

of the package) and the individual Hall sensors each sulting in the sine and cosine signals shown in Figure

generate their own positive signal voltage.

5 being produced.

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 12/25

28 27 26 25 24 23 22

(top view)

21

20

19

18

17

16

15

21

20

19

18

17

16

15

1

2

3

4

5

6

7

1

2

3

4

5

6

7

S

28 27 26 25 24 23 22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

N

a > 0

8

9

10 11 12 13 14

8

9

10 11 12 13 14

a = 0

0

V_COS= V_PCOS- V_NCOS

V_SIN= V_PSIN- V_NSIN

+2V

-90°

90°

180°

270°

360°

a

-2V

8

9

10 11 12 13 14

C041007-3

C040907-1

Figure 5: Pattern of the analog sensor signals with

the angle of rotation

Figure 4: Zero position of the magnet

Hall Signal Processing

The iC-MH8 module has a signal calibration function The second ampliﬁer stage can be varied in an addi-

that can compensate for the signal and adjustment er- tional range. With the amplitude control (ENAC = ’0’)

rors. The Hall signals are ampliﬁed in two steps. First, deactivated, the ampliﬁcation in the GAINF register is

the range of the ﬁeld strength within which the Hall sen- used. With the amplitude control (ENAC = ’1’) acti-

sor is operated must be roughly selected. The ﬁrst vated, the GAINF register bits have no effect.

ampliﬁer stage can be programmed in the following

ranges:

GCC(6:0)

0x00

0x01

...

Addr. 0x01; bit 6:0

1,000

1,0015

exp(

GAING(1:0)

Addr. 0x00; bit 7:6

ln(20)

2048

00

01

10

11

5-fold

· GCC)

10-fold

15-fold

20-fold

0x3F

0x40

...

1,0965

0,9106

ln(20)

exp(− ₂₀₄₈· (128 − GCC))

0x7F

0,9985

Table 6: Range selection for Hall signal ampliﬁcation

Table 8: Ampliﬁcation calibration cosine

The operating range can be speciﬁed in advance in

accordance with the temperature coefﬁcient and the

magnet distance. The integrated amplitude control can

correct the signal amplitude between 1 and 20 via an-

other ampliﬁcation factor. Should the control reach the

range limits, a different signal ampliﬁcation must be se-

lected via GAING.

The GCC register is used to correct the sensitivity of

the sine channel in relation to the cosine channel. The

cosine amplitude can be corrected within a range of

approximately ±10%.

ENAC

Addr. 0x01; bit 7

amplitude control deactivated

amplitude control active

0

1

GAINF(5:0)

0x00

...

Addr. 0x00; bit 5:0

1,000

1,048

Table 9: Activation of amplitude control

0x02

0x03

...

exp(^ln(20)· GAINF − 2)

64

The integrated amplitude control can be activated with

the ENAC bit. In this case the differential signal am-

plitude is adjusted to 4 Vss and the values of GAINF

have no effect here.

0x3F

17,38

Table 7: Hall signal ampliﬁcation

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 13/25

PRM

Addr. 0x03; bit 7

PSIN−NSIN

0

1

Energy-saving mode deactivated

Energy-saving mode active

4Vss

PCOS−NCOS

Table 11: Energy-saving mode

Figure 6: Deﬁnition of differential amplitude

In the energy-saving mode the current consumption of

the Hall sensors can be quartered. This also reduces

the maximum rotating frequency by a factor of 4.

After switch-on the ampliﬁcation is increased until the

setpoint amplitude is reached. The ampliﬁcation is

automatically corrected in case of a change in the

input amplitude by increasing the distance between

the magnet and the sensor, in case of a change in

the supply voltage or a temperature change. The

sine signals are therefore always converted into high-

resolution quadrature signals at the optimum ampli-

tude.

CIBM(3:0)

Addr. 0x04; bit 3:0

0x0

...

-40 %

...

0x8

0x9

...

0 %

+5 %

...

0xF

+35 %

VOSS(6:0)

VOSC(6:0)

0x00

Addr. 0x02; bit 6:0

Addr. 0x03; bit 6:0

Table 12: Calibration of bias current

0 mV

1 mV

...

0x01

...

The bias current is factory calibrated to 200 µA. The

calibration can be veriﬁed in test mode (TEST = 0x43)

by measuring the current from Pin B to Pin VNA.

0x3F

63 mV

0 mV

-1 mV

...

0x40

0x41

...

HCLH

Addr. 0x04; bit 7

250 kHz

500 kHz

0x7F

-63 mV

0

1

Table 10: Offset calibration for sine and cosine

Table 13: Activation of high Hall clock pulse

Should there be an offset in the sine or cosine signal

that, among other things, can also be caused by an

inexactly adjusted magnet, then this offset can be cor- The switching-current hall sensors can be operated at

rected by the VOSS and VOSC registers. The output two frequencies. At 500 kHz the sine has twice the

voltage can be shifted by ±63 mV in each case to com- number of support points. This setting is of interest at

pensate for the offset.

high speeds above 30,000 rpm.

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 14/25

Test modes for signal calibration

For signal calibration iC-MH8 has several test settings

which make internal reference quantities and the am-

pliﬁed Hall voltages of the individual sensors accessi-

ble at external pins A, B, Z and U for measurement pur-

poses. This enables the settings of the offset (VOSS,

VOSC), gain (GAING, GAINF) and amplitude ratio of

the cosine to the sine signal (GCC) to be directly ob-

served on the oscilloscope.

iC-MH8

PSIN

A

B

Z

HPSP

HPSN

HNSP

HNSN

V_PSIN

B

V_NSIN

U

NSIN

HALL SENSORS

Test mode can be triggered by connecting pin VZAP

to VPD and programming the TEST register (address

0x0E). The individual test modes are listed in the fol-

lowing table:

VNA

C021107-1acr

Test Mode: Analog SIN

Figure 7: Output signals of the sine Hall sensors in

test mode Analog SIN

Output signals in test mode

Mode

TEST Pin A Pin B Pin Z Pin U

0x00

0x20 HPSP HPSN HNSP HNSN

Normal

Analog SIN

A

B

Z

U

iC-MH8

PCOS

A

B

Z

HPCP

HPCN

HNCP

HNCN

Analog COS 0x21 HPCP HPCN HNCP HNCN

Analog OUT 0x22 PSIN NSIN PCOS NCOS

V_PCOS

B

Analog REF 0x43 VREF IBM

Digital CLK 0xC0 CLKD

VBG

VOSR

B

V_NCOS

U

NCOS

HALL SENSORS

Table 14: Test modes and available output signals

VNA

C021107-2acr

Test Mode: Analog COS

The output voltages are provided as differential sig-

nals with an average voltage of 2.5 V. The gain is de-

termined by register values GAING and GAINF and

should be set so that output amplitudes from the sine

and cosine signals of about 1 V are visible.

Figure 8: Output signals of the cosine Hall sensors

in test mode Analog COS

Test modes Analog SIN and Analog COS

iC-MH8

In these test modes it is possible to measure the sig-

nals from the individual Hall sensors independent of

one another. The name of the signal is derived from

the sensor name and position. HPSP, for example,

is the (ampliﬁed) Hall voltage of sensor PSIN at the

positive signal path; similarly, HNCN is the Hall voltage

of sensor NCOS at the negative signal path. The effec-

tive Hall voltage is accrued from the differential voltage

between the positive and negative signal paths of the

respective sensor.

PSIN

PCOS

A

B

Z

PSIN

V_SIN

B

NSIN

PCOS

NCOS

B

V_COS

U

NCOS

NSIN

HALL SENSORS

VNA

C021107-3acr

Test Mode: Analog OUT

Test mode Analog OUT

Figure 9: Differential sine and cosine signals in test

mode Analog OUT

In this test mode the sensor signals are available at

the outputs as they would be when present internally

for further processing on the interpolator. The interpo-

lation accuracy which can be obtained is determined Test mode Analog REF

by the quality of signals V_sinand V_cosand can be inﬂu- In this mode various internal reference voltages are

enced in this particular test mode by the calibration of provided. VREF is equivalent to half the supply voltage

the offset, gain and amplitude ratio.

(typically 2.5 V) and is used as a reference voltage for

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 15/25

Test Mode: Analog REF

the Hall sensor signals. VBG is the internal bandgap

reference (1.24 V), with VOSR (0.5 V) used to gener-

ate the range of the offset settings. Bias current IBM

determines the internal current setting of the analog

circuitry. In order to compensate for variations in this

current and thus discrepancies in the characteristics

of the individual iC-MH8 devices (due to ﬂuctuations in

production, for example), this can be set within a range

of -40% to +35% using register parameter CIBM. The

nominal value of 200 µA is measured as a short-circuit

current at pin B to ground.

iC-MH8

A

B

Z

VREF

~ 2.5 V

IBM

VBG

VOSR

~ 1.24 V

~ 0.5 V

U

~ 200 µA

VNA

C021107-4acr

Test mode Digital CLK

If, due to external circuitry, it is not possible to mea-

sure IBM directly, by way of an alternative clock signal

CLKD at pin A can be calibrated to a nominal 1 MHz

in this test mode via register value CIBM.

Figure 10: Setting bias current IBM in test mode

Analog REF

Calibration procedure

The calibration procedure described in the following

applies to the optional setting of the internal analog

sine and cosine signals and the mechanical adjust-

ment of the magnet and iC-MH8 in relation to one an-

other.

V_sin

+2 V

BIAS SETTING

a

The BIAS setting compensates for possible manufac-

turing tolerances in the iC-MH8 devices. A magnetic

ﬁeld does not need to be present for this setting which

can thus be made either prior to or during the assem-

bly of magnet and iC-MH8.

-2 V

+2 V

V_cos

If the optional setup process is not used, register CIBM

should be set to an average value of 0x8 (which is

equivalent to a change of 0%). As described in the

previous section, by altering the value in register CIBM

in test mode Analog REF current IBM is set to 200 µA

or, alternatively, in test mode Digital CLK signal CLKD

is set to 1 MHz.

-2 V

C141107-1

Figure 11: Ideal Lissajous curve

CALIBRATION USING ANALOG SIGNALS

In test mode Analog OUT as shown in Figure 5 the in-

ternal signals which are transmitted to the sine/digital

converter can be tapped with high impedance. With

a rotating magnet it is then possible to portray the dif-

ferential signals V_SINand V_COSas an x-y graph (Lis-

sajous curve) with the help of an oscilloscope. In an

ideal setup the sine and cosine analog values describe

a perfect circle as a Lissajous curve, as illustrated by

Figure 11.

MECHANICAL ADJUSTMENT

iC-MH8 can be adjusted in relation to the magnet in

test modes Analog SIN and Analog COS, in which the

Hall signals of the individual Hall sensors can be ob-

served while the magnet rotates.

In test mode Analog SIN the output signals of the sine

Hall sensors which are diagonally opposite one an-

other are visible at pins A, B, Z and U. iC-MH8 and

the magnet are then adjusted in such a way that dif- At room temperature and with the amplitude control

ferential signals V_PSINand V_NSINhave the same am- switched off (ENAC = 0) a rough GAING setting is se-

plitude and a phase shift of 180°. The same applies lected so that at an average ﬁne gain of GAINF = 0x20

to test mode Analog COS, where differential signals (a gain factor of ca. 4.5) the Hall signal amplitudes are

V_PCOSand V_NCOSare calibrated in the same manner.

as close to 1 V as possible. The amplitude can then

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 16/25

V_sin

be set more accurately by varying GAINF. Variations in

the gain factor, as shown in Figure 12, have no effect

on the Lissajous curve, enabling the angle information

for the interpolator to be maintained.

VOSS

a

V_sin

GAING

GAINF

V_cos

a

C141107-3

V_cos

Figure 13: Effect of the sine offset setting

V_sin

VOSC

C141107-2

Figure 12: Effect of gain settings GAING and

GAINF

a

Deviations of the observed Lissajous curve from the

ideal circle can be corrected by varying the ampli-

tude offset (register VOSS, VOSC) and amplitude ratio

(register GCC). Changes in these parameters are de-

scribed in the following ﬁgures 13 to 15. Each of these

settings has a different effect on the interpolated angle

value. A change in the sine offset thus has a maximum

effect on the angle value at 0° and 180°, with no al-

terations whatsoever taking place at angles of 90° and

270°. When varying the cosine offset exactly the oppo-

site can be achieved as these angle pairs can be set

independent of one another. Setting the cosine/sine

amplitude ratio does not change these angles (0°, 90°,

180° and 270°); however, in-between values of 45°,

135°, 225° and 315° can still be inﬂuenced by this pa-

rameter.

V_cos

C141107-4

Figure 14: Effect of the cosine offset setting

V_sin

GCC

a

Once calibration has been carried out a signal such as

the one illustrated in Figure 11 should be available.

V_cos

In the ﬁnal stage of the process the amplitude control

can be switched back on (ENAC =1) to enable devi-

ations in the signal amplitude caused by variations in

the magnetic ﬁeld due to changes in distance and tem-

perature to be automatically controlled.

C141107-5

Figure 15: Effect of the amplitude ratio

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 17/25

CALIBRATION USING INCREMENTAL SIGNALS

distance of the rising edge (equivalent to angle posi-

If test mode cannot be used, signals can also be cali- tions of 0° and 180°) at signal A should be exactly half

brated using the incremental signals or the values read a period (PER). Should the edges deviate from this in

out serially. In order to achieve a clear relationship be- distance, the offset of the sine channel can be adjusted

tween the calibration parameters which have an effect using VOSS. The same applies to the falling edges of

on the analog sensor signals and the digital sensor val- the A signal which should also have a distance of half

ues derived from these, the position of the zero pulse a period; deviations can be calibrated using the offset

should be set to ZPOS = 0x0 and the rotating direction of cosine parameter VOSC. With parameter GCC the

should be set to CFGDIR=0, so that the digital signal distance between the neighboring ﬂanks of signals A

starting point matches that of the analog signals.

and B can then be adjusted to the exact value of an

eighth of a cycle (a 45° angle distance).

At an incremental resolution of 8 edges per revolu-

tion (CFGRES = 0x1) those angle values can be dis-

played at which calibration parameters VOSS, VOSC

and GCC demonstrate their greatest effect. When ro-

tating the magnet at a constant angular speed the in-

cremental signals shown in Figure 16 are achieved,

with which the individual edges ideally succeed one

another at a temporal distance of an eighth of a cy-

cle (a 45° angle distance). Alternatively, the angle po-

sition of the magnet can also be determined using a

reference encoder, rendering an even rotational action

unnecessary and allowing calibration to be performed

using the available set angle values .

A

B

Z

VOSS

VOSC

GCC

PER

The various possible effects of parameters VOSS,

VOSC and GCC on the ﬂank position of incremental

signals A and B are shown in Figure 16. Ideally, the

Figure 16: Calibration using incremental signals

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 18/25

Sine/Digital Converter

100%

The iC-MH8 module integrates a high-resolution

sine/digital converter. In the highest output resolution

with an interpolation factor of 1024, 4096 edges per

rotation are generated and 4096 angular steps can be

differentiated. Even in the highest resolution, the abso-

lute position can be calculated in real time at the max-

imum speed.

A

B

Z

This absolute position is used to generate quadrature

signals (ABZ) and commutation signals (UVW). The

zero point of the quadrature signals and the commu-

tation signals can be set seperately. This enables the

commutation at other angles based on the index track

Z.

Figure 17: ABZ signals and relative accuracy

The incremental signals can be inverted again inde-

pendently of the output drivers. As a result, other

phase angles of A and B relative to the index pulse Z

can be generated. The standard is A and B high level

for the zero point, i.e. Z is equal to high.

The resolution of the incremental output signals is pro-

grammed with CFGRES.

The value of the 12-bit sine-digital converter is avail-

able in full resolution in the ’Extended SSI-Mode’ and

in a resolution according to CFGRES in the ’SSI-

Mode’.

Figure 17 shows the position of the incremental sig-

nals around the zero point. The relative accuracy of

the edges to each other at a resolution setting of 10

bit is better than 10%. This means that, based on a

period at A or B, the edge occurs in a window between

40% and 60%.

CFGRES(2:0)

Addr. 0x06; bit 3:0

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

1024

512

256

128

64

32

16

8

CFGHYS(1:0)

Addr. 0x08; bit 7:6

0x0

0x1

0x2

0x3

0,17°

4

0,35°

0,7°

2

1

1,4°

Table 15: Programming interpolation factor

Table 17: Programming angular hysteresis

After the resolution is changed, a module reset is trig-

gered internally and the absolute position is recalcu-

lated.

With rotating direction reversal, an angular hysteresis

prevents multiple switching of the incremental signals

at the reversing point. The angular hysteresis corre-

sponds to a slip which exists between the two rotating

directions. However, if a switching point is approached

from the same direction, then the edge is always gen-

erated at the same position on the output. The fol-

lowing ﬁgure shows the generated quadrature signals

for a resolution of 360 edges per rotation (interpolation

factor 90) and a set angular hysteresis of 1.4°.

CFGAB(1:0)

Addr. 0x08; bit 1:0

A and B not inverted

0x0

0x1

0x2

0x3

B inverted, A normal

A inverted, B normal

A and B inverted

Table 16: Inversion of AB signals

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 19/25

10°

0°

It should be noted then, however, that the maximum

rotation speed is reduced.

−10°

A

B

CFGDIR

Addr. 0x08; bit 5

Rotating direction CCW

Rotating direction CW

Z

0

1

0°

1.4°

0°

Figure 18: Quadrature signals for rotating direction

reversal (hysteresis 1.4°)

Table 20: Rotating direction reversal

At the reversal point at +10°, ﬁrst the corresponding

edge is generated at A. As soon as an angle of 1.4°

has been exceeded in the other direction in accor-

dance with the hysteresis, the return edge is generated

at A again ﬁrst. This means that all edges are shifted

by the same value in the rotating direction.

The rotating direction can easily be changed with

the bit CFGDIR. When the setting is CCW (counter-

clockwise, CFGDIR = ’0’) the resulting angular position

values will increase when rotation of the magnet is per-

formed as shown in ﬁgure 5. To obtain increasing an-

gular position values in the CW (clockwise) direction,

CFGDIR then has to be set to ’1’.

CFGZPOS(7:0)

Addr. 0x07; bit 7:0

0x0

0x1

0x2

...

0°

1,4°

2,8°

The internal analoge sine and cosine signal which are

available in test mode are not affected by the setting of

CFGDIR. They will always appear as shown in ﬁgure

5.

360

₂₅₆·CFGZPOS

0xFF

358,6°

Table 18: Programming AB zero position

The position of the index pulse Z can be set in 1.4°

steps. An 8-bit register is provided for this purpose,

which can shift the Z-pulse once over 360°.

CFGSU

Addr. 0x08; bit 4

0

1

ABZ output "111" during startup

AB instantly counting to actual position

CFGMTD(2:0)

Addr. 0x06; bit 6:4

Table 21: Conﬁguration of output startup

0

Minimum edge spacing 125 ns at IPO 1024 (max.

2 MHz at A)

1

2

Minimum edge spacing 250 ns at IPO 1024

Minimum edge spacing 500 ns at IPO 1024 (max.

500 kHz at A)

Depending on the application, a counter cannot bear

generated pulses while the module is being switched

on. When the supply voltage is being connected, ﬁrst

the current position is determined. During this phase,

the quadrature outputs are constantly set to "111". In

the setting CFGSU = ’1’, edges are generated at the

output until the absolute position is reached. This en-

ables a detection of the absolute position with the in-

cremental interface.

3

4

5

6

7

Minimum edge spacing 1 µs at IPO 1024

Minimum edge spacing 2 µs at IPO 1024

Minimum edge spacing 4 µs at IPO 1024

Minimum edge spacing 8 µs at IPO 1024

Minimum edge spacing 16 µs at IPO 1024

Table 19: Minimum edge spacing

The CFGMTD register deﬁnes the time in which two

consecutive position events can be output at the high-

est resolution. The default is a maximum output fre- The converter for the generation of the commutation

quency of 500 kHz on A. This means that at the high- signals can be conﬁgured for two, four and eight-pole

est resolution, speeds of 30,000 rpms can still be cor- motors. Three rectangular signals each with a phase

rectly shown. In the setting with an edge spacing of shift of 120° are generated. With two-pole commuta-

125 ns, the edges can be generated even at the high- tion, the sequence repeats once per rotation. With a

est revolution and the maximum speed. However, the four-pole setting, the commutation sequence is gener-

counter connected to the module must be able to cor- ated twice per rotation. With a eight-pole setting, the

rectly process all edges in this case. The settings commutation sequence is generated four times per ro-

with 2 µs, and 8 µs can be used for slower counters. tation.

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 20/25

CFGPOLE(1:0)

Addr. 0x8; bit 3,2

2 pole commutation

4 pole commutation

8 pole commutation

PSIN

00

01

1-

PCOS

U

V

W

Table 22: Commutation

U

V

W

The zero position of the commutation, i.e. the rising

edge of the track U, can be set as desired over a rota-

tion. Here 256 possible positions are available.

U

V

W

CFGCOM(7:0)

Addr. 0x09; bit 7:0

0x00

0x01

...

0°

-1,4°

360

-

₂₅₆· CFGCOM

Figure 19: UVW signals for different settings of

CFGPOLE

Table 23: Commutation

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 21/25

Output Drivers

PSIN

Six RS422-compatible output drivers are available,

which can be conﬁgured for the incremental signals

and commutation signals. The following table on the

CFGO register bits provides an overview of the possi-

ble settings.

PCOS

A

B

Z

U

V

W

CFGO(1:0)

Addr. 0x05; bit 5:4

00

01

10

11

Incrementral Diff ABZ (U=NA, V=NB, W=NZ)

Incr ABZ + Comm UVW

Figure 20: ABZ differential incremental signals

Commutation Diff UVW (A=NU, B=NV, Z=NW)

Incr. ABZ + AB4 (U=A4, V=B4, W=0)

PSIN

PCOS

Table 24: Conﬁguration of output drivers

A

B

Z

U

V

W

In the differential incremental mode (CFGO = ’00’, Fig-

ure 20), quadrature signals are available on the Pins

A, B and Z. The respective inverted quadrature sig-

nals are available on the pins U, V and W. As a result,

lines can be connected directly to the module. Another

conﬁguration of the incremental signals is speciﬁed in

the section "Sine/Digital Converter".

Figure 21: ABZ and UVW single ended signals

PSIN

PCOS

A

B

Z

U

V

W

With CFGO = ’01’ (Figure 21) the ABZ incremental sig-

nals and the UVW commutation signals are available

on the six pins. As long as the current angular posi-

tion is not yet available during the start-up phase, all

commutation signals are at the low level.

Figure 22: UVW differential commutation signals

With CFGO = ’10’, the third mode (Figure 22) is avail-

able for transferring the commutation signals via a dif-

ferential line. The non-inverted signals are on the pins

U, V and W, the inverted signals on A, B and Z.

PSIN

PCOS

A

B

Z

U

V

W

The ABZ quadrature signals with an adjustable higher

resolution and quadrature signals with one period per

rotation are available in the fourth mode (Figure 23).

Four segments can be differentiated with the pins U

and V. This information can be used for an external

period counter which counts the number of scanned

complete rotations.

Figure 23: ABZ incremental signals / period counter

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 22/25

The property of the RS422 driver of the connected line able a high transmission rate. A lower slew rate is of-

can be adjusted in the CFGDR register.

fered by the setting CFGDR = ’10’, which is excellent

for longer lines in an electromagnetically sensitive en-

vironment. Use of the setting CFGDR = ’11’ is advis-

able at medium transmission rates with a limited driver

capability.

CFGDR(1:0)

Addr. 0x05; bit 1:0

10 MHz 4 mA (default)

00

01

10

11

10 MHz 60 mA

300 kHz 60 mA

3 MHz 20 mA

TRIHL

00

Addr. 0x05; bit 3:2

Push Pull Output Stage

Highside Driver

Table 25: Driver property

01

10

Lowside Driver

11

Tristate

Signals with the highest frequency can be transmitted

in the setting CFGDR = ’00’. The driver capability is

at least 4 mA, however it is not designed for a 100 Ω

line. This mode is ideal for connection to a digital in-

Table 26: Tristate Register

put on the same assembly. With the setting CFGDR = The drivers consist of a push-pull stage in each case

’01’ the same transmission speed is available and the with low-side and high-side drivers which can each be

driver power is sufﬁcient for the connection of a line activated individually. As a result, open-drain outputs

over a short distance. Steep edges on the output en- with an external pull-up resistor can also be realized.

Serial Interface

The serial interface is used to read out the absolute tailed description of the protocol, see separate inter-

position and to parameterize the module. For a de- face speciﬁcation.

CDM

MA

SLI

Ack Start CDS D11 D10

D0

nE nW CRC5CRC4

Data Range

CRC0 Stop

Timeout

SLO

Figure 24: Serial Interface Protocol

Serial Interface

Protocol

Mode C

The sensor sends a ﬁxed cycle-start sequence con-

taining the Acknowledge-, Start and Control-Bit fol-

lowed by the binary 12 bit sensor data. The low-active

error bit nE a ’0’ indicates an error which can be fur-

ther identiﬁed by reading the status register 0x77. The

following bit nW is always at ’1’ state. Following the

6 CRC bits the data of the next sensors, if available,

are presented. Otherwise, the master stops generat-

ing clock pulse on the MA line an the sensor runs into

a timeout, indicating the end of communication.

Cycle start sequence

Lenght of sensor data

CRC Polynom

Ack/Start/CDS

12 Bit + ERR + WARN

0b1000011

CRC Mode

inverted

Multi Cycle Data

max. Data Rate

not available

10 MHz

Table 27: Interface Protocol

ENSSI

Addr. 0x05; bit 7

Extended SSI-Mode

SSI-Mode

0

1

Table 28: Activation of SSI mode

The extended SSI-Mode is active if V(VZAP) = V()ZAP

or Bit ENSSI is 0. The extended SSI-Mode must be

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 23/25

forced by applying V(VZAP) = V()ZAP before chang- With the proﬁle ID, the data format can be requested

ing the value of Bit ENSSI to avoid an aborted register for the following sensor data cycles in the module. A

communication.

read operation at address 0x42 results in 0x2C, with is

the equivalent to 12-bit single-cycle data.

In the SSI mode the absolute position is output with 13

bits according to the SSI standard. (The data is trans-

mitted as Gray code with trailing zeros.)

The status register provides information on the status

of the module. There are 5 different errors that can

be signaled. Following unsuccessful programming of

the zapping diodes, the bit PROGERR is set. If an

attempt is made to read the current position via the se-

rial interface during the start-up phase, an error is sig-

naled with ERRSDATA, as the actual position is not yet

known. The ERRAMAX bit is output to signal that the

amplitude is too high, while the ERRAMIN bit signals

an amplitude which is too low, caused, for example, by

too great a distance to the magnet. If the NERR pin

is pulled against VND outside the module, this error is

also signaled via the serial interface. The ERREXT bit

is then equal to ’1’. The error bits are reset again after

the status register is read out at the address 0x77. The

error bit in the data word is then also read in the next

cycle as ’0’.

Figure 25: SSI protocol, data GRAY-coded

The register range 0x00 to 0x0F is equivalent to the

settings with which the IC can be parameterized. The

settings directly affect the corresponding switching

parts. The range 0x10 to 0x1F is read-only and reﬂects

the contents of the integrated zapping diodes. Follow-

ing programming the data can be veriﬁed via these ad-

dresses. After the supply voltage is connected, the

contents of the zapping diodes are copied to the RAM

area 0x00 to 0x0F. Then the settings can be overwrit-

ten via the serial interface. Overwriting is not possible

if the CFGPROT bit is set.

CFGTOS

CFGTOB

Timeout

16 µs

2 µs

0

1

x

0

1

2 µs

Errors in the module are signaled via the error mes-

sage output NERR. This open-drain output signals an

error if the output is pulled against VND. If the er-

ror condition no longer exists, then the pin is released

again after a waiting time of approximately 1 ms. If the

integrated pull-up resistor is deactivated with DPU =

’1’, then an external resistor must be provided. With

DPU = ’0’ it brings the pin up to the high level again.

Table 30: Timeout for sensor data

The timeout can be programmed to a shorter value

with the CFGTOS bit. However, this setting is reset

to the default value 16 µs again following a reset. The

timeout can be permanently programmed for faster

data transmission with the CFGTOB register via a zap-

ping diode. Resetting to slower data transmission is

then not possible.

DPU

Addr. 0x04; bit 6

Pull-up activated

0

1

Pull-up deactive

The registers 0x7D to 0x7F are reserved for the man-

ufacturer and can be provided with an ID so that the

manufacturer can identify its modules

Table 29: Activation of NERR pull-up

OTP Programming

CFGPROT

Addr. 0x05; bit 6

ENHC

Addr. 0x0f; bit 7

Default setting

0

1

no protection

0

1

write/read protection

ZAP diode testing: Use a higher current for reading

the ZAP diodes memory (0x10-0x1f)

Table 31: Write/read protection of conﬁguration

Table 32: Enable High Current

With CFGPROT = ’0’, the registers at the addresses

0x00 to 0x0F and 0x78 to 0x7F are readable and write-

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 24/25

able. The addresses 0x10 to 0x1F and 0x77 are read-

only. With CFGPROT = ’1’, all registers except the ad-

dresses 0x7B and 0x7C are write-protected; the ad-

dresses 0x77 to 0x7F are readable, while all others

are read-protected.

100 nF

Programming

Board

+ 5V

VPD VPA

VZAP

+ 7V

MA

SLI

iC-MH8

Serial

Interface

An internal programming algorithm for the ZAP diodes

is started by setting the bit PROGZAP. This process

can only be successful if the voltage at VZAP is greater

than 6.5 V and the test register TEST (2:0) is not set.

Following programming, the register is reset internally

again. In the process, the bit PROGOK is set in the

status register (address 0x77) when programming is

successful, and the bit PROGERR if it is not.

SLO

10 µF

100 nF

0V

VND VNA1 VNA2

Figure 26: Recommended setup for external program-

ming. A short low impedance path (shown in

light red) must be provided directly from pin

VZAP to pins VNA1, VNA2.

The ZAP memory can be tested by reading the regis-

ter range 0x10-0x1f. This test can be done with with a

higher readout current (Bit ENHC=1) to simulate dete-

riorated working conditions.

For reliable ROM writing, a low impedance connection

path as shown in Figure 26 must be established for the

VZAP blocking capacitor (about 100 nF) between pin

VZAP and pins VNA1, VNA2 to ensure stable VZAP

voltage during programming. A further capacitor of

10 µF which may be located externally (e.g. on the pro-

gramming board) is recommended for additional block-

ing purpose.

Figure 27: Example PCB layout showing low impedance

connection of capacitors to supply voltages

(VPA, VPD, VZAP) and common ground

A typical PCB layout may look like the one shown in

Figure 27.

iC-Haus expressly reserves the right to change its products and/or speciﬁcations. An info letter gives details as to any amendments and additions made to the

relevant current speciﬁcations on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by

email.

Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source.

iC-Haus does not warrant the accuracy, completeness or timeliness of the speciﬁcation and does not assume liability for any errors or omissions in these

materials.

The data speciﬁed is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, ﬁtness

for a particular purpose or of any other nature are made hereunder with respect to information/speciﬁcation or the products to which information refers and no

guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of

the product.

iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade

mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.

As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and speciﬁcally designed for appropriate use in technical

applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of

use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued

annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in

Hanover (Hannover-Messe).

We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations

of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can

be put to.

iC-MH8

12 BIT ANGULAR HALL ENCODER

Rev A0.9, Page 25/25

ORDERING INFORMATION

Type

Package

QFN28

Order Designation

iC-MH8 QFN28-5x5

iC-MH8

For technical support, information about prices and terms of delivery please contact:

iC-Haus GmbH

Tel.: +49 (61 35) 92 92-0

Am Kuemmerling 18

D-55294 Bodenheim

GERMANY

Fax: +49 (61 35) 92 92-192

Web: http://www.ichaus.com

E-Mail: sales@ichaus.com

Appointed local distributors: http://www.ichaus.com/sales_partners


型号：	IC-MH8_11
厂家：	IC-HAUS GMBH
描述：	12 BIT ANGULAR HALL ENCODER 12几分棱角霍尔编码器编码器
文件：	总25页 (文件大小：703K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IC-MH8_11 [ICHAUS]

相关型号：

IC-MHA

IC-MHEVALMH1D

IC-MHQFN28

IC-ML

IC-MLEVALML1D

IC-MLTSSOP20

IC-MN

IC-MNEVALMN1D

IC-MNQFN48

IC-MP

IC-MPDFN10

IC-MPEVALMP1D