IC-MNEVALMN1D_技术文档

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 1/59

FEATURES

APPLICATIONS

♦ Multi-channel sine-to-digital

converter

♦ Optical and magnetic position

sensors

♦ Singleturn and multiturn

absolute encoders

♦ Linear scales for absolute

position

♦ 3 chan. simultaneous sampling 13 bit sine-to-digital conversion

♦ Differential and single-ended PGA inputs to 200 kHz

♦ Input adaptation to current or voltage signals

♦ Adjustable signal conditioning for offset, amplitude and phase

♦ Input signal stabilization by LED or MR bridge supply tracking

(via controlled 50 mA and 2 x 10 mA highside sources)

♦ 2 or 3 track nonius calculation of up to 25 bit singleturn position

♦ Data update within 7 µs supported by ﬂash period counting

♦ Serial 2-wire interface to multiturn sensors (BiSS, SSI, 2-bit)

♦ Fast, serial I/O interface with fail-safe RS422 transceiver

(SSI to 4 MHz, BiSS C to 10 MHz)

♦ Resolver systems

PACKAGES

♦ Differential 1 Vpp sin/cos outputs to 100 Ω, short-circuit-proof

♦ Position preset function, selectable up/down code direction

♦ Signal and system monitoring with conﬁgurable error/warning

messaging and diagnosis memory

♦ Device setup via I/O interface (BiSS) or serial EEPROM

♦ Reverse-polarity-proof and tolerant against faulty output wiring

♦ Power-good switch protecting the peripheral circuitry

♦ Single 5 V supply, operation from -40 to +95 (+110) °C

QFN48 7x7

BLOCK DIAGRAM

http://www.ichaus.com

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 2/59

DESCRIPTION

Encoder device iC-MN is a 3-channel, simultaneous For the purpose of input signal stabilization the con-

sampling sine-to-digital converter which interpolates ditioned signals are fed into signal level controllers

sine/cosine sensor signals using a high precision featuring current source outputs of up to 50 mA (mas-

SAR converter with a selectable resolution of up to ter channel) and of up to 10 mA (for the nonius and

13 bits. Each input has a separate sample-and-hold segment channels each). These ACOx source pins

stage which halts the track signal for the subsequent either power the LEDs of an optical encoder or the

sequential digitization. Various 2- and 3-track Vernier magneto resistor bridges of a magnetic encoder. If

scale computations (after Nonius) can be conﬁgured the control thresholds are reached this event can be

for the calculation of high resolution angle positions; released for alarm messaging using the serial inter-

these computations permit angle resolutions of up to face or the NERR output.

25 bits.

Both major chip functions and sensor errors are also

The absolute angle position is output via the serial monitored and can be enabled for alarm indication.

Interface with clock rates of up to 4 Mbit/s (SSI com- In this manner typical sensor errors, such as signal

patible; up to 10 Mbit/s with BiSS C protocol). The loss due to wire breakage, short circuiting, dirt or ag-

RS422 transceiver required to this end is integrated ing, for example, can be signaled by alarms.

on the chip and has both a differential clock input and

a differential line driver for data output.

The device features further digital encoder functions

covering the correction of phase errors between the

Programmable instrumentation ampliﬁers with a se- tracks, for example, or the zeroing or presetting of a

lectable gain and offset and phase correction can speciﬁc position offset for data output. Using the SSI

be adjusted separately for each channel; these al- master also integrated on the chip position data from

low differential or single-ended input signals. At multiturn sensors, provided by a second iC-MN, for

the same time the inputs can either be set to high example, can be read in and synchronized.

impedance for voltage signals from magneto resistor

sensor bridges, for example, or to low impedance for iC-MN is protected against a reversed power supply

adaptation and use with photosensors which provide voltage; the integrated supply switch for loads of up

current signals, for instance. This enables the device to 20 mA extends this protection to cover the over-

to be directly connected up to a number of different all system. The device is conﬁgured via an external

optical and magnetic sensors.

EEPROM.

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 3/59

CONTENTS

PACKAGES

5

6

S/D CONVERSION with MULTITURN

SYNCHRONIZATION

33

ABSOLUTE MAXIMUM RATINGS

THERMAL DATA

Op. Mode Descriptions Of Multiturn Modes . 33

MODE_ST Code 0x0C . . . . . . . . . . . . . 33

MODE_ST Code 0x0D . . . . . . . . . . . . . 33

MODE_ST Code 0x0E . . . . . . . . . . . . . 33

MODE_ST Code 0x0F . . . . . . . . . . . . . 33

6

ELECTRICAL CHARACTERISTICS

OPERATING REQUIREMENTS: I/O Interface

CONFIGURATION PARAMETERS

REGISTER MAP (EEPROM)

7

15

16

17

S/D CONVERSION with DIRECT OUTPUT

34

Op. Mode Descriptions Of Direct Output

Modes . . . . . . . . . . . . . . . . . . . 34

MODE_ST Code 0x0C . . . . . . . . . . . . . 34

MODE_ST Code 0x0D . . . . . . . . . . . . . 34

MODE_ST Code 0x0E . . . . . . . . . . . . . 34

MODE_ST Code 0x0F . . . . . . . . . . . . . 34

OPERATING MODES and CALIBRATION

PROCEDURES

21

Calibration Using

Comparated Sine/Cosine Signals . . . . 22

TRACK OFFSET CALIBRATION

35

I/O INTERFACE

36

SIGNAL CONDITIONING for MASTER-,

SEGMENT- and NONIUS-Channel (x= M,S,N) 23

Protocol . . . . . . . . . . . . . . . . . . . . . 36

Output Data Length . . . . . . . . . . . . . . 36

Output Options . . . . . . . . . . . . . . . . . 37

Current Signals . . . . . . . . . . . . . . . . . 23

Voltage Signals . . . . . . . . . . . . . . . . . 23

Gain Adjustment . . . . . . . . . . . . . . . . 24

Offset Calibration . . . . . . . . . . . . . . . . 24

Phase Correction . . . . . . . . . . . . . . . . 26

I/O INTERFACE with EXTENDED FUNCTIONS 38

Protocol . . . . . . . . . . . . . . . . . . . . . 38

Output Data Length . . . . . . . . . . . . . . 39

Output Options . . . . . . . . . . . . . . . . . 39

Safety Application Settings . . . . . . . . . . 40

Busy Register . . . . . . . . . . . . . . . . . . 40

ANALOG PARAMETERS

27

Signal Level Controller . . . . . . . . . . . . . 27

Bias Current Source . . . . . . . . . . . . . . 28

Temperature Sensor . . . . . . . . . . . . . . 28

Signal Noise Filters . . . . . . . . . . . . . . . 28

CONFIGURATION OF DIGITAL DRIVER

OUTPUTS

41

42

SINE-TO-DIGITAL CONVERSION MODES

29

COMMAND and STATUS REGISTERS

Internal Bit Lengths . . . . . . . . . . . . . . 29

Execution Of Internal Commands . . . . . . . 42

Execution Of Protocol Commands . . . . . . 42

Automatic Reset Function . . . . . . . . . . . 42

Status Register . . . . . . . . . . . . . . . . . 43

Non-Volatile Diagnosis Memory . . . . . . . . 43

S/D CONVERSION with NONIUS

CALCULATION

30

Output Data Veriﬁcation . . . . . . . . . . . . 30

Op. Mode Descriptions Of Nonius Modes . . 30

MODE_ST Codes 0x00, 0x01, 0x02 . . . . . 30

MODE_ST Codes 0x03, 0x04 . . . . . . . . . 30

MODE_ST Codes 0x05, 0x06, 0x7 . . . . . . 31

MODE_ST Codes 0x08, 0x09, 0xA . . . . . . 31

MODE_ST Code 0x0B . . . . . . . . . . . . . 31

ERROR AND WARNING BIT

44

Visibility Of Latched Status Messages . . . . 45

MT INTERFACE

46

Conﬁguration Of Data Lengths . . . . . . . . 46

Error Handling . . . . . . . . . . . . . . . . . 47

MT Interface with 2-bit mode . . . . . . . . . 48

Principle PPR And Bit Length Dependencies

31

Digital Frequency Monitoring . . . . . . . . . 32

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 4/59

MT INTERFACE with EXTENDED FUNCTIONS 49

Bank-Wise Addressing . . . . . . . . . . . . . 52

Direct Communication To Multiturn Sensor

.

49

50

51

52

APPLICATION NOTES: Conﬁguration As

BiSS C-Slave Including EDS (Electronic

PRESET FUNCTION

Data Sheet)

55

57

STARTUP BEHAVIOR

APPLICATION NOTES: PLC Operation

EEPROM INTERFACE

PLC Operation . . . . . . . . . . . . . . . . . 57

Memory Map And Register Access . . . . . . 52

Direct Addressing . . . . . . . . . . . . . . . 52 DESIGN REVIEW: Notes On Chip Functions

58

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 5/59

PACKAGES

PIN CONFIGURATION QFN48

PIN FUNCTIONS

No. Name

21 MAO

22 SLI

23 NMA*

24 MA*

Function

I/O Interface, clock output

I/O Interface, data input

I/O Interface, clock input -

I/O Interface, clock input +

25 NSLO* I/O Interface, data output -

26 SLO*

27 MTSLI

28 T3

I/O Interface, data output +

Multiturn Interface, data input

External Trigger Input,

Test Signal Input

29 MTMA

30 T2

Multiturn Interface, clock output

Test Signal Input

31 GND*

32 VDD*

Ground

+4.5 to 5.5 V Supply Voltage

33 NERR* Error Message Output,

System Error Message Input

34 n.c.

35 n.c.

36 n.c.

37 NSOUT* Analog Output Sine - (Master)

38 PSOUT* Analog Output Sine + (Master)

39 NCOUT* Analog Output Cosine - (Master)

40 PCOUT* Analog Output Cosine + (Master)

PIN FUNCTIONS

No. Name Function

1 NSINS Signal Input Sine - (Segment)

2 PSINS Signal Input Sine + (Segment)

3 PCINS Signal Input Cosine + (Segment)

4 NCINS Signal Input Cosine - (Segment)

5 NSINM Signal Input Sine - (Master)

6 PSINM Signal Input Sine + (Master)

7 PCINM Signal Input Cosine+ (Master)

8 NCINM Signal Input Cosine - (Master)

9 NSINN Signal Input Sine - (Nonius)

10 PSINN Signal Input Sine + (Nonius)

11 PCINN Signal Input Cosine + (Nonius)

12 NCINN Signal Input Cosine - (Nonius)

13 n.c.

41 T0

42 T1

Test Signal Output

43 ACOM* Signal Level Controller Outp. (Master)

44 VACO* +4.5 to 5.5 V Signal Level Controller

Supply

45 ACON* Signal Level Controller Output

46 ACOS* Signal Level Controller Output,

VREFin Ref. Voltage Input/Output

47 GNDA

48 VDDA

Sub-System Ground Output

Sub-System Positive Supply Output

* :

Pin is immune against faulty output

or supply connection.

14 n.c.

15 n.c.

16 n.c.

n.c. :

Pin is not connected.

17 DIR

Sense of Rotation Preselection Input,

Calibration Signal IPB

18 PRES Preset Input

19 SCL

20 SDA

EEPROM Interface, clock line

EEPROM Interface, data line

Wiring unused input pins can be recommended, especially for pins SLI, DIR, PRES and T2 (to GNDA). For

calibrating the internal bias current source a pull-down resistor of 5 kΩ ±1 % connected from pin DIR to GNDA

is useful (see Figure 10).

To improve heat dissipation the thermal pad of the QFN package (bottom side) should be joined to an extended

copper area which must have GNDA potential.

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 6/59

ABSOLUTE MAXIMUM RATINGS

These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur.

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Max.

G001 V()

Voltage at VDD, GND, NSLO, SLO,

NERR, PSOUT, NSOUT, PCOUT,

NCOUT, VACO

referenced to GND

-6

6

V

G002 V()

G003 V()

Voltage at MA, NMA

referenced to GND

-9

14

6

V

Pin-to-Pin Voltage vs. VDD, GND,

NSLO, SLO, NERR, PSOUT, NSOUT,

PCOUT, NCOUT, VACO

G004 V()

Voltage at NSINS, PSINS, PCINS,

NCINS, NSINM, PSINM, PCINM,

NCINM, NSINN, PSINN, PCINN,

NCINN, DIR, PRES, SCL, SDA, MAO,

SLI, MTSLI, T2, MTMA, T3, T0, T1,

ACOM, ACON, ACOS, GNDA, VDDA

referenced to AGND, V() < VDD + 0.3 V

-0.3

6

V

G005 I(VDD)

G006 I()

Current in VDD

-100

-50

400

50

mA

Current in VDDA, GNDA, PSOUT,

NSOUT, PCOUT, NCOUT

G007 I()

Current in PSINM, NSINM, PCINM,

NCINM, PSINS, NSINS, PCINS,

NCINS, PSINN, NSINN, PCINN,

NCINN, DIR, PRES, SCL, SDA, MAO,

SLI, T3, T2, NERR, T0, T1

-20

20

mA

G008 I()

Current in SLO, NSLO, VACO

Current in MA, NMA

-120

-0.6

-100

-50

120

1

mA

kV

G009 I()

G010 I(ACOM)

G011 I()

Current in ACOM

20

2

Current in ACOS, ACON

ESD Susceptibility at all pins

Junction Temperature

G012 Vd()

G013 Tj

HBM 100 pF discharged through 1.5 kΩ

-40

150

° C

G014 Ts

Storage Temperature Range

THERMAL DATA

Operating conditions: VDD = 5 V ±10 %

Item Symbol

No.

Parameter

Conditions

Unit

Min. Typ. Max.

-40 110

T01 Ta

Operating Ambient Temperature Range package QFN48

° C

T02 Rthja

Thermal Resistance Chip to Ambient; QFN48 surface mounted to PCB according to

30

K/W

QFN48

JEDEC 51

All voltages are referenced to ground unless otherwise stated.

All currents ﬂowing into the device pins are positive; all currents ﬂowing out of the device pins are negative.

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 7/59

ELECTRICAL CHARACTERISTICS

Operating conditions: VDD = VACO = 5 V ±10 %, Tj = -40...125 °C,

IBP calibrated to 200 µA, reference point GNDA (GND for digital I/O pins), unless otherwise stated

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

Total Device

001 VDD,

VACO

Permissible Supply Voltage

Supply Current in VDD

4.5

5.5

V

002 I(VDD)

Tj = 27 °C, no load

45

60

0

mA

003 I(VDDA)

Permissible Load Current at

VDDA

-20

0.4

004 Vc()hi

Clamp Voltage hi

(all pins with the exception of MA,

NMA)

Vc()hi = V() − VDD, I() = 1 mA

1.5

V

005 Vc()hi

006 Vc()lo

Clamp Voltage hi MA, NMA

Vc()hi = V() − VDD, I() = 10 mA

I() = -1 mA

12.5

-1.5

16

V

Clamp Voltage lo

-0.3

(all pins with the exception of

VDDA, MA, NMA)

007 Vc()lo

008 Vc()lo

Clamp Voltage lo at VDDA

I() = -1 mA

-1.5

-17

-0.2

-10

V

Clamp Voltage lo at MA, NMA

I() = -10 mA

Signal Conditioning and Inputs: PSINx, NSINx, PCINx, NCINx (x = M, S, N)

101

Vin()sig

Permissible V-Mode Input Voltage

UIN = 1, TUIN = 0

0.75

-0.1

VDDA

− 1.5

VDDA

+ 0.1

V

UIN = 1, TUIN = 1, DCPOS = 1

102 Iin()

103 Rin()

V-Mode Input Current

UIN = 1, TUIN = 0

-100

16.4

100

nA

V-Mode Input Resistance

Permissible I-Mode Input Current

vs. VREFin, Tj = 27 °C, UIN = 1, TUIN = 1

20

23.6

kΩ

104

Iin()sig

UIN = 0;

DCPOS = 0

DCPOS = 1

-10

10

-300

300

µA

105 SCR()

106

Permissible Signal Contrast Ratio ratio of Iin()pk vs. Iin()dc

0.125

1

Rin()

I-Mode Input Resistance

Tj = 27 °C, vs. VREFin;

UIN = 0, RIN = 00

UIN = 0, RIN = 01

UIN = 0, RIN = 10

UIN = 0, RIN = 11

1.1

1.6

2.2

3.2

1.6

2.3

3.2

4.6

2.1

3.0

4.2

6.0

kΩ

107 TCRin

108

Temperature Coefﬁcient Rin

Input Reference Voltage

0.15

%/K

VREFin

DCPOS = 1

DCPOS = 0

1.35

2.25

1.5

2.5

1.65

2.75

V

109 Vin()os

110

Input Offset Voltage

referred to side of input

150

µV

Vin()diff

Recommended Differential Input

Voltage

Vin()diff = V(PSINx) − V(NSINx),

Vin()diff = V(PCINx) − V(NCINx);

TUIN = 0

20

80

1000

4000

mVpp

TUIN = 1

111 Vcore()

112

Recommended Internal Signal

Level

G * Vin()diff

6

Vpp

GF, GC

Selectable Gain Factors

TUIN = 0

TUIN = 1

6

1.5

300

75

113 ∆GFdiff

114 ∆GFdiff

Differential Gain Accuracy

(Master)

referenced to ﬁne gain range

-1

-2

1

LSB

%

Differential Gain Accuracy

(Segment, Nonius)

referenced to ﬁne gain range

2

115 ∆GFSabs Absolute Gain Accuracy Sine

referenced to ﬁne gain range, guaranteed

monotony

-20

-1

20

1

(Master)

116 ∆GFCabs Absolute Gain Accuracy Cosine referenced to ﬁne gain range, guaranteed

(Master)

monotony

117 ∆GFSabs Absolute Gain Accuracy Sine

referenced to ﬁne gain range, guaranteed

monotony

-20

-1

20

1

(Segment, Nonius)

118 ∆GFCabs Absolute Gain Accuracy Cosine referenced to ﬁne gain range, guaranteed

(Segment, Nonius)

monotony

119 ∆GCabs Gain Accuracy

referenced to coarse gain range

-8

8

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 8/59

ELECTRICAL CHARACTERISTICS

Operating conditions: VDD = VACO = 5 V ±10 %, Tj = -40...125 °C,

IBP calibrated to 200 µA, reference point GNDA (GND for digital I/O pins), unless otherwise stated

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

120

121

122

123

VOScal

Offset Calibration Range

measured at output, source V(ACOx) = 3 V,

REFVOS = 00;

ORS_x/ORC_x = 00

ORS_x/ORC_x = 01

ORS_x/ORC_x = 10

±450

±900

±2700

±5400

mV

ORS_x/ORC_x = 11

VOScal2

VOScal3

VOScal4

Offset Calibration Range

measured at output, source V05,

REFVOS = 01;

ORS_x/ORC_x = 00

ORS_x/ORC_x = 01

ORS_x/ORC_x = 10

ORS_x/ORC_x = 11

±1500

±3000

±9000

±18000

mV

measured at output, source V025,

REFVOS = 10;

ORS_x/ORC_x = 00

ORS_x/ORC_x = 01

ORS_x/ORC_x = 10

ORS_x/ORC_x = 11

±750

±1500

±4500

±9000

mV

measured at output, source VDC = 125 mV,

REFVOS = 11;

ORS_x/ORC_x = 00

ORS_x/ORC_x = 01

ORS_x/ORC_x = 10

ORS_x/ORC_x = 11

±375

±750

±2250

±4500

mV

124 ∆VOSdiff Differential Linearity Error of

-0.5

-2

0.5

2

LSB

Offset Correction Master

125 ∆VOSdiff Differential Linearity Error of Off-

set Correction Segment, Nonius

126 ∆VOSint Integral Linearity Error of Offset

-100

100

Correction Master

127 ∆VOSint Integral Linearity Error of Offset

Correction Segment, Nonius

128 PHIcal

Phase Correction Range

sine vs. cosine signal

±10.4

°

129 ∆PHIdiff

Differential Linearity Error of

Phase Correction Master

-0.25

-2

0.25

2

LSB

130 ∆PHIdiff

Differential Linearity Error of

Phase Correction Segment, Non-

ius

LSB

131 ∆PHIint

132 ∆PHIint

Integral Linearity Error of Phase

Correction Master

-20

200

250

20

LSB

kHz

Integral Linearity Error of Phase

Correction Segment, Nonius

133

ﬁn()max

Permissible Input Frequency

angle accuracy better 8 bit

134 fhc()

Input Ampliﬁer Cut-off Frequency

(-3 dB)

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 9/59

ELECTRICAL CHARACTERISTICS

Operating conditions: VDD = VACO = 5 V ±10 %, Tj = -40...125 °C,

IBP calibrated to 200 µA, reference point GNDA (GND for digital I/O pins), unless otherwise stated

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

Signal Level Controller: ACOM

401

Vs()hi

Saturation Voltage hi

Short-circuit Current hi

Vs()hi = V(VACO) - V();

ACOR_M(6:5) = 00, I() = -5 mA

ACOR_M(6:5) = 01, I() = -10 mA

ACOR_M(6:5) = 10, I() = -25 mA

ACOR_M(6:5) = 11, I() = -50 mA

1

V

402

Isc()hi

V() = 0...V(VACO) − 1 V;

ACOR_M(6:5) = 00

ACOR_M(6:5) = 01

ACOR_M(6:5) = 10

ACOR_M(6:5) = 11

-9.5

-19

-46

-85

-7

-14.5

-36

-5

mA

-10

-25

-50

-73

403 Ilk()

404 Tctrl

Residual Current With Reversed

Supply

50

µA

Control Time Constant

quadratic or sum regulation

1.6

3

ms

V

405 Vscq()avg Controlled Average S/C Signal

Amplitude:

quadratic regulation: ACOT_M(8:7) = 00,

Op.mode ANA_M

2.7

3.3

SQRT of [V(PSOUT)-

V(NSOUT)]²+ [V(PCOUT)-

V(NCOUT)]²

406 Vt()min

407 Vt()max

408 It()min

409 It()max

Signal Monitoring AM_Min

Signal Monitoring AM_Max

Control Monitoring ACM_Min

Control Monitoring ACM_Max

referred to Vscq()

40

135

3

%

referred to Vscq()

%

referenced to range ACOR_M()

%Isc

90

Signal Level Controller: ACOS, ACON

501

Vs()hi

Saturation Voltage hi

Vs()hi = V(VACO) − V();

ACOR_x(5) = 0, I() = -5 mA

ACOR_x(5) = 1, I() = -10 mA

1

V

502

Isc()hi

Short-circuit Current hi

V() = 0...V(VACO) − 1 V;

ACOR_x(5) = 0

-9.5

-19

-7

-14.5

-5

-10

mA

ACOR_x(5) = 1

503 Ilk()

504 Tctrl

Residual Current with Reverse

Polarity

50

µA

Control Time Constant

control to sine square or sum

1.6

3

ms

V

505 Vscq()avg Controlled Average S/C Signal

Amplitude:

quadratic regulation: ACOT_x(7:6) = 00,

operating mode ANA_x

2.7

3.3

SQRT of [V(PSOUT)-

V(NSOUT)]²+ [V(PCOUT)-

V(NCOUT)]²

506 Vt()min

507 Vt()max

508 It()min

509 It()max

Signal Monitoring AN_Min,

AS_Min

referred to Vscq()

40

135

3

%

Signal Monitoring AN_Max,

AS_Max

referred to Vscq()

Control Monitoring ACN_Min,

ACS_Min

referenced to range ACOR_x()

%Isc

V

Control Monitoring ACN_Max,

ACS_Max

90

510 Vin(ACOS) Permissible Ref. Input Voltage at CVREF = 11

ACOS

0.75

VDDA

− 2

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 10/59

ELECTRICAL CHARACTERISTICS

Operating conditions: VDD = VACO = 5 V ±10 %, Tj = -40...125 °C,

IBP calibrated to 200 µA, reference point GNDA (GND for digital I/O pins), unless otherwise stated

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

Sample-&-Hold Stage, Signal Filter and Sine-To-Digital Conversion

601

fc1()

Cut-off Frequency of M/S/N

Channel Signal Filter

(-3 dB lowpass ﬁlter)

ENF(1) = 1;

ﬁn (master channel) < 20 Hz

ﬁn (master channel) > 1300 Hz

4

300

kHz

602 amax

Permissible Angle Acceleration

for 3(2) track nonius calculation

ENF(1) = 1

1000

Mrad/s²

603 AAabs

604 AAR

Absolute Angular Accuracy

Repeatability

Used bit length UBL_x = 0x0D: 13 bit

±2

±1

LSB

605

tcnv

Used bit length UBL_x:

0x0D: 13 bit

0x0C: 12 bit

0x0B: 11 bit

0x0A: 10 bit

0x09: 9 bit

0x08: 8 bit

0x07: 7 bit

0x06: 6 bit

0x05: 5 bit

Conversion Time (1 Channel)

4.25

3.88

3.5

3.13

2.75

2.5

2.25

2.0

1.75

1.5

µs

0x04: 4 bit

606 trec()

Recovery Time Sampling-to-

Sampling

termination of calculation and synchronization

(Nonius or MT modes) to follow-up S&H trigger

1.25

300

µs

Analog Line Driver Outputs: PSOUT, NSOUT, PCOUT, NCOUT

701 Vout()

702

Output Amplitude

RLdiff = 100 Ω, VDD = 4.5 V, DC level = VDD/2

mV

fc2()

Cut-off Frequency of Line Driver

Signal Filter

(-3 dB lowpass ﬁlter)

ENF(0) = 1;

ﬁn (master channel) < 20 Hz

ﬁn (master channel) > 1300 Hz

8

600

kHz

703 fc3()

Cut-off Frequency of Line Driver CL = 500 pF, Vpp = 0.5 V, ENF0 = 1

(-3 dB)

500

kHz

704 Voffs()

705 Isc()hi

706 Isc()lo

707 SR()

708 Ilk()

Offset Voltage

-8

-40

15

8

mV

mA

V/µs

µA

Short-circuit Current hi

Short-circuit Current lo

Slew Rate

V() = GND

-20

20

5

-15

40

V() = VDD

RLdiff = 100 Ω, CL = 25 pF

Residual Current with Reverse

Polarity

-50

50

2

709 Vout()err

Output Signal with Temperature VTs > VTth

Error

50

5

%VDD

710 Rout()

Output Impedance

Op.Mode ANA_M, ANA_N, ANA_S

kΩ

711 fout()cal

Permissible Output Frequency

During Calibration

Op.Mode ANA_M, ANA_N, ANA_S;

CL = 200 pF

kHz

Bias Current Source and Reference Voltages

801 IBP

Bias Current Source

IBP calibrated to 200 µA

referenced to GNDA

92.5

48

100

50

107.5

52

%

802 VPAH

803 V05

804 V025

Reference Voltage VPAH

Reference Voltage V05

Reference Voltage V025

%VDD

mV

460

512

50

570

%V05

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 11/59

ELECTRICAL CHARACTERISTICS

Operating conditions: VDD = VACO = 5 V ±10 %, Tj = -40...125 °C,

IBP calibrated to 200 µA, reference point GNDA (GND for digital I/O pins), unless otherwise stated

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

Power-Down-Reset

901 VDDon

Turn-on Threshold VDD

(power on release)

increasing voltage VDD

decreasing voltage VDD

VDDhys = VDDon − VDDoff

includes tbusy()cfg;

MODE_MT = 00

3.6

3.1

400

3.9

3.4

4.3

3.8

V

902 VDDoff

Turn-off Threshold VDD

(power down reset)

903 VDDhys

Hysteresis

mV

904

tready()cfg Operation Start-Up Time

21

29

ms

Clock Oscillator

A01 fosc

Clock Frequency

8

MHz

mV

Supply Switch and Reverse Polarity Protection: VDDA, GNDA

B01 Vs()

Switch Drop-Off Voltage vs. VDD V() = V(VDD) − V(VDDA), I(VDDA) = 0

115

(unloaded)

B02 Rs()

B03 Vs()

VDDA Switch On-Resistance

VDD vs. VDDA, load current to 20 mA

5

1

10

20

7

Ω

Switch Drop-Off Voltage vs.

GNDA (unloaded)

V() = V(GNDA) − V(GND), I(GNDA) = 0

105

mV

B04 Rs()

GNDA Switch On-Resistance

ground current to 20 mA

3.8

Ω

Temperature Monitoring

C01

VTSw

Sensor Voltage for Warning

Temperature

VTSw() = VDDA − V(T1), Tj = 27 °C,

610

635

640

665

670

695

mV

operating mode TWIB

C02

VTSe

Sensor Voltage for Shutdown

Temperature

VTSe() = VDDA − V(T1), Tj = 27 °C,

operating mode TEIB

C03 TCs

C04

Sensor Voltage Temperature

Coefﬁcient

-1.95

mV/K

VTth

Activation Threshold Temperature

Warning

VTth() = VDDA − V(T0), Tj = 27 °C;

CFGTA(4:0) = 0x00

CFGTA(4:0) = 0x0F

225

400

585

285

498

725

355

615

895

mV

CFGTA(4:0) = 0x1F

C05 TCth

Activation Threshold Temperature

Coefﬁcient

1.32

‰/K

C06 Thys_w

C07 ∆T

Warning Temperature Hysteresis

4

5

9

15

30

19

20

39

°C

Relative Shutdown Temperature ∆T = Te − Tw

Shutdown Temperature Hystere-

sis

C08 Thys_e

EEPROM Interface: SCL, SDA

D01 Vs()lo

D02 Isc()lo

D03 Vt()hi

D04 Vt(lo)

D05 Vt()hys

D06 Ipu()

D07 Vpu()

Saturation Voltage lo

I() = 4 mA

450

60

2

mV

mA

V

Short-circuit Current lo

Input Threshold Voltage hi

Input Threshold Voltage lo

Input Hysteresis

4

800

150

-750

mV

µA

Vt(hys) = Vt()hi − Vt()lo

V() = 0...VDD − 1 V

Vpu() = VDD − V(), I() = -5 µA

250

Input Pull-up Current

Input Pull-up Voltage

-300

-60

400

80

mV

kHz

ms

D08 fclk(SCL) Clock Frequency

45

62.5

13

D09 tbusy()cfg Duration Of Startup Conﬁguration error free EEPROM access

15

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 12/59

ELECTRICAL CHARACTERISTICS

Operating conditions: VDD = VACO = 5 V ±10 %, Tj = -40...125 °C,

IBP calibrated to 200 µA, reference point GNDA (GND for digital I/O pins), unless otherwise stated

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

I/O Interface: RS442 Line Driver Outputs SLO, NSLO

E01

Vs()hi

Saturation Voltage hi

Vs() = VDD − V();

DSC(1:0) = 00, I() = -1.2 mA

DSC(1:0) = 01, I() = -4 mA

DSC(1:0) = 10, I() = -20 mA

DSC(1:0) = 11, I() = -50 mA

200

400

900

mV

E02

E03

Vs()lo

Isc()hi

Saturation Voltage lo

Short-circuit Current hi

DSC(1:0) = 00, I() = 1.2 mA

DSC(1:0) = 01, I() = 4 mA

DSC(1:0) = 10, I() = 20 mA

DSC(1:0) = 11, I() = 50 mA

200

400

900

mV

V() = 0 V;

DSC(1:0) = 00

DSC(1:0) = 01

DSC(1:0) = 10

DSC(1:0) = 11

-3

-10

-45

-120

-1.2

-4

-20

-50

mA

E04

Isc()lo

Short-circuit Current lo

V() = VDD

DSC(1:0) = 00

DSC(1:0) = 01

DSC(1:0) = 10

DSC(1:0) = 11

1.2

4

20

50

3

10

45

120

mA

E05 Ilk()tri

Tristate Leakage Current

Rise Time hi

DTRI(1:0) = 11

-10

10

µA

E06

tr()

RL = 100 Ω to GND, DSC(1:0) = 11;

DSR(1:0) = 00

DSR(1:0) = 01

DSR(1:0) = 10

DSR(1:0) = 11

10

22

60

30

40

140

350

ns

250

E07

tf()

Fall Time lo

RL = 100 Ω to VDD, DSC(1:0) = 11;

DSR(1:0) = 00

5

22

60

250

15

40

140

350

ns

DSR(1:0) = 01

DSR(1:0) = 10

DSR(1:0) = 11

E08 Ilk()

Residual Current with Reverse

Polarity

-100

100

µA

I/O Interface: RS442 Line Receiver MA, NMA

F01 Vin()

F02 Rin()

F03 Vhys()

F04 Vt()hi

F05 Vt()lo

Permissible Input Voltage

Input Resistance

-7

15

50

12

25

200

2

V

kΩ

mV

V

MA vs. GND, NMA vs. GND

Vhys() = ( V(MA) - V(NMA) ) / 2

20

Differential Input Hysteresis

Input Threshold Voltage hi at MA pin NMA open

Input Threshold Voltage lo at MA pin NMA open

800

mV

MHz

F06

fclk()

Permissible Clock Frequency:

SSI protocol

MODE_ST = 0x05 to 0x0B, 0x0D to 0x0F

4

F07 fclk()

Permissible Clock Frequency:

BiSS protocol

NBISS = 0

10

50

MHz

ns

F08 tp(MA-

SLO)

Propagation Delay:

MA edge vs. SLO output

RL(SLO/NSLO) = 120 Ω

10

F09

Processing Time Singlecycle

Data (delay of start bit)

Nonius modes:

tbusy_s

MODE_ST = 0x00 to 0x02

MODE_ST = 0x03 to 0x04, 2 track

MODE_ST = 0x03 to 0x04, 3 track

MODE_ST = 0x05 to 0x0B

MT modes:

tcnv *1

tcnv *2

tcnv *3

0

µs

MODE_ST = 0x0C, 3 track

MODE_ST = 0x0D to 0x0F

tcnv *3

0

µs

F10 tbusy_r

F11 tidle

Processing Time Register Ac-

cess (delay of start bit)

with read access to EEPROM

2

ms

Interface Blocking Time

powering up without EEPROM

ms

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 13/59

ELECTRICAL CHARACTERISTICS

Operating conditions: VDD = VACO = 5 V ±10 %, Tj = -40...125 °C,

IBP calibrated to 200 µA, reference point GNDA (GND for digital I/O pins), unless otherwise stated

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

I/O Interface: Clock Line Output MAO

G01 Vs()hi

G02 Vs()lo

G03 Isc()hi

G04 Isc()lo

Saturation Voltage hi

Saturation Voltage lo

Short-circuit Current hi

Short-circuit Current lo

Vs()hi = VDD − V(), I() = -4 mA

I() = 4 mA

450

-30

65

mV

mA

-85

20

Test Signal Inputs: T2, T3

H01 Vt()hi

H02 Vt()lo

H03 Vt()hys

H04 Ipd()

H05 Vpd()

H06 Ipu()

H07 Vpu()

Input Threshold Voltage hi

2

V

Input Threshold Voltage lo

Input Hysteresis

800

150

4

mV

µA

250

30

Input-Pull-Down-Current at T2

Input-Pull-Down-Voltage at T2

Input Pull-up Current at T3

Input Pull-up Voltage at T3

V() = 1 V...VDD

75

650

-5

I() = 5 µA

mV

µA

V() = 0...VDD − 1 V

Vpu() = VDD − V(), I() = -5 µA

-65

30

650

mV

Test Signal Outputs: T0, T1

I01 Vs()hi

I02 Vs()lo

I03 Isc()hi

I04 Isc()lo

I05 Voffs()

Saturation Voltage hi

Vs()hi = VDD − V(), I() = -4 mA

500

600

-15

60

mV

mA

mV

Saturation Voltage lo

Short-circuit Current hi

Short-circuit Current lo

I() = 4 mA

-60

15

Analog Buffer Offset Voltage at

T0

Vos() = V(T1) − V(T0), operating mode TBOS

-25

25

I/O Interface: Input SLI

J01 Vt()hi

J02 Vt()lo

J03 Vt()hys

J04 Ipd()

J05 Vpd()

Input Threshold Voltage hi

2

V

Input Threshold Voltage lo

Input Hysteresis

0.8

150

4

V

250

30

mV

µA

mV

Input Pull-down Current

Input Pull-Down Voltage

V() = 1 V...VDD

I() = 5 µA

75

650

Digital Inputs: DIR, PRES

K01 Vt()hi

K02 Vt()lo

K03 Vt()hys

K04 Ipd()

K05 Vs()hi

K06 Vs()lo

K07 Vpd()

Input Threshold Voltage hi

2

V

Input Threshold Voltage lo

Input Hysteresis

0.8

150

20.5

V

250

120

mV

µA

mV

Input Pull-down Current

Saturation Voltage hi

Saturation Voltage lo

Input Pull-down Voltage

V() = 1 V ... VDD

296

295

275

600

Vs()hi = VDD - V(); I() = 1.6 mA

during test function, I() = 1.6 mA

during test function, I() = 5 µA

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 14/59

ELECTRICAL CHARACTERISTICS

Operating conditions: VDD = VACO = 5 V ±10 %, Tj = -40...125 °C,

IBP calibrated to 200 µA, reference point GNDA (GND for digital I/O pins), unless otherwise stated

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

Error Message Input/Output: NERR

L01 Vs()lo

L02 Isc()lo

L03 Vt()hi

L04 Vt()lo

L05 Vt()hys

L06 Ipu()

L07 Vpu()

L08 Ilk()

Saturation Voltage lo

Short-circuit Current lo

Input Threshold Voltage hi

Input Threshold Voltage lo

Input Hysteresis

I() = 4 mA

450

60

2

mV

mA

V

4

0.8

150

-750

V

Vt(hys) = Vt()hi - Vt()lo

V() = 0... VDD - 1 V

250

mV

µA

mV

µA

Input Pull-up Current

Input Pull-up Voltage

-300

-60

400

100

Vpu() = VDD - V(), I() = -5 µA

Residual Current with Reverse

Polarity

-100

Multiturn Interface: MTMA, MTSLI

Input Threshold Voltage hi

M01 Vt()hi

M02 Vt()lo

M03 Vt()hys

M04 Ipd()

M05 Vpd()

M06 Ipu()

M07 Vpu()

M08 Vs()hi

M09 Vs()lo

M10 Isc()hi

M11 Isc()lo

M12 fclk()

M13 fclk()

M14 t_cycle

M15 t_cycle

MODE_MT = 11

2

V

Input Threshold Voltage lo

MODE_MT = 11

0.8

150

4

Input Hysteresis

MODE_MT = 11

250

30

mV

µA

Input Pull-down Current MTSLI

Input Pull-down Voltage MTSLI

Input Pull-up Current MTMA

Input Pull-up Voltage MTMA

Saturation Voltage hi at MTMA

Saturation Voltage lo at MTMA

Short-circuit Current hi at MTMA

Short-circuit Current lo at MTMA

SSI Clock Frequency at MTMA

V() = 1 V ... VDD

I() = 5 µA

75

650

-20.5

600

450

-30

mV

µA

V() = 0 V ... VDD - 1 V

Vpu() = VDD - V(), I() = -5 µA

Vs()hi = VDD - V(), I() = 4 mA

I() = 4 mA

-296

-120

mV

mA

MHz

µs

-85

20

65

0.125

1

BiSS Clock Frequency at MTMA MODE_MT = 01

Max. BiSS Read Cycle Duration MODE_MT = 01

256

MT Data Update Interval

MODE_MT = 01 or 10, CHK_MT = 1

8

ms

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 15/59

OPERATING REQUIREMENTS: I/O Interface

Operating conditions: VDD = 5 V ±10 %, Ta = -40...95(110) °C,

IBP calibrated for fosc = 8 MHz, reference point GNDA (GND for digital I/O pins), unless otherwise stated

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Max.

SSI Protocol

I001 T_MAS

I002 t_MASh

I003 t_MASl

I004 t_cycle

Permissible Clock Period

t_outselected in accordance to Table 50

250

25

2x t_out

t_out

ns

µs

Clock Signal Hi Level Duration

Clock Signal Lo Level Duration

25

t_out

Permissible Cycle Time:

MODE_ST = 0x05...0x07,

11.25

Example for 19-bit ST data from

3-track nonius calculation

UBL_M = 13 bit, UBL_N + SBL_N = 7 bit,

UBL_S + SBL_S = 7 bit

BiSS C Protocol (NBISS = 0x0)

I005 T_MAS

I006 t_MASh

I007 t_MASl

I008 t_busy

Permissible Clock Period

t_outselected in accordance to Table 58

100

25

ns

µs

Clock Signal Hi Level Duration

Clock Signal Lo Level Duration

Minimum Data Output Delay

t_out

25

MODE_ST = 0x05...0x0B, 0x0D...0x0F,

2x T_MAS

MA lo→hi until SLO lo→hi

I009 t_busy

I010 t_busy

I011 t_busy

Maximum Data Output Delay:

Example for 19-bit ST data from

3-track nonius calculation

MODE_ST = 0x00...0x02, fclk(MA) = 10 MHz,

UBL_x and SBL_x see I004

5.3

10

14

µs

Maximum Data Output Delay:

Example for 19-bit ST data from

3-track nonius calculation

MODE_ST = 0x03...0x04, fclk(MA) = 10 MHz,

UBL_x and SBL_x see I004

Maximum Data Output Delay:

Example for 39-bit ST data from

3-track interpolation without

synchronization

MODE_ST = 0x0C, fclk(MA) = 10 MHz,

UBL_M 13 bit, UBL_N 13 bit, UBL_S 13 bit

I012 t_cycle

Permissible Cycle Time:

Example for 19-bit ST data from

3-track nonius calculation

MODE_ST = 0x05...0x07,

UBL_x and SBL_x see I004

11.25

µs

Figure 1: I/O Interface timing with SSI protocol

Figure 2: I/O Interface timing with BiSS C protocol

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 16/59

CONFIGURATION PARAMETERS

Analog Parameters (valid for all channels)

I/O Interface With Extended Functions

NBISS:

TOS:

DL_ST:

M2S:

Interface Protocol (P. 38)

Timeout (S. 38)

ST Data Length (P. 39)

MT Data Output (P. 39)

Inversion Of Code Direction (P. 39)

CFGIBP:

CFGTA:

DCPOS:

ENF:

CVREF:

REFVOS:

RIN:

Bias Trimming (P. 28)

Temperature Sensor Calib. (P. 28)

Input Current Polarity (P. 23)

Noise Filter Enable (P. 28)

VREF Source Selection (P. 23)

Offset Reference Source (P. 24)

Input Resistance (P. 23)

DIR:

GRAY_SCD: Data Format (P. 39)

CID_SCD:

NC_BISS:

ELC:

CRC Start Value (P. 39)

Communication Disable (S. 39)

Lifecounter (P. 40)

TUIN:

UIN:

Input Voltage Divider (P. 23)

Signal Mode (P. 23)

Driver Settings

Signal Conditioning

x = M, S, N (for master, segment, nonius channel)

DSC:

DTRI:

DSR:

Driver Short-Circuit Current (P. 41)

Driver Output Mode (P. 41)

Driver Slew Rate (P. 41)

ACOC_x:

ACOR_x:

ACOT_x:

GFC_x:

GR_x:

Signal Level Control: Current (P. 27)

Signal Level Control: Range (P. 27)

Signal Level Control: Op. Mode (P. 27)

Gain Factor Cosine (P. 24)

Command And Status Register

STATUS:

Status Register (P. 43)

MN_CMD:

Implemented Commands (P. 42)

Gain Range (P. 24)

AUTORES: Automatic Reset Function (S. 42)

GFS_x:

MPS_x:

MPC_x:

OFC_x:

ORC_x:

OFS_x:

ORS_x:

PH_x:

Gain Factor Sine (P. 24)

Intermediate Voltage Sine (P. 25)

Intermediate Voltage Cosine (P. 25)

Offset Factor Cosine (P. 26)

Offset Range Cosine (P. 25)

Offset Factor Sine (P. 25)

Error And Warning Bit

CFGEW:

S2ERR:

S2WRN:

E2EPR:

Error And Warning Bit Conﬁg. (P. 44)

Visibility For Warning Bit (P. 45)

Visibility For Error Bit (P. 45)

Diagnosis Memory Enable (P. 43)

Offset Range Sine (P. 25)

S/C Phase Correction (P. 26)

MT Interface

MODE_MT: MT Interface Operating Mode (P. 46)

DL_MT:

SBL_MT:

LNT_MT:

MT Data Length (P. 46)

Operating Modes

TRACMODE: Op. Mode Parameter (P. 21)

MT Synch. Bit Length (P. 47)

Leading/Trailing Gear Box Assembly

(P. 47)

CALMODE:

BYP:

Op. Mode Parameter (P. 21)

Bypass Switch (P. 21)

CHK_MT:

Period Counter Veriﬁcation (P. 47)

GRAY_MT: MT Interface Data Format (P. 47)

Sine-To-Digital Conversion

MODE_ST: S/D Conversion Mode (P. 30)

MT Interface with Extended Functions

MODE_MT: MT Interface Operating Mode (P. 46)

UBL_M:

UBL_N:

SBL_N:

UBL_S:

SBL_S:

FRQ_TH:

SPO_N:

SPO_S:

Bit Length Master (P. 29)

Used Bit Length Nonius (P. 29)

Synch. Bit Length Nonius (P. 29)

Used Bit Length Segment (P. 29)

Synch. Bit Length Segment (P. 29)

Signal Frequency Monitoring (P. 32)

Offset Nonius Track (P. 35)

GET_MT:

Direct BiSS Communication Enable for

MT Sensor via I/O Interface (P. 49)

NCRC_MT: MT Interface CRC Veriﬁcation (P. 49)

SWC_MT: MT Interface CRC Polynomial (P. 49)

Preset Function

OFFS_ST: Position Offset for ST Data Output

(P. 50)

Offset Segment Track (P. 35)

PRES_ST: Preset Value for ST Data Output (P. 50)

OFFS_MT: Position Offset for MT Data Output

(P. 50)

I/O Interface

TOS:

DL_ST:

M2S:

Timeout (P. 36)

ST Data Length (P. 36)

MT Data Output (P. 39)

Error Bit (P. 37)

PRES_MT: Preset Value for MT Data Output (P. 50)

ESSI:

EEPROM Interface

GRAY_SCD: Data Format (P. 37)

CFG_E2P: Conﬁg. Of External Memory (P. 52)

CRC_E2P: EEPROM Data Check Sum (P. 52)

PROT_E2P: Register Access Control (P. 53)

RSSI:

DIR:

Ring Operation (P. 37)

Inversion Of Code Direction (P. 37)

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 17/59

REGISTER MAP (EEPROM)

OVERVIEW

Adr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Signal Conditioning Master Channel

0x00

0x01

GFC_M

GR_M

GFS_M(7:0)

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

MPS_M(4:0)

GFS_M(10:8)

MPS_M(9:5)

MPC_M(2:0)

ORS_M(0)

MPC_M(9:3)

OFS_M(6:0)

ORS_M(1)

OFC_M(1:0)

ORC_M

OFS_M(10)*

OFS_M(9:7)

OFC_M(9:2)

PH_M(6:0)

OFC_M(10)*

PH_M(9)*

PH_M(8:7)

Signal Conditioning Master Channel and Analog Parameters

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

1

DCPOS

REFVOS

TUIN

RIN

UIN

1

CVREF

0

BYP

ACOT_M(0)

ACOR_M(1:0)

CFGTA(2:0)

ACOC_M(4:0)

CFGIBP(3:0)

ACOT_M(1)

ENF(1:0)

CFGTA(4:3)

*) MSB and signum respectively.

Table 5: Register layout

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 18/59

OVERVIEW

Adr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Signal Conditioning Segment Channel

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

GFC_S

GR_S

GFS_S(7:0)

MPS_S(4:0)

GFS_S(10:8)

MPC_S(2:0)

MPS_S(9:5)

ORS_S(0)

MPC_S(9:3)

OFS_S(6:0)

ORS_S(1)

OFC_S(1:0)

ORC_S

OFS_S(10)*

OFS_S(9:7)

OFC_S(9:2)

PH_S(6:0)

OFC_S(10)*

PH_S(9)*

PH_S(8:7)

ACOT_S(0)

ACOR_S

ACOC_S(4:0)

ACOT_S(1)

Signal Conditioning Nonius Channel

0x20

0x21

GFC_N

GR_N

GFS_N(7:0)

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

MPS_N(4:0)

GFS_N(10:8)

MPS_N(9:5)

MPC_N(2:0)

OSR_N(0)

MPC_N(9:3)

OFS_N(6:0)

OSR_N(1)

OFC_N(1:0)

ORC_N

OFS_N(10)*

OFS_N(9:7)

OFC_N(9:2)

PH_N(6:0)

OFC_N(10)*

PH_N(9)*

PH_N(8:7)

ACOT_N(0)

ACOR_N

ACOC_N(4:0)

ACOT_N(1)

*) MSB and signum respectively.

Table 6: Register layout

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 19/59

OVERVIEW

Adr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Digital Parameters

0x30

0x31

0x32

0x33

OFFS_ST(7:0)

OFFS_ST(15:8)

OFFS_ST(23:16)

OFFS_ST(31:24)

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50^∗

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

...

0

OFFS_ST(38:32)

OFFS_MT(7:0)

OFFS_MT(15:8)

OFFS_MT(23:16)

SPO_S(7:0)

SPO_N(2:0)

SPO_S(12:8)

SPO_N(10:3)

UBL_M(3:0)

UBL_S(1:0)

UBL_N(2:0)

MODE_ST(3:0)

DL_MT(2:0)

SPO_N(12:11)

UBL_S(3:2)

UBL_N(3)

SBL_S(2:0)

SBL_N(2:0)

DL_ST(4:0)

GRAY_SCD

ELC

ESSI

RSSI

NBISS

M2S(1:0)

CFG_E2P(2:0)

DL_MT(3)

0

CHK_MT

SWC_MT

DIR

MODE_MT(1:0)

E2EPR

GET_MT

NCRC_MT

GRAY_MT

LNT_MT

SBL_MT(1:0)

CFGEW(7:0)

FRQ_TH(1:0)

NC_BISS

0

S2ERR

S2WRN

PROT_E2P(1:0)

AUTORES(1:0)

0

TRACMODE(1:0)

CALMODE(2:0)

DSR(1:0)

DTRI(1:0)

DSC(1:0)

CID_SCD(3:0)

TOS(1:0)

0

1

CRC_E2P(9:2)

CRC_E2P(1:0)

PRES_ST(7:0)

PRES_ST(15:8)

PRES_ST(23:16)

PRES_ST(31:24)

0

PRES_ST(38:32)

PRES_MT(7:0)

PRES_MT(15:8)

PRES_MT(23:16)

0x74

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 20/59

OVERVIEW

Adr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

STATUS Register (with read access)

0x75

0x76

0x77

TH_WRN

ACS_MAX

CMD_EXE

EPR_ERR

AM_MIN

AN_MIN

FRQ_WDR

AM_MAX

AN_MAX

FRQ_STUP

ACM_MIN

ACN_MIN

NON_CTR

ACM_MAX

ACN_MAX

MT_CTR

CT_ERR

AS_MIN

MT_ERR

RF_ERR

AS_MAX

MT_WRN

TH_ERR

ACS_MIN

COMMAND Register: MN_CMD (with write access)

0x77

0

MN_CMD(2:0)

Device Identiﬁcation (preset values after start-up without EEPROM)

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

Hints

0x4D ≡ M

0x4E ≡ N

Internal identiﬁer (0x04 ≡ Y2)

0

BANK_ACT*

GRAY_SCD

M2S(1:0)

DL_MT(3)

equivalent to address 0x4C

equivalent to address 0x3E

0x69 ≡ i

0x43 ≡ C

All registers can be written and read as long as no protection level has been set (see PROT_E2P). Addresses with gray

face box are located in the external EEPROM

*) Bank selection is active. BANK_ACT = 1, if CFG_E2P /= 000

Table 7: Register layout

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 21/59

OPERATING MODES and CALIBRATION PROCEDURES

iC-MN supports a number of different calibration troller signal CGUCKx available at pin T0 are devoid of

strategies, providing both digital and analog test sig- AC contents.

nals to this end. The following tables give the various

modes of operation.

In calibration modes TWIB and TEIB the temper-

ature monitoring and bias reference source IBP can

For the adjustment of the signal conditioning unit be adjusted. Here the temperature threshold is set to

analog test signals are output in analog calibration the required value for either warning or shutdown; the

modes ANA_x, with digital signals activated by digital other value is determined by the ﬁxed difference of the

calibration modes DIG_x, enabling the signal condi- switching thresholds.

tioning to be set across measurements of various duty

cycles. The order of the procedure for both modes of As the VTTx measurement voltages and CGUCKx sig-

calibration is described in the following chapter.

nals are only available via a buffer stage the buffer off-

set voltage must be taken into account if the tempera-

Alternatively, with an active signal level controller iC- ture thresholds are to be adjusted with any accuracy.

MN can be calibrated in controller modes AAC_x, To this end the buffer offset voltage can be measured

where the residual signal ripple is minimized. For this in calibration mode TBOS. A voltage is then applied

purpose the signal gain, offset and phase correction to pin T1, with the buffer offset voltage being the differ-

parameters must be set in such a way that the con- ence between this and pin T0.

Parameter

Output Signals

Op. Mode TRACMODE CALMODE BYP* Pins PSOUT, NSOUT, PCOUT, NCOUT Pin T0 Pin T1 Pin DIR

Normal

0

Output of master track via line driver

Table 8: Normal operating mode

0

-

Parameter

Output Signals

Op. Mode TRACMODE CALMODE BYP* Pins PSOUT, NSOUT, PCOUT, NCOUT Pin T0

Pin T1

Pin DIR

Signal calibration modes with VDCx intermediate voltages

ANA_M

ANA_S

ANA_N

1

2

3

0

1

0

1

0

1

Calib. signals of master chan.

PSINM, NSINM, PCINM, NCINM

Calib. signals of segment chan.

PSINS, NSINS, PCINS, NCINS

Calib. signals of nonius chan.

PSINN, NSINN, PCINN, NCINN

SVDCM

SVDCS

SVDCN

CVDCM

CVDCS

CVDCN

-

Signal calibration modes with AC noise evaluation (with active sine-square level controlling)

AAC_M

AAC_S

AAC_N

1

2

3

4

Calib. signals of master chan.

Calib. signals of segment chan.

Calib. signals of nonius chan.

CGUCKM

CGUCKS

CGUCKN

-

Bias calibration, temperature-sensor calibration, and buffer offset measurement

TWIB

TEIB

0

5

6

7

Output of master track via line driver

VTS_w

VTS_e

VTth

IBP

-

VTth_err

TBOS

Notes

BUFFOUT BUFFIN

S/D conversion modes with a cyclic conversion, such as 0x08, 0x09, 0x0A, are not permitted during

signal calibration. Cyclic BiSS data requests must also be avoided due to its trigger for sample-and-hold.

Analog calibration signals are output via 5 kΩ source impedance. The maximum permissible signal

frequency is 2 kHz for a load of 200 pF (see Elec. Char. 709, 710)

* Bypass function: inputs (without voltage divider) to outputs, ca. 7 kΩ source impedance

Table 9: Operating modes for analog signal calibration

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 22/59

Calibration Using

Comparated Sine/Cosine Signals

Parameter

Output Signals

Op. Mode TRACMODE CALMODE BYP* Pins PSOUT, NSOUT, PCOUT, NCOUT Pin T0

Pin T1

Pin DIR

Signal calibration modes with comparated sine/cosine signals

DIGO_M

DIGA_M

DIGP_M

DIGO_S

DIGA_S

DIGP_S

DIGO_N

DIGA_N

DIGP_N

1

2

3

1

2

3

1

2

3

1

2

3

Calib. signals of master chan.

Calib. signals of segment chan.

Calib. signals of nonius chan.

DIGOFFCOS DIGOFFSIN

-

0

DIGAMP

DIGPHASE

DIGOFFCOS DIGOFFSIN

0

DIGAMP

DIGPHASE

DIGOFFCOS DIGOFFSIN

0

DIGAMP

DIGPHASE

Table 10: Operating modes for digital signal calibration

Calibration Of Signal Offsets Calibration Of Signal Amplitudes And Phase

Fig. 3: The duty ratio is set accurately to 50 % using Fig. 5: To calibrate the duty cycle to exactly 50 % the

parameter OFS_x. This measurement requires a high ﬁne gain parameters GFC_x und GFS_x can balance

resolution, for instance of 0.06 %, for calibrating the off- the signal amplitudes. If a signal amplitude difference

set to 0.2 % with reference to the signal amplitude. The of 0.67 % remains after calibration, the interpolation

resulting interpolation error of 3 LSB (referred to a res- error enlarges to approx. 4.5 LSB at 13 bit resolution.

olution of 13 bits) corresponds to an angle error of 0.11

degree (360 degree means one signal period).

Fig. 6: Duty cycle calibration to exactly 50 % is carried

out using parameter PH_x. A remaining phase error of

Fig. 4: The duty ratio is set accurately to 50 % using 0.7 degree reduces the interpolation accuracy to 10 bit

parameter OFC_x.

(equal to 8 LSB error at 13 bit resolution, respectively).

degree

0.2

degree

0.2

0.1

0

0.1

0

-0.1

-0.2

-0.1

-0.2

0

90

180

270

360

0

90

180

270

360

Figure 3: Mode DIGO_x: DIGOFFSIN at Pin T1.

Figure 5: Mode DIGA_x: DIGAMP at Pin T1.

degree

0.4

degree

0.2

0.1

0

0.2

0

-0.1

-0.2

-0.4

0

90

180

270

360

0

90

180

270

360

Figure 4: Mode DIGO_x: DIGOFFCOS at Pin T0.

Figure 6: Mode DIGP_x: DIGPHASE at Pin T1.

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 23/59

SIGNAL CONDITIONING for MASTER-, SEGMENT- and NONIUS-Channel (x= M,S,N)

DCPOS

Addr. 0x0A; bit 6

Polarity I_sensor

Code

VREFin()

2.5 V

0

1

Negative

Positive

1.5 V

Table 12: Input current polarity

RIN

Addr. 0x0A; bit 2:1

Code

Resistance

1.6 kΩ

0

1

2

3

2.3 kΩ

3.2 kΩ

4.6 kΩ

Table 13: Input resistance with I mode

Voltage Signals

If the voltage signals are too large the input signal can

be quartered by an internal divider. The voltage divider

is referenced to the VREFin reference source which is

set by DCPOS. In order to use the input voltage range

of the input ampliﬁer to its full capacity DCPOS should

be set to 1 in voltage divider mode.

Figure 7: Schematic of Input Stage

The input stages for sine and cosine are instrumen-

tation ampliﬁers and can process current and voltage

signals; selection is made for all three tracks using

UIN. Signal conditioning should be performed in the

order given in the following.

TUIN

Code

0

Addr. 0x0A; bit 3

Function

Not active

UIN

Code

0

Addr. 0x0A; bit 0

Function

1

Voltage divider active

Table 14: Input voltage divider

I Mode: current inputs

V Mode: voltage inputs

1

Table 11: Signal mode

Additionally, using CVREF the user can select whether

VREFin is the reference potential generated internally

or a voltage provided externally.

CVREF

Code

00

Addr. 0x0B; bit 4:3

Function

Generated internally

01

Reserved

10

Internal VREFin() output to pin ACOS*

External ref. voltage supplied to pin ACOS

*) No load permitted, buffer required.

11

Figure 8: Direction of current ﬂow

Note

Table 15: VREF Source Selection

Current Signals

For current signals internal reference VREFin is

adapted to the input current polarity using DCPOS.

The input resistance is set using RIN (1:0). When All other settings are to be carried out for each indi-

selecting the input resistance the average potentials vidual track separately. A small x in the register name

SVDC and CVDC should be between 125 mV and stands for (M)aster, (S)egment and (N)onius respec-

250 mV to obtain a reasonable offset calibration range. tively.

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 24/59

Gain Adjustment

Offset Calibration

The gain is set in three stages. The gain range When calibrating the offset the offset reference source

is ﬁrst determined for sine and cosine using register must ﬁrst be selected using REFVOS (1:0). This set-

GR_x (2:0). Register GFC_x (4:0) can then be used ting is valid for all three tracks. If VDC is selected

to ﬁnely adjust the gain of the cosine track. In the as the offset reference SVDCx is the reference for the

ﬁnal stage of the process the amplitude of the sine sine track and CVDCx for the cosine. The VDC refer-

track is adapted to suit the cosine track using regis- ence enables the offset calibration to be automatically

ter GFS_x (10:0). With differential input signals the tracked dependent on the DC level of the input signal.

overall sine gain of one track is thus calculated as If ACO is chosen as the offset reference the voltage at

1

GAINS_x = GR_x * GFS_x; the total cosine gain is then pin ACOx, divided into /₂₀, acts as a reference. This

GAINC_x = GR_x * GFC_x.

enables the offset to be calibrated dependent on the

supply voltage of the sensor.

GR_M

Addr. 0x00; bit 2:0

GR_S

Addr. 0x10; bit 2:0

Addr. 0x20; bit 2:0

GR_N

Code

Coarse gain

0

1

2

3

4

5

6

7

6.0

12.4

16.2

20.2

26.0

31.6

39.5

48.0

Table 16: Gain range sine/cosine

GFC_M

GFC_S

GFC_N

Code k

0x00

Addr. 0x00; bit 7:3

Addr. 0x10; bit 7:3

Addr. 0x20; bit 7:3

k

31

Fine gain GFC = 6.25

1

0x01

1.07

1.13

...

0x02

...

Figure 9: Principle offset calibration circuit with se-

lectable reference sources.

0x1F

6.25

Table 17: Gain factor cosine

REFVOS

Addr. 0x0A; bit 5:4

Type of source

Code

GFS_M

GFS_S

GFS_N

Addr. 0x02; bit 2:0

Addr. 0x01; bit 7:0

Addr. 0x12; bit 2:0

Addr. 0x11; bit 7:0

Addr. 0x22; bit 2:0

0

1

2

3

Feedback of pin ACO

Reference V05

REFVOS = V(ACOx)/20

REFVOS = 0.5 V

Reference V025

REFVOS = 0.25 V

Tracked source VDC

REFVOS = SVDCx,

CVDCx

Addr. 0x21; bit 7:0

k

Table 19: Offset reference source

1984

Code k

0x000

0x001

0x002

...

Fine gain GFS = 6.25

1

1.0009

1.0018

...

Source VDC is to be used as reference for current

inputs. The average potentials of sine (SVDCx) and

cosine (CVDCx) are determined by:

0x7FF

6.6245

Table 18: Gain factor sine

SVDCx = (1 − k_s) · V(PSi) + k_s· V(NSi)

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 25/59

ORC_M

Addr. 0x06; bit 5:4

ORC_S

Addr. 0x16; bit 5:4

Addr. 0x26; bit 5:4

and

ORC_N

Code

Range

CVDCx = (1 − k_c) · V(PCi) + k_c· V(NCi)

0

1

2

3

maxVOSC_x = 3 * REFVOS

maxVOSC_x = 6 * REFVOS

Using MPS_x (9:0) and MPC_x (9:0) k_sand k_cshould

be conﬁgured in such a way that the AC fraction is min-

imal with both voltages.

maxVOSC_x = 18 * REFVOS

maxVOSC_x = 36 * REFVOS

Table 23: Offset range cosine

MPS_M

MPS_S

MPS_N

Addr. 0x03; bit 4:0

Addr. 0x02; bit 7:3

Addr. 0x13; bit 4:0

Addr. 0x12; bit 7:3

Addr. 0x23; bit 4:0

Addr. 0x22; bit 7:3

SVDC = (1 − k_s) · V(PSi) + k_s· V(NSi)

k_s= 0.3333

The achievable angle accuracy following interpolation

is affected by the internal signal strength and the offset

calibration step width, depending on the set correction

range and reference source. By way of example these

dependencies are shown in the following table, for half

and full scale signal levels (FS means 6 Vpp).

Code

0x000

0x001

...

k_s= 0.3336

...

Range

x Source

maxVOSC_x

maxVOSS_x

Cal. Step

Width (LSB)

Limitation Of

0x3FF

k_s= 0.6666

Angle Accuracy

@ 100 % (6 Vpp)

@ 50 % (3 Vpp)

Table 20: Intermediate voltage sine

3 x 0.25 V

6 x 0.25 V

6 x 0.5 V

750 mV

1.5 V

3 V

732 µV

none (>13 bit)

MPC_M

MPC_S

MPC_N

Addr. 0x04; bit 6:0

Addr. 0x03; bit 7:5

Addr. 0x14; bit 6:0

Addr. 0x13; bit 7:5

Addr. 0x24; bit 6:0

Addr. 0x23; bit 7:5

CVDC = (1 − k_c) · V(PCi) + k_c· V(NCi)

k_c= 0.3333

1465 µV

4396 µV

8789 µV

none (>13 bit)

0.08°, ca. 12 bit

0.16°, ca. 11 bit

18 x 0.5 V

9 V

0.16°, ca. 11 bit

0.32°, ca. 10 bit

Code

0x000

0x001

...

Table 24: Offset calibration and inﬂuence on angle ac-

curacy

k_c= 0.3336

...

0x3FF

k_c= 0.6666

The sine and cosine offsets are calibrated by a linear

voltage divider using OFS_x (10:0) and OFC_x (10:0).

Table 21: Intermediate voltage cosine

OFS_M

OFS_S

OFS_N

Addr. 0x06; bit 3:0

Addr. 0x05; bit 7:1

Addr. 0x16; bit 3:0

Addr. 0x15; bit 7:1

Addr. 0x26; bit 3:0

Addr. 0x25; bit 7:1

OFS_x = OffsS_x*maxVOSS_x

OffsS_x = 0

The calibration range for the offset of sine and cosine

is dependent on the source selected by REFVOS and

is set using ORS_x (1:0) and ORC_x (1:0). The offset

correction accuracy is inﬂuenced with the above.

ORS_M

ORS_S

ORS_N

Addr. 0x05; bit 0

Addr. 0x04; bit 7

Addr. 0x15; bit 0

Addr. 0x14; bit 7

Addr. 0x25; bit 0

Addr. 0x24; bit 7

Code

0x000

0x001

0x002

...

OffsS_x = -0.0009

OffsS_x = -0.0019

...

0x3FF

0x400

0x401

0x402

...

OffsS_x = -1

Code

Range

OffsS_x = 0

0

1

2

3

maxVOSS_x = 3 * REFVOS

maxVOSS_x = 6 * REFVOS

maxVOSS_x = 18 * REFVOS

maxVOSS_x = 36 * REFVOS

OffsS_x = 0.0009

OffsS_x = 0.0019

...

0x7FF

OffsS_x = 1

Table 22: Offset range sine

Table 25: Offset voltage sine

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 26/59

OFC_M

OFC_S

OFC_N

Addr. 0x08; bit 0

Addr. 0x07; bit 7:0

Addr. 0x06; bit 7:6

Addr. 0x18; bit 0

Addr. 0x17; bit 7:0

Addr. 0x16; bit 7:6

Addr. 0x28; bit 0

Addr. 0x27; bit 7:0

Addr. 0x26; bit 7:6

OFC_x = OffsC_x*maxVOSC_x

OffsC_x = 0

Phase Correction

The phase between sine and cosine is calibrated by

PH_x (9:0). With a phase error of 2.5° or more the am-

plitude and offset must be readjusted for a track reso-

lution accuracy of 13 bits.

PH_M

PH_S

PH_N

Addr. 0x09; bit 2:0

Addr. 0x08; bit 7:1

Addr. 0x19; bit 2:0

Addr. 0x18; bit 7:1

Addr. 0x29; bit 2:0

Addr. 0x28; bit 7:1

Code

0x000

0x001

0x002

...

OffsC_x = -0.0009

OffsC_x = -0.0019

...

Code

0x000

0x001

...

Function

+ 0 °

0x3FF

0x400

0x401

0x402

...

OffsC_x = -1

+ 0.0204 °

...

OffsC_x = 0

OffsC_x = 0.0009

OffsC_x = 0.0019

...

0x1FF

0x200

0x201

...

+ 10.396 °

- 0 °

- 0.0204 °

...

0x7FF

OffsC_x = 1

0x3FF

- 10.396 °

Table 26: Offset voltage cosine

Table 27: Sine/cosine phase correction

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 27/59

ANALOG PARAMETERS

ACOC_M(4:0)

Addr. 0x0C; bit 4:0

Signal Level Controller

Code

0x00

0x01

...

Setpoint

By tracking the sensor’s power supply via the con-

trolled current sources (outputs ACOM, ACOS and

ACON) iC-MN can keep the sine/cosine track signals

for the ensuing sine-to-digital converter constant re-

gardless of temperature and aging effects.

3.125% * I_max(ACOM)

6.25% * I_max(ACOM)

...

0x1E

0x1F

96.875% * I_max(ACOM)

100% * I_max(ACOM)

When adjusting the signal conditioning a constant cur-

rent source is used in place of the controlled current

source, the set current of which can be adjusted using

ACOR_M(6:0) or ACOR_x(5:0) (x = S, N). This current

must be so low as to leave enough reserve for tem-

perature and aging effects and ensure that no unnec-

essary power dissipation is generated. However, the

source current may not be too low so as to permit a

better signal contrast and improved signal to noise ra-

tio. Using this current the signal calibration can then be

performed so that the sine/cosine signals at the sine-

to-digital converter have a (differential) value of 6 Vpp

in their calibrated state. Once calibration has proved

successful the signal level controller can be activated.

Table 30: Current source setpoint, ACOM output

ACOT_S(7:6)

ACOT_N(7:6)

Addr. 0x1D; bit 0

Addr. 0x1C; bit 7

Addr. 0x2D; bit 0

Addr. 0x2C; bit 7

Code

00

Operating mode

Quadratic regulation active

Sum regulation active

Constant current source mode

Not permitted

01

10

11

Table 31: Controller op. mode, ACOS/ACON outputs

There are three integrated signal level control units in

iC-MN, all of which are powered by VACO. It is thus

possible to regulate each track individually or, in opti-

cal systems with an LED, for example, all three tracks

using the master signal level controller. If the control

unit’s working range is exceeded, an error is gener-

ated.

ACOR_S(5)

Addr. 0x1C; bit 5

ACOR_N(5)

Addr. 0x2C; bit 5

Code

Current range I_max(ACOS), I_max(ACON)

0

1

5 mA

10 mA

Table 32: Current source range, ACOS/ACON outputs

ACOT_M(8:7)

Addr. 0x0D; bit 0

Addr. 0x0C; bit 7

ACOC_S(4:0)

ACOC_N(4:0)

Addr. 0x1C; bit 4:0

Addr. 0x2C; bit 4:0

Code

00

Operating mode

Code

0x00

0x01

...

Setpoint

Quadratic regulation active*

Sum regulation active

Constant current source mode

Not permitted

3.125% * I_max(ACOS, ACON)

6.25% * I_max(ACOS, ACON)

...

01

10

11

0x1E

0x1F

96.875% * I_max(ACOS, ACON)

100% * I_max(ACOS, ACON)

*) Quadratic regulation of V()scq =

p

(V(PSOUT − V(NSOUT))²+ (V(PCOUT − V(NCOUT))²

Table 33: Current source setpoint, ACOS/ACON out-

put

Table 28: Controller op. mode, ACOM output

ACOR_M(6:5)

Addr. 0x0C; bit 6:5

Code

00

Current range I_max(ACOM)

5 mA

01

10 mA

25 mA

50 mA

10

11

Table 29: Current source range, ACOM output

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 28/59

Bias Current Source

required warning temperature T_w, temperature coef-

The calibration of the bias current source in operation ﬁcients TCs and TCth (see Electrical Characteristics,

mode TWIB or TEIB is prerequisite for adherence to Section C) and measurement value VTS_w(T_curr) are

the given electrical characteristics and also instrumen- entered into this calculation:

tal in the determination of the chip timing (e.g. SCL

clock frequency). For the calibration of source IBP to

its target value of 200 µA the voltage across the 5 kΩ

measurement resistor has to be adjusted to 1 V.

VTS_w(T_curr) + TCs · (Tw − T_curr

)

VTth(T_curr) =

TCth

1 +

· (Tw − T_curr

)

1+TCth·(T

−T

)

norm

curr

CFGIBP

Code k

0x0

Addr. 0x0D; bit 4:1

31

31−k

IBP ∼

The reference temperature T_normis 27 °C. Activation

threshold voltage VTth(T_curr) is provided for a high

impedance measurement (10 MΩ) at output pin T0 and

must be set by programming CFGTA(4:0) to the calcu-

lated value.

100.00 %

103.3 %

...

0x1

...

0xF

193.7 %

Table 34: Bias current source calibration

CFGTA

Addr. 0x0E; bit 1:0

Addr. 0x0D; bit 7:5

100+5k

100

Code k

0x00

0x01

...

VTth ∼

100 %

105 %

...

i C- M N

IBP

D I R

Pa ra m

TRACMODE

CALMODE

Co d e O p. M o d e

R

5kΩ

0x0

0x5

0x6

V

TWIB

TEIB

0x1F

255 %

G

N

D

A

Table 35: Calibration of temperature monitoring

Signal Noise Filters

Figure 10: Measurement circuit

Temperature Sensor

As regards temperature two settings can be made; ei-

ther a temperature threshold for an excessive tempera-

ture warning or an excessive temperature error can be

set. The excessive temperature error and warning are

coupled to one another (see Characteristics C07). Cal-

ibration of the excessive temperature warning in cali-

bration mode TWIB is described by way of example.

iC-MN has a noise ﬁlter for both the analog output

drivers and the sine-to-digital converter. These ﬁlters

can be activated by ENF.

ENF(0)

Addr. 0x0E; bit 1

Function

Code

0

1

Disabled

Sin/Cos Output driver noise ﬁlter activated

Table 36: Noise ﬁlter for the output drivers

To set the required warning temperature T_wthe tem-

perature sensor voltage VTS_w(T_curr) at which the warn-

ing is generated is ﬁrst determined. T_curris the actual

temperature. To this end a voltage ramp from VDD

towards GND is applied to pin T1 until pin NERR in-

dicates the error message. The necessary activation

threshold voltage VTth(T_curr) is then calculated. The

ENF(1)

Addr. 0x0E; bit 2

Function

Code

0

1

Disabled

S/D Conversion noise ﬁlter activated

Table 37: Noise ﬁlter for the sine-to-digital converter

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 29/59

SINE-TO-DIGITAL CONVERSION MODES

iC-MN has two principle modes of operation. In no- Internal Bit Lengths

nius modes 2 or 3 tracks are combined by a nonius The used bit length is set for the master, segment

calculation with synchronization; in multiturn modes and nonius tracks using registers UBL_M, UBL_S and

the up to 3 tracks are combined to form an absolute UBL_N. From these used bits the internal singleturn

word via gear box code synchronization.

data word is then generated, for which purpose syn-

chronization bits are used. The bit lengths used

The used and synchronization bit lengths (parameters for synchronization can be set separately via register

UBL_x and SBL_x) are selectable for both operating SBL_S for the segment track and register SBL_N for

modes; in multiturn modes it is also possible to output the nonius track. Limitations governing the settable bit

unsynchronized data from all tracks.

lengths are summarized in Table 41.

With both principle operating modes iC-MN offers var-

ious sine-to-digital conversion modes. With a data re-

quest via the I/O interface this determines:

UBL_M

Code

Addr. 0x3B; bit 5:2

Bit length master

0x00

0

0x01..0x03 not permitted

0x04

...

4

• The sample time and thus the ”age” of the output

data

...

13

0x0D

• The necessary processing time prior to genera-

tion of the output data word.

Table 38: Bit length master

UBL_S

UBL_N

Addr. 0x3C; bit 1:0

Addr. 0x3B; bit 7:6

Addr. 0x3D; bit 0

Addr. 0x3C; bit 7:5

Code

0x00

...

Used bit length

0

...

13

0x0D

Table 39: Used bit length for segment and nonius

SBL_S

SBL_N

Code

0x00

...

Addr. 0x3C; bit 4:2

Addr. 0x3D; bit 3:1

Synchronization bit length

0

...

4

0x04

Table 40: Synchronization segment and nonius

P

Track

Count of bits processed Possible bit count

Master

UBL_M

0, 4..13

Segment

Nonius

UBL_S+SBL_S

UBL_N+SBL_N

Table 41: Possible bit counts for

UBL_M and UBL_x+SBL_x

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 30/59

S/D CONVERSION with NONIUS CALCULATION

For the nonius modes iC-MN has a ﬂash counter which Output Data Veriﬁcation

counts the zero crossings of the master track. When It is possible to verify the counted period when a non-

the system is started this ﬂash counter is preloaded ius calculation has been completed. Possible settings

with the absolute period information which has been include:

most recently calculated using the nonius and segment

tracks (or only the nonius track).

1. No veriﬁcation of counted periods

The output data word always is the ﬂash counter value

2. Frequency-dependent veriﬁcation of counted pe-

synchronized with the master track. Furthermore, it is

riods. Exceeding the maximum master track sig-

possible to output synchronized singleturn and multi-

nal frequency set by FRQ_TH (see Table 46) dis-

turn position data which can be set using the parame-

ables the ﬂash counter veriﬁcation versus nonius

ter MODE_MT (see page 46).

calculation. If the limit is again undershot, future

conversions are again veriﬁed.

MODE_ST

Addr. 0x3D; bit 7:4

Operation modes with nonius calculation (Nonius Modes)

3. Period veriﬁcation versus nonius calculation is al-

ways enabled and executed with each conver-

sion.

Code

Description

Data outp. following S/D conversion of master track

Period veriﬁcation disabled

0x00

0x01

0x02

Frequency-dependent period veriﬁcation

Period veriﬁcation enabled

Op. Mode Descriptions Of Nonius Modes

Data output following S/D conversion of all tracks

Frequency-dependent period veriﬁcation

Period veriﬁcation enabled

0x03

0x04

MODE_ST Codes 0x00, 0x01, 0x02

With this mode the processing time is largely deter-

mined by the conversion time of the master track. The

conversion procedure is as follows:

Zero-delay data output: result of previously

triggered S/D conversion

0x05

0x06

0x07

Period veriﬁcation disabled

Frequency-dependent period veriﬁcation

Period veriﬁcation enabled

1. A data readout request triggers the conversion of

all selected tracks

Zero-delay data output: last result of background

S/D conversion (asynchronous)

0x08

0x09

0x0A

Period veriﬁcation disabled

2. Following conversion of the master track: syn-

chronization with the internal ﬂash counter and

output of the synchronized postion value

Frequency-dependent period veriﬁcation

Period veriﬁcation enabled

Zero-delay data output: last result of S/D

conversion triggered by pin T3

3. During data readout: conversion of the remaining

tracks and nonius calculation

0x0B

Period veriﬁcation enabled

Notes

On changing parameter MODE_ST during

operation command SOFT_RES should be issued.

4. Generation of NON_CTR with the next data read-

out cycle

Modes 0x08, 0x09, 0x0A are not permitted during

calibration via Op.Mode’s ANA_x oder DIGx_x.

Table 42: Nonius modes

MODE_ST Codes 0x03, 0x04

The processing time is largely determined by the sum

of the conversion time of the tracks for conversion. The

conversion procedure is as follows:

1. A data readout triggers the complete conversion

of the set tracks

2. Following conversion of the master track: syn-

chronization with the internal ﬂash counter

3. Following conversion of the remaining tracks: no-

nius calculation and generation of NON_CTR

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 31/59

4. Transmission of the synchronized position value. Principle PPR And Bit Length Dependencies

The transmitted NON_CTR counts as part of the With a nonius system with three tracks UBL_M must be

current conversion.

set so that it is at least as large as the maximum value

of MAX(UBL_S+SBL_S, UBL_N+SBL_N). If only two

tracks are used, UBL_S and SBL_S must be set to

zero. UBL_M must then at least match the maximal

value of MAX(UBL_N+SBL_N).

MODE_ST Codes 0x05, 0x06, 0x7

The processing time is low as "old" data is transmitted,

the time of sampling is, however, known (NB: The data

from the ﬁrst readout is invalid following a SOFT_RES).

The conversion procedure is as follows:

The necessary number of signal periods per revolution

for the individual tracks is then determined by the se-

lected used bit lengths:

1. With a data readout: immediate transmission of

the data from the last readout cycle including the

relevant NON_CTR

Track

Required signal periods

2^UBL_S+UBL_N

Master

Segment

Nonius

2. With a data readout: start of a new conversion

and providing of data for the next data readout

cycle. NON_CTR is output directly at the NERR

pin.

2^UBL_S+UBL_N− 2^UBL_N

2^UBL_S+UBL_N− 1

The following tables show the possible settings and

required number of signal periods. The total physi-

cal angle resolution in nonius mode is obtained from

the sum of UBL_M+UBL_S+UBL_N. At the same time

the bit lengths set for synchronization determine a limit

up to which a nonius calculation is possible. This limit

is given in Table 45 as the maximum tolerable phase

deviation which may occur between the segment and

master track or nonius and master track (with reference

to the electrical 360° period of the master signal).

MODE_ST Codes 0x08, 0x09, 0xA

The processing time is low and the time of sampling

not precisely known. The conversion procedure is as

follows:

1. Regardless of the data readout: permanent

background conversion

2. With a data readout: transmission of current

data. Each NON_CTR is output directly at the

NERR pin. In data transmission a NON_CTR er-

ror is only signaled when the error occurs during

the relevant nonius calculation.

Bits/Track

Signal periods/Turn

Physical

resolution ^a

)

UBL_S UBL_N Master Segm. Nonius min ^b

)

max

2

3

4

5

6

2

3

4

5

6

16

32

64

128

256

512

1024

2048

4096

12

28

56

120

240

496

992

2016

4032

15

31

63

127

255

511

1023

2047

4095

2+2+4

2+2+13

2+3+13

3+3+13

3+4+13

4+4+13

4+5+13

5+5+13

5+6+13

6+6+13

2+3+5

3+3+5

3+4+6

4+4+6

4+5+7

5+5+7

5+6+8

6+6+8

MODE_ST Code 0x0B

This mode can be used in systems in which sampling

must be synchronized to a frequency determined ex-

ternally and independent of the data readout cycles.

The conversion procedure is as follows:

^a) For conﬁguration of the output data length, see Table 51

^b) For the minimum data length SBL_x = 0x02 is assumed

1. A conversion with nonius synchronization is trig-

gered via pin T3. NON_CTR is output directly at

the NERR pin.

Table 43: Settings for 3-track nonius mode

2. With a data readout the most recent conversion

data triggered by pin T3 is transmitted including

the relevant NON_CTR.

Bits/Track Signal periods/Turn Physical resolution ^a

)

UBL_N

Master Nonius

min ^b

4+6

5+7

6+8

)

max

4

5

6

16

32

64

15

31

63

4+13

5+13

6+13

^a) For conﬁguration of the output data length, see Table 51

^b) For the minimum data length SBL_x = 0x02 is assumed

Table 44: Settings for 2-track nonius mode

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 32/59

UBL_N/ SBL_N/ Permissible Max. Phase Deviation

UBL_S SBL_S [given in degree per signal period of 360°]

Digital Frequency Monitoring

iC-MN features an integrated frequency monitoring cir-

cuit for the master track. A signal frequency warning

threshold can be conﬁgured by FRQ_TH.

2

3

4

5

6

2

3

4

2

3

4

2

3

4

2

3

4

2

3

4

+/- 22.5°

+/- 33.75°

+/- 39.38°

+/- 11.25°

+/- 16.88°

+/- 19.69°

+/- 5.63°

+/- 8.44°

+/- 9.84°

+/- 2.81°

+/- 4.22°

+/- 4.92°

+/- 1.41°

+/- 2.11°

+/- 2.46°

FRQ_TH

Code

00

Addr. 0x43; bit 7:6

Warning Threshold

7.625 kHz

31.25 kHz

62.5 kHz

125 kHz

01

10

11

Table 46: Signal frequency monitoring

FRQ_TH is used by the frequency-dependent period

veriﬁcation feature available for nonius modes (see

MODE_ST = 0x01, 0x03, 0x06 and 0x09).

Table 45: Tolerable phase deviation for the master ver-

sus the nonius or segment track (with refer-

ence to 360°, electrical)

The following applies to all modes with nonius synchro-

nization: if the frequency of the master track is too high

at power on, FRQ_STUP and FRQ_WDR remain set

until the period veriﬁcation was successful below the

frequency warning threshold. In nonius modes without

an enabled period veriﬁcation it must be observed that

FRQ_STUP remains permanently set and can only be

reset by SOFT_RES when the warning threshold is un-

dershot.

The synchronization principle is summarized in Figure

11, where ϕ represents the digitized angle of the rele-

vant track.

Figure 11: Principle of nonius mode synchroniza-

tion

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 33/59

S/D CONVERSION with MULTITURN SYNCHRONIZATION

In multiturn modes the output data word always Op. Mode Descriptions Of Multiturn Modes

matches the current converted and synchronized track

data. For 1 to 3 selected tracks parameters SBL_S and

SBL_N adjust the gear box synchronization, whereas MODE_ST Code 0x0C

the selected used bit lengths (UBL_x) determine the The processing time is largely determined by the sum

reduction ratio required for the multiturn gear box:

of the conversion time of the conﬁgured tracks. Proce-

dure of conversion:

Synchronization

Gear reduction

2^UBL_M

Master track ↔ Singleturn

Segment track ↔ Master track

Nonius track ↔ Segment track

1. A data readout request triggers the complete

conversion of the set tracks

2^UBL_S

2^UBL_N

2. Gear box synchronization

One limitation in multiturn mode is that neither an ex-

ternal multiturn can be conﬁgured nor counted mul-

titurn data output. Parameters MODE_MT and M2S

must be set to 0. Figure 12 shows the synchronization

principle, where ϕ represents the digitized angle of the

relevant track.

3. Transmission of the output data

MODE_ST Code 0x0D

The processing time is low as ”old” data is transmitted,

the time of sampling is, however, known. The conver-

sion procedure is as follows:

1. With a data readout: immediate transmission of

the data from the last readout cycle

2. With a data readout: start of a new conversion

and providing of data for the next readout cycle.

NB: The data from the ﬁrst readout is invalid following

a SOFT_RES.

MODE_ST Code 0x0E

The processing time is low and the time of sampling

not precisely known. The conversion procedure is as

follows:

Figure 12: Principle of multiturn synchronisation

1. Regardless of the data readout: permanent

background conversion

MODE_ST

Addr. 0x3D; bit 7:4

Operation modes with multiturn synchronization (MT Modes)

Code

0x0C

Description

2. With a data readout: transmission of current

data.

Data output following S/D conversion of all tracks

with MT synchronization conﬁgured via SBL_x

Data output: result of previously triggered S/D

conversion

MODE_ST Code 0x0F

0x0D

0x0E

with MT synchronization conﬁgured via SBL_x

This mode can be used in systems which require that

asynchronous sampling is independent of the data

readout timing. The conversion procedure is as fol-

lows:

Data output: last result of background S/D

conversion (asynchronous)

with MT synchronization conﬁgured via SBL_x

Data output: last result of S/D conversion triggered

by pin T3

0x0F

with MT synchronization conﬁgured via SBL_x

1. A conversion is triggered via pin T3, if applicable

with gear box code synchronization.

Notes

On changing parameter MODE_ST during

operation command SOFT_RES should be issued.

2. With a data readout the most recent output data

triggered by pin T3 is transmitted.

Table 47: Multiturn modes

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 34/59

S/D CONVERSION with DIRECT OUTPUT

iC-MN functions as a simultaneous sampling, 3- Op. Mode Descriptions Of Direct Output Modes

channel sine-to-digital converter when the multiturn

modes are selected with deactivated synchronization.

When SBL_S = 0 and SBL_N = 0 no track synchro- MODE_ST Code 0x0C

nization takes place; the data from all three tracks is The processing time is largely determined by the sum

queued up for output without any further processing.

of the conversion time of the conﬁgured tracks. The

conversion procedure is as follows:

1. A data readout request triggers the complete

conversion of the set tracks

2. Transmission of the output data

MODE_ST Code 0x0D

The processing time is low as ”old” data is transmitted,

the time of sampling is, however, known (NB: The data

from the ﬁrst readout is invalid following a SOFT_RES).

The conversion procedure is as follows:

Figure 13: Principle of simultaneous sampling, 3-

channel S/D conversion with direct data

output

1. With a data readout: immediate transmission of

the data from the last readout cycle

MODE_ST

Addr. 0x3D; bit 7:4

2. With a data readout: start of a new conversion

and providing of data for the next readout cycle.

Direct output via MT modes with deactivated

synchronization

Code

Description

Data output following S/D conversion of all tracks;

synchronization disabled (SBL_x = 0)

MODE_ST Code 0x0E

0x0C

The processing time is low and the time of sampling

not precisely known. The conversion procedure is as

follows:

Data output: result of previously triggered S/D

conversion;

0x0D

0x0E

synchronization disabled (SBL_x = 0)

Data output: last result of background S/D

conversion (asynchronous);

1. Regardless of the data readout: permanent

background conversion

synchronization disabled (SBL_x = 0)

Data output: last result of S/D conversion triggered

by pin T3;

2. With a data readout: transmission of current

data.

0x0F

synchronization disabled (SBL_x = 0)

Notes

On changing parameter MODE_ST during

operation command SOFT_RES should be issued.

MODE_ST Code 0x0F

This mode can be used especially for resolver sys-

tems, in which 1 to 3 channels need to be sampled in

synchronism with a speciﬁc carrier frequency. An ex-

ternal trigger signal supplied to pin T3 takes over the

sampling control and thus decouples it from the data

readout timing. The conversion procedure is as fol-

lows:

Table 48: MT modes used for direct output

1. A conversion is triggered by pin T3

2. With a data readout the most recent output data

triggered by pin T3 is transmitted.

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 35/59

TRACK OFFSET CALIBRATION

SPO_N

SPO_S

Addr. 0x3B; bit 1:0

Depending on the track resolution the offset values of

the nonius and segment tracks (POV = Phase-Offset-

Value) must be justiﬁed to the left in the SPO_N and

SPO_S registers. These offsets are added to the con-

version result of each track prior to synchronization

and are instrumental in calibrating the track.

Addr. 0x3A; bit 7:0

Addr. 0x39; bit 7:5

Addr. 0x39; bit 4:0

Addr. 0x38; bit 7:0

0x0000

. . .

Track Offset

0x1FFF

datalength defined by UBL_x+SBL_x

Table 49: Track offsets for nonius and segment

MSB

POV_x

LSB

POV_x

SPO_x

register:

0

Note: For nonius synchronization (see MODE_ST) it is

important that the used tracks within the 2^UBL_S+UBL_N

master track periods have a shared zero crossing

once. With SPO_S or SPO_N the segment and nonius

tracks can be shifted to the master track accordingly.

S: ADR 0x38, bit 0

N: ADR 0x39, bit 5

S: ADR 0x39, bit 4

N: ADR 0x3B, bit 1

Figure 14: SPO_x (x=S,N)

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 36/59

I/O INTERFACE

TOS

Code

00

Addr. 0x4C; bit 1:0

Protocol

Timeout t_out

typ. 16 µs

Internal clock counts

iC-MN can transmit position data according to the SSI

protocol where both data length and error messag-

ing are conﬁgurable. The selected mode of opera-

tion for sine-to-digital conversion can limit the permissi-

ble SSI clock frequency (see Operating Conditions on

page 15). The highest possible SSI clock frequency

of 4 MHz is permissible for converter modes with an

immediate data output.

31-32

15-16

3-4

01

typ. 8 µs

10

typ. 2 µs

11

typ. 1 µs

1-2

4

fosc

Notes

One clock count is equal to

(see Char. A01)

Table 50: Timeout

Figure 15: Example of SSI line signals

DL_ST

Addr. 0x3E; bit 4:0

Output Data Length

Code

0x00

...

Bit count

For singleturn data lengths (DL_ST) which are less

than 13 bits the SSI data word is zero ﬁlled. The op-

tional error bit is always the ﬁnal bit of the data word.

8 bit plus zeroes (+1 error bit)*

...

0x05

...

13 bit (+1 error bit)*

...

If enabled by M2S, multiturn data is always transmitted

upfront the singleturn data. The format option Gray or

binary code covers the MT and ST data word in its en-

tirety; ﬁlled in zeros and the error bit remain untouched.

0x11

25 bit (+1 error bit)*

Bit counts listed below are valid only for multiturn

synchronization mode (s.P. 30 ff.)

0x12

...

26 bit (+1 error bit)*

...

The output bit count is determined by parameters

DL_ST, M2S and ESSI:

0x19

0x1A

Notes

33 bit (+1 error bit)*

39 bit (+1 error bit)*

*) When enabled by ESSI = 1

max(13, DL_ST+ESSI) + MT bits

Table 51: ST Data length

Example: DL_ST = 0 (≡8 Bit); ESSI = 1.

Result: 8 bits of data + 4 zeros + 1 error bit are trans-

mitted = 13 bits of data.

M2S

Code

00

Addr. 0x3F; bit 2:1

Function

no output

01

MT data output of lowest 4 bits

MT data output of lowest 8 bits

Complete output, MT bit count following DL_MT

10

11

Table 52: MT Data output

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 37/59

RSSI

Code

0

Addr. 0x3F; bit 4

Output Options

Ring operation

Normal output

If the clock count exceeds the data length, zero bits

are supplied.

ESSI

Addr. 0x3F; bit 5

Error bit output

Not included

Error bit enabled

Code

1

Ring operation

0

1

Notes

When enabling RSSI with the BiSS C protocol, pin

SLI reads in data to be output via SLO.

Table 53: Error bit

Table 55: Ring operation

GRAY_SCD

Addr. 0x3F; bit 7

Data format

The behavior of the output data depending on the

sense of rotation can be altered using pin DIR or via

register DIR. Both signals are EXOR-gated and switch

output data from increasing to decreasing values or

vice versa.

Code

0

1

Binary coded

Gray coded

Table 54: Data format (covers MT and ST data)

DIR

Code

0

Addr. 0x3D; bit 6

Code direction

Not inverted

Inverted

1

Table 56: Code direction up/down

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 38/59

I/O INTERFACE with EXTENDED FUNCTIONS

NBISS

Addr. 0x3F; bit 3

Protocol

Code

For the fast and safe transmission of converter data iC-

MN’s serial I/O interface has a BiSS C protocol which

enables bidirectional register communication without

changing the permanent cyclic data output. In order to

simplify master implementation at the control unit end

this protocol does not utilize multicycle data.

0

1

BiSS C protocol (NC_BiSS = 0, RSSI = 1)

Advanced SSI protocol (NC_BiSS = 0)

SSI protocol (NC_BiSS = 1)

Table 57: Interface protocol

Alternatively, an advanced SSI protocol can be se-

lected which permits unidirectional register communi-

cation for the transferral of parameters from the master

to the slave iC-MN.

TOS

Code

00

Addr. 0x4C; bit 1:0

Timeout t_out

typ. 16 µs

Internal clock counts

31-32

15-16

3-4

01

typ. 8 µs

10

typ. 2 µs

11

typ. 1 µs

1-2

4

fosc

Notes

One clock count is equal to

(see Char. A01)

Table 58: Timeout

Figure 16: Example of line signals for BiSS C protocol

Figure 17: Example of line signals for Advanced SSI protocol

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 39/59

Output Data Length

The code direction of the output data word can be al-

The output bit count is derived from the parameters tered using pin DIR or register DIR. Both signals are

DL_ST, M2S and DL_MT. In accordance with the se- EXOR-gated and together comprise the internal direc-

lected protocol two additional bits for the error and tion of rotation signal.

warning messages are always transmitted.

DIR

Code

0

Addr. 0x3D; bit 6

The output bit length for singleturn data can be set in-

dependent of the internal converter resolution. For bit

lengths which exceed the internal word length the data

following the LSB is zero ﬁlled. If enabled by M2S mul-

titurn data is always transmitted before singleturn data.

Direction of rotation

Not inverted

Inverted

1

Table 62: Inversion of code direction

DL_ST

Code

0x00

...

Addr. 0x3E; bit 4:0

Bit count

For reasons of data security iC-MN provides ﬁxed CRC

polynomials (see Table 63). The CRC start value can

be freely selected, thus enabling a PLC to clearly allo-

cate data to the source (for safety applications). Reg-

ister communication can be optionally blocked by pa-

rameter NC_BiSS.

8 bit +2 bit for E/W

...

0x05

...

13 bit +2 bit for E/W

...

0x11

25 bit +2 bit for E/W

Bit counts listed below are valid only for multiturn

synchronization mode (see P. 30)

Data

Channel

CRC

HEX Code

Polynomial

Calculation

Start Value

0x12

...

26 bit +2 bit for E/W

...

SCD

0x43

x⁶+x¹+x⁰

x⁴+x¹+x⁰

see CID_SCD

0x0

CDM, CDS 0x13

0x19

0x1A

33 bit +2 bit for E/W

39 bit +2 bit for E/W

Table 63: BiSS CRC polynomials

Table 59: ST Data length

CID_SCD

Code

0x00

Addr. 0x4C; bit 7:4

CRC start value SCD

M2S

Code

00

Addr. 0x3F; bit 2:1

Function

. . .

CID_SCD

No output

0x0F

01

MT data output of lowest 4 bits

MT data output of lowest 8 bits

Complete output, MT bit count following DL_MT

10

Table 64: CRC start value for SCD

11

NC_BISS

Addr. 0x43; bit 2

Function

Table 60: MT Data output

Code

0

1

BiSS C register communication enabled

Output Options

Communication disable

(no execution of commands, no access to RAM or

EEPROM

The Gray or binary code format option covers the sin-

glecycle word in its entirety (MT and ST data); only

ﬁlled in zeros and the error and warning bits remain

unaltered.

Notes

If the device setup and a set communication disable

NC_BiSS are to be stored to the EEPROM, the

preset function can be triggered at pin PRES.

GRAY_SCD

Addr. 0x3F; bit 7

Data format

Table 65: Communication disable

Code

0

1

Binary coded

Gray coded

Table 61: Data format (covers MT and ST data)

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 40/59

ELC

Code

0

Addr. 0x3F; bit 6

Function (only with BiSS C protocol)

Safety Application Settings

It is possible to transmit a life counter value in the sen-

sor data for safety applications. When the life counter

is activated, a 6-bit counter value is transmitted in the

sensor data which is incremented with each new sen-

sor data readout. The life counter has a range of 1 to

64.

Life counter not active

Life counter enabled

1

Table 66: Life counter

Figure 18: Example of line signals for BiSS C protocol with life counter

the two slaves. Should the busy register not be sufﬁ-

Busy Register

iC-MN has a 16-bit busy register. If, for example, two cient, i.e. should iC-MN need longer to convert data

identically conﬁgured iC-MNs are connected up to the than the subsequent slave, iC-MN generates the start

BiSS master as slaves in a chain, with the help of the bit and marks the data it has output as faulty. This en-

busy register an internal clock jitter can be avoided sures that the data of the ensuing slave is not lost.

which could lead to different data conversion times for

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 41/59

CONFIGURATION OF DIGITAL DRIVER OUTPUTS

DSC

Code

00

Addr. 0x48; bit 1:0

The digital outputs SLO and NSLO can be used as ei-

ther a push-pull, lowside or highside driver. The mode

of operation is determined by DTRI. The driving capa-

bility is set via the short-circuit current parameter.

Short-circuit current

50 mA

01

20 mA

10

4 mA

11

1.2 mA

In order to meet RS422 speciﬁcations a short-circuit

current of 50 mA should be selected as well as to re-

duce the internal power dissipation. The driving ca-

pability can be reduced when external line drivers are

used.

Table 68: Driver short-circuit current

DSR

Addr. 0x48; bit 5:4

Code

Slew rate

Permissible

transmission frequency

In order to reduce crosstalk and to improve EMC the

slew rate can be selected to suit the line length. If

the edge steepness is reduced to 300 ns the maxi-

mum permissible transmission frequency is limited to

ca. 300 kHz if RS422 speciﬁcations are to be adhered

to.

00

01

10

11

10 ns

10 MHz max.

3 MHz max.

1 MHz max.

300 kHz max.

30 ns

100 ns

300 ns

Table 69: Driver slew-rate

DTRI

Code

00

Addr. 0x48; bit 3:2

Operating mode

Push-pull operation

01

Highside driver mode (P channel open drain)

Lowside driver mode (N channel open drain)

Not permitted

10

11

Table 67: Driver output mode

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 42/59

COMMAND and STATUS REGISTERS

Execution Of Internal Commands

command can be used for SSI encoders to later enable

The command register at address 0x77 can be ac- parameterization, for example.

cessed fully independent of the internal state of op-

eration. Depending on the data value written to this Execution Of Protocol Commands

register the execution of an implemented command is iC-MN supports selected BiSS C protocol commands:

triggered.

CMD

Selected address

(IDS > 0x00)

Broadcast address

(IDS = 0x00)

MN_CMD

Code

Addr. 0x77; bit 2:0

Command

W

10

11

Execute SOFT_PRES

Execute CRC_CHECK

-

Description

0x0

SOFT_RES

Soft reset

(new startup using

internal conﬁg. data)

Table 71: Implemented protocol commands

0x1

WRITE_CONF

Transfers internal conﬁg.

data to the EEPROM

Automatic Reset Function

0x2

0x3

SOFT_PRES

CRC_CHECK

Calls preset routine

AUTORES can be used to set whether the command

SOFT_RES is automatically generated or not if the er-

ror AM_MIN occurs.

CRC veriﬁcation of the

internal conﬁg. data

0x4

TOG_BISS

No function

Temporal toggle of

interface protocol:

BiSS C ↔ SSI

AUTORES

Addr. 0x44; bit 1:0

Function

...0xF

Code

00

No automatic reset

Table 70: Implemented commands

01

SOFT_RES after error AM_MIN, timeout 8 ms

SOFT_RES after error AM_MIN, timeout 16 ms

SOFT_RES after error AM_MIN, timeout 32 ms

10

11

The command SOFT_RES resets internal state ma-

chines, counters, and the status registers. The conﬁg-

uration RAM is not reset here. During the command

execution a write access to the conﬁguration RAM is

still possible, whereas the external EEPROM is not ac-

cessible.

Table 72: Automatic reset function

For as long as the amplitude of the master track is too

low or the AM_MIN error is set, SOFT_RES is active.

When AM_MIN is no longer set, the timeout conﬁg-

ured using AUTORES expires. It is only after this that

SOFT_RES is reset and the device subsequently re-

turns to normal operation.

If the device is in nonius mode (see page 30), the ﬁrst

conversion is used to determine the period and the re-

sult stored as an initial value for the period fraction of

the internal ﬂash counter. If an external multiturn de-

vice is conﬁgured (MODE_MT = 00), its data is read

in and stored as the initial value for the multiturn data

fraction of the internal ﬂash counter.

Should an AM_MIN error occur while a command or

the preset function is being carried out, SOFT_RES is

only implemented once the command has been termi-

nated.

With WRITE_CONF the internal conﬁguration is stored

to the EEPROM. The CRC (CRC_E2P) is automat-

ically updated and written to address 0x4E or 0x4F.

For a description of the preset routine initiated by

SOFT_PRES see page 50.

The behavior of the I/O interface with an active

SOFT_RES depends on the protocol selected. For

BiSS C a zero is returned as a data value and the error

and warning bits are set; for SSI the last data value to

be output is repeated (the error bit is set if conﬁgured

via SSIE). In both cases the error state is indicated at

pin NERR by a low signal.

CRC_CHECK starts a CRC veriﬁcation of the inter-

nal conﬁguration RAM. During the check the internal

data bus may not be accessed. Should the check not

conﬁrm the conﬁguration data as error free, status bit

EPR_ERR is set.

Command TOG_BISS only causes the communication

protocol to switch temporarily (BiSS → SSI, or SSI →

BiSS). RAM parameter NBISS is not altered here. The

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 43/59

Status Register

ROM has been recognized, EPR_ERR remains set

The status register is reached by a read access to ad- even after SOFT_RES.

dresses 0x75 to 0x77. In the event of an error the

relevant bit is set and maintained until the status reg- CMD_CNV and CMD_EXE are signaled on the same

ister is read out or the command SOFT_RES is per- status bit and not stored, as opposed to the other

formed (with the exception of status bits EPR_ERR status bits. CMD_CNV is set on the initialization

and CMD_EXE). The status register can be accessed of a command which requires the internal converter.

independent of the internal state of operation.

CMD_EXE is set on commands which employ the in-

ternal data bus.

STATUS

Addr. 0x75; bit 7:0

R

STATUS

Addr. 0x77; bit 7:0

R

Bit

7

Name

TH_WRN

Description of status message

Excessive temperature warning

Bit

7

Name

Description of status message

CMD_EXE Command execution in progress, or

CMD_CNV iC-MN in startup phase

6

EPR_ERR Conﬁguration error on startup:

- No EEPROM (ﬂag EPR_NO set)

6

5

4

3

2

1

0

AN_Min

AN_Max

ACN_Min

Signal error: poor level (nonius track)

Signal error: clipping (nonius track)

Control error: range at min. limit

- Invalid check sum (ﬂag EPR_NV set)

5

4

3

2

1

FQ_WDR

Excessive signal frequency on master track*:

on current readout request

FQ_STUP Excessive signal frequency on master track*:

during startup

ACN_Max Control error: range at max. limit

AS_Min

AS_Max

ACS_Min

Notes

Signal error: poor level (segment track)

Signal error: clipping (segment track)

Control error: range at min. limit

NON_CTR Period counter consistency error:

counted period ↔ calculated Nonius position

Multiturn data consistency error:

counted multiturn ↔ external MT data

Multiturn communication error:

- Error bit set

MT_CTR

MT_ERR

Error indication logic: 1 = true, 0 = false

Table 75: Status register 0x77

- CRC error

- No start bit

- General communication error

Non-Volatile Diagnosis Memory

By enabling E2EPR all status messages can be stored

to the external EEPROM the ﬁrst time they occur

(physical EEPROM addresses 0x75 to 0x77).

0

MT_WRN

Notes

Multiturn data indicates warning message

(BiSS warning bit set)

*) Relevant for nonius synchronization

modes (MODE_ST = 0x00 to 0x0B); the

warning threshold can be set using

parameter FRQ_TH;

On a system startup iC-MN reads in the status mes-

sages already stored in the EEPROM. As soon as an

error message occurs which has not been noted in the

external memory the corresponding status register bit

is transfered to the EEPROM. This way a "cumulative"

error register is compiled in which all messages are

stored which occur during operation. Only the current

errors can be read out via the status register (BiSS ad-

dresses 0x75 to 0x77).

Error indication logic: 1 = true, 0 = false

Table 73: Status register 0x75

STATUS

Addr. 0x76; bit 7:0

R

Bit

7

Name

ACS_Max

Description of status message

Control error: range at max. limit

Signal error: poor level (master track)

Signal error: clipping (master track)

Control error: range at min. limit

6

AM_Min

AM_Max

ACM_Min

5

The cumulative errors which are stored at EEPROM

addresses 0x75 to 0x77 can only be read out via BiSS

with CFG_E2P > 000 and PROT_E2P = 00 to bank 1,

address 0x35-0x37 (see page 52 ff. for memory map).

4

3

ACM_Max Control error: range at max. limit

2

CT_ERR

RF_ERR

Readout cycle repetition to short*

1

Excessive SSI clock frequency: conversion

data not valid when latching data for output.

Note: Once conﬁguration has been completed and be-

fore the system is delivered the data at the EEPROM

addresses 0x75 to 0x77 should be initialized with ze-

roes.

0

TH_ERR

Notes

Excessive temperature error

*) Relevant for nonius synchronization

modes MODE_ST = 0x00 to 0x07

(calculation routines must end before a new

request is received)

Error indication logic: 1 = true, 0 = false

E2EPR

Addr. 0x41; bit 7

Description

Code

Table 74: Status register 0x76

0

1

Disabled

EEPROM savings of cumulative status messages

enabled

EPR_ERR indicates that no EEPROM was found on

system startup (EPR_NO) or that a CRC error was rec-

ognized for the internal setup (EPR_NV). If no EEP-

Table 76: Diagnosis memory enable

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 44/59

ERROR AND WARNING BIT

For the error and warning bit output the logic is always featuring open-drain alarm outputs a wired-or bus logic

low active; a logic zero displays an active error or warn- can be installed.

ing message. With the exception of an external system

EXT_ERR

error message (read in via I/O pin NERR and assigned

Code

Description

to EXT_ERR) all error codes mentioned in the follow-

ing are stored in the status register should the corre-

sponding error event occur.

0

1

No external error

External component indicating an error to pin

NERR

The allocation of error messages to the error and warn-

ing bit is either ﬁxed or can be varied with the CFGEW

parameter. The following tables explain the ﬁxed and

optional visibility.

Table 79: External error message

CFGEW

Adr 0x42, bit(7:0)

Visibility for error bit

Ax_MAX, Ax_MIN

EXT_ERR

Fixed Allocation Of Error Messages

Bit

7

Message

Visibility via error bit

Conditions

None

EPR_NV*

EPR_NO

CMD_CNV**

CT_ERR

•

6

5

TH_ERR

Enables additional functions, please refer to the

description given below.

RF_ERR

•

Visible when

NBISS = 1

Bit

Visibility for warning bit

FQ_WDR

4

MT_ERR

MT_CTR

Visible when

MODE_MT = 01, 10

3

Ax_MAX and Ax_MIN

ACx_MAX and ACx_MIN

TH_WRN

NON_CTR

FQ_STUP

Visible when

MODE_ST set for

nonius synch.

2

1

0

MT_WRN

Notes

*) Reset by command SOFT_RES

**) CMD_CNV is also visible for warning bit.

Notes

x = M, S, N

Encoding of bit 7...0:

0 = message enabled, 1 = message disabled

Table 77: Fixed allocation of messages for error bit in-

dication

Table 80: Error and warning bit conﬁguration

Variable Allocation Of Error Messages

The visibility of the temperature error can be conﬁg-

ured on the error bit by CFGEW(5) = 0. The occurrence

of a temperature error then causes:

Message

Visibility via error bit

Visibility via warning

bit

MT_WRN

TH_WRN

FQ_WDR

ACx_MAX

ACx_MIN

Ax_MAX

Ax_MIN

n/a

◦

1. The setpoint of the signal level controller to be

reduced to the lowest setting

◦

2. The analog output voltages to switch to VDD/2 at

outputs PSOUT, NSOUT, PCOUT and NCOUT

◦

TH_ERR

EXT_ERR

Notes

◦

n/a

3. The RS422 output driving capability to be limited

to 20 mA.

◦ = conﬁgurable via CFGEW

x = M, S, N

The following must also be taken into account:

Table 78: Variable allocation of error messages for er-

ror/warning bit indication

• Error messages which are signaled via the error

bit of the serial I/O interface are also indicated by

a low signal at the NERR pin

EXT_ERR can only be conﬁgured to the error bit and

is not latched by the status register. It permits iC-MN to

signal an error state of further ICs to the PLC, when the

messaging IC pulls down the NERR pin. With devices

• Nonius synchronization errors (NON_CTR) are

indicated directly at the NERR pin

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 45/59

• Temperature and signal level errors are indicated of the error bit and the NERR pin can be inﬂuenced by

directly at the NERR pin. These errors are only S2ERR.

signaled via the error bit if they are active at the

point when data is accepted into the output shift

register.

S2WRN

Addr. 0x43; bit 2

Code

Visibility for warning bit

0

1

Current messages conﬁgured to the warning bit

As above, or-gated with latched status messages

which are conﬁgured to the warning bit

All errors which occur during operation are stored in

the status register regardless of the conﬁguration of

the error/warning bit (see page 43).

Table 81: Visibility for warning bit

S2ERR

Addr. 0x43; bit 3

Code

Visibility for error bit and NERR

Current messages conﬁgured to the error bit

Visibility Of Latched Status Messages

0

1

Parameter S2WRN enables status messages conﬁg-

ured to the warning bit using CFGEW and stored in the

status register to be output to the warning bit. In this

instance the warning bit is set until the relevant status

register is read out. Parallel to S2WRN the behavior

As above, or-gated with latched status messages

which are conﬁgured to the error bit

Table 82: Visibility for error bit (and NERR pin)

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 46/59

MT INTERFACE

In nonius modes iC-MN can connect to an external

ST MSB-1

multiturn sensor via the serial MT interface. Follow-

ing synchronization of the MT data with the ST data

the multiturn period counter is set to its initial position.

ST MSB

Each further revolution is then logged by the internal

period counter.

MT LSB -1

MT LSB

Even when the MT interface is not employed, the in-

ternal 24-bit multiturn period counter can be conﬁg-

ured to complement singleturn position data output by

multiturn

data output

a counted multiturn position (see M2S).

MT LSB -1

MT LSB

Additionally, the MT interface can be conﬁgured as a

parallel two-pin interface to read in a single bit multi-

turn position accompanied by a synchronization bit. In

this way coverage of the absolute singleturn position

can be doubled if additional sensors provide 180 and

90 degree sector information.

multiturn

data output

+1

MT LSB -1

MT LSB

multiturn

data output

MODE_MT

Code

00*

Addr. 0x40; bit 4:3

Function

-1

°/ST

Multiturn position counted internally

Serial MT interface active (SSI)

10*

Figure 19: Principle of MT synchronization for 1 bit

and 2 bit synchronization signals

11*

Parallel MT interface active (2-bit mode):

Pin MTMA is input for 180° and pin MTSLI input for

90° sector information

Notes

*) NCRC_MT = 0 required

If MODE_MT is altered during operation, command

SOFT_RES must be issued (see page 42).

Table 83: MT Interface operation mode

With a synchronization bit length of two or more bits

iC-MN ignores parameter LNT_MT selecting for lead-

ing or trailing MT data. Synchronization bit lengths of

3 bit or 4 bit enlarge further the synchronization toler-

ance between multiturn and singleturn (see Table 85).

Conﬁguration Of Data Lengths

The bit length of the internal MT counter and of the

multiturn data word is set using parameter DL_MT.

For synchronization purposes the synchronization bit

length must be set by SBL_MT. Synchronization oc-

curs between the external multiturn data read in and

the period information counted internally. At synchro-

nization bit lengths > 1 bit synchronization can occur

automatically within the relevant phase tolerances.

DL_MT

Code

0x00

...

Addr. 0x3E; bit 7:5

Multiturn bit count*

With a single synchronization bit (SBL_MT = 00) no au-

tomatic synchronization can take place. Here, iC-MN

cannot recognize whether the external multiturn sen-

sor provides leading or trailing position data (what may

vary depending on gear box assembly). This must be

set manually by parameter LNT_MT.

8

...

20

24

1

0x0C

0x0D

0x0E

0x0F

Notes

4

*) Does not include synchronization bits of the

external MT sensor.

Figure 19 shows the principle of MT synchronization

for ideal signals (without indication of synchronization

tolerance limits). It shows 2 bit and 1 bit synchroniza-

tion for leading and trailing signals.

Table 84: MT data length (and counter depth)

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 47/59

SBL_MT

Addr. 0x41; bit 1:0

further readouts are attempted and MT_ERR remains

permanently set.

Code

MT synchronization bit

length

Synchronization range

(ST resolution)

00

01

10

11

1 bit

2 bit

3 bit

4 bit

± 90°

startup

sequence with

16 ms timeout

± 90°

± 135°

± 157.5°

Table 85: MT synchronization bit length

mt-error-counter ++

read external

multiturn

LNT_MT

Addr. 0x41; bit 2

yes

mt_error-counter < 4

no

Code

Function (single sync. bit, SBL_MT = 0x00)

serial-communication error?

yes

0

1

Trailing

Leading

no

set MT_ERR

Table 86: Leading/trailing gear box assembly

sync to flashcounter

proceed with

startup-sequence

proceed with

Via CHK_MT the device can be conﬁgured so that the

counted multiturn period is veriﬁed every 8 ms. An

error in the multiturn check (the comparison of the

counted multiturn period and the external multiturn po-

sition data) is signaled via the error bit (MT_CTR is set

in the status register, see page 43).

startup-sequence

no further multiturn-readouts

started

Figure 20: Error handling during start up phase

normal operation:

ready for

sensordata-requests

CHK_MT

Addr. 0x40; bit 6

Function

Code

CHK_MT?

0

1

Veriﬁcation disabled

Cyclic veriﬁcation each 8 ms

yes

start timer

Table 87: Period counter veriﬁcation

GRAY_MT

Addr. 0x41; bit 3

Data format

read external

multiturn

timer == 8 ms?

yes

Code

0

1

Binary coded

Gray coded

sync to flashcounter

and compare to counted

multiturn-value

serial

communication

error?

no

Table 88: MT Interface data format

yes

no

compare-error?

yes

Error Handling

If a communication error appears when reading in ex-

ternal multiturn data during the startup phase (such

as pin MTSLI reading a permanent logic 0 or the exter-

nal MT sensor not responding), the ﬁrst conversion and

request for the external multiturn data are repeated up

to three times (see Figure 20). If the error persists after

a fourth attempted readin, the device goes into normal

operating mode. Conversion requests for the single-

turn position data are possible, but MT_ERR remains

permanently set.

set MT_CTR

set MT_ERR

Figure 21: Error handling during normal operation

with cyclic period counter veriﬁcation

M TMA

M TSL I

M

S

B

L

S

B

D

L

_

M

T

+

S

B

L

_

M

T

t

o

u

t

The error handling in normal operating mode when

the multiturn data veriﬁcation is activated is shown in

Figure 21. If there is an error in communication no

Figure 22: Line signals of the serial MT interface

MODE_MT = 0x10 (SSI)

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 48/59

MT Interface with 2-bit mode

max

In this mode pin MTMA functions as an additional in-

put, besides pin MTSLI. The inputs now expect digi-

tal signals phase shifted by 90°, whereas MTMA reads

the single bit period information, and MTSLI the shifted

synchronization bit. The following ﬁgure explains the

principle and the table below gives the necessary set-

tings.

sector 0

sector 1

MTSLI

MTMA

calculated nonius position

master

max

segment

nonius

resulting dataword

2*max

sector 0

sector 1

0

360°

°/rev

.

iC-MN

2 bit sector code (gray coded)

MTSLI

MTMA

0

360°

MTSLI

MTMA

°/rev

.

0

360°

°/rev

Figure 23: Principle of 2-bit mode

°/rev

Figure 24: Position of switch points in reference to

the parameter LNT_MT

Parameter

Description

MODE_MT = 11

DL_MT = 0x0E

SBL_MT = 00

MT interface op. mode: 2-bit mode

MT data length: 1 bit

Synchronization bit length: 1 bit

A typical application example where the 2-bit mode can

be used for, is a magnetic angle encoder scanning the

pole wheel by MR sensors. A nonius coded wheel of

16, 15 and 12 pole pairs yields 32, 30 and 24 sine pe-

riods per turn on iC-MN’s analog inputs. The nonius

calculation would not produce absolute angle position

data over a single revolution since the maximum sin-

gleturn value is achieved twice. The distinction as to

which half of the revolution the axis is in can only be

LNT_MT = 0 or 1 Depending on MTMA signal: leading or

trailing

GRAY_MT = 1

M2S = 11

MT data format: Gray coded

Enable for MT plus ST data output

Table 89: Required settings for 2-bit mode

The required position of the multiturn and synchro- made using section sensors, two Hall sensors for ex-

nization bit depends on parameter LNT_MT. Figure 24 ample, whose digital outputs are connected up directly

shows the required signal positions with leading re- to MTMA and MTSLI. Furthermore, the 2-bit mode can

spectively trailing operation. The green arrows are in- be used also with systems based on a 2 track nonius

dicating the permissible relative position tolerances.

calculation.

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 49/59

MT INTERFACE with EXTENDED FUNCTIONS

SWC_MT

Addr. 0x41; bit 6

The serial multiturn interface can be operated in the

BiSS C protocol which enables multiturn sensor error

messages to be evaluated (via the error and warning

bits, each of which are low active) and communica-

tion to be monitored (evaluation of the CRC bits, see

Figure 25).

Code

CRC polynomial (HEX)

0

1

0x43

0x25

Table 91: MT Interface CRC polynomial

The error behavior of the multiturn interface has al-

ready been described in Figures 20 and 21; only a set

error bit (low) or a CRC error are now also classiﬁed

as a communication error.

NCRC_MT

Addr. 0x41; bit 4

Function

Code

0*

CRC veriﬁcation active

Disabled

1

Note

*) Only permitted with MODE_MT = 01.

MODE_MT

Code

00

Addr. 0x40; bit 4:3

Function

Table 92: MT Interface CRC veriﬁcation

Internal multiturn period counting

BiSS C protocol

01

Notes

If MODE_MT is altered during operation, command

SOFT_RES must be issued (see page 42).

Table 90: MT Interface operation mode

M TM A

M TS L I

A

C

K

S

T

A

R

T

M

S

B

L

S

B

N

E

R

N

W

R

N

M

S

B

L

S

B

MT_ E R R +

MT_ WR N

D

L

_

M

T

+

S

B

L

_

M

T

C

R

C

(

N

C

R

C

_

M

T

=

0

)

t

o

u

t

Figure 25: Example of the MT interface line signals with BiSS C protocol

Direct Communication To Multiturn Sensor

ing the singleturn data. With GET_MT enabled, the

Making use of the BiSS Interface bus capabilities, iC- external multiturn can then be addressed via BiSS ID

MN can connect the external multiturn sensor to the 0 and the singleturn via BiSS ID 1. This temporal

BiSS master controller when GET_MT is enabled. To chain operation eases device parameterization during

this end pin MA receiving the BiSS master’s clock sig- encoder manufacturing.

nal is fed through to pin MTMA and the MTSLI pin is

activated in place of the SLI pin. Upon enabling this

GET_MT

Addr. 0x41; bit 5

Function

mode the singlecycle timeout must have elapsed and

an additional init command carried out by the BiSS

master, before it can run the ﬁrst register communi-

cation.

Code

0

1

Disabled

MT sensor communication enabled

Table 93: Direct BiSS communication enable for MT

sensor via I/O Interface

Example: external multiturn sensor built with iC-MN is

connected to the MT interface of a ﬁrst iC-MN, prepar-

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 50/59

PRESET FUNCTION

The preset function sets the output position data to a Figure 26; see Figure 27 for multiturn synchronization

predeﬁned position value and is initiated by a high ﬂank operating mode.

at pin PRES or by calling the SOFT_PRES command

(writing 0x02 to the command register, see Table 70).

If an external EEPROM is available the preset values

are read in from the preset registers. A preset value of

zero is otherwise assumed. The current position is de-

termined. Correction factors for the output (OFFS_ST,

OFFS_MT) are calculated and stored in the internal

RAM. With an EEPROM available the entire contents

of the RAM are written to said EEPROM, thus storing

the OFFS_ST and OFFS_MT data.

In the PRES_MT register the multiturn preset values

are always justiﬁed to the right with the LSB (starting

at address 0x55, bit 0).

OFFS_MT

Addr. 0x37; bit 7:0

Addr. 0x36; bit 7:0

Addr. 0x35; bit 7:0

0x000

. . .

Multiturn output offset

0xFFF

Note: Command SOFT_PRES blocks iC-MN’s internal

RAM for accesses over a certain time.

Table 96: Position offset for MT data output

For the output the OFFS_ST and OFFS_MT values are

subtracted from the internal synchronized result with

each conversion (Note: In MODE_ST = 0x05-0x07 and

0x0D the sensor data is designated faulty after the ﬁrst

readout. The readout data is equivalent to the correc-

tion factor.)

PRES_MT

Addr. 0x57; bit 7:0

Addr. 0x56; bit 7:0

Addr. 0x55; bit 7:0

0x000

. . .

Preset register multiturn (EEPROM only)

0xFFF

OFFS_ST

Addr. 0x34; bit 6:0

Addr. 0x33; bit 7:0

Addr. 0x32; bit 7:0

Addr. 0x31; bit 7:0

Addr. 0x30; bit 7:0

Table 97: Preset value for MT data output

up to 12 bit period-information

UBL_S+UBL_N

up to 13 bit master-information

UBL_M

0x00000

. . .

physical

resolution:

MSB

period

LSB

period

MSB

master

LSB

master

Singleturn output offset

0x7FFFF

PRES_ST

register:

MSB

ST_DW

LSB

ST_DW

0

Table 94: Position offset for ST data output

ADR 0x54

bit 6

ADR 0x53

bit 3

ADR 0x53

bit 2

ADR 0x51

bit 6

datalength defined by DL_ST

PRES_ST

Addr. 0x54; bit 6:0

Addr. 0x53; bit 7:0

Addr. 0x52; bit 7:0

Addr. 0x51; bit 7:0

Addr. 0x50; bit 7:0

Figure 26: PRES_ST with nonius synchronization

mode

up to 39 bit preset-information MSB left aligned

datalength defined by DL_ST

0x00000

. . .

Preset register singleturn (EEPROM only, see text)

0x7FFFF

PRES_ST

register:

MSB

ST_DW

LSB

ST_DW

0

Table 95: Preset value for ST data output

ADR 0x54

bit 6

ADR 0x50

bit 0

The position of the preset value for the singleturn data

word (ST_DW) in preset register PRES_ST varies de-

pending on the converter mode (MODE_ST see Table

42). For nonius synchronization operating mode see

Figure 27: PRES_ST with multiturn synchronization

mode

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 51/59

STARTUP BEHAVIOR

Figure 28 shows the startup behavior of iC-MN. After If an error occurs while the EEPROM data is being

turning on the power supply (power-on reset) iC-MN read (a CRC error or communication error with the

reads the conﬁguration data from the EEPROM. If the EEPROM), the current readin process is canceled and

data can be read without error, a timeout of 8 ms is restarted. Following a third failed attempt the readin

allowed to elapse.

procedure is ended and the internal iC-MN conﬁgura-

tion registers (addresses 0x00 to 0x4D) initialized with

If the multiturn interface has been conﬁgured for an ex- a zero.

ternal sensor, the device waits for a longer timeout of

16 ms to elapse. The multiturn data is then read in and In doing so, NBISS = 0 selects for the BiSS C protocol

the ﬁrst conversion performed in order to determine the for the I/O interface enabling BiSS C register commu-

absolute position (see page 47). iC-MN then goes into nication.

normal operation.

If an attempt to read sensor data is made iC-MN would

reply an 8-bit zero value with set error and warning

startup

bits (sequence: start bit 1x high, position 8x zero, er-

ror/warning 2x zero, CRC 6x high followed by zero bits

read EEPROM

(max 3 times on error)

when the clock signal is continued).

EEPROM ok?

Following successful conﬁguration using the I/O inter-

face command SOFT_RES must be issued in order to

switch iC-MN to normal operation (see page 42).

serial-interface active

for configuration

(no sensor data request

MODE_MT = 00

possible)

yes

no

8 ms timeout

16 ms timeout

via command SOFT_RES

MODE_ST:

sync_mode is

nonius?

yes

no

yes

MODE_MT = 00

no

normal operation:

ready for

sensor data requests

first conversion to get

initial period information

command execution

multiturn-startup

Figure 28: Startup behavior

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 52/59

EEPROM INTERFACE

CFG_E2P

Adr 0x40; Bit 2:0

Banks per area

(64 bytes each)

CONF EDS USER EEPROM, Typ

The serial EEPROM interface consists of the two pins

SCL and SDA and enables read and write access to a

serial EEPROM (such as a 24C02 with 128 bytes, 5 V

type with a 3.3 V function). The data in the EEPROM

is secured by a CRC to the addresses 0x4E and 0x4F.

Code

For SSI applications:

000*

001

Bytes

128

256

2

3

-

1

-

1 kbit, C01 up

2 kbit, C02 up

For BiSS applications with EDS:

Application Hints

010

011

100

101

110

111

Notes

512

3

4

12

4

12

24

1

9

1

25

17

5

4 kbit, C04 up

8 kbit, C08 up

16 kbit, C016 up

To protect the EEPROM against a reversed power sup-

ply voltage it can be connected to the integrated supply

switch (pins VDDA and GNDA). The EEPROM speci-

ﬁcations and absolute maximum ratings should com-

ply to the pin voltages of VDDA, SCL and SDA during

startup and operation. A protective circuit may be ad-

visable depending on the EEPROM model.

1024

2048

*) direct addressing mode

Table 99: Conﬁguration of external memory

Direct Addressing

The registers can be accessed via the I/O interface

and direct addressing (for CFG_E2P = 000). In ac-

cordance with the BiSS protocol the number of bytes

addressed is restricted to 128. Accessing addresses

0x00 to 0x4F reads or writes to iC-MN’s internal RAM

register. The data from this special address area can

only be transmitted to the EEPROM by the command

WRITE_CONF.

For EEPROM selection the following minimal require-

ments must be fulﬁlled: (e. g. Atmel AT24C01B, 128x8)

• Operation from 3.3 V to 5 V, I²C-Interface

• Minimal 1024 bit, 128x8

The registers for addresses 0x50 to 0x70, 0x78 to

0x7B and 0x7D to 0x7F are in the EEPROM and can

be accessed byte-wise by a BiSS register access for

read or write.

CRC_E2P(1:0)

CRC_E2P(9:2)

Addr. 0x4F; bit 7:6

Addr. 0x4E; bit 7:0

Code

0x000

. . .

Description

CRC formed by CRC polynomial 0x409

The addresses missing in the above are located in iC-

MN: the status register from 0x75 to 0x77 (read only),

the MN_CMD register at 0x77 (write only), and the I/O

interface parameters CID_SCD and TOS at address

0x7C. The latter has no access limitations and can

always be read and written to (content is mirrored to

0x4C).

0x3FF

Table 98: EEPROM Data Check Sum

Memory Map And Register Access

Depending on the EEPROM size different bank assign-

ments can be conﬁgured using CFG_E2P. There are

three areas, placed one after the other, which are des-

ignated for this purpose in the memory:

Bank-Wise Addressing

iC-MN also supports bank-wise addressing (for

CFG_E2P = 000) according to the BiSS Interface C

Protocol Description. In this mode of conﬁguration iC-

MN divides the internal address sections into banks of

64 bytes each. The address sections visible via the I/O

interface recognizes a ”dynamic” section (addresses

0x00 to 0x3F) and a ”static” section which is perma-

nently visible (addresses 0x40 to 0x7F). The static ad-

dress section is always independent of the bank cur-

rently selected. Figure 29 illustrates how the banks

selected by BANKSEL are addressed.

1. CONF: iC-MN conﬁguration data

2. EDS : Electronic Data Sheet

3. USER: OEM data, free user area

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 53/59

iC-MN internal

address-space visible via BiSS

linear address-

(CFG_E2P > 000)

space divided into n

banks of size 64

bank n-1

byte

(e.g. CFG_E2P > 101; n=32)

bank 3

bank 2

bank 1

ADR

bank 0

0x00

0x3F

0x40

0x7F

0x80

0x3F

0x40

BANKSEL

EDSBANK

profile ID

selects

0xBF

0xC0

serial number

SLAVE-registers

STATUS

0xFF

BiSS-ID

0x7F

Figure 29: Principle of bank-wise memory addressing

PROT_E2P(1:0)

Range

Addr. 0x43; bit 1:0

Register access can be restricted via PROT_E2P (see

Table 100). PROT_E2P = 10 selects safety level 2, a

shipping mode with limited access. Shipping 2 can be

set back to level 1 (shipping 1), for which purpose the

content of address 0x43 must be written anew.

RPL*

RP0

RP1

CONF

r/w

EDS

r/w

USER

r/w

STATUS n/a

r/w for others

r/w

RP2

Note

n/a

r only

r/w

PROT_E2P(1:0)

Addr. 0x43; bit 1:0

* Register Protection Level

Code

Mode

Access Limitation

(see Figure 30 and 31)

00

Conﬁguration Mode,

free access

RP0

RP1

RP2

Table 101: Register Read/Write Protection Levels

(n/a: iC-MN refuses access to those regis-

ter addresses.)

01

Conﬁguration Mode,

limited access

10

Shipping Mode 1,

reset to RP1 is possible

Figure 30 shows the static memory area and Figure 31

the area which can be altered by BANKSEL. The BiSS

register access limitations which are generated by pa-

rameter PROT_E2P are marked ”R/W” for read/write

access and ”R” for read only. The original site of data

returned by access to the BiSS register is designated

11

Shipping Mode 2,

reset is not possible

Table 100: Register Access Control

Sections CONF, EDS and USER are protected at dif- by ”RAM” for iC-MN’s internal RAM, by ”E2P” for the

ferent levels in shipping mode for read and write ac- EEPROM and by ”INT” for those of iC-MN’s internal

cess.

registers which cannot be preloaded on startup.

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 54/59

static part: BiSS addresses 0x3F-0x7F

register-

protection-

addressing scheme

level

data

bank address

0x40

content

mapped to address RP1 RP2 location

BANKSEL

EDSBANK

internal

0x081

0x082

0x083

0x084

R/W

INT

0x41

0x42

0x43

0x44

profile ID

serial number

0x47

0x48

0x087

0x088

R

E2P

SLAVE-registers

reserved

0x6F

0x70

0x0AF

0x0B0

0-31

R/W

0x74

0x75

0x76

0x77

0x78

0x0B4

internal

0x078

0x04C

0x07F

STATUS

STATUS/MN_CMD

R/W

INT

R

R/W

R

E2P

RAM

E2P

0x7C

0x7F

BISS-ID

Figure 30: User view: BiSS memory access 0x40 to 0x7F, con-

tent independent of BANKSEL; CFG_E2P = 000

bank switched part: BiSS addresses 0x00-0x3F

register-

protection-

addressing scheme

level

data

bank address

content

mapped to address RP1 RP2 location

0x00

0x000

0

n/a

0x3F

0x00

parameter values

with CRC

0x03F

0x040

RAM

0x0C

0x04C

R/W

n/a

R/W

0x0F

0x10

0x04F

0x050

preset-values

free

R/W

n/a

0x17

1

0x057

0x35

0x36

0x37

0x38

0x075

0x076

0x077

0x078

E2P

STATUS accumulated

(see E2EPR for

details)

n/a

R

0x3C

0x04C

BiSS-ID

R/W

RAM

0x3F

0x00

0x01

0x07F

0x080

0x081

reserved

EDSBANK, profile ID,

serial number, SLAVE-

registers

R

2

0x2F

0x30

0x0AF

0x0B0

R/W

reserved

E2P

0x3F

0x00

0x0BF

0x0C0

3

0x3F

0x00

0x3F

0x0FF

0x7C0

0x7FF

R

or

R/W

31

Figure 31: User view: BiSS memory access 0x00 to 0x3F, con-

tent switchable with BANKSEL; CFG_E2P = 000

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 55/59

APPLICATION NOTES: Conﬁguration As BiSS C-Slave Including EDS (Electronic Data Sheet)

BiSS Proﬁle 12-12

Preconditions:

MODE_ST

NBISS

ELC

0x00-0x0B (Nonius)

0

1. CFG_E2P <> b000. The bank switch function must

be activated.

GRAY_SCD

DL_ST

DL_MT

M2S

0

0x04 (12)

0x03

2. EDSBANK = 0x03. No other values possible. Ad-

dressing via BiSS: Bank: 2, Adr: 0x01 or direct to EEP-

ROM: Adr: 0x081

R_MT

0x0C (12)

R_ST

SBL_x

Notes

UBL_M+UBL_S+UBL_N

= 0x00

UBL_M+UBL_S+UBL_N ≤ 12

3. Setting of proﬁle ID according to the following ta-

bles; Addressing via BiSS: Bank: 2, Adr: 0x02-0x03 or

direct to EEPROM: Adr: 0x082-0x083

Table 105: Setup for BiSS proﬁle 12-12

BiSS Proﬁle 0-12

BiSS Proﬁle 12-24

MODE_ST

NBISS

ELC

0x00-0x0B (Nonius)

0

0x0C-0x0F (Multiturn)

MODE_ST

NBISS

ELC

0x00-0x0B (Nonius)

0

GRAY_SCD

DL_ST

DL_MT

M2S

0

GRAY_SCD

DL_ST

DL_MT

M2S

0

0x04 (12)

-

0x00

0x10 (24)

0x04 (12)

0x03

R_MT

0x00 (0)

R_MT

0x0C (12)

R_ST

SBL_x

Notes

UBL_M+UBL_S+UBL_N

= 0x00

UBL_M+UBL_S+UBL_N ≤ 12

R_ST

SBL_x

Notes

UBL_M+UBL_S+UBL_N

= 0x00

UBL_M+UBL_S+UBL_N ≤ 24

-

Table 102: Setup for BiSS proﬁle 0-12

Table 106: Setup for BiSS proﬁle 12-24

BiSS Proﬁle 0-24

MODE_ST

NBISS

ELC

GRAY_SCD

DL_ST

DL_MT

M2S

R_MT

R_ST

SBL_x

Notes

0x00-0x0B (Nonius)

0

0x10 (24)

-

0x00

0x00 (0)

UBL_M+UBL_S+UBL_N

= 0x00

UBL_M+UBL_S+UBL_N ≤ 24

0x0C-0x0F (Multiturn)

BiSS Proﬁle 12-24++

MODE_ST

NBISS

ELC

0x00-0x0B (Nonius)

0

GRAY_SCD

DL_ST

DL_MT

M2S

0

0x11(25)

0x04 (12)

0x03

R_MT

0x0C (12)

R_ST

0x19 (25)

SBL_x

Notes

= 0x00

UBL_M=13, UBL_S=6, UBL_N=6

Table 103: Setup for BiSS proﬁle 0-24

Table 107: Setup for BiSS proﬁle 12-24++

BiSS Proﬁle 0-24++

MODE_ST

NBISS

0x00-0x0B (Nonius)

0

0x0C-0x0F (Multiturn)

ELC

GRAY_SCD

DL_ST

0

BiSS Proﬁle 24-12

MODE_ST

NBISS

ELC

0x00-0x0B (Nonius)

0

0x11(25)

> 0x10 (24)

< 0x18 (32)

DL_MT

M2S

R_MT

R_ST

SBL_x

Notes

-

GRAY_SCD

DL_ST

DL_MT

M2S

0

0x00

0x04 (12)

0x0D (24)

0x03

0x00 (0)

0x19 (25)

= 0x00

UBL_M=13,

UBL_N=6

UBL_M+UBL_S+UBL_N

R_MT

0x18 (24)

UBL_S=6, UBL_M+UBL_S+UBL_N

=

>

R_ST

SBL_x

Notes

UBL_M+UBL_S+UBL_N

= 0x00

UBL_M+UBL_S+UBL_N ≤ 12

DL_ST;

UBL_M+UBL_S+UBL_N

24

Table 104: Setup for BiSS proﬁle 0-24++

Table 108: Setup for BiSS proﬁle 24-12

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 56/59

BiSS Proﬁle 24-24

Remarks to iC-MN with EDS:

MODE_ST

NBISS

ELC

0x00-0x0B (Nonius)

0

1. CFG_E2P = b000 (i.e. bank switch function has

been activated.)

GRAY_SCD

DL_ST

DL_MT

M2S

R_MT

R_ST

0

0x10 (24)

0x0D (24)

0x03

0x18 (24)

UBL_M+UBL_S+UBL_N

= 0x00

UBL_M+UBL_S+UBL_N ≤ 24

2. EDSBANK must be set 0x03 (no other values are

possible)

Addressing via BiSS: Bank: 2, Adr: 0x01

or direct to EEPROM: Adr: 0x081

SBL_x

Notes

3. Set proﬁle ID.

Table 109: Setup for BiSS proﬁle 24-24

Addressierung via BiSS: Bank: 2, Adr: 0x02-

0x03

BiSS Proﬁle 24-24++

or direct to EEPROM: Adr: 0x082-0x083

MODE_ST

NBISS

ELC

0x00-0x0B (Nonius)

0

GRAY_SCD

DL_ST

DL_MT

M2S

0

0x11(25)

0x0D (24)

0x03

R_MT

0x18 (24)

R_ST

0x19 (25)

SBL_x

Notes

= 0x00

UBL_M=13, UBL_S=6, UBL_N=6

Table 110: Setup for BiSS proﬁle 24-24++

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 57/59

APPLICATION NOTES: PLC Operation

PLC Operation

ther the supply VDD nor the output pins, which are

There are PLCs with a remote sense supply which re- also monitored, must fall to below ground potential (pin

quire longer for the voltage regulation to settle. At the GND); otherwise the device is not conﬁgured and the

same time the PLC inputs can have high-impedance outputs remain permanently set to tristate.

resistances versus an internal, negative supply voltage

which deﬁne the input potential for open inputs.

In order to ensure that iC-MN starts with the PLCs

In this instance iC-MN’s reverse polarity protection fea- mentioned above pull-up resistors can be used in the

ture can be activated as the outputs are tristate during encoder. Values of 100 kΩ are usually sufﬁcient; it

the start phase and the resistances in the PLC deter- is, however, recommended that PLC speciﬁcations be

mine the pin potential. During the start phase nei- speciﬁcally referred to here.

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 58/59

DESIGN REVIEW: Notes On Chip Functions

iC-MN Y2

No.

Function, Parameter/Code

Description and Application Hints

No exclusions known at time of printing.

Table 111: Notes on chip functions regarding iC-MN chip releas Y2

iC-Haus expressly reserves the right to change its products and/or speciﬁcations. An Infoletter gives details as to any amendments and additions made to the

relevant current speciﬁcations on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by

email.

Copying – even as an excerpt – is only permitted with iC-Haus approval in writing and precise reference to source.

iC-Haus does not warrant the accuracy, completeness or timeliness of the speciﬁcation on this site and does not assume liability for any errors or omissions

in the materials. The data speciﬁed is intended solely for the purpose of product description. No representations or warranties, either express or implied, of

merchantability, ﬁtness for a particular purpose or of any other nature are made hereunder with respect to information/speciﬁcation or the products to which

information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or

areas of applications of the product.

iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade

mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.

As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and speciﬁcally designed for appropriate use in technical

applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of

use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued

annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in

Hanover (Hannover-Messe).

We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations

of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can

be put to.

iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev D1, Page 59/59

ORDERING INFORMATION

Type

Package

Order Designation

iC-MN

48-pin QFN 7x7 mm

iC-MN QFN48

Evaluation Board

Size 140mm x 100mm

iC-MN EVAL MN1D

For technical support, information about prices and terms of delivery please contact:

iC-Haus GmbH

Tel.: +49 (61 35) 92 92-0

Am Kuemmerling 18

D-55294 Bodenheim

GERMANY

Fax: +49 (61 35) 92 92-192

Web: http://www.ichaus.com

E-Mail: sales@ichaus.com

Appointed local distributors: http://www.ichaus.com/sales_partners


型号：	IC-MNEVALMN1D
厂家：	IC-HAUS GMBH
描述：	25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION 25位游标编码器， 3 -CH 。采样13位仙/ D插值编码器
文件：	总59页 (文件大小：1705K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IC-MNEVALMN1D [ICHAUS]

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