IC-MPEVALMP1D [ICHAUS]
8-BIT HALL ANGLE ENCODER WITH RATIOMETRIC OUTPUT; 提供比例输出8位HALL角度编码器
| 型号： | IC-MPEVALMP1D |
| 厂家： | 
IC-HAUS GMBH |
| 描述： | 8-BIT HALL ANGLE ENCODER WITH RATIOMETRIC OUTPUT |
| 文件： | 总22页 (文件大小：1471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 1/22
FEATURES
APPLICATIONS
♦ Hall sensor array with automatic signal control
♦ Differential scanning for excellent magnetic stray field
tolerance
♦ Contactless potentiometer
♦ Absolute 360° angle sensor
♦ Magnetic rotary encoders
♦ Real-time tracking interpolation of up to 256 angle steps,
permitting up to 12,000 rpm
♦ Ratiometric output with 0.5 V to 4.5 V or 0 V to 5 V and
selectable full-scale angle of 90, 180, 270 or 360 degrees
♦ Programmable zero position
♦ Fast, serial absolute angle data output
♦ Easy daisy chaining of multiple sensors: all analog/digital
outputs can be used in buses
♦ Loss-of-magnet and excessive frequency indication via error
output
PACKAGES
♦ Non-volatile setup provided by 3x reconfigurable Zener zap
ROM
♦ 5 V single-supply operation
♦ Power-saving standby function
♦ Operational temperature range of -40 to +125 °C
♦ Space-saving 10-pin DFN package measuring 4 mm x 4 mm
DFN10 4 x 4 mm
BLOCK DIAGRAM
VDD
VZAP
MA
8
B
I
T
B
B
P
S
I
N
N
C
O
S
SLO
SLI
B
B
P
C
O
S
N
S
I
N
H
A
L
L
S
E
N
S
O
R
S
A
M
P
S
I
N
/
D
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A
P
P
I
N
G
S
E
R
I
A
L
I
N
T
E
R
F
A
C
E
NERR
2
2
S
I
N
+
C
O
S
S
I
G
N
A
L
C
O
N
V
E
R
S
I
O
N
C
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T
R
O
L
L
O
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C
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/
O
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N
T
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R
F
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C
E
PSMO
PSMI
LAO
i
C
-
M
P
P
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R
S
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V
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M
O
D
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/
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5
Copyright © 2010 iC-Haus
http://www.ichaus.com
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 2/22
DESCRIPTION
iC-MP consists of a quadruple Hall sensor array sine/cosine signals. The absolute position angle is
which has been optimized for the magnetic mea- output via the serial interface together with a bit indi-
surement of an axis angle. The array permits error- cating an error. The maximum resolution of 8 bits is
tolerant adjustment of the magnet, reducing the time maintained up to revolutions of 12,000 rpm.
and effort required assembly. The integrated signal
conditioning unit provides a differential sine/cosine The absolute angle is converted back to a linear ana-
signal at its outputs. The sensor generates one sine log output voltage using the internal D/A converter.
cycle per full rotation of the magnet, enabling the The analog output voltage range can be programmed
angle to be clearly determined. At the same time to be either rail to rail or 10 % to 90 % of the supply
the internal amplitude control unit produces a regu- voltage. The angular range of the analog signal is
lated output amplitude of 2 Vpp, regardless of vari- configurable to 90°, 180°, 270° or 360°.
ations in the magnetic field strength, supply voltage
and temperature. Furthermore, error signals are pro- iC-MP can be easily cascaded, enabling scanning of
vided which report any magnet loss and an exces- multiple axes. In Fast Scanning Mode all devices
sively high RPM speed.
connected in a queue are read consecutively. In Slow
Scanning Mode (Power Save Mode) each individual
With the aid of the integrated 8-bit sine-to-digital device is booted up before the serial data or analog
converter the axis angle is determined from the output voltage is put on the common bus.
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 3/22
CONTENTS
PACKAGES
4
5
5
6
8
OPERATING MODES
11
12
PROGRAMMING MODE
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
ENERR . . . . . . . . . . . . . . . . . . . . . 14
Calculating the position offset . . . . . . . . . 14
CRCID . . . . . . . . . . . . . . . . . . . . . . 15
ELECTRICAL CHARACTERISTICS
SENSOR PRINCIPLE
FAST SCANNING MODE
SLOW SCANNING MODE
APPLICATION CIRCUITS
16
18
20
HALL SENSOR POSITION AND INTERNAL
ANALOG SIGNALS
8
9
Stand-alone example . . . . . . . . . . . . . 20
LINEAR ANALOG OUTPUT (LAO)
SERIAL OUTPUT (SLO)
TEST MODES
21
21
10 DESIGN REVIEW: Notes On Chip Functions
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 4/22
PACKAGES
PIN CONFIGURATION DFN10
PIN FUNCTIONS
No. Name Function
1 PSMI Power Save Mode Input
2 GND Ground
3 PSMO Power Save Mode Output
1
2
10
9
4 LAO
5 MA
6 SLO
7 SLI
Linear Analog Output
Serial Clock Input
Serial Data Output
Serial Data Input
3
8
iC-MP
...
...yyww
4
7
8 VZAP Zapping Voltage Input
9 VDD +5 V Supply Voltage
5
6
10 NERR Error Message Output (low active)
/ Serial ROM Data Output
TP
Thermal Pad
The thermal pad must be connected to ground potential on the PCB.
Orientation of the logo ( MP CODE ...) is subject to alteration.
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 5/22
ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
-0.3
-20
Max.
6
G001 V()
G002 I()
G003 V()
Supply Voltage at VDD
Current in VDD
V
mA
V
20
Voltage at pins PSMI, PSMO, LAO,
MA, SLO, SLI, NERR
-0.3
VDD +
0.3
G004 V()
G005 I()
Voltage at pin VZAP
-0.3
-10
8
V
Current in pins PSMI, PSMO, LAO,
MA, SLO, SLI, NERR, VZAP
10
mA
G006 I()
Current in pins PSMI, PSMO, LAO,
MA, SLO, SLI, NERR, VZAP
Pulse width < 10µs
-100
100
mA
G007 Vd()
G008 Tj
ESD Susceptibility at all pins
Junction Temperature
HBM, 100 pF discharged through 1.5 kΩ
2
kV
°C
°C
-40
-40
125
125
G009 Ts
Storage Temperature Range
THERMAL DATA
Operating conditions: VDD = 5 V ±10 %
Item Symbol
No.
Parameter
Conditions
Unit
Min. Typ. Max.
-40 125
T01 Ta
Operation Ambient Temperature Range
Thermal Resistance, Chip to Ambient
°C
T02 Rthja
Package mounted on PCB, thermal pad at
approx. 2 cm² cooling area
40
K/W
All voltages are referenced to ground unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 6/22
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 5 V ±10 % , Tj = -40 ... 125 °C, unless otherwise stated
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
General
001 VDD
002 I(VDD)
Supply Voltage
4.5
5
8
5.5
12
V
mA
µA
V
Supply Current in VDD
PSMI = lo, other pins open
PSMI = hi
003 I(VDD)sb Standby Supply Current
200
4.1
3.9
004 VDDon
005 VDDoff
006 VDDhys
Power-On Threshold
Power-Down Threshold
Hysteresis
Increasing voltage VDD
Decreasing voltage VDD
VDDhys = VDDon - VDDoff
3.0
2.6
200
V
mV
ms
007
ton()1
Turn-On Delay Following
Power-On
Time to data valid after enabling,
VDD: VDDoff → VDDon
Time to data valid after standby,
PSMI: hi → lo
VDD = 0 V; I() = 1 mA
VDD = 0 V; I() = 4 mA
I() = -4 mA
1
008
ton()2
Turn-On Delay Following Standby
900
1.6
1.6
-0.3
µs
V
009 Vc()hi
010 Vc()hi
011 Vc()lo
Clamp Voltage hi at
PSMI, MA, SLI, NERR
0.3
0.3
Clamp Voltage hi at
PSMO, LAO, SLO
V
Clamp Voltage lo at
-1.5
V
PSMI, PSMO, LAO, MA, SLO,
SLI, NERR, VDD, VZAP
Hall Sensor Array
101 Hext
Operating Magnetic Field
Strength
At surface of chip
20
50
100
kA/m
102 RPM
103 ferr()
104 fmag()
105 dsens
106 xpac
107 φpac
108 hpac
Permissible RPM Speed
Excessive Frequency Alarm
Magnetic Field Frequency
Diameter of Hall Sensor Array
Chip Placement Tolerance
Chip Tilt Angle
12 000
rpm
kHz
Hz
ENERR(1) = 1; NERR: hi → lo
1
2
200
mm
mm
DEG
µm
Versus DFN10 package outlines
Versus DFN10 package outlines
-0.2
-3
0.2
3
Distance Surface of Package to DFN10 package
Surface of Chip
400
Sine-To-Digital Converter
301 RES
302 HYS
303 AAabs
Converter Resolution
Per 360 degree
8
bit
Converter Hysteresis
1.4
DEG
DEG
Absolute Angle Accuracy
Magnet with 4 mm in diameter, axis centered to
chip
-3
-1
3
1
D/A Converter And Ratiometric Output LAO
401
RES()
D/A Converter Resolution
MODE(1:0) = 00 (range 360°)
MODE(1:0) = 01 (range 270°)
MODE(1:0) = 10 (range 180°)
MODE(1:0) = 11 (range 90°)
8
7.5
7
bit
bit
bit
bit
6
402 Iload()
Permissible Output Current
mA
403
dV0()hi
Output Voltage hi, Rail-To-Rail
dV0()hi = V(VDD) - V(LAO), MODE(3) = 0;
I() = -1 mA
I() = 0 mA
170
85
mV
mV
404
dV0()lo
Output Voltage lo, Rail-To-Rail
MODE(3) = 0;
I() = 1 mA
170
85
mV
mV
I() = 0 mA
405 dV1()hi
406 dV1()lo
407 Ilk()
Output Voltage hi, 10/90% Range MODE(3) = 1; I() = -1...+1 mA
Output Voltage lo, 10/90% Range MODE(3) = 1; I() = -1...+1 mA
85
5
95
15
5
%VDD
%VDD
µA
Leakage Current
Slew Rate hi
V(LAO) = 0...VDD, PSMI = hi
V(LAO): 20% → 80% of range
V(LAO): 80% → 20% of range
-5
2
408 SR()hi
409 SR()lo
V/µs
Slew Rate lo
2
V/µs
Zapping Input VZAP
501 Vt1()hi
502 Vt1()lo
Voltage Threshold hi vs. GND
Voltage Threshold lo vs. GND
2
V
V
0.8
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 7/22
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 5 V ±10 % , Tj = -40 ... 125 °C, unless otherwise stated
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
400
1.3
503 Vt1()hys
504 Vt2()hi
Threshold Hysteresis
Vt1()hys = Vt1()hi − Vt1()lo
Vt2()hi = V() - VDD,
230
mV
V
Voltage Threshold hi vs. VDD
VDD = 5 V ±5%, Tj = 10 ... 40 °C
505 Vt2()lo
Voltage Threshold lo vs. VDD
Vt2()lo = V() - VDD;
0.7
V
VDD = 5 V ±5%, Tj = 10 ... 40 °C
506 Vt2()hys
507 Vzap()
508 Izap()
Threshold Hysteresis
Vt2()hys = Vt2()hi − Vt2()lo
20
150
7.5
90
mV
V
Permissible Zapping Voltage
Required Zapping Current
VDD = 5 V ±5%, Tj = 10 ... 40 °C
7.3
7.4
VDD = 5 V ±5%, Tj = 10 ... 40 °C
mA
Serial Interface and Power Save Mode Inputs: MA, SLI, PSMI
601 Vt()hi
602 Vt()lo
603 Vt()hys
604 Ipu()
Input Threshold Voltage hi
Input Threshold Voltage lo
Input Hysteresis
2
V
V
0.8
230
Vt()hys = Vt()hi − Vt()lo
V() = 0...VDD − 1 V
mV
µA
Input Pull-up Current
-240
0.080
-120
5
-10
10
605 fclk(MA)
Permissible Clock Frequency at Normal mode
MA
MHz
606 tzap(MA) Permissible Zapping Cycle at MA Programming mode,
VDD = 5 V ±5%, Tj = 10 ... 40 °C
Time from MA last edge to SLO lo → hi
Serial Interface and Power Save Mode Outputs: SLO, PSMO
4.5
5.5
15
µs
µs
607 tout(MA)
Interface Timeout
701 Vs()hi
702 Vs()lo
703 Isc()hi
704 Isc()lo
705 tr()
Saturation Voltage hi
Saturation Voltage lo
Short-Circuit Current hi
Short-Circuit Current lo
Rise Time
Vs()hi = VDD − V(), I() = -4 mA
I() = 4 mA
0.4
0.4
-10
90
V
V
V() = 0 V
-90
10
mA
mA
ns
ns
V() = VDD
CL() = 50 pF, V(): 20 → 80%
CL() = 50 pF, V(): 80 → 20%
60
706 tf()
Fall Time
60
I/O Interface NERR
801 Vs()lo
802 Ilk()
Saturation Voltage lo
Leakage Current
I() = 4 mA
0.4
5
V
V() = 0...VDD, PSMI = hi
V() = VDD
-5
µA
mA
803 Isc()lo
Short-Circuit Current lo
4.5
90
Test Signals at NERR, LAO, PSMO (iC-Haus device test only)
902 VREF
Reference Voltage at LAO
Op. mode: Test 2
Op. mode: Test 0
45
50
2
55
%VDD
Vpp
904 Vpp(PSIN) Pos. Sine Sensor AC Signal
at NERR
905 Vdc(PSIN) Pos. Sine Sensor DC Signal
at NERR
Op. mode: Test 0
Op. mode: Test 0
Op. mode: Test 0
Op. mode: Test 1
Op. mode: Test 1
Op. mode: Test 1
VREF
2
V
Vpp
V
906 Vpp(PCOS) Pos. Cosine Sensor AC Signal
at LAO
907 Vdc(PCOS) Pos. Cosine Sensor DC Signal
at LAO
VREF
2
908 Vpp(NSIN) Neg. Sine Sensor AC Signal
at NERR
Vpp
V
909 Vdc(NSIN) Neg. Sine Sensor DC Signal
at NERR
VREF
2
910 Vpp(NCOS)Neg. Cosine Sensor AC Signal
at LAO
Vpp
V
911 Vdc(NCOS) Neg. Cosine Sensor DC Signal Op. mode: Test 1
at LAO
VREF
912 dVoff()
Diff. Sine and Cosine Signal
Offsets
dVoff() = V(PSIN) − V(NSIN),
-50
50
mV
dVoff() = V(PCOS) − V(NCOS)
913 VR()
Sine/Cosine AC Signal Ratio
VR() = V(PSIN) / V(PCOS),
VR() = V(NSIN) / V(NCOS)
0.95
1.05
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 8/22
SENSOR PRINCIPLE
coder system or a contactless potentiometer. A dia-
metrically magnetized, cylindrical permanent magnet
made of neodymium iron boron (NdFeB) or samarium
cobalt (SmCo) generates optimum sensor signals. The
diameter of the magnet should be in the range of 3 mm
to 6 mm.
The iC-MP has four Hall sensors adapted for angle
determination and to convert the magnetic field into
a measurable Hall voltage. Only the z-component of
the magnetic field is evaluated, whereby the field lines
pass through two opposing Hall sensors in the oppo-
site direction. Figure 1 shows an example of field vec-
tors.
The arrangement of the Hall sensors is selected so
that the mounting of the magnets relative to iC-MP is
extremely tolerant. Two Hall sensors combined provide
a differential Hall signal. When the magnet is rotated
around the longitudinal axis, sine and cosine output
z
y
+Bz
B
x
-Bz
Figure 1: Sensor principle
C151107-1
In conjunction with a rotating permanent magnet, the voltages are produced which can be used to determine
iC-MP module can be used to create a complete en- angles.
HALL SENSOR POSITION AND INTERNAL ANALOG SIGNALS
The Hall sensors are placed in the center of the DFN10 In order to calculate the angle position of a diametri-
package at 90° to one another and arranged in a circle cally polarized magnet placed above the device a dif-
with a diameter of 2 mm as shown in Figure 2.
ference in signal is formed between opposite pairs of
Hall sensors, resulting in the sine being VSIN = VPSIN
-
VNSIN and the cosine VCOS = VPCOS - VNCOS. The zero
angle position of the magnet is marked by the resulting
cosine voltage value being at a maximum and the sine
voltage value at zero.
P in 1 M a rk
1
1 0
9
P
S
I
N
PCO S
2
3
4
5
8
This is the case when the south pole of the magnet is
exactly above the PCOS sensor and the north pole is
above sensor NCOS, as shown in Figure 3. Sensors
PSIN and NSIN are placed along the pole boundary so
that neither generate a Hall signal.
7
N
C
O
S
NSI N
6
( t o p vie w)
C
0
4
0
1
1
0
-
1
Figure 2: Position of the Hall sensors
When the magnet is rotated counterclockwise the
When a magnetic south pole comes close to the sur- poles then also cover the PSIN and NSIN sensors, re-
face of the package the resulting magnetic field has a sulting in the sine and cosine signals shown in Figure
positive component in the +z direction (i.e. from the top 4 being produced. The signals are internal but can be
of the package) and the individual Hall sensors each made externally available for test purposes (see chap-
generate their own positive signal voltage.
ter ’TEST MODES’).
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 9/22
(t o p v ie w)
1
2
1 0
9
1
2
3
4
5
1 0
S
N
9
8
7
1
2
3
4
5
10
9
3
4
5
8
7
6
6
α > 0
8
α = 0
0
7
V
= V
- V
PC OS N COS
6
V
= V - V
NS IN
CO S
SIN
PS IN
+ 2 V
(
T
o
p
v
i
e
w
)
C0260809-1
-
9
0
°
9
0
°
1
8
0
°
2
7
0
°
3
6
0
°
Figure 3: Zero position of the magnet
α
-
2
V
C
0
2
6
0
8
0
9
-
1
Figure 4: Pattern of the internal analog sensor sig-
nals with the angle of rotation
LINEAR ANALOG OUTPUT (LAO)
The LAO pin provides a linear analog output voltage
representing the actual position. The output voltage
can be either rail to rail or within a range of 10% to
90% of the supply voltage VDD, depending on the pro-
grammed configuration. In 10%-to-90% mode a short-
circuit with VDD or GND is recognizable.
The zero position therefore begins at the minimum volt-
age (either GND or 10% of VDD) and reaches its max-
imum (either VDD or 90% of VDD) at the selected an-
gular range limit (90°, 180°, 270° or 360°), depending
on the chosen configuration.
LAO is tristate when the device is disabled.
Figure 5: Linear analog output voltage
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 10/22
SERIAL OUTPUT (SLO)
T1
T2
T3
T4
T5
tout
MA
SLO
ACK START
D7
D1
D0
NERR CRC3
CRC0 STOP
Figure 6: Serial data timing
D0 to D7 make up the absolute position data with re- second device (slave 2) outputs the position latched at
spect to the programmed position offset (OFFSET1 xor T1 at pin SLO.
OFFSET2 xor OFFSET3).
The absolute position data (D0-D7) is binary coded.
The position data and the error bit (NERR) are CRC
The absolute position is latched by a low to high tran-
protected. The CRC polynomial is X4+X+1 = 0x13.
sition at MA (see T1).
CRC_ Value = CRCID;
CRC_ Poly = 0x13;
//CR C star t value,
//Parameter CRCID D (45: 42 )
//CR C Poly noma
After an acknowledge (T2) at SLO iC-MP requests pro-
cessing time until the start condition (T3) is sent. Pro-
cessing time must be provided in Slow Scanning Mode
during startup.
S
e
n
s
_
D
a
t
a
=
D
+
N
E
R
R
;
/
/
P
r
o
t
e
c
t
e
d
S
e
n
s
o
r
D
a
t
a
9
b
i
t
f
o
r
(
i
=
0
;
i
<
8
;
i
+
+
)
{
i
f
(
(
C
R
C
_
V
a
l
u
e
&
0
x
1
0
0
)
!
=
(
S
e
n
s
_
D
a
t
a
&
0
x
1
0
0
)
)
C
R
C
_
V
a
l
u
e
=
(
C
R
C
_
V
a
l
u
e
<
<
1
)
^
C
R
C
_
P
o
l
y
;
With rising edge T4 at the clock pin the most significant
bit (D7) is placed on the serial data line SLO. After T5
has elapsed the controller can stop clocking at MA and
the device is ready to latch a new position after a time-
out (tout). If the controller continues to clock in a daisy
chain in Fast Scanning Mode after T5 has elapsed, the
e
l
s
e
C
R
C
_
V
a
l
u
e
=
(
C
R
C
_
V
a
l
u
e
<
<
1
)
;
Se ns_Dat a = Sens_D ata << 1;
}
Figure 7: Example CRC calculation
F
a
s
t
S
c
a
n
n
i
n
g
M
o
d
e
P SM I
M A
t
o
u
t
S
L
O
A
C
K
S
T
A
R
T
D
7
C
R
C
0
S
T
O
P
Figure 8: Timing in Fast Scanning Mode
P S MI
M A
t
>
5
0
µ
s
S
l
o
w
S
c
a
n
n
i
n
g
M
o
d
e
t
o
u
t
S
L
O
A
C
K
S
T
A
R
T
D
7
C
R
C
0
S
T
O
P
t
£
t
O
N
(
)
2
Figure 9: Timing in Slow Scanning Mode
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 11/22
OPERATING MODES
V( VD D ) > VD D on
Sta rtup
Po we r- On R eset
V (V ZA P) < V 1t() lo
V( VZ AP ) > V 1t( )hi
E nte r
En ter
N orma l Mode
Pr ogr ammi ng Mode
SL I= 0; P SMI= 0
S
L
I
=
1
;
P
S
M
I
=
0
V
(
V
Z
A
P
)
=
V
D
D
VV (( VV ZZ AA PP )) == VV zz aa pp (( ))
WWrr ii tt ee RR OO MM
V( VZ AP ) = V D D
R ead R O M
F as t Mo de
(O pe ra te )
S lo w Mo de
(Op erat e)
W
r
i
t
e
R
A
M
t
o
u
t
(
M
A
)
Sl ow Mode
Sl eep
P
S
M
I
=
1
P
S
M
I
=
1
S
l
e
e
p
Figure 10: Operation Modes
Figure 10 shows the different modes of iC-MP. There
are two major modes of operation:
the chapter on ’PROGRAMMING MODE’ for further
details. There are three minor modes:
– Read ROM:
• Normal Mode:
iC-MP’s Zener zap ROM structure is read.
Readout position data and error bit. Normal mode is
subdivided into two minor modes of operation:
– Fast Scanning Mode:
– Write RAM:
iC-MP’s internal registers can be temporarily
programmed for test purposes.
iC-MP is always activated.
– Slow Scanning Mode (Power Save Mode):
iC-MP goes into Slow Mode Sleep following the
first transmission of sensor data via the serial
interface.
– Write ROM:
iC-MP’s zapping structure is programmed.
A Power-On Reset is required after a Read ROM and
Write ROM instruction. Each state is quit by a Power-
• Programming Mode:
iC-MP can be configured in programming mode. See On Reset.
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 12/22
PROGRAMMING MODE
When pulling the VZAP pin to high during startup, • Write RAM Mode (V(VZAP) = VDD):
the programming mode is entered (see ’OPERATING
MODES’). In this mode there are three different cate-
gories of operation:
In Write RAM Mode the iC-MP reacts as in Write
ROM Mode but there is no zapping of the Zener zap
diodes. This mode can be used to temporarily pro-
gram iC-MP (non-permanent) for test purpose.
• Read ROM (V(VZAP) = VDD):
• Write ROM Mode (V(VZAP) = Vzap(), according to
ELEC.CHAR., no. 507):
In Read ROM Mode the content of the Zener zap
diodes is read out. A Read ROM operation over-
writes iC-MP’s RAM content.
In Write ROM Mode each Zener zap diode is burned
(= zapped) immediately on the rising edge of MA.
See Figure 13 for details. For the conditions of oper-
ation of Write ROM Mode, see ELEC.CHAR., ’Zap-
ping Input VZAP’.
1
fc l k ()
tpr >
th > 0m s
tp r
t > 50µ s
PSMI
VZA P= Vtl( )hi
th
VDD
tp r
MA
S
T
A
R
T
S
L
I
X
D
0
X
D
1
D
5
0
X
D
5
1
X
N
E
R
R
Figure 11: Serial timing of Read ROM Mode
t
>
4
0
µ
s
1
fc l k ( )
t
p
r
>
t
h
>
0
m
s
t > 50 µ s
th
t
p
r
P
S
M
I
t
>
4
0
µ
s
V
Z
A
P
=
V
t
l
(
)
h
i
VD D
MA
t
p
r
D0
X
D 1
X
D 50
X
D
5
1
S
T
A
R
T
S
L
I
X
X
X
X
X
N
E
R
R
Figure 12: Serial timing of Write RAM Mode
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 13/22
th > 0m s
tz ap( )
t > 50µ s
PSMI
V Z A P = V t( )z a p
th
VDD
tz a p ()
MA
D0
X
D1
X
D50
X
D51
S TA RT
SLI
X
X
X
X
X
NER R
Figure 13: Serial timing of Write ROM Mode
RO M
Z a p pi n g Dio d e s
R
A
M
Figure 13 shows the serial timing of a Write ROM op-
eration (burning the Zener zap diodes). The bit stream
is described in Table 4. Each Zener zap diode can be
programmed once with a logic of ’1’. The default value
of the Zener zap diodes is a logic ’0’ (with the excep-
tion of ZTEST(1:0)). The resulting parameter (OFF-
SET, MODE and ENERR) are generated by an xor op-
eration of the three sets of bits (see Figure 15).
O FF SET1
O FF SET2
O FF SET3
=1
=1
=1
OF F SE T
MO DE
1
0
0
n
F
M OD E 1
M OD E 2
M OD E 3
V DD
+ 5 V
+ 7 V
V ZAP
1
0
0
n
F
1
0
µ
F
+
P
r
o
g
r
a
m
m
i
n
g
Boa r d
M A
S LI
iC -M P
Serial
Interface
EN ER R 1
EN ER R 2
EN ER R 3
NE RR
P SMI
E NE R R
0 V
G
N
D
Figure 14: In-circuit programming
CR CI D
Z TE S T
T ES T
C RC ID
Z TES T
A 100 nF ceramic block capacitor must be placed on
the board directly between iC-MP’s VZAP and GND
pins. A 10 µF capacitor must also be present at the
end of the programming line as close to the connec-
tor as possible (see Figure 14). During programming,
up to 90 mA flow from pin VZAP to pin GND, making
it necessary to ensure proper PCB layout to minimize
voltage drops.
Figure 15: ROM construction
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 14/22
D(51:0)
7:0
Parameter
Description
ENERR
OFFSET1(7:0)
MODE1(3:0)
Offset of the first set
The parameter ENERR indicates two kind of errors. If
the magnetic field strength is at low a ’Loss of Mag-
net’ is generated. An ’Excessive Frequency Alarm’ is
generated when the revolution per minute is to high.
Parameter ENERR handles the various error types.
11:8
Mode of the first set,
see Table 5 and 6
13:12
ENERR1(1:0)
Error mask of the first
set, see Table 8
21:14
25:22
OFFSET2(7:0)
MODE2(3:0)
Offset of the second set
Mode of the second set,
see Table 5 and 6
ENERR1(1:0)
ENERR2(1:0)
ENERR3(1:0)
D(13:12)
D(27:26)
D(41:40)
27:26
ENERR2(1:0)
Error mask of the
second set, see Table 8
Code
00
Error
No Error
35:28
39:36
OFFSET3(7:0)
MODE3(3:0)
Offset of the third set
Mode of the third set,
see Table 5 and 6
01
Loss of Magnet*
41:40
ENERR3(1:0)
Error mask of the third
set, see table 8
10
Excessive Frequency Alarm
Excessive Frequency Alarm or Loss of Magnet*
11
45:42
47:46
CRCID(3:0)
ZTEST(1:0)
CRC ID
*) see ’DESIGN REVIEW’
Zener zap diodes, for
iC-Haus test purposes
only
Table 8: Error masks
51:48
TEST(3:0)
See ’TEST MODES’
Calculating the position offset
Table 4: Programming Datastream
Before iC-MP outputs the actual position via the serial
interface or the linear analog output (LAO), an offset is
added internally. This offset consists of the following
parameters:
MODE1(1:0)
D(9:8)
D(23:22)
D(37:36)
Full Scale Angle
360°
MODE2(1:0)
MODE3(1:0)
OFFSET = OFFSET1 xor OFFSET2 xor OFFSET3
Code
00
The offset is programmed in several stages (see Fig-
ure 16). It is important that the direction of rotation is
programmed prior to this (MODE Bit 2). To determine
the actual configured offset, all three offset parameters
must be read out. After these parameters have been
xored the actual offset is determined:
01
270°
10
180°
11
90°
Table 5: Linear Analog Output - Mode Bit 1:0
MODE1(2)
D(10)
D(24)
D(38)
Actual Offset = OFFSET1 xor OFFSET2 xor OFFSET3
MODE2(2)
MODE3(2)
To calculate the new offset the actual position at the
required offset is required. The formula used to calcu-
late this new offset is as follows:
Code
Rotation
0
1
CW*
CCW*
*) CW = clockwise, CCW = counter-clockwise
New Offset = 256 - Actual Position + Actual Offset
Table 6: Mode Bit 2
MODE1(3)
MODE2(3)
MODE3(3)
Code
D(11)
D(25)
D(39)
Range
0
(0 % - 100 %) * VDD
(10 % - 90 %) * VDD
1
Table 7: Linear Analog Output - Mode Bit 3
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 15/22
CRCID
S tar t
The CRCID parameter contains the CRC start value.
Configuring the CRC starting value enables a data
value to be clearly assigned to a slave, as the CRC
check fails with a faulty configuration of the master or
an exchange sequence. For example, the controller
assigns a start value for each slave and writes these
to the CRCID slave parameter.
S et: MOD Ex ( bi t 2)
f i nal l y
For CRC calculation, see ’SERIAL OUTPUT (SLO)’.
OFFS E T1
Re ad out: OFFS E T2
OFFS E T3
R ead out
ac tu al pos i t i on
C al cul a te ac tu al
pos i t i on o ff set
C al cul a te ne w
pos i t i on o ff set
OFFS E T1
Se t par am: OFFSE T2
OFFS E T3
E nd
Figure 16: Principle of offset calculation
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 16/22
FAST SCANNING MODE
VZAP
PSMI
FAST SCANNING
VDD
VDD
VDD
VZAP
VZAP
VZAP
MP0
MP0
MP0
Hall Angle Encoder
XFS3
Hall Angle Encoder
XFS2
Hall Angle Encoder
XFS1
PSMI
PSMI
PSMI
PSMO
SLO
PSMO
SLO
PSMO
SLO
B
B
B
SLI
SLI
SLI
SLI
MA
MA
MA
R1
2.2k
NERR
LAO
NERR
LAO
NERR
LAO
SLAVE 3
SLAVE 2
SLAVE 1
GND
GND
GND
MA
NERR
LAO(2:0)
0
1
2
LAO(2:0)
SLO
Figure 17: Fast Scanning Mode
In Fast Scanning Mode all devices are active at the page 17). Parameter CRCID can be used for improved
same time. With a start condition at MA the abso- differentiation of the individual data words. See ’PRO-
lute position of all devices is latched and all absolute GRAMMING MODE’.
positions are transferred as one long data word (see
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 17/22
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 18/22
SLOW SCANNING MODE
VZAP
PSMI
VDD
VDD
VDD
VZAP
VZAP
VZAP
MP0
MP0
MP0
SLOW SCANNING
Hall Angle Encoder
XSS3
Hall Angle Encoder
XSS2
Hall Angle Encoder
XSS1
R1
2.2k
PSMI
PSMI
PSMI
PSMO
SLO
PSMO
SLO
PSMO
SLO
B
B
B
SLI
SLI
SLI
SLI
MA
MA
MA
NERR
LAO
NERR
LAO
NERR
LAO
SLAVE 3
SLAVE 2
SLAVE 1
GND
GND
GND
MA
NERR
LAO
SLO
Figure 18: Slow Scanning Mode
In Slow Scanning Mode only one device is activated in tiation of the individual data words. See ’PROGRAM-
a chain. This device transmits its absolute position on MING MODE’.
the SLO bus and the analog output voltage to the LAO The chain is reset by a logic high at the PSMI pin (see
bus. After an timeout at SLI, the next device is enabled page 19).
(PSMO hi → lo). The devices needs some time after
activation to find the actual position.
Application hints:
Parameter CRCID can be used for improved differen- See ’DESIGN REWIEW’.
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 19/22
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 20/22
APPLICATION CIRCUITS
Stand-alone example
Figure 19 shows an example circuit for stand-alone op-
eration of iC-MP. The device is in Fast Scanning Mode.
If the device is also to be programmed, pins PSMI, SLI
and VZAP should be connected to GND by a pull-down
resistor (e.g. 2.2 kΩ).
VD D
i C- MP
P S MI
G ND
P S MO
L AO
MA
N ER R
VD D
VZ AP
SL I
1µ F
B
S
L
O
H
a
l
l
A
n
g
l
e
E
n
c
o
d
e
r
Li near
A nal og O utput
Figure 19: Circuit for stand-alone operation
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 21/22
TEST MODES
iC-MP has several test settings which make internal Test modes can be triggered by programming the pa-
reference quantities and the amplified, differential Hall rameter TEST (D(51:48)). The individual test modes
voltages of the sensor pairs accessible at external pins are listed in the following table.
for measurement purposes. This signals enables a See ’ELECTRICAL CHARACTERISTICS’.
chip/package to be adjusted in relation to the magnet.
Op. Mode
TEST(3:0)
Pin NERR
analog
-
PSIN
NSIN
GAIN
Pin LAO
Pin PSMO
Comments
digital
NERR
-
-
-
Normal
Test 0
Test 1
Test 2
Notes
0ddd
1000
1001
1010
LAO
PSMO
PSMO
PSMO
PSMO
PCOS
NCOS
VREF
d = don’t care
Table 9: Test modes
DESIGN REVIEW: Notes On Chip Functions
iC-MP Y
No.
1
Function, Parameter/Code
Description and Application Notes
Slow Scanning Mode
(without a magnet):
Serial Interface Mode is discontinued without a magnet
- The start bit is not available
- The daisy chain is stopped
Table 10: Notes on chip functions regarding iC-MP chip releas Y
iC-Haus expressly reserves the right to change its products and/or specifications. An Infoletter gives details as to any amendments and additions made to the
relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by
email.
Copying – even as an excerpt – is only permitted with iC-Haus approval in writing and precise reference to source.
iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions
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merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which
information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or
areas of applications of the product.
iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical
applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of
use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued
annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in
Hanover (Hannover-Messe).
We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations
of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can
be put to.
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 22/22
ORDERING INFORMATION
Type
Package
DFN10
Order Designation
iC-MP
iC-MP DFN10
Evaluation Board
iC-MP EVAL MP1D
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Tel.: +49 (61 35) 92 92-0
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Fax: +49 (61 35) 92 92-192
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E-Mail: sales@ichaus.com
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