IC-MSA [ICHAUS]
SIN/COS SIGNAL CONDITIONER with AGC and 1Vpp DRIVER; SIN / COS信号调理器，带有AGC和1Vpp典型DRIVER
| 型号： | IC-MSA |
| 厂家： | 
IC-HAUS GMBH |
| 描述： | SIN/COS SIGNAL CONDITIONER with AGC and 1Vpp DRIVER |
| 文件： | 总29页 (文件大小：718K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 1/29
FEATURES
APPLICATIONS
♦ PGA inputs for differential and single-ended sensor signals up
to 20 kHz
♦ Selectable adaptation to voltage or current signals
♦ Flexible signal assignment due to input multiplexers
♦ Sine/Cosine signal conditioning for offset, amplitude and
phase
♦ Programmable sensor interface
for optical and magnetic position
sensors
♦ Linear gauges and incremental
encoders
♦ Linear scales
♦ Separate index signal conditioning
♦ Short-circuit-proof and reverse polarity tolerant output drivers
(1 Vpp to 100 Ω)
♦ Stabilized output signal levels due to automatic gain control
♦ Signal and system monitoring with configurable alarm output
♦ Supply voltage monitoring with integrated switches for
reversed-polarity-safe systems
PACKAGES
♦ Excessive temperature protection with sensor calibration
♦ I2C multi-master interface
♦ Supply from 4.3 to 5 V, operation within -40 °C to +115 °C
♦ Verifyable chip release code
♦ Pin compatible with iC-MSB
TSSOP20-TP
BLOCK DIAGRAM
VDDS
GNDS
VDD
REVERSE POLARITY
PROTECTION
GND
ERR
SCL
MONITORING
Tw Toff
SERIAL I2C
INTERFACE
CONFIGURATION
REGISTER
PwrOn
iC-MSA
SDA
PGA INPUT
SIGNAL PATH MUX
CALIBRATION
AUTOMATIC GAIN
CONTROL
ANALOG DRIVER
OUTPUT
X1
X2
X3
X4
X5
X6
PZ
NZ
PC
NC
PS
NS
I/V
x
CH0
-
I/V
I/V
I/V
I/V
I/V
x
x
x
CH2
-
x
+
-
x
x
ADJ
+
CH1
-
x
x
Copyright © 2013 iC-Haus
http://www.ichaus.com
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 2/29
DESCRIPTION
iC-MSA is a signal conditioner with line drivers for signals which controls the gain of all channels. Tem-
sine/cosine sensors which are used to determine po- perature and aging effects can be compensated for
sitions in linear and angular encoders, for example.
and the set signal amplitude is maintained with ab-
solute accuracy. At the same time the control cir-
Programmable instrumentation amplifiers with se- cuitry monitors both whether the sensor is functioning
lectable gain levels permit differential or referenced correctly and whether it is properly connected; signal
input signals; at the same time the modes of op- loss due to wire breakage, short circuiting, dirt or ag-
eration differentiate between high and low input ing, for example, is recognized when control thresh-
impedance. This adaptation of the iC to voltage or olds are reached and indicated at alarm output ERR.
current signals enables MR sensor bridges or photo-
sensors to be directly connected up to the device.
iC-MSA is protected against a reversed power supply
voltage; the integrated voltage switch for loads of up
The integrated signal conditioning unit allows signal to 20 mA extends this protection to cover the overall
amplitudes and offset voltages to be calibrated accu- system. The analog output drivers are directly cable-
rately and also any phase error between the sine and compatible and tolerant to false wiring; if supply volt-
cosine signals to be corrected. Separate zero signal age is connected up to these pins, the device is not
conditioning settings can be made for the gain and destroyed.
offset; data is then output either as an analog or a
differential square-wave signal (low/high level analo- The device configuration and calibration parameters
gous to the sine/cosine amplitude).
are CRC protected and stored in an external EEP-
ROM; they are loaded automatically via the I2C in-
For the stabilization of the output levels a signal is terface once the supply voltage has been connected
generated from the conditioned and calibrated input up.
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 3/29
CONTENTS
PACKAGING INFORMATION
4
SIGNAL PATH MULTIPLEXING
SIGNAL CONDITIONING CH1, CH2
20
PIN CONFIGURATION TSSOP20-TP . . . .
4
21
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
5
5
Gain Settings CH1, CH2 . . . . . . . . . . . . 21
Offset Calibration CH1, CH2 . . . . . . . . . 22
Phase Correction CH1 vs. CH2 . . . . . . . . 22
ELECTRICAL CHARACTERISTICS
PROGRAMMING
6
SIGNAL CONDITIONING CH0
23
10
Gain Settings CH0 . . . . . . . . . . . . . . . 23
Offset Calibration CH0 . . . . . . . . . . . . . 23
SERIAL CONFIGURATION INTERFACE
(EEPROM)
13
AUTOMATIC SIGNAL GAIN CONTROL and
Example of CRC Calculation Routine . . . . . 13
EEPROM Selection . . . . . . . . . . . . . . 13
I2C Slave Mode (ENSL = 1) . . . . . . . . . . 14
SIGNAL MONITORING
24
25
ERROR MONITORING AND ALARM OUTPUT
Alarm Output: I/O pin ERR . . . . . . . . . . 25
Excessive Temperature Warning . . . . . . . 25
Driver Shutdown . . . . . . . . . . . . . . . . 25
Error Protocol . . . . . . . . . . . . . . . . . . 25
BIAS SOURCE AND TEMPERATURE
SENSOR CALIBRATION
15
16
OPERATING MODES
Calibration Op. Modes . . . . . . . . . . . . . 16
Special Device Test Functions . . . . . . . . 16
Signal Filter . . . . . . . . . . . . . . . . . . . 16
REVERSE POLARITY PROTECTION
APPLICATION HINTS
26
27
TEST MODE
INPUT CONFIGURATIONS
17
18
PLC Operation . . . . . . . . . . . . . . . . . 27
Connecting MR sensor bridges for
safety-related applications . . . . . . . . 27
Current Signals . . . . . . . . . . . . . . . . . 18
Voltage Signals . . . . . . . . . . . . . . . . . 18
Motor feedback encoder with iC-MSA,
iC-MSB and single EEPROM . . . . . . 28
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 4/29
PACKAGING INFORMATION
PIN CONFIGURATION TSSOP20-TP
PIN FUNCTIONS
No. Name Function
1 X1
2 X2
3 X3
4 X4
Signal Input 1 (Index +)
Signal Input 2 (Index -)
Signal Input 3
Signal Input 4
5 VDDS1) Switched Supply Output and Internal
Analog Supply Voltage
(reverse-polarity-proof, load 20 mA
max.)
6 GNDS1) Switched Ground
(reverse-polarity-proof)
7 X5
8 X6
Signal Input 5
Signal Input 6
9 N.C.
10 SDA
Not Connected
Serial Configuration Interface,
data line
11 SCL
Serial Configuration Interface,
clock line
12 NC
13 PC
14 NS
15 PS
16 GND
17 VDD
18 NZ
19 PZ
Neg. Cosine Output
Pos. Cosine Output
Neg. Sine Output
Pos. Sine Output
Ground
+4.3 V to +5.5 V Supply Voltage
Neg. Index Output
Pos. Index Output
Error Signal (In/Out),
Test Mode Trigger Input
20 ERR
TP2)
Thermal Pad (TSSOP20-TP)
1) It is advicable to connect a bypass capacitor of at least 100 nF close to the chip’s analog supply terminals.
2) To improve heat dissipation the thermal pad of the package (bottom side) should be joined to an extended copper area which must have GNDS potential.
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 5/29
ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Max.
G001 V()
Voltage at VDD, GND, PC, NC, PS, NS,
PZ, NZ
-6
6
V
G002 V()
G003 V()
Voltage at ERR
-6
8
6
V
V
Pin-To-Pin Voltage between VDD,
GND, PC, NC, PS, NS, PZ, NZ, ERR
G004 V()
Voltage at X1...X6, SCL, SDA
-0.3
VDDS +
0.3
V
G005 I(VDD)
G006 I()
Current in VDD
-100
-50
100
50
mA
mA
mA
Current in VDDS, GNDS
G007 I()
Current in X1...X6, SCL, SDA, ERR,
PC, NC, PS, NS, PZ, NZ
-20
20
G008 Vd()
G009 Ptot
G010 Tj
ESD Susceptibility at all pins
Permissible Power Dissipation
Junction Temperature
HBM 100 pF discharged through 1.5 kΩ
2
kV
mW
°C
TSSOP20-TP
400
150
150
-40
-40
G011 Ts
Storage Temperature Range
°C
THERMAL DATA
VDD = 4.3...5.5 V
Item Symbol
No.
Parameter
Conditions
Unit
Min. Typ. Max.
-40 115
T01 Ta
Operating Ambient Temperature Range TSSOP20-TP
°C
T02 Rthja
Thermal Resistance Chip to Ambient TSSOP20-TP surface mounted to PCB
according to JEDEC 51
35
K/W
All voltages are referenced to Pin GNDS unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 6/29
ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = 4.3...5.5 V, Tj = -40...125 °C, IBN calibrated to 200 µA, reference point GNDS, unless otherwise stated.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
Total Device
001
VDD
Permissible Supply Voltage
Load current I(VDDS) < -10 mA
Tj = 27 °C, no load
4.3
4.5
5.5
5.5
V
V
002 I(VDD)
003 I(VDDS)
004 Vcz()hi
005 Vc()hi
Supply Current in VDD
25
50
0
mA
mA
V
Permissible Load Current VDDS
Clamp Voltage hi at all pins
-20
11
1.5
Clamp Voltage hi at inputs
SCL, SDA
Vc()hi = V() − V(VDDS), I() = 1 mA
Vc()hi = V() − V(VDDS), I() = 4 mA
I() = -4 mA
0.4
0.3
V
006 Vc()hi
007 Vc()lo
Clamp Voltage hi at inputs
X1...X6
1.2
V
Clamp Voltage lo at all pins
-1.2
-1
-0.3
1
V
008 Irev(VDD) Reverse-Polarity Current VDD vs. V(VDD) = −5.5 V...−4.3 V
mA
GND
Signal Conditioning, Inputs X3...X6
101
102
Vin()sig
Iin()sig
Permissible Input Voltage Range
Permissible Input Current Range
RIN12(3:0) = 0x01
RIN12(3:0) = 0x09
0.75
0
VDDS
− 1.5
VDDS
V
V
RIN12(0) = 0, BIAS12 = 0
RIN12(0) = 0, BIAS12 = 1
-300
10
-10
300
µA
µA
103 Iin()
104
Input Current
RIN12(3:0) = 0x01
-10
10
µA
Rin()
Input Resistance vs. VREFin
Tj = 27 °C;
RIN12(3:0) = 0x09
RIN12(3:0) = 0x00
RIN12(3:0) = 0x02
RIN12(3:0) = 0x04
RIN12(3:0) = 0x06
16
1.1
1.6
2.2
3.2
20
1.6
2.3
3.2
4.6
24
2.1
3.0
4.2
6.0
kΩ
kΩ
kΩ
kΩ
kΩ
105 TCRin()
Temperature Coefficient Rin
0.15
%/K
106
VREFin12 Reference Voltage
RIN12(0) = 0, BIAS12 = 1
RIN12(0) = 0, BIAS12 = 0
1.35
2.25
1.5
2.5
1.65
2.75
V
V
107
G12
Gain Factors
GC2 = 0x80;
RIN12(3:0) = 0x01, GR12 and AGCGF1 = min.
RIN12(3:0) = 0x01, GR12 and AGCGF1 = max.
0.8
116
RIN12(3:0) = 0x09, GR12 and AGCGF1 = min.
RIN12(3:0) = 0x09, GR12 and AGCGF1 = max.
0.2
29
108 ∆Gdiff
109 ∆Gabs
Differential Gain Accuracy
Absolute Gain Accuracy
calibration range 11 bit
-0.5
-1
0.5
1
LSB
LSB
calibration range 11 bit, guaranteed monotony
110
Vin()diff
Recommended Differential Input
Voltage
Vin()diff = V(CHPx) - V(CHNx),
RIN12(3) = 0
10
40
500
2000
mVpp
mVpp
RIN12(3) = 1
111 Vin()os
112
Input Offset Voltage
refered to side of input
0
20
µV
VOScal
Offset Calibration Range
referenced to the selected source (VOS12);
ORx = 00
ORx = 01
ORx = 10
ORx = 11
±100
±200
±600
±1200
%V()
%V()
%V()
%V()
113 ∆VOSdiff Differential Linearity Error of
calibration range 11 bit
-0.5
-1
0.5
1
LSB
Offset Correction
114 ∆VOSint Integral Linearity Error of Offset calibration range 11 bit
LSB
Correction
115 PHIkorr
Phase Error Calibration Range
CH1 versus CH2
±10.4
°
116 ∆PHIdiff
Differential Linearity Error of
Phase Calibration
calibration range 10 bit
-0.5
-1
0.5
1
LSB
117 ∆PHIint
Integral Linearity Error of Phase calibration range 10 bit
Calibration
LSB
kHz
119 fin()max
Permissible Input Frequency
20
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 7/29
ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = 4.3...5.5 V, Tj = -40...125 °C, IBN calibrated to 200 µA, reference point GNDS, unless otherwise stated.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
120 fhc()
Input Amplifier Cut-off Frequency
(-3dB)
100
kHz
Signal Conditioning, Inputs X1, X2
201
Vin()sig
Permissible Input Voltage Range
RIN0(3:0) = 0x01
RIN0(3:0) = 0x09
0.75
0
VDDS
− 1.5
VDDS
V
V
202
Iin()sig
Permissible Input Current Range
RIN0(0) = 0, BIAS0 = 0
RIN0(0) = 0, BIAS0 = 1
-300
10
-10
300
µA
µA
203 Iin()
Input Current
RIN0(3:0) = 0x01
-10
95
10
µA
%
204 Vout(X2)
Output Voltage at X2
BIASEX = 10, I(X2) = 0, referenced to VRE-
Fin12
100
28
105
205 Vin(X2)
206 Rin(X2)
Permissible Input Voltage at
Input Resistance at X2
BIASEX = 11
0.5
20
VDDS
− 2
35
V
BIASEX = 11, RIN0(3:0) = 0x01, RIN12(3:0) =
0x01
kΩ
207
Rin()
Input Resistance vs. VREFin
Tj = 27 °C;
RIN0(3:0) = 0x09
RIN0(3:0) = 0x00
RIN0(3:0) = 0x02
RIN0(3:0) = 0x04
RIN0(3:0) = 0x06
16
1.1
1.6
2.2
3.2
20
1.6
2.3
3.2
4.6
24
2.1
3.0
4.2
6.0
kΩ
kΩ
kΩ
kΩ
kΩ
208 TCRin()
Temperature Coefficient Rin
0.15
%/K
209
VREFin0 Reference Voltage
RIN0(0) = 0, BIAS0 = 1
RIN0(0) = 0, BIAS0 = 0
1.35
2.25
1.5
2.5
1.65
2.75
V
V
210
G0
Gain Factors
GC0 = 0x80;
RIN0(3:0) = 0x01, GR0 and AGCGF1 = min.
RIN0(3:0) = 0x01, GR0 and AGCGF1 = max.
0.8
116
RIN0(3:0) = 0x09, GR0 and AGCGF1 = min.
RIN0(3:0) = 0x09, GR0 and AGCGF1 = max.
0.2
29
211 ∆Gdiff
212 ∆Gabs
Differential Gain Accuracy
Absolute Gain Accuracy
calibration range 5 bit
-0.5
-1
0.5
1
LSB
LSB
calibration range 5 bit, guaranteed monotony
213
Vin()diff
Recommended Differential Input
Voltage
Vin()diff = V(CHP0) - V(CHN0),
RIN0(3:0) = 0x01
10
40
500
2000
mVpp
mVpp
RIN0(3:0) = 0x09
214 Vin()os
215
Input Offset Voltage
referred to side of input
0
75
µV
VOScal
Offset Calibration Range
referenced to the selected source (REFVOS);
OR0 = 00
OR0 = 01
OR0 = 10
OR0 = 11
±100
±200
±600
±1200
%V()
%V()
%V()
%V()
216 ∆VOSdiff Differential Linearity Error of
calibration range 6 bit
-0.5
-1
0.5
1
LSB
Offset Correction
217 ∆VOSint Integral Linearity Error of Offset calibration range 6 bit
LSB
Correction
Signal Filter
301
4000
10
kHz
°
fg
Cut-off Frequency
Phase Shift
302
fin 500 kHz for sine/cosine
phi
Index Pulse Comparator Output PZ, NZ
401 Vpk()
Output Amplitude With Automatic EAZ = 1, AGCOFF = 0, ADJ = 0x32
Gain Control
225
225
250
1
275
mV
402 SR()
Output Slew Rate
EAZ = 1
V/µs
Line Driver Outputs PS, NS, PC, NC, PZ, NZ
501
Vpk()max Permissible Output Amplitude
VDD = 4.5 V, DC level = VDD / 2,
RL = 50 Ω vs. VDD / 2
300
275
mV
mV
502 Vpk()
Output Amplitude With Automatic AGCOFF = 0, ADJ (5:0) = 0x32
Gain Control
250
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 8/29
ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = 4.3...5.5 V, Tj = -40...125 °C, IBN calibrated to 200 µA, reference point GNDS, unless otherwise stated.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
503 fg
Cut-off Frequency
Offset Voltage
CL = 250 pF
500
kHz
µV
504 Vos
505 Isc()
506 Ilk()
±200
30
Short-circuit Current
Tristate Leakage Current
pin shorten to VDD or GND
tristate or reversed supply
10
-1
50
1
mA
µA
Automatic Signal Gain Controller
601 tset()
Automatic Gain Settling Time
square control active, AGCGF1: 0x40 → 0x80
CH1 gain/GR12, AGCGF1 = 0x10
2
ms
602 Gt()min
Control Range Monitoring 1:
lower limit
1.2
603 Gt()max
604 Vt()min
605 Vt()max
Control Range Monitoring 2:
upper limit
CH1 gain/GR12, AGCGF1 = 0xF0
referenced to Vscq()
16.6
40
Signal Level Monitoring 1:
lower limit
%Vpp
%Vpp
Signal Level Monitoring 2:
upper limit
referenced to Vscq()
130
Test Current ERR
701 I(ERR)
Permissible Test Current
test mode activated
0
1
mA
Bias Current Source and Reference Voltages
801 IBN()
802 VPAH
Bias Current Source
MODE(3:0) = 0x01, I(NC) vs. VDDS
referenced to GND
180
45
200
50
220
55
µA
%VDD
mV
Reference Voltage VPAH
Reference Voltage V05
Reference Voltage V025
803 V05
450
500
50
550
804 V025
%V05
Power-Down-Reset
901 VDDon
Turn-on Threshold
(power-on release)
increasing voltage at VDD vs. GND
decreasing voltage at VDD vs. GND
VDDhys = VDDon − VDDoff
3.7
3.2
0.3
4
4.3
3.8
V
V
V
902 VDDoff
Turn-off Threshold
(power-down reset)
3.5
903 VDDhys
Clock Oscillator
A01 fclk()
Threshold Hysteresis
Internal Clock Frequency
MODE(3:0) = 0x0A, fclk(NS)
vs. GND, I() = 4 mA
120
160
200
0.4
kHz
Error Signal Input/Output, Pin ERR
B01 Vs()lo
B02
Saturation Voltage lo
Short-circuit Current lo
V
Isc()
vs. GND; V(ERR) ≤ VDD
4
2
mA
mA
V(ERR) > VTMon
B03 Vt()hi
B04 Vt()lo
B05 Vt()hys
B06 Ipu()
Input Threshold Voltage hi
Input Threshold Voltage lo
Input Hysteresis
vs. GND
2
V
V
vs. GND
0.8
300
-400
Vt()hys = Vt()hi − Vt()lo
V() = 0...VDD − 1 V, EPU = 1
EPU = 0
500
-300
500
mV
µA
kΩ
V
Input Pull-up Current
Input Pull-Up Resistor
Pull-up Voltage
-200
0.4
B07 Rpu()
B08 Vpu()
B09 VTMon
Vpu() = VDD - V(), I() = -5 µA, EPU = 1
Test Mode Activation Threshold increasing voltage at ERR
VDD +
1.5
V
B10 VTMoff
Test Mode Disabling Threshold
decreasing voltage at ERR
VDD +
0.5
V
B11 VTMhys
B12 Ilk()
Test Mode Hysteresis
Leakage Current
VTMhys = VTMon − VTMoff
tristate or reversed supply voltage
0.15
-1
0.3
-10
V
-50
µA
Supply Switch and Reverse Polarity Protection VDDS, GNDS
C01
Vs()
Saturation Voltage
VDDS vs. VDD
Vs(VDDS) = VDD − V(VDDS)
I(VDDS) = -10 mA...0 mA
I(VDDS) = -20 mA...-10 mA
150
250
mV
mV
C02
Vs()
Saturation Voltage
GNDS vs. GND
Vs(GNDS) = V(GNDS) − GND
I(GNDS) = 0 mA...10 mA
150
250
mV
mV
I(GNDS) = 10 mA...20 mA
C03 C()
Backup Capacitor Analog Supply
VDDS vs. GNDS
100
nF
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 9/29
ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = 4.3...5.5 V, Tj = -40...125 °C, IBN calibrated to 200 µA, reference point GNDS, unless otherwise stated.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
Serial Configuration Interface SCL, SDA
D01 Vs()lo
D02 Isc()
Saturation Voltage lo
Short-circuit Current lo
I() = 4 mA
400
80
2
mV
mA
V
4
D03 Vt()hi
D04 Vt()lo
D05 Vt()hys
D06 Ipu()
D07 Vpu()
Input Threshold Voltage hi
Input Threshold Voltage lo
Input Hysteresis
0.8
300
-600
V
Vt()hys = Vt()hi − Vt()lo
V() = 0...VDDS − 1 V
500
mV
µA
V
Input Pull-up Current
-300
-60
0.4
Input Pull-up Voltage
Vpu() = VDDS − V(), I() = -5 µA
D08
fclk(SCL) Clock Frequency at SCL
ENFAST = 0
ENFAST = 1
60
240
80
320
100
400
kHz
kHz
D09
tbusy()cfg Duration of Startup Configuration
IBN not calibated, EEPROM access without
read failure, time to outputs operational;
ENFAST = 0
40
25
55
35
ms
ms
ENFAST = 1
D10
D11
tbusy()err End Of I2C Communication;
IBN not calibrated;
Time Until I2C Slave Is Enabled V(SDA) = 0 V
4
indef.
45
12
ms
ms
ms
ms
V(SCL) = 0 V or arbitration lost
no EEPROM
CRC ERROR
135
285
95
td()
Start Of Master Activity On I2C
Protocol Error
SCL without clock signal: V(SCL) = constant;
IBN not calibrated
IBN calibrated to 200 µA
25
64
80
80
240
120
µs
µs
D12 td()i2c
Delay for I2C-Slave-Mode Enable no EEPROM, V(SDA) = 0 V
4
6.2
ms
Temperature Monitoring
E01
E02 TCs
E03
VTs
Temperature Sensor Voltage
VTs() = VDDS − V(PS), Tj = 27 °C,
600
650
-1.8
700
mV
Calibration Mode 3, no load
Temp. Co. of Temperature Sen-
sor Voltage
mV/K
VTth
Temperature Warning Activation
Threshold
VTth() = VDDS − V(NS), Tj = 27 °C,
Calibration Mode 3, no load;
CFGTA(3:0) = 0x00
260
470
310
550
360
630
mV
mV
CFGTA(3:0) = 0x0F
E04 TCth
Temp. Co. Temperature Warning
Activation Threshold
0.06
%/K
E05 Thys
Temperature Warning Hysteresis
4
4
12
12
20
20
°C
°C
E06 ∆T
Relative Shutdown Temperature ∆T = Toff − Twarn
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 10/29
PROGRAMMING
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 11 Signal Conditioning CH1, CH2 (X3...X6) . . Page 21
GR12:
VOS12:
OR1:
OF1:
OR2:
OF2:
PH12:
GC2:
Gain Range CH1, CH2 (coarse)
Offset Reference Source CH1, CH2
Offset Range CH1 (coarse)
Offset Factor CH1 (fine)
Offset Range CH2 (coarse)
Offset Factor CH2 (fine)
Configuration Interface . . . . . . . . . . . . . . . . . . . Page 13
ENFAST:
ENSL:
I2C Fast Mode Enable
I2C Slave Mode Enable
DEVID:
Device ID of EEPROM providing the
chip configuration data (e.g. 0x50)
CRC of chip configuration data
(address range 0x40 to 0x5E)
Chip Release
Phase Correction CH1 vs. CH2
Gain Correction CH2 (fine)
CHKSUM:
Signal Conditioning CH0 (X1, X2) . . . . . . . . . Page 23
CHPREL:
NTRI:
GC0:
GR0:
VOS0:
OR0:
OF0:
Gain Correction CH0 (fine)
Gain Range CH0 (coarse)
Offset Reference Source CH0
Offset Range CH0 (coarse)
Offset Factor CH0 (fine)
Tristate Function and
Op. Mode Change
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 15
CFGIBN:
CFGTA:
Bias Calibration
Temperature Sensor Calibration
Signal Level Controller . . . . . . . . . . . . . . . . . . . . Page 24
AGCOFF:
ADJ:
Setup of AGC
AGC Setpoint
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . Page 16
MODE:
ENF:
Operation Mode
Signal Filtering
Error Monitoring and Alarm Output . . . . . . Page 25
EMTD:
EPH:
Minimal Alarm Indication Time
Alarm Input/Output Logic
Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Seite 17
TMODE: Test Mode Functions
EPU:
EMASKA:
Alarm Output Pull-Up Enable
Error Mask For Alarm Indication (pin
ERR)
Input Configuration and
Signal Path Multiplexer . . . . . . . . . . . . . . . . . . . Page 18
EMASKE:
EMASKO:
Error Mask For Protocol (EEPROM)
Error Mask For Driver Shutdown
INMODE:
RIN12:
Diff./Single-Ended Input Mode
I/V Mode and Input Resistance CH1,
CH2
ERR1:
ERR2:
ERR3:
Error Protocol: First Error
Error Protocol: Last Error
Error Protocol: History
BIAS12:
RIN0:
BIAS0:
MUXIN:
Reference Voltage CH1, CH2
I/V Mode and Input Resistance CH0
Reference Voltage CH0
Input-To-Channel Assignment:
X3...X6 to CH1, CH2
PDMODE:
AGCGF1:
Driver Activation After Cycling Power
AGC Gain Fine CH1 (read-only)
INVZ:
EAZ:
BIASEX:
BYP
Index Signal Inversion
Index Comparator Enable
Input Reference Selection
Input-to-output Feedthrough
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 11/29
OVERVIEW
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Configuration Interface
0x40
ENFAST
DEVID(6:0)
Calibration
0x41
CFGIBN(3:0)
CFGTA(3:0)
Operation Modes
0x42 NTRI
1
0
–
MODE(3:0)
Input Configuration and Signal Path Multiplexer
0x43
0x44
EAZ
0
0
0
0
1
INVZ
0
INMODE
MUXIN(1:0)
0
0
0
0
0
Signal Level Controller
0x45 AGCOFF
Signal Conditioning CH1, CH2
0
ADJ(5:0)
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0
0
0
0
0
0
0
1
0
0
1
0
GR12(2:0)
0
0
0
0
0
0
0
0
OR1(0)
OF1(6:0)
OR1(1)
OF2(1:0)
OR2(1:0)
OF1(10:7)
OF2(9:2)
PH12(6:0)
1
OF2(10)
BIASEX(1:0)
ENF BIAS12
BYP
1
PH12(9:7)
RIN12(3:0)
VOS12(1:0)
GC2(7:0)
Signal Conditioning CH0
0x50
0x51
0x52
GC0(7:0)
-
GR0(2:0)
OR0(1:0)
OF0(5:0)
0x53
0
BIAS0
VOS0(1:0)
RIN0(3:0)
Error Monitoring and Alarm Output
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
–
–
–
EMASKA(6:0)
TMODE(1:0)
EMTD(2:0)
EPH
EPU
–
–
–
EMASKO(6:0)
EMASKE(3:0)
PDMODE
ENSL
–
–
–
–
EMASKE(6:4)
EEPROM: not defined
/ RAM: AGCGF1(10:3) (read-only)
not defined
OEM Data
OEM Data
0x5B..
0x5E
Check Sum
/ Chip Release
0x5F
EEPROM: CHKSUM(7:0) / ROM: CHPREL(7:0)
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 12/29
OVERVIEW
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Error Register
0x60
0x61
0x62
0x63
Notes
–
ERR1(6:0)
ERR2(5:0)
–
–
ERR3(3:0)
–
–
–
–
ERR2(6)
–
–
–
–
ERR3(6:4)
Register entries specified 0 or 1 mean a mandatory programming.
Table 4: Register layout
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 13/29
SERIAL CONFIGURATION INTERFACE (EEPROM)
The serial configuration interface consists of the two Example of CRC Calculation Routine
pins SCL and SDA and enables read and write access
to an EEPROM with I2C interface. The readout speed
can be adjusted using register bit ENFAST.
unsigned char ucDataStream
int iCRCPoly 0x11D ;
unsigned char ucCRC=0;
int 0;
= 0;
=
i
=
ENFAST
Code
0
Adr 0x40, bit 7
ucCRC = 1; / / s t a r t value ! ! !
Function
for ( iReg
= 0; iReg <31; iReg ++)
{
Regular clock rate, f(SCL) approx. 80 kHz
High clock rate, f(SCL) approx. 320 kHz
ucDataStream
for ( i =0; i <=7; i ++)
i f ( (ucCRC & 0x80 ) != ( ucDataStream & 0x80 ) )
ucCRC = (ucCRC << 1) iCRCPoly ;
else
ucCRC = (ucCRC << 1 ) ;
ucDataStream ucDataStream << 1;
= ucGetValue ( iReg ) ;
1
{
Notes
For in-circuit programming bus lines SCL and SDA
require pull-up resistors.
For line capacitances to 170 pF, adequate values
are:
4.7 kΩ with clock frequency 80 kHz
2 kΩ with clock frequency 320 kHz
^
=
}
}
The pull-up resistors may not be less than 1.5 kΩ.
To separate the signals a ground line between SCL
and SDA is recommended.
iC-MSA requires a supply voltage during EEPROM
programming (5 V to VDD).
EEPROM Selection
The following minimal requirements must be fulfilled:
• Operation from 3.3 to 5 V, I2C interface
Table 5: Config. Interface Clock Frequency
• Minimal 1024 bit, 128x8
Once the supply has been switched on (power down
reset) the iC-MSA outputs are high impedance (tris-
tate) until a valid configuration is read out from the
EEPROM using device ID 0x50.
(address range used is 0x40 to 0x7F)
• Support of Page Write with Pages of at least 4
bytes. Otherwise error events can not be saved
to the EEPROM (EMASKE(9:0) = 0x000).
Bit errors in the 0x40 to 0x5E memory section are
pinpointed by the CRC deposited in register CHK-
SUM(7:0) (address 0x5F; the CRC polynomial used is
"1 0001 1101").
• Device ID 0x50 "101 0000", no occupation of
0x57 (A2...A0 = 0). Otherwise iC-MSA is not ac-
cessible in I2C slave mode via 0x57 (ENSL = 0).
Recommended devices:
M24C01W, ST M24C02 (2K), ROHM BR24L01A-W,
BR24L02-W
Atmel AT24C01B, ST
Should no valid configuration data being available (in-
correct CRC value or EEPROM missing), the readin
process is repeated; the system aborts following a
fourth faulty attempt and iC-MSA switches to I2C slave
mode.
For devices loading valid configuration data from the
EEPROM, the register bit ENSL decides for enabling
the I2C slave function.
ENSL
Code
0
Adr 0x17, bit 3
Function
Normal operation
1
I2C Slave Mode Enable (Device ID 0x57)
Table 6: Config. Interface Mode
The device ID for the EEPROM can be entered in reg-
ister DEVID(6:0) (address 0x40), from which iC-MSA
will take its configuration after exiting test mode (see
page 17). The DEVID(6:0) stored therein is then ac-
cepted.
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 14/29
I2C Slave Mode (ENSL = 1)
Register
Read access in I2C slave mode (ENSL = 1)
Content
In this mode iC-MSA behaves like an I2C slave with the
device ID 0x57 and the configuration interface permits
write and read accesses to iC-MSA’s internal registers.
Address
0x00-0x03 Current error memory
0x04-0x3F Not available
0x40-0x58 Configuration: register addresses 0x40-0x58
0x59
0x5A
AGCGF1(10:3)
Not available
For chip release verification purposes an identification
value is stored under ROM address 0x5F; a write ac-
cess to this address is not permitted.
0x5B-0x5E OEM data: register addresses 0x5B-0x5E
0x5F Chip release (ROM)
0x60-0x63 Configuration: register addresses 0x60-0x63
0x64-0x77 Not available
CHPREL
Code
Adr 0x5F, bit 7:0 (ROM)
Chip Release
0x78
Configuration: register address 0x58
0x10
iC-MSA
0x79-0x7A Not available
0x7B-0x7E OEM data: register addresses 0x5B-0x5E
Table 7: Chip Release
0x7F
Chip release (ROM)
NTRI
Code
0
Adr 0x42, bit 7
Table 9: RAM Read Access
Function
Output drivers disabled
Register
Address
0x40
Write access in I2C slave mode (ENSL = 1)
Access and conditions
1
Setting the operating mode, output drivers active
NTRI is evaluated only during I2C slave mode.
Notes
Changes possible, no restrictions
0x41
Changes possible (wrong entries for CFGIBN can
limit functions)
Table 8: Tristate Function And Op. Mode Change
0x42
Bit 7 = 0 (NTRI): changes to bits (6:0) permitted
A change of operating mode follows only on writing
Bit 7 = 1 (NTRI); when doing so changes to bits
(6:0) are not permitted.
0x43-0x56 Changes possible, no restrictions
0x57
Bit 3 = 1 (ENSL):
changes to bits (7:4) and (2:0) permitted
0x58
Changes possible, no restrictions
0x59-0x5A Not available
0x5B-0x5E Changes possible, no restrictions
others
No changes permitted
Table 10: RAM Write Access
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 15/29
BIAS SOURCE AND TEMPERATURE SENSOR CALIBRATION
Bias Source Calibration
The necessary activation threshold voltage VTth(T1) is
The calibration of the bias current source in operation then calculated. The required warning temperature T2,
mode Calibration 1 (Tab. 13) is prerequisite for adher- temperature coefficients TCs and TCth (see Electrical
ence to the given electrical characteristics and also in- Characteristics, Section E) and measurement value
strumental in the determination of the chip timing (e.g. VTs(T1) are entered into this calculation:
SCL clock frequency). For setup purposes the IBN
value is measured using a 10 kΩ resistor by pin VDDS
connected to pin NC. The setpoint is 200 µA which is
equivalent to a measurement voltage of 2 V.
VTs(T1) + TCs · (T2 − T1)
VTth(T1) =
1 + TCth · (T2 − T1)
CFGIBN
Code k
0x0
Adr 0x41, bit 7:4
Example: For T2 = T1 + 100 K, VTth(T1) must be pro-
grammed to 443 mV.
31
39−k
31
39−k
IBN ∼
Code k
0x8
IBN ∼
100 %
103 %
107 %
111 %
115 %
119 %
124 %
129 %
79 %
81 %
84 %
86 %
88 %
91 %
94 %
97 %
0x1
0x9
Activation threshold voltage VTth(T1) is provided for a
high impedance measurement (10 MΩ) at output pin
NS (measurement versus VDDS) and must be set by
programming CFGTA(3:0) to the calculated value.
0x2
0xA
0xB
0xC
0xD
0xE
0xF
0x3
0x4
0x5
0x6
Example: Altering VTth(T1) from 310 mV (measured
with CFGTA(3:0)= 0x0) to 443 mV is equivalent to
143 %, the closest value for CFGTA is 0x9;
0x7
Table 11: Bias Current Source Calibration
CFGTA
Code k
0x0
Adr 0x41, bit 3:0
65+3k
VTth ∼
65
65+3k
65
Code k
0x8
VTth ∼
140 %
145 %
150 %
155 %
160 %
165 %
170 %
175 %
Temperature Sensor
The temperature monitor is calibrated in operating
mode Calibration Mode 3.
100 %
105 %
110 %
115 %
120 %
125 %
130 %
135 %
0x1
0x9
0x2
0xA
0xB
0xC
0xD
0xE
0xF
0x3
To set the required warning temperature T2 the tem-
perature sensor voltage VTs at which the warning is
generated is first determined. To this end a volt-
age ramp from VDDS towards GNDS is applied to
pin PS until pin ERR triggers an error message (for
EMASKA = 0x20 and EMTD = 0x00).
0x4
0x5
0x6
0x7
Notes
With CFGTA = 0xF Toff is 80 °C typ.,
with CFGTA = 0x0 Toff is 155 °C typ.
Example: VTs(T1) is ca. 650 mV, measured from
VDDS versus PS, with T1 = 25 °C;
Table 12: Calibration of Temperature Monitoring
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 16/29
OPERATING MODES
In order to calibrate iC-MSA, compensate for the input to the various operating modes; the line drivers and
signals and test iC-MSA the mode of operation must protection against reverse polarity facility are only ac-
be changed. The output function changes according tive in normal mode.
MODE(3:0)
BYP
Addr. 0x42; bit 3:0
Addr. 0x4D; bit 5
Code
0x00
Operating Mode
Normal operation
Calibration 1
Pin PS
PS
Pin NS
NS
Pin PC
PC
Pin NC
NC
Pin PZ
PZ
Pin NZ
NZ
Pin ERR
ERR
ERR
—
0x01
TANA0(2)
PCH1
VREFI0
NCH1
VPD
VREFI12
PCH2
—
IBN
PZI
NZI
0x02
Calibration 2
NCH2
CGUCK
NC_out
NC_out
—
—
0x03
iC-Haus Test 1
iC-Haus Test 2
iC-Haus Test 3
VPAH
IPF
V05
IERR
IERR
ERR
0x04
PS_out
PS_out
NS_out
NS_out
PC_out
PC_out
PZ_out
PZ_out
NZ_out
NZ_out
0x05
0x06
iC-Haus Test 4, BYP = 0
iC-Haus Test 4, BYP = 1
TANA12(0) TANA12(1) TANA12(2) TANA12(3) TANA12(4) TANA12(5) IERR
X4
X6
X3
X5
X1
X2
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Calibration 3
VTs
VTth
—
—
—
—
ERR
Saturation low
SCL, SDA and ERR low
—
—
—
—
—
—
—
—
—
—
—
—
TP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
iC-Haus Test 5
CLK6
—
—
—
—
—
—
IDDQ-Test
—
All PU/PD resistors, oscillator and supply voltage deactivated
—
—
—
—
—
—
—
Table 13: Selection of Operating Modes
Calibration Op. Modes
Signal Filter
In Calibration Mode 1 the user can measure the BIAS iC-MSA has a noise limiting signal filter to filter the con-
current (IBN), input amplifier reference potential VREFI ditioned analog signals. This can be activated using
and the analog signals from channel 0 following signal ENF.
conditioning (PCH0 and NCH0).
ENF
Code
0
Adr 0x4E, bit 7
In Calibration Mode 2 the conditioned signals from
channels 1 and 2 are output (PCH1, NCH1, PCH2 and
NCH2).
In Calibration Mode 3 the internal temperature moni-
toring signals are provided.
Function
Noise limiter deactivated
Noise limiter activated
1
Table 14: Signal Filtering
Special Device Test Functions
IDDQ-Test, Saturation Low, Saturation High, and Test
1 to 5 are test modes for iC-Haus device tests. With an
activated bypass (BYP = 1), mode iC-Haus Test 4 per-
mits the direct feedthrough of X1 - X6 input signals to
the output pins; in this instance the output impedance
is high-ohmic. Furthermore, if the input voltage divider
is selected (by RINx = 1- -1), it reduces the signal am-
plitudes to approx. 7/8.
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 17/29
TEST MODE
iC-MSA switches to test mode if a voltage larger cessible at the device ID filed to DEVID(6:0) of address
than VTMon is applied to pin ERR (precondition: 0x40.
TMODE(0) = 1). In response iC-MSA transmits its con- In TMODE = 0x03 the EEPROM is read completely; in
figuration settings as current-modulated data using I/O all other cases only the address range 0x40 to 0x61 is
pin ERR after re-reading the EEPROM. If the voltage read to keep the configuration time for device testing
at pin ERR falls below VTMoff test mode is terminated short.
and data transmission aborted.
TMODE
Addr 0x55, bit 7:6
Code
Function during test
mode
Function following test
mode
The clock rate for the data output is determined by EN-
FAST. Two clock rates can be selected: 780 ns for EN-
FAST = 1 or 3.125 µs for ENFAST = 0 (see Elec. Char.
D08 for clock frequency and tolerances).
00
01
Normal operation
Transmission of
EEPROM data, address EEPROM
range 0x5B-0x7F and
0x00-0x3F
Normal operation
Repeated read out of
Data is output in Manchester code via two clock pulses
per bit. To this end the lowside current source switches
between a Z state (OFF = 0 mA) and an L state (ON =
2 mA).
10
11
Normal operation
Repeated read out of
EEPROM
Transmission of
Repeated read out of
EEPROM data, address EEPROM
range 0x40-0x7F and
0x00-0x3F
The bit information lies in the direction of the current
source switch:
Zero bit: change of state Z → L (OFF to ON)
Table 15: Test Mode Functions
One bit: Change of state L → Z (ON to OFF)
VP
U23-B
VP LM393
VP
7
8
6
5
VP
VP
C21
100nF
C22
100nF
-
U22-S
AD8029
VN
U23-S
LM393
GND
7
Transmission consists of a start bit (a one bit), 8 data
bits and a pause interval in Z state (the timing is iden-
tical with an EEPROM access via the I2C interface).
+
4
4
JP4
R24
470
ERR
max. 5V
VDD
M22
C24
IRLML6401
VP
R26
100pF
Example: byte value = 1000 1010
Transmission including the start bit: 1 1000 1010
In Manchester code: LZ LZZL ZLZL LZZL LZZL
100k
R23
2K
C26
R28
51k
U22-A
U23-A
LM393
100nF
R25
2k
2
D21
LL4148
-
M21
6
2
3
DATA_ON
AD8029
NDIS
-
2N7002
3
1
DATA_OUT
+
8
+
R21
475k
8
4
R27
100k
U21
LM285
VP
5
C25
100nF
R22
365k
Decoding of the data stream:
VDD
C23
100nF
dra_mq1d_error_schem
ZZZZZZ LZ LZ ZL ZL ZL LZ ZL LZ ZL ZZZZZZ
Pause 1 1 0 0 0 1 0 1 0 Pause
Figure 1: Example circuit for the decoding and con-
version of the current-modulated signals
to logic levels.
If test mode is quit with TMODE = 0x00, iC-MSA con-
tinues operation without any interruption.
If test mode is quit with TMODE > 0x00, then iC-MSA
again reads out its configuration from the EEPROM ac-
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 18/29
INPUT CONFIGURATIONS
INMODE
Addr 0x43, bit 2
All input stages are configured as instrumentation am-
Code
Function
plifiers and thus directly suitable for differential input
0
Differential input signals
Single-ended input signals *
signals. Referenced input signals can be processed
as an option; in this mode input X2 acts as a reference.
1
Note
* Input X2 is reference for all inputs.
Both current and voltage signals can be processed as
input signals, selected using RIN12(0) and RIN0(0).
Table 16: Input Signal Mode
RIN12
RIN0
Code
–000
–010
–100
–110
1—1
0—1
Addr 0x4E, bit 3:0
Addr 0x53, bit 3:0
Nominal Rin() Intern Rui()
I/V Mode
1.7 kΩ
2.5 kΩ
3.5 kΩ
4.9 kΩ
20 kΩ
1.6 kΩ
2.3 kΩ
3.2 kΩ
4.6 kΩ
5 kΩ
current input
current input
current input
current input
voltage input 4:1*
voltage input 1:1
high
1 MΩ
impedance
Notes
For single-ended signals identical settings of RIN0
and RIN12 are required.
Figure 2: Signal conditioning input circuit.
*) VREFin is the voltage divider’s footpoint; input
currents may be positive or negative (Vin > VREFin,
or Vin < VREFin).
Current Signals
Table 17: I/V Mode and Input Resistance
In I Mode an input resistor Rin() becomes active at
each input pin, converting the current signal into a volt-
age signal. Input resistance Rin() consists of a pad
wiring resistor and resistor Rui() which is linked to the
adjustable bias voltage source VREFin(). The follow-
ing table shows the possible selections, with Rin() giv-
ing the typical resulting input resistance (see Electrical
Characteristics for tolerances).
BIAS12
BIAS0
Code
0
Addr 0x4E, bit 6
Addr 0x53, bit 6
Function
VREFin = 2.5 V
for low-side current sinks (e.g. photodiodes with
common anode at GNDS)
1
VREFin = 1.5 V
for high-side currrent-sources (e.g. photodiodes
with common cathode at VDDS)
for voltage sources versus ground
(e.g. iC-SM2, Wheatstone sensor bridges)
for voltage sources with low-side reference
(e.g. iC-LSHB, when using BIASEX = 11)
NB. The input circuit is not suitable for back-to-back
photodiodes.
Table 18: Reference Voltage
Voltage Signals
In V Mode an optional voltage divider can be selected
which reduces unacceptably large input amplitudes to
ca. 25%. The circuitry is equivalent to the resistor
chain in I Mode; the pad wiring resistor is considerably
larger here, however.
BIASEX
Code
00
Addr 0x4D, bit 7:6
VREFin
internal
internal
external
Pin function of X2
Input Index- (negative zero signal)
Output of VREFin12*
10
11
Input for external reference**:
V(X2) replaces VREFin
Notes
*) Do not load, buffering recommended
**) See Elec. Char. Nos. 205 and 206
For sensors whose offset calibration is to be propor-
tional to an external DC voltage source the reference
source can be selected using BIASEX; for all other
sensors BIASEX should be set to ’00’.
Table 19: Input Reference Selection
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 19/29
5V
VDDS= 4.25 V
VDDS= 4.25 V
4V
VCM 3.75 V
3V
2.75 V
+IN
VCM 2.625 V
VCM
+IN
2V
-IN
-IN
VIN 1 V max.
VIN 250 mV max.
VCM 1.125 V
1V
VCM 0.75 V
1 V
GNDS 0.25 V
V-Mode 1:1
V-Mode 4:1
VREFin 1.5 V
VREFin 1.5 V or 2.5 V
NB: VREFin is referenced to GNDS.
Figure 3: Permissible common mode range and maximum input signal for lowest gain (GR12 = 0x0,
GF1, GF2 = 0x00); left side: voltage input 1:1, right side: voltage input 4:1.
5V
VDDS= 4.25 V
VDDS= 4.25 V
4V
VCM 3.75 V
VCM 3.75 V
VCM 3.75 V
VIN 1 V max.
3V
2V
1V
2.75 V
+IN
VCM
VCM 2.25 V
VCM 2.25 V
-IN
VCM 1.75 V
1.75 V
VCM 0.75 V
VCM 0.75 V
1 V
GNDS 0.25 V
V-Mode 4:1
VREFex 0.5 V
(BIASEX = 11)
V-Mode 4:1
VREFex 0.75 V
(BIASEX = 11)
V-Mode 4:1
V-Mode 4:1
VREFex 1.5 V
(BIASEX = 11)
- or -
VREFex 2.5 V
(BIASEX = 11)
- or -
VREFin 1.5 V
VREFin 2.5 V
NB: VREFex and VREFin are referenced to GNDS.
Figure 4: Permissible common mode range for voltage input 4:1 in dependancy to the reference voltage.
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 20/29
SIGNAL PATH MULTIPLEXING
Figure 5: Multiplexer Schematics
The signals for index channel CH0 are connected up to EAZ permits the activation of an analog comparator for
pins X1 and X2. Pins X3 to X6 are allocated to internal index channel CH0.
channels CH1 and CH2 via MUXIN. INMODE can be
EAZ
Code
0
Addr 0x43, bit 7
activated for referenced input signals; this then selects
X2 as the reference input.
Function
Comparator bypass
Comparator active
1
MUXIN
Code
00
Addr 0x43, bit 1:0
PCH1i
X4
NCH1i
PCH2i
X3
NCH2i
X5
Table 22: Index Output
X6
X6
X5
X3
01
X4
X5
X5
10
X4
X3
X6
For output purposes INVZ allows the index signal
phase to be inverted.
11
X4
X5
X6
Table 20: Input Multiplexer for INMODE = 0
INVZ
Code
0
Addr 0x43, bit 3
PZ_out
NZ_out
NCH0o
PCH0o
PCH0o
MUXIN
Addr 0x43, bit 1:0
1
NCH0o
Code
-0
PCH1i
X4
NCH1i
PCH2i
X3
NCH2i
X2
X2
X2
Table 23: Index Signal Inversion
-1
X4
X5
X2
Table 21: Input Multiplexer for INMODE = 1
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 21/29
SIGNAL CONDITIONING CH1, CH2
GR12
Addr 0x46, bit 2:0
AGC on (AGCOFF = 0)
0.20 .. 2.77
The voltage signals necessary for the conditioning of
channels 1 and 2 can be measured in operation mode
Calibration 2.
Code
AGC off (AGCOFF = 1)
0x0
0.75
1.27
1.89
2.65
3.73
4.77
6.24
7.83
0x1
0.34 .. 4.69
0x2
0.51 .. 7.03
Gain Settings CH1, CH2
The gain is set in four stages:
0x3
0.71 .. 9.82
0x4
1.01 .. 13.8
0x5
1.28 .. 17.7
1. The automatic gain control is shut down (set register
AGCOFF to a value of 1).
0x6
1.68 .. 23.2
0x7
2.11 .. 29.1
2. The gain range is selected so that the differential
signal amplitude of CH1 is closest to 1 Vpp (signal Px
vs. Nx, see Figure below).
Table 24: Gain Range CH1, CH2 with voltage divider
inputs (RIN12=0x9)
3. The automatic gain control is turned on (set register
AGCOFF to a value of 0) and adjust ADJ to obtain a
signal amplitude of 1 Vpp for CH1.
GR12
Code
0x0
Addr 0x46, bit 2:0
AGC on (AGCOFF = 0)
0.80 .. 11.1
AGC off (AGCOFF = 1)
2.98
5.06
7.58
10.6
14.9
19.1
25.0
31.3
0x1
1.36 .. 18.8
4. The CH2 signal amplitude can then be adjusted rel-
ative to the CH1 signal amplitude via gain correction
ratio GC2.
0x2
2.04 .. 28.1
0x3
2.85 .. 39.3
0x4
4.02 .. 55.4
0x5
5.14 .. 70.8
AGC gain range reserve can be checked by the value
of read-only register AGCGF1 which represents the 8
most significant bits of the current automatic gain set-
ting for channel 1.
0x6
6.73 .. 92.6
0x7
8.44 .. 116
Table 25: Gain Range CH1, CH2 (RIN12=0x9)
NB: automatic gain control is halted during AGCGF1
readout and will continue automatically afterwards.
GC2
Addr 0x4F, bit 7:0
Ratio
Code
0x00
0x01
0.8292
0.8304
20GC2−128
2047
...
0x80
1.00
20GC2−128
0.25 Vp
0.25 Vp
1 Vpp
2047
...
0xFE
0xFF
1.2025
1.2043
iC-MSA
Table 26: Gain Correction Ratio CH2/CH1
Px
Vpeak-to-peak
R0
Vpk(Px)
Nx
Vpk(Nx)
AGCGF1
Value
Addr 0x59, bit 7:0
AGC reserve
GND
0xF0
alarm (±0.0 dB)
0x80
0.27 .. 3.7 (±11.4 dB)
0.33 .. 3.0 (±9.5 dB)
0.50 .. 2.0 (±6.0 dB)
0.67 .. 1.5 (±3.5 dB)
alarm (±0.0 dB)
0x5E...92
0x4B...B4
0x33...CD
0x10
Figure 6: Definition of 1 Vpp signal. Termination R0
must be high-ohmic during all Test and
Calibration modes.
Table 27: Minimum AGC Reserve (read only)
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 22/29
OF1
Addr 0x4A, bit 3:0; Addr 0x49, bit 7:1
Offset Calibration CH1, CH2
OF2
Addr 0x4C, bit 0; Addr 0x4B, bit 7:0; Addr 0x4A, bit
7:6
In order to calibrate the offset the reference source
must first be selected using VOS12. Two fixed volt-
ages and one dependent source are available for this
purpose.
Code
Factor
Code
0x400
0x401
...
Factor
0
0x000
0
0x001
...
+ 0.00098
+ Code / 1023
− 0.00098
− (Code - 1024)
VOS12
Code
0x0
Addr 0x4E, bit 5:4
Type of source
/ 1023
0x3FF
+ 1
0x7FF
− 1
Feedback of sensor supply voltage: VDDS
for supply-dependent differential voltage signals
for Wheatstone sensor bridges
Table 30: Offset Factors CH1, CH2
0x1, 0x2
0x3
Fixed reference: V05 of 500 mV, V025 of 250 mV
for single-ended or differential signals
(regulated sensor or waveform generator)
Phase Correction CH1 vs. CH2
The phase shift between CH1 and CH2 can be ad-
justed using parameter PH12. Following phase cal-
ibration other calibration parameters may have to be
adjusted again (those as gain ratio, intermediate po-
tentials and offset voltages).
not permitted
Table 28: Offset Reference Source CH1, CH2
The calibration range for the CH1/CH2 offset is depen-
dent on the selected VOS12 source and is set using
OR1 and OR2. Both sine and cosine signals are then
calibrated using factors OF1 and OF2. The calibration
target is reached when the DC fraction of the differen-
tial signals PCHx versus NCHx is zero.
PH12
Code
0x000
0x001
...
Addr 0x4D, bit 2:0; Addr 0x4C, bit 7:1
Correction angle
0 °
Code
0x200
0x201
...
Correction angle
0 °
+ 0.0204 °
− 0.0204 °
− 10.42 ° ·
+ 10.42 ° ·
PH12 /511
(PH12 - 512) /511
OR1
OR2
Code
0x0
Addr 0x49, bit 0; Addr 0x48, bit 7
0x1FF
+ 10.42 °
0x3FF
− 10.42 °
Addr 0x4A, bit 5:4
Range
x1
Table 31: Phase Correction CH1 vs. CH2
0x1
x2
0x2
x6
0x3
x12
Table 29: Offset Range CH1, CH2
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 23/29
SIGNAL CONDITIONING CH0
GC0
Addr 0x50, bit 7:0
Ratio
The voltage signals needed to calibrate channel 0 are
available in Calibration Mode 1.
Code
0x00
0x01
0.8292
0.8304
20GC0−128
Gain Settings CH0
2047
...
The CH0 gain is set in the following stages:
0x80
1.00
20GC0−128
2047
...
0xFE
1.2025
1.2043
1. Adjust CH1 and CH2.
0xFF
Table 34: Gain Correction Ratio CH0/CH1
2. Set gain range GR0 to the same value as GR12.
Offset Calibration CH0
3. GC0 then permits fine gain ratio adjustment relative
to CH1.
To calibrate the offset the source of supply must first
be selected using VOS0 (see Offset Calibration CH1
and CH2 for further information).
GR0
Code
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Addr 0x51, bit 2:0
AGC on (AGCOFF = 0)
0.20 .. 2.77
VOS0
Code
0x0
Addr 0x53, bit 5:4
Source
AGC off (AGCOFF = 1)
0.75
1.27
1.89
2.65
3.73
4.77
6.24
7.83
0.05 · V(VDDS)
0.5 V
0.34 .. 4.69
0x1
0.51 .. 7.03
0x2
0.25 V
0.71 .. 9.82
0x3
not permitted
1.01 .. 13.8
1.28 .. 17.7
Table 35: Offset Reference Source CH0
1.68 .. 23.2
2.11 .. 29.1
OR0
Code
0x0
Addr 0x52, bit 1:0
Range
x1
Table 32: Gain Range CH0 with voltage divider inputs
(RIN0=0x9)
0x1
x2
0x2
x6
0x3
x12
GR0
Code
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Addr 0x51, bit 2:0
AGC on (AGCOFF = 0)
0.80 .. 11.1
AGC off (AGCOFF = 1)
Table 36: Offset Range CH0
2.98
5.06
7.58
10.6
14.9
19.1
25.0
31.3
1.36 .. 18.8
OF0
Code
0x00
0x01
...
Addr 0x52, bit 7:2
2.04 .. 28.1
Factor
0
Code
0x20
0x21
...
Factor
2.85 .. 39.3
4.02 .. 55.4
0
5.14 .. 70.8
+ 0.0322
+ OF0 /31
+ 1
− 0.0322
− (OF0 - 32 ) /31
− 1
6.73 .. 92.6
8.44 .. 116
0x1F
0x3F
Table 33: Gain Range CH0 (RIN0=0x9)
Table 37: Offset Factor CH0
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 24/29
AUTOMATIC SIGNAL GAIN CONTROL and SIGNAL MONITORING
AGCOFF
Addr 0x45, bit 7
Via its automatic gain control iC-MSA can keep the out-
put signals for the ensuing sine-to-digital conversion
constant regardless of changes in input signal level.
Code
Function
0
1
Sine/cosine square control
AGC turned off
Both the controller operating range and input signal
amplitude for the controller are monitored and can be
enabled for error messaging.
Table 38: Controller Operating Mode
ADJ
Code
0x00
0x01
Addr 0x45, bit 5:0
Square control AGCOFF = 0
Vpp() ca. 300 mV (60 %)
Vpp() ca. 305 mV (61 %)
77
...
Vpp() ≈ 300 mV 77−(0.625∗Code)
0x32
...
Vpp() ca. 500 mV (98 %)
...
0x3F
Vpp() ca. 600 mV (120 %)
Table 39: Vpp Setpoint For Square Control
Figure 7: Signal level monitoring with square control
(example for AGCOFF = 0, ADJ = 0x32;
see Elec. Char. Nos.604 and 605 regard-
ing Vt()min resp. Vt()max).
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 25/29
ERROR MONITORING AND ALARM OUTPUT
EPH
Addr 0x55, bit 2
State on error
active low
The following table gives the errors which can both be
recognized by iC-MSA and enabled either for messag-
ing, output shutdown or protocol in the EEPROM.
Code
State w/o error
0
high impedance,
with input function for a
low-active system error;
Mask EMASKA stipulates that errors should be sig-
1
high impedance
active low
naled at pin ERR, mask EMASKO determines whether
the line drivers are to be shutdown or not (with
PDMODE defining reactivation) and mask EMASKE
Table 41: I/O Logic, Alarm Output ERR
governs the storage of error events in the EEPROM.
EMTD
Addr 0x55, bit 5:3
Code
Indication Time
0 ms
Code
0x4
0x5
0x6
0x7
Indication Time
50 ms
EMASKA
EMASKO
EMASKE
Bit
Addr 0x54, bit 6:0
0x0
0x1
0x2
0x3
Addr 0x56, bit 6:0
12.5 ms
25 ms
62.5 ms
75 ms
Addr 0x58, bit 2:0; Addr 0x57, bit 7:4
Error Event
37.5 ms
87.5 ms
6*
Configuration error (SDA or SCL pin error, no Ack
signal from EEPROM or invalid check sum);
EMASKO(6) = 1 (ROM bit): The line drivers remain
high impedance (tristate) when cycling power.
Table 42: Min. Indication Time, Alarm Output ERR
5
4
3
2
1
0
Excessive temperature warning
External system error
EPU
Code
0
Addr 0x57, bit 2
Function
Control error 2: range at max. limit
Control error 1: range at min. limit
Signal error 2: clipping
No internal pull-up
1
Internal 300 µA pull-up current source active
Signal error 1: loss of signal (poor differential
amplitude**, wrong s/c phase)
Table 43: Pull-Up Enable, Alarm Output ERR
Excessive Temperature Warning
EMASKA
Error Mask Alarm Output ERR
Exceeding the temperature warning threshold Tw (cor-
responds to T2, refer to Tempeprature Sensor, page
15) can be signaled at pin ERR or used to shut down
the line drivers (via mask EMASKO). The temperature
warning is cleared when the temperature falls below
1
Enable: event changes state of pin ERR
(if EMASKO does not disable the output function).
0
Disable: event does not affect pin ERR.
Error Mask Driver Shutdown
EMASKO
1
Enable: event resets pin ACO to the 5 mA range,
tristates the line driver outputs and pin ERR (i.e.
low-active error messages can not be displayed)
Tw -Thys
.
0
Disable: output functions remain active
Error Mask EEPROM Savings
Enable: event will be latched
Notice: If the temperature shutdown threshold Toff
=
EMASKE
Tw + ∆ T is exceeded, the line drivers are shut down
independently of EMASKO. For ∆ T refer to Elec.
Char. E06.
1
0
Disable: event will not be latched
Notes
*) Pin ERR can not pull low on configuration error,
use high-active error logic instead (EPH = 1);
**) Also due to excessive input signals or internal
signal clipping.
Driver Shutdown
Table 40: Error Masking
PDMODE
Addr 0x58, bit 6
Code
Function
0
1
Line driver active when no error persists
Line driver active after power-on
Alarm Output: I/O pin ERR
Pin ERR is operated by a current-limited open drain
output driver and has an internal pull-up which can be
shutdown. The ERR pin also acts as an input for exter-
nal system error messaging and for switching iC-MSA
Table 44: Driver Activation
to test mode for which a voltage of greater than VTMon Error Protocol
must be applied. Interpretation of external system er- Out of the errors pinpointed by EMASKE both the first
ror messaging and the phase length of the message (under ERR1) and last error (under ERR2) which occur
output can be set using EPH; the minimum signaling after the iC-MSA is turned on are stored in the EEP-
duration for internal errors is adjusted using EMTD.
ROM.
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 26/29
ERR1
Addr 0x60, bit 6:0
The EEPROM also has a memory area in which all
ERR2
Addr 0x62, bit 0; Addr 0x61, bit 7:2
Addr 0x63, bit 2:0; Addr 0x62, bit 7:4
Error Event
occurring errors can be stored (ERR3). Only the fact
that an error has occurred can be recorded, with no
information as to the time and frequency of that error
ERR3
Bit
6:0
Assignation according to EMASKE
given. The EEPROM memory can be used to statisti-
cally evaluate the causes of system failure, for exam-
Code
Function
ple.
0
1
No event
Registered error event
Table 45: Error Protocol
REVERSE POLARITY PROTECTION
The line drivers in iC-MSA are protected against re- are also reverse polarity protected: PC, NC, PS, NS,
verse polarity and short-circuiting. A defective device PZ, NZ, ERR, VDD, and GND (as long as GNDS is
cable or one wrongly connected cause damage neither only loaded versus VDDS). The maximum voltage dif-
to iC-MSA nor to the components protected against re- ference between the pins should not be greater than
verse polarity by VDDS and GNDS. The following pins 6 V, the exception here being pin ERR.
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 27/29
APPLICATION HINTS
PLC Operation
There are PLCs with a remote sense supply which require longer for the voltage regulation to settle. At the same
time the PLC inputs can have high-impedance resistances versus an internal, negative supply voltage which
define the input potential for open inputs.
In this instance iC-MSA’s reverse polarity protection feature can be activated as the outputs are tristate during the
start phase and the resistances in the PLC determine the pin potential. During the start phase neither the supply
VDD nor the output pins, which are also monitored, must fall to below ground potential (pin GND); otherwise the
device is not configured and the outputs remain permanently set to tristate.
In order to ensure that iC-MSA starts with the PLCs mentioned above pull-up resistors can be used in the en-
coder. Values of 100 kΩ are usually sufficient; it is, however, recommended that PLC specifications be specifically
referred to here.
Connecting MR sensor bridges for safety-related applications
For safety-related applications iC-MSA requires an external overvoltage protection of supply VDD (Zener diode
with fuse, for instance) and external pull-down resistors at the inputs X3 to X6 towards GNDS (of up to 100 kΩ).
F1
+5V
C1
100nF
C2
100nF
R6
R5
4.7kS 4.7kS
D1
5.6V
VP
SCL
VDDS
VDD
SCL
ERR
I2C
24xx
ERR
SDA
SDA
VN
iC-MSA
AUTOMATIC
GAIN
CONTROL
PZ
NZ
PC
NC
PS
NS
RL
100S
MR0
X1
X2
+
-
INPUT ZERO
MR1
RL
100S
X3
X5
+
-
R1
R2
INPUT COS
100kS 100kS
MR2
X4
X6
+
RL
100S
-
R3
R4
100kS 100kS
INPUT SIN
GNDS
GND
0V
TVS diode array
Figure 8: Example circuit for safety-related applications with iC-MSA.
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 28/29
Motor feedback encoder with iC-MSA, iC-MSB and single EEPROM
In this application iC-MSB is fed with typically 2048 CPR sine and cosine signals, and an index signal. A constant
signal level is achieved by controlling the sensor’s LED current. iC-MSA is utilized to provide C/D commutation
signals, typically with 1 CPR, at a constant amplitude. At higher rotation speed the sine/cosine amplifier cut-off-
frequency is exceeded and iC-MSB increases the LED current. In order to keep the low frequency signals of C/D
constant, iC-MSA automatically reduces the gain.
iC-MSA and iC-MSB are multi-master I2C capable and feature non-overlapping configuration register addresses.
Thus, both devices can share a single EEPROM providing individual configuration data.
+5V
C2
100nF
C1
1μF
C3
100nF
R6
2.2k
R5
2.2k
R1
1k
VP
D2
VDDS
VDD
SCL
SDA
SCL
24xx
I2C
Reverse
Polarity
Protection
ERR
PS
SDA
ERR
VN
iC-MSB
PSIN
X4
X6
+
-
NS
PC
NSIN
X3
X5
+
-
PCOS
iC-TL85
D3
R9
47
NC
PZ
NCOS
PZ
X1
X2
+
-
Disc
SIGNAL
LEVEL
ACO
NZ
NZ
VN
C7
100nF
VCC
CONTROL
iC-PD3948
GNDS
GND
VREF
DPZ
PZ
NZ
VRSC
VRDC
DPC
C6
C5
C4
100nF
100nF
1μF
TVS-Diode-Array
DNC
PSIN
NSIN
VDDS
VDD
SCL
SDA
I2C
Reverse
ERR
PS
PCOS
NCOS
Polarity
Protection
DNCOS
DPSIN
DPCOS
DNSIN
iC-MSA
PC
X4
X6
PC
NC
+
DPD
-
NS
PC
NC
PD
X3
X5
PD
ND
+
-
DND
NC
PZ
ND
X1
X2
+
-
DNZ
GND
AUTOMATIC
GAIN
NZ
CONTROL
GNDS
GND
Figure 9: Example circuit with iC-MSA, iC-MSB and single EEPROM.
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materials.
The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness
for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no
guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of
the product.
iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
iC-MSA SIN/COS SIGNAL
CONDITIONER with AGC and 1Vpp DRIVER
Rev A1, Page 29/29
ORDERING INFORMATION
Type
Package
Order Designation
iC-MSA TSSOP20 with thermal pad iC-MSA TSSOP20-TP
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Tel.: +49 (61 35) 92 92-0
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Fax: +49 (61 35) 92 92-192
Web: http://www.ichaus.com
E-Mail: sales@ichaus.com
Appointed local distributors: http://www.ichaus.com/sales_partners
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