ICS1523 [ICSI]
High-Performance Programmable Line-Locked Clock Generator; 高性能可编程行同步时钟发生器
| 型号： | ICS1523 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | High-Performance Programmable Line-Locked Clock Generator |
| 文件： | 总27页 (文件大小：1215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS1523
High-PerformanceProgrammableLine-LockedClockGenerator
General Description
Features
Pixel clock frequencies up to 250 MHz
The ICS1523 is a low-cost but very high-performance
frequency generator for line-locked and genlocked high-
resolution video applications. Using ICSs advanced
low-voltage CMOS mixed-mode technology, the ICS1523
is an effective clock solution for video projectors and dis-
plays at resolutions from VGA to beyond UXGA.
Very low jitter
Dynamic Phase Adjust (DPA) for clock outputs
Balanced PECL differential outputs
Single-ended SSTL_3 clock outputs
Double-buffered PLL/DPAcontrol registers
Independent software reset for PLL/DPA
External or internal loop filter selection
Uses 3.3Vdc. Inputs are 5V-tolerant.
The ICS1523 offers pixel clock outputs in both differential
(to 250 MHz) and single-ended (to 150 MHz) formats.
Dynamic Phase Adjust circuitry allows user control of
the pixel clock phase relative to the recovered sync signal.
A second differential output at half the pixel clock rate
enables deMUXing of multiplexed analog-to-digital con-
verters. The FUNC pin provides either the regenerated
input from the phase-locked loop (PLL) divider chain out-
put or a re-synchronized and sharpened input HSYNC.
I2C-bus serial interface can run at either low speed
(100 kHz) or high speed (400 kHz).
Lock detection
24-pin 300-mil SOIC package
Applications
The advanced PLL uses either its internal programmable
feedback divider or an external divider. The device is pro-
grammed by a standard I2C-bus serial interface and is
available in a 24-pin wide small-outline integrated circuit
(SOIC) package.
LCD monitors and video projectors
Genlocking multiple video subsystems
Frequency synthesis
Block Diagram
Pin Configuration
24-Pin SOIC
I2C-bus is a trademark of Philips Corporation.
Dynamic Phase Adjust is a trademark of Integrated Circuit Systems, Inc.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
ICS1523 Rev S 5/21/99
information being relied upon by the customer is current and accurate.
ICS1523
Document Revision History
Rev P (First Release)
Pin Descriptions changed to add type column. (pg 3)
Added SDA and AC Input Characteristics. (pg 18)
Changed VCO Output, Intrinsic Jitter graph to show slow and fast cases (pg 19)
Timing diagram changes to reference t0 to REF and notes on test conditions added (pg 22)
Lock Renamed Lock/Ref (Throughout).
General cleanup for readability.
Rev Q
Added typical external loop filter values. (pg 17)
Added section on power supply considerations and SSTL_3 outputs. (pg 18)
Correct labels and scale on VCO Output, Intrinsic Jitter graph. (pg 20)
Correct depiction of timing diagram and added typical transition timing. (pg 23)
Added Document Revision History. (pg 25)
RevR
Change to descriptions for pins 20 to 23. (pg 3)
Change to description for Reg 0h bits 0 and 1, added table. (pg 6)
Within table for Reg 0h bits 6 and 7, changed Osc_En to IN_SEL . (pg 6)
Moved Reg 0 bits 4 through 7 from pg 6 to new pg 7.
Change to Software Programming Flow diagram. (pg 13).
Added underAbsolute Maximum Ratings ESD ratings and warning. (pg 19)
Under Recommend Operating Conditions, PECL Outputs, Output Low Voltage, added a note and added a new page. (pg 19)
Under Recommend Operating Conditions, SSTL-3 Outputs, Output Low Voltage, changed direction of symbols. (pg 19)
Change to VCO Output Frequency and Intrinsic Jitter graph to reflect correct VCO frequency (pg 20)
Rev S
Moved Revision History from last page of data sheet to second page. (pg 2)
In Layout Guideline 2, changed shunt capacitor value from 150 pF to 33 pF. (pg 19)
Changed various cross-references within Layout Guidelines. (pg 19)
2
ICS1523
Overview
Dynamic Phase Adjust
The ICS1523 addresses stringent graphics system line-locked
and genlocked applications and provides the clock signals
required by high-performance video analog-to-digital convert-
ers. Included are a phase-locked loop (PLL) with a 500-MHz
voltage controlled oscillator (VCO), a Dynamic PhaseAdjust to
provide a user-programmed pixel clock delay, the means for
deMUXing multiplexed ADCs, and both balanced-program-
mable (PECL) and single-ended (SSTL_3) high-speed clock
outputs.
The Dynamic Phase Adjust allows addition of a program-
mable delay to the pixel clock output, relative to the recovered
HSYNC signal. The ability to add delays is particularly useful
when multiple video sources must be synchronized. Adelay of
up to one pixel clock period is selectable in the following
increments:
1/64 period for pixel clock rates to 40 MHz
1/32 period for pixel clock rates to 80 MHz
1/16 period for pixel clock rates to 160 MHz
Phase-Locked Loop
The phase-locked loop is optimized for line-locked applica- Output Drivers and Logic Inputs
tions, for which the inputs are horizontal sync signals. A The ICS1523 utilizes low-voltage TTL(LVTTL) inputs as well
high-performance Schmitt trigger preconditions the HSYNC as SSTL_3 (EIA/JESD8-8) and low-voltage PECL (pseudo-
input, whose pulses can be degraded if they are from a remote ECL) outputs, operating at 3.3-V supply voltage. The LVTTL
source. This preconditioned HSYNC signal is provided as a inputs are 5 V-tolerant. The SSTL_3 and differential PECL out-
clean reference signal with a short transition time. (In contrast, put drivers drive resistive terminations or transmission lines.
the signal that a typical PC graphics card provides has a transi- At lower clock frequencies, the SSTL_3 outputs can be oper-
tion time of tens of nanoseconds.)
ated unterminated.
A second high-frequency input such as a crystal oscillator and
a 7-bit programmable divider can be selected. This selection al- I2C-bus Serial Interface
lows the loop to operate from a local source and is also useful The ICS1523 utilizes the industry-standard I2C-bus serial in-
for evaluating intrinsic jitter.
terface. The interface uses 12 registers: one write-only, eight
read/write, and three read-only. Two ICS1523 devices can be
A 12-bit programmable feedback divider completes the loop. addressed, according to the state of the I2CADR pin. When
Designers can substitute an external divider.
the pin is low, the read address is 4Dh, and the write address is
4Ch. When the pin is high, the read address is 4Fh, and the
Either the conditioned HSYNC input or the loop output (recov- write address is 4Eh. The I2C-bus serial interface can run at ei-
ered HSYNC) is available at the FUNC pin, aligned to the edge ther low speed (100 kHz) or high speed (400 kHz) and provides
of the pixel clock.
5V-tolerant input.
Automatic Power-On Reset Detection
The ICS1523 has automatic power-on reset detection circuitry
and it resets itself if the supply voltage drops below threshold
values. No external connection to a reset signal is required.
3
ICS1523
Pin Descriptions
PIN NO.
PIN NAME
VDDD
TYPE
DESCRIPTION
Digital supply
COMMENTS
3.3V to digital sections
1
2
PWR
PWR
IN/OUT
IN
VSSD
SDA
Digital ground
Serial data
3
I2 C-bus1
I2 C-bus1
4
SCL
Serial clock
5
PDEN
EXTFB
HSYNC
EXTFIL
XFILRET
VDDA
VSSA
OSC
IN
PFD enable
Suspends charge pump1
External divider input to PFD1
Clock input to PLL1
6
IN
External feedback in
Horizontal sync
External filter
External filter return
Analog supply
Analog ground
Oscillator
7
IN
8
IN
External PLL loop filter
External PLL loop filter return
3.3V for analog circuitry
Ground for analog circuitry
Input from crystal oscillator package1 ,
9
IN
10
11
12
PWR
PWR
IN
2
Chip I2 C address select
Low = 4Dh read, 4Ch write
High = 4Fh read, 4Eh write
13
I2 CADR
IN
I2 C address
LOCK/REF
(SSTL)
14
OUT
Lock indicator/reference
Displays PLL or DPA lock or REF input
15
16
17
18
19
20
21
FUNC (SSTL)
CLK/2 (SSTL)
CLK (SSTL)
VDDQ
OUT
OUT
OUT
PWR
PWR
OUT
OUT
Function output
Pixel clock/2 out
Pixel clock out
SSTL_3 selectable HSYNC output
SSTL_3 driver to ADC deMUX input
SSTL_3 driver to ADC
Output driver supply
Output driver ground
Pixel clock out
3.3V to output drivers
VSSQ
Ground for output drivers
CLK– (PECL)
CLK+ (PECL)
Inverted PECL driver to ADC. Open drain.
PECL driver to ADC. Open drain.
Pixel clock out
Inverted PECL driver to ADC deMUX input.
Open drain.
22
CLK/2– (PECL)
OUT
Pixel clock/2 out
23
24
CLK/2+ (PECL)
IREF
OUT
IN
Pixel clock/2 out
Reference current
PECL driver to ADC deMUX input. Open drain.
Reference current for PECL outputs
Notes:
1. These LVTTL inputs are 5V-tolerant.
2. Connect to ground if unused.
4
ICS1523
Block Diagram
5
ICS1523
I2C Register Map Summary
Register
Index
Reset
Value
Name
Access
Bit Name
Bit #
Description
0h
Input Control
R / W
PDen
PD_Pol
Ref_Pol
Fbk_Pol
Fbk_Sel
Func_Sel
EnPLS
0
1
2
3
4
5
6
7
1
0
0
0
0
0
1
0
Phase Detector Enable (0=External Enable, 1=Always Enabled)
Phase Detector Enable Polarity (0=Not Inverted, 1=Inverted)
External Reference Polarity (0=Positive Edge, 1=Negative Edge)
External Feedback Polarity (0=Positive Edge, 1=Negative Edge)
External Feedback Select (0=Internal Feedback, 1=External)
Function Out Select (0=Recovered HSYNC, 1=Input HSYNC)
Enable PLL Lock/Ref Status Output (0=Disable 1=Enable)
Enable DPA Lock/Ref Status Output (0=Disable 1=Enable)
EnDLS
1h
Loop Control
R / W *
PFD0-2
Reserved
PSD0-1
0-2
3
0
0
0
0
Phase Detector Gain
Reserved
4-5
6-7
Post-Scaler Divider (0 = ÷2, 1 = ÷4, 2 = ÷8, 3 = ÷16)
Reserved
Reserved
2h
3h
FdBk Div 0
FdBk Div 1
R / W *
R / W *
FBD0-7
0-7
FF PLL FeedBack Divider LSBs (bits 0-7) *
FBD8-11
Reserved
0-3
4-7
F
0
PLL Feedback Divider MSBs (bits 8-11) *
Reserved
4h
DPA Offset
R / W
DPA_OS0-5
Reserved
Fil_Sel
0-5
6
0
0
0
Dynamic Phase Aligner Offset
Reserved
7
Loop Filter Select (0=External, 1=Internal)
5h
6h
DPA Control
R / W ** DPA_Res0-1
Metal_Rev
0-1
2-7
3
0
DPA Resolution (0=16 delay elements, 1=32, 2=Reserved, 3=64)
Metal Mask Revision Number
Output Enables
R / W
OE_Pck
OE_Tck
OE_P2
OE_T2
OE_F
0
1
0
0
0
0
0
0
0
Output Enable for PECL PCLK Outputs ( 0=High Z, 1=Enabled)
Output Enable for STTL_3 CLK Output ( 0=High Z, 1=Enabled)
Output Enable for PECL CLK/2 Outputs ( 0=High Z, 1=Enabled)
Output Enable for STTL_3 CLK/2 Output ( 0=High Z, 1=Enabled)
Output Enable for STTL_3 FUNC Output ( 0=High Z, 1=Enabled)
CLK/2 Invert (0=Not Inverted, 1= Inverted)
2
3
4
Ck2_Inv
Out_Scl
5
6-7
SSTL Clock Scaler (0 = ÷1, 1 = ÷2, 2 = ÷4, 3 = ÷8)
7h
8h
Osc_Div
Reset
R / W
Write
Osc_Div 0-6
In-Sel
0-6
7
0
1
Osc Divider modulus
Input Select (0=HSYNC Input, 1=Osc Divider)
DPA
PLL
0-3
4-7
x
x
Writing xAh resets DPA and loads working register 5
Writing 5xh resets PLL and loads working registers 1-3
10h
11h
12h
Chip Ver
Chip Rev
Rd_Reg
Read
Read
Read
Chip Ver
Chip Rev
0-7
0-7
17
01
Chip Version 23 Dec (17 Hex) as in 1523
Initial value 01h. Value Increments with each all-layer change.
DPA_Lock
PLL_Lock
Reserved
0
1
N/A DPA Lock Status (0=Unlocked, 1=Locked)
N/A PLL Lock Status (0=Unlocked, 1=Locked)
2-7
0
Reserved
* Identifies double-buffered registers. Working registers are loaded during software PLL reset.
** Identifies double-buffered register. Working registers are loaded during software DPA reset.
6
ICS1523
Detailed Register Description
Name: Input Control
Register: 0h
Index: Read/Write
Bit Name Bit # Reset Value Description
PDen
0
1
2
3
4
5
6
7
1
0
0
0
0
0
1
0
Phase/Frequency Detector Enable
PD_Pol
Ref_Pol
Fbk_Pol
Fbk_Sel
Func_Sel
EnPLS
Phase/Frequency Detector Enable Polarity
Phase/Frequency Detector External Reference Polarity
External Reference Feedback Polarity
External Feedback Select
Function Output Select
Enable PLL Lock Status Output on LOCK/REF pin
Enable DPA Lock Status Output on LOCK/REF pin
EnDLS
Bit Name
Description
Phase/Frequency Detector
Is Enabled When:
0
PDen
Phase/Frequency
Detector Enable
PDen PD_Pol
0
X
1
0
1
0
PDEN= 1
Always (Default)
PDEN = 0
1
PD_Pol
Ref_Pol
Phase/Frequency Detector
Enable Polarity
2
Phase/Frequency Detector External Reference Polarity
Edge of input signal on which Phase Detector triggers.
0 = Rising Edge (default)
1 = Falling Edge
3
Fbk_Pol
External Reference Feedback Polarity Edge of EXTFB (pin 6) signal on which
Phase/Frequency Detector triggers when external feedback is used (Reg0 [4]=1).
0 = Positive Edge (default)
1 = Negative Edge
Table continues on next ppage
7
ICS1523
Name: Input Control
Register: 0h
Bit Name
Description
4
5
Fbk_Sel
External Feedback Select
0 = Internal Feedback (default)
1 = External Feedback
Func_Sel
Function Output Select Selects re-clocked output to FUNC (pin 15).
0 = Recovered HSYNC (default). Re-generated HSYNC output.
1 = External HSYNC. Schmitt-trigger conditioned input from HSYNC (pin 7).
EnPLS EnDLS IN_SEL
LOCK/REF(14)
0
6
7
EnPLS
EnDLS
Enable PLL Lock Status Output
on LOCK/REF pin
0
0
1
0
1
0
N/A
N/A 1 if DPA locked, 0 otherwise
N/A 1 if PLL locked, 0 otherwise
Enable DPA Lock Status Output
on LOCK/REF pin
Post Schmitt trigger
HSYNC(7) XOR Ref_Pol
1
1
1
1
0
1
Fosc
¸
Osc_Div
Bits 6,7 enable multiple functions
at LOCK/REF, (pin 14)
8
ICS1523
Name: Loop Control Register
Register: 1h
Index: Read/Write*
Bit Name Bit # Reset Value Description
PFD0-2
Reserved
PSD0-1
Reserved
0-2
3
4-5
6-7
0
0
0
0
Phase Frequency Detector Gain
Reserved
Post-Scaler Divider
Reserved
Bit Name
Description
0-2 PFD0-2
Phase/Frequency Detector Gain
Bit 2
Bit 1
Bit 0
PFD Gain (µA/2π rad)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
16
32
64
128
3
Reserved
PSD0-1
4-5
Post-Scaler Divider Divides the output of the VCO to the DPA and Feedback Divider.
Bit 5
Bit 4
PSD Divider
0
0
1
1
0
1
0
1
2 (default)
4
8
16
6-7 Reserved
Double-buffered register. Actual working registers are loaded during software PLL reset.
See register 8h for details.
*
9
ICS1523
Name: Feedback Divider 0 Register / Feedback Divider 1 Register
Register: 2h, 3h
Index: Read/Write*
Bit Name Index Bit # Reset Value Description
FBD 0-7
2
0-7
FF
PLL Feedback Divider LSBs (0-7).* When Bit 0 = 0, then the total
number of pixels is even. When Bit 0 = 1, then the total number of
pixels is odd.
FBD8-11
Reserved
3
3
0-3
4-7
F
PLL Feedback Divider MSBs (8-11)*
Reserved
The value that is programmed into these two registers, plus a value of 8, defines the total number of clock periods that the ICS
1523 generates between HSYNCs. Program these registers with the total number of horizontal pixels per line minus 8.
Reg 3
Reg 2
3
2
1
0
7
6
5
4
3
2
1
0
Feedback Divider Modulus
=
+8
12 £ Feedback Divider Modulus £ 4103
Double-buffered registers. Actual working registers are loaded during software PLL reset.
See Register 8h for details.
*
Name: DPA Offset Register
Register: 4h
Index: Read/Write
Bit Name
Bit # Reset Value Description
DPA_OS0-5
Reserved
Fil_Sel
0-5
6
7
0
0
0
Dynamic Phase Adjust Offset
Reserved
Loop Filter Select
Bit Name
Description
0-5
DPA_OS0-5
Dynamic Phase Adjust Offset.
Selects clock edge offset in discrete steps from zero to one clock period minus one step.
Resolution (number of delay elements per clock cycle) is selected by DPA_Res0-1 (Reg 5:0-1).
Note: Offsets equal to or greater than one clock period are neither recommended nor supported.
Example: For DPA_Res0-1=01H, the clock can be delayed from 0 to 31 steps.
7
Fil_Sel
Selects external loop filter (0) or internal loop filter (1).
The use of an external loop filter is strongly recommended for all designs. Suggested component
values are available from the ICS1523 Demo Board Guide (1523DB.pdf) or the ICS1523 Register
Tool (inst1523.exe) available on our web site at: (http://www.icst.com/products/pinfo/1523.htm).
10
ICS1523
Name: DPA Control Register
Register: 5h
Index: Read/Write*
Bit Name
Bit # Reset Value Description
DPA_Res0-1
Metal_Rev
0-1
2-7
3
0
Dynamic Phase Adjust Resolution Select.
Metal Mask Revision Number.
Bit
Name
Description
0-1
DPA_Res0-1
Dynamic Phase Adjust (DPA) Resolution Select.
It is not recommended to use the DPA above 160 MHz.
CLK Range, MHz
48
Bit 1 Bit 0 Delay Elements
0
0
1
1
0
1
0
1
16
32
Reserved
64
160
24
80
12
40
2-7
Metal_Rev
Metal Mask Revision Number.
After power-up, register bits 7:2 must be written with 111111. After this write,
a read indicates the metal mask revision, as below.
Revision Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
A
B
C1
C2
D
E
F
G
1
0
1
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
Double-buffered register. Actual working registers are loaded during software DPA reset.
See register 8h for details.
*
11
ICS1523
Name: Output Enable Register
Register: 6h
Index: Read/Write
Bit Name Bit # Reset Value Description
OE_Pck
OE_Tck
OE_P2
OE_T2
OE_F
0
1
2
3
4
0
0
0
0
0
0
0
Output Enable for CLK Outputs (PECL)
Output Enable for CLK Output (SSTL_3)
Output Enable for CLK/2 Outputs (PECL)
Output Enable for CLK2 Output (SSTL_3)
Output Enable for FUNC Output (SSTL_3)
CLK/2 Invert
Ck2_Inv
Out_Scl
5
6-7
CLK Scaler
Bit
Name
Description
0
OE_Pck
Output Enable for CLK Outputs (PECL)
0 = High Z
1 = Enabled
1
OE_Tck
OE_P2
OE_T2
OE_F
Output Enable for CLK Output (SSTL_3)
0 = High Z
1 = Enabled
2
Output Enable for CLK/2 Outputs (PECL)
0 = High Z
1 = Enabled
3
Output Enable for CLK/2 Output (SSTL_3)
0 = High Z
1 = Enabled
4
Output Enable for FUNC Output (SSTL_3)
0 = High Z
1 = Enabled
5
Ck2_Inv
Out_Scl
CLK/2 Invert
0 = Not Inverted
1 = Inverted
6-7
Clock (CLK) Scaler
Bit 7
Bit 6
CLK Divider
0
0
1
1
0
1
0
1
1
2
4
8
12
ICS1523
Name: Oscillator Divider Register
Register: 7h
Index: Read/Write
Bit Name
Bit # Reset Value
Description
Osc_Div 0-6
In_Sel
0-6
7
0
1
Osc Divider Modulus
Input Select
Bit
Name
Description
0-6
Osc_Div 0-6
Oscillator Divider Modulus.
Divides the input from OSC (pin 12) by the set modulus.
The modulus equals the programmed value, plus 2.
Therefore, the modulus range is from 3 to 129.
7
In_Sel
Input Select Selects the input to the Phase/Frequency Detector
0 = HSYNC
1 = Osc Divider
Name: RESET Register
Register: 8h
Index: Write
Bit Name
Bit # Reset Value
Description
DPA Reset
PLL Reset
0-3
4-7
x
x
Writing xAh to this register resets DPA working register 5
Writing 5xh to this register resets PLL working registers 1-3
Bit
Name
Description
0 -3
4-7
DPA
PLL
Writing xAh to this register resets DPA working register 5
Writing 5xh to this register resets PLL working registers 1-3
Value
xA
Resets
DPA
5x
PLL
5A
DPA and PLL
13
ICS1523
Name: Chip Version Register
Register: 10h
Index: Read
Bit Name
Bit # Reset Value
Description
Chip Ver
0-7
17
Chip Version 23 (17h)
Name: Chip Revision Register
Register: 11h
Index: Read
Bit Name
Bit # Reset Value
Description
Chip Rev
0-7
01+
Initial value 01h.
+Value increments with each all-layer change.
Name: Status Register
Register: 12h
Index: Read
Bit Name
Bit # Reset Value Description
DPA_Lock
PLL_Lock
Reserved
0
1
2-7
N/A
N/A
0
DPA Lock Status
PLL Lock Status
Reserved
Bit
Name
Description
0
DPA_Lock
PLL_Lock
Reserved
DPA Lock Status. (Refer to Register 0h, bits 6 and 7.)
0 = Unlocked
1 = Locked
1
PLL Lock Status. (Refer to Register 0h, bits 6 and 7.)
0 = Unlocked
1 = Locked
2-7
14
ICS1523
ICS1523 Software Programming Flow
15
ICS1523
I2C Data Characteristics
Bit transfer on the I2C-bus
START and STOPconditions
Acknowledge on the I2C-bus
These waveforms are from "The I2C-bus and how to use it," published by Philips Semiconductor.
The document can be obtained from http://www-us2.semiconductors.philips.com/acrobat/various/i2c_bus_specification_1995.pdf
16
ICS1523
I2C Data Format
RANDOM REGISTER WRITE PROCEDURE
S 0 1 0 0 1 1 x W A
A
A P
7 bit address
register address
Acknowledge
data
Acknowledge
STOP condition
Acknowledge
START condition
WRITE command
RANDOM REGISTER READ PROCEDURE
S 0 1 0 0 1 1 X W A
A S 0 1 0 0 1 1 X R A
7 bit address
A P
7 bit address
register address
Acknowledge
data
Acknowledge
Repeat START
STOP condition
START condition
WRITE command
Acknowledge
READ command
NO Acknowledge
SEQUENTIAL REGISTER WRITE PROCEDURE
S 0 1 0 0 1 1 X W A
7 bit address
A
A
A
A P
register address
Acknowledge
data
Acknowledge
data
Acknowledge
Acknowledge Acknowledge
START condition
WRITE command
STOP condition
SEQUENTIAL REGISTER READ PROCEDURE
S 0 1 0 0 1 1 X W A
A S 0 1 0 0 1 1 X R A
7 bit address
A
A P
7 bit address
register address
Acknowledge
data
Acknowledge
data
Repeat START
NO Acknowledge
START condition
WRITE command
Acknowledge
READ command
Acknowledge STOP condition
Direction:
From bus host to device
From device to bus host
Note:
1. All values are transmitted with the most-significant bit first and the least-significant bit last.
2. The value of the X bit equals the logic state of pin 13 (I2CADR).
3. R = READ = 1 and W = WRITE = 0
17
ICS1523
ICS1523 Video Mode Reference Table
The use of an external loop filter is strongly recommended inAll Designs.
The ICS1523 Video Mode Reference Table (previously included in this data sheet) lists information on the various video modes
that can be used with the ICS1523. To reference this table, see the ICS1523 Demo Board Guide (1523DB.pdf) available on our
web site at: (http://www.icst.com) under the ICS1523 area.
18
ICS1523
General Layout Guidelines
Use a PC board with at least four layers: one power, one
ground, and two signal.
5. PECL Outputs Implement these outputs as
microstrip transmission lines. The trace widths shown are
for 75W characteristic impedance, presuming .067 in.
between layers. Locate the optional series snubbing re-
sistors as close as possible to the pins. If the termination
resistors are included on-board, locate them as close as
possible to the load and connect directly to the power and
ground planes.
No special cutouts are required for power and ground
planes.
All supply voltages must be supplied from a common
source and must ramp up together.
Flux and other board surface debris can degrade the perfor-
mance of the external loop filter. Ensure that the 1523 area of
the board is free of contaminants.
[These termination resistors are omitted if the load device
implements them internally. For details, see the ICS appli-
cation note on microstrip and striplines (1572AN1) and
within the ICS1523 Applications Guide, the application
note on Designing a Custom Interface for the ICS1523
(1523AN4.)]
Specific Layout Guidelines
1. Digital Supply (VDD) Bypass pin 1 (VDD) to pin 2
(VSS) with 4.7-µF and 0.1-µF capacitors, located as close
as possible to the pins. Traces must be maximally wide and
include multiple surface-etched vias to the appropriate
plane.
6. Output Driver Supply Bypass pin 18 (VDDQ) to pin
19 (VSSQ) with 4.7-µF and 0.1-µF capacitors, located as
close as possible to the pins. Traces must be maximally
wide and include multiple surface-etched vias to the ap-
propriate plane.
2. External Loop Filter The use of an external loop fil-
ter is strongly recommended in All Designs. Locate loop
filter components as close to pins 8 and 9 (EXTFIL and
EXTFILRET) as possible. Typical loop filter values are
6.8K W for the series resistor, 3300 pF RF-type capacitor for
the series capacitor, and 33 pF for the shunt capacitor. (For
details, see the Frequently Asked Questions part of the
ICS1523 Applications Guide, FAQ2 and FAQ3.).
7. SSTL_3 Outputs SSTL_3 outputs can be used like
conventional CMOS rail-to-rail logic or as a terminated
transmission line system at higher-output frequencies.
With terminated outputs, the considerations of item 5,
PECL Outputs apply. See JEDEC documents JESD8-A
and JESD8-8.
3. Analog PLL Supply (VDDA) Decouple pin 10
(VDDA) with a series ferrite bead. Bypass the supply end
of the bead with 4.7-µF and 0.1-µF capacitors. Bypass pin
10 to pin 11 (VSSA) with a 0.1-µF capacitor. Locate these
components as close as possible to the pins. Traces must
be maximally wide and have multiple surface-etched vias to
4
1
1
the power or ground planes.
.
5
4. PECL Current Set Resistor Locate PECL current-
set resistor as close as possible to pin 24 (IREF). Bypass
pin 24 to ground with a 0.1-µF capacitor.
6
2
3
7
Note: Drawing is not to scale. It is for illustrative purposes only.
19
ICS1523
Power Supply Considerations
The ICS1523 incorporates special internal power-on reset circuitry that requires no external reset signal connection. The supply
voltage (VDD) must remain within the recommended operating conditions during normal operation. To reset the ICS1523, the
supply voltage at the part must be reduced below the threshold voltage (Vth) of the power-on reset circuit. The supply voltage
must remain below that threshold voltage such that board power conditioning capacitors are drained and the proper reset state
is latched. The amount of time (td) to hold the voltage in a reset state varies with the design. However, a typical value of 10 ms
should be sufficient.
SSTL_3 Outputs
Unterminated Outputs
In the ICS1523, unterminated SSTL output pins display exponential transitions similar to those of rectangular pulses presented to
RC loads. The 10-90% rise time is typically 1.6 ns, and the corresponding fall time is typically 700 ps. In turn, this asymmetry
contributes to duty cycle asymmetry at higher output frequencies. In the absence of significant load capacitance (which can
further increase rise and fall time), this asymmetry is the dominant factor determining high-frequency performance of these single-
ended outputs. Typically, no termination is required either for the LOCK/REF, FUNC, and CLK/2 outputs or for CLK outputs up to
approximately 135 MHz.
Terminated Outputs
SSTL_3 outputs are intended to terminate in low impedances to reduce the effect of external circuit capacitance. Use of transmis-
sion line techniques enables use of longer traces between source and driver without increasing ringing due to reflections. Where
external capacitance is minimal and substantial voltage swing is required to meet LVTTLVIH and VOL requirements, the intrinsic
rise and fall times of ICS1523 SSTL outputs are only slightly improved by termination in a low impedance.
The ICS1523 SSTLoutput source impedance is typically less than 60W. Termination impedance of 100W reduces output swing by
less than 30% which is more than enough to drive a single load of LVTTL inputs.
20
ICS1523
Absolute Maximum Ratings
VDD, VDDA, VDDQ (measured to VSS) . . . . . . . . . . . . . . . . . 4.3V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS 0.3V to 5.5V
Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSSA 0.3V to VDDA +0.3V
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSSQ 0.3V to VDDQ +0.3V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Soldering Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
ESD Susceptibility* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 2 KV
(*Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation.)
21
ICS1523
Recommended Operating Conditions
VDD, VDDQ, VDDA (measured to VSS) . . 3.0 to 3.6 V
Operating Temperature (Ambient) . . . . . . . . . 0 to +70°C
DC Supply Current
PARAMETER
Supply Current, Digital
Supply Current, Output Drivers
Supply Current, Analog
SYMBOL
IDDD
CONDITIONS
VDDD = 3.6V
MIN
—
MAX UNITS
25
6
mA
mA
mA
IDDQ
VDDQ = 3.6V, no output drivers enabled.
—
IDDA
VDDA = 3.6V
—
5
2
Digital Inputs (SDA, SCL, PDEN, EXTFB, HSYNC, OSC, I CADR)
PARAMETER
Input High Voltage
SYMBOL
VIH
CONDITIONS
MIN
MAX UNITS
2
VSS-0.3
0.2
5.5
0.8
V
V
Input Low Voltage
Input Hysteresis
VIL
0.6
V
Input High Current
Input Low Current
Input Capacitance
IIH
IIL
Cin
VIH = VDD
VIL = 0
—
±10
±200
10
µA
µA
pF
—
—
SDA (In Output Mode: SDA is Bidirectional)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX UNITS
0.4
IOUT = 3 mA. VOH = 6.0V maximum as
determined by the external pull-up resistor.
Output Low Voltage
VOL
V
PECL Outputs (CLK+, CLK–, CLK/2+, CLK/2–)
PARAMETER
SYMBOL
VOH
CONDITIONS
MIN
—
MAX UNITS
Output High Voltage
IOUT = 0
VDD
V
Output Low Voltage
(Note: VOL must not fall below
the level given so that the
correct value for IOUT can be
maintained.)
VOL
IOUT = programmed value
1.0
—
V
SSTL-3 Outputs (CLK, CLK/2, FUNC, LOCK/REF)
PARAMETER
Output Resistance
SYMBOL
RO
CONDITIONS
MIN
—
MAX UNITS
W
1 <VO<2V
80
AC Input Characteristics
PARAMETER
SYMBOL
fHSYNC
CONDITIONS
MIN
.008
.02
MAX UNITS
HSYNC Input Frequency
OSC Input Frequency
Reg 7:7 = 0
Reg 7:7 = 1
10
MHz
MHz
fOSC
100
22
ICS1523
VCO Output Frequency and Intrinsic Jitter
700
600
500
400
300
200
100
0
100
0
Frequency (Slow: 3.0V @ 70ºC)
Frequency (Nominal: 3.3V @ 30ºC)
Frequency (Fast: 3.6V @ 0ºC)
Jitter (3.0V @ 70ºC)
Jitter (3.3V @ 30ºC)
Jitter (3.6V @ 0ºC)
Frequency
Jitter
0
2
.
4
.
6
8
.
1
2
.
4
6
8
.
2
2
4
.
6
8
.
3
2
.
3
.
0
.
1
.
1
.
2
.
2
0
0
0
1
1
2
2
VCO Voltage
23
ICS1523
DPA Delay-16 Element Resolution
20
18
16
14
12
10
8
50 MHz - SVGA @ 72 Hz
157.5 MHz - SXGA @ 85 Hz
6
4
2
0
16
0
4
8
12
DPA Setting
DPA Delay - 32 Element Resolution
45
40
35
30
25
20
15
10
5
25.175 MHz - VGA @ 60 Hz
78.75 MHz - XGA @ 75 Hz
0
32
0
4
8
12
16
20
24
28
DPA Setting
DPA Delay - 64 Element Resolution
90
80
70
60
50
40
30
20
10
0
12.27 MHz - NTSC
39.8 MHz - SVGA @ 60
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
DPA Setting
Note:
Maximum number of data points used for this graph.
24
* Timing when Register 2, Bit 0 = 0 (Total number of pixels is even.)
** Timing when Register 2, Bit 0 = 1 (Total number of pixels is odd.)
ICS1523
Output Timing Diagram
Typical Transition Times*
Symbol
Timing Description
Rise Fall Units
tR
tP
tS
tF
REF
2.8
1.0
1.6
1.2
1.8
1.2
0.7
1.0
ns
ns
ns
ns
PECL CLK
SSTL-CLK
FUNC_OUT
Output Timing*
Symbol
Timing Description
HSYNC to REF delay
REF to PECL clock delay
Min
Typ Max Units
t0
t1
11.3
-1.0
45
11.5
0.8
50
12
2.2
55
ns
ns
%
ns
ns
ns
ns
%
t2, t3 PECL clock duty cycle
t4
t5
t6
t7
PECL clock to SSTL_3 clock delay
PECL clock to FUNC_OUT delay
PECL clock to PECL/2 clock
0.2
1.5
1.0
1.1
45
0.75
1.9
1.3
1.4
50
1.2
2.3
1.5
1.8
55
PECL clock to SSTL_3–CLK/2 delay
t8, t9 SSTL clock duty cycle
*Note: Measured at 3.6V 0°C, 135-MHz output frequency, PECL clock lines to 75W termination, SSTL_3 clock lines
unterminated, 20-pF load. Transition times vary based on termination.
26
ICS1523
24-Pin SOIC (wide body)
Ordering Information
ICS1523M
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
27
information being relied upon by the customer is current and accurate.
相关型号：
©2020 ICPDF网 联系我们和版权申明