ICS477R-05ILFT [ICSI]
Quad PLL with VCXO for HDTV; 四PLL VCXO与高清电视
| 型号： | ICS477R-05ILFT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Quad PLL with VCXO for HDTV |
| 文件： | 总7页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS477-05
Quad PLL with VCXO for HDTV
Description
Features
• Packaged in 28-pin SSOP (QSOP)
• Available in Pb-free packaging
The ICS477-05 generates five high-quality,
high-frequency clock outputs including two reference
outputs from a low frequency pullable crystal. It is
designed to replace crystals and crystal oscillators in
most electronic systems.
• Replaces a VCXO plus multiple crystals and
oscillators
• On-chip patented VCXO pull range 200 ppm
(minimum)
Using Phase-Locked-Loop (PLL) techniques, the
device runs from a fundamental mode, pullable crystal.
It can replace multiple crystals and oscillators, saving
board space and cost.
• Duty cycle of 45/55
• Operating voltage of 3.3V
• Advanced, low power, CMOS process
• Input crystal frequency of 27 MHz
• Five output clocks
• Industrial temperature range available
Block Diagram
VDD
6
VIN
54.054M
27 MHz
Pullable
Crystal
PLLA
Divide
Logic
and
74.175M
X1
PLLB
PLLC
PLLD
Voltage
Controlled
Crystal
Output
Enable
Control
X2
Oscillator
54M
External capacitors
may be required
2
27M
10
GND
PDTS
MDS 477-05 H
1
Revision 062404
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS477-05
Quad PLL with VCXO for HDTV
Pin Assignment
X 1
G N D
G N D
V IN
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
X 2
2
V D D
P D TS
G N D
V D D
V D D
V D D
G N D
G N D
G N D
54M
N C
3
4
5
V D D
V D D
6
G N D
G N D
G N D
G N D
54.054M
N C
7
8
9
10
11
12
13
14
N C
27M
27M
74.175M
28 pin (150 m il) S S O P
Pin Descriptions
Pin
Pin
Pin Type
Pin Description
Number
Name
1
2
3
4
XI
Input
Power
Power
Input
Crystal connection. Connect to a 27 MHz fundamental mode pullable crystal.
GND
GND
VIN
Connect to ground.
Connect to ground.
VCXO Voltage input. Zero to 3.3 V analog control voltage for VCXO.
Connect to +3.3 V.
5, 6, 22, 23,
24, 27
VDD
Power
7, 8, 9, 10, 19,
20, 21
GND
Power
Connect to ground.
11
12, 13, 17
14
54.054M
NC
Output 54.054 MHz clock output. Weak internal pull-down when tri-state.
No connect. Do not connect anything to these pins.
-
74.175M
27M
Output 74.175 MHz clock output. Weak internal pull-down when tri-state.
Output 27 MHz reference clock output. Weak internal pull-down when tri-state.
Output 54 MHz clock output. Weak internal pull-down when tri-state.
15, 16
18
54M
25
GND
PDTS
X2
Power
Input
Input
Connect to ground.
26
Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up.
Crystal connection. Connect to a 27 MHz fundamental mode pullable crystal.
28
MDS 477-05 H
2
Revision 062404
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS477-05
Quad PLL with VCXO for HDTV
Crystal Tuning Load Capacitors
External Components
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
The ICS477-05 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01µF must be connected
between VDD and GND, as close to these pins as
possible. For optimum device performance, the
decoupling capacitors should be mounted on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of
your final layout, a frequency counter capable of about
1 ppm resolution and accuracy, two power supplies,
and some samples of the crystals which you plan to
use in production, along with measured initial accuracy
for each crystal at the specified crystal load
capacitance, CL.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be
used. To series terminate a 50Ω trace (a commonly
used trace impedance) place a 33Ω resistor in series
with the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20Ω.
To determine the value of the crystal capacitors:
1. Connect VDD of the ICS477-05 to 3.3 V. Connect pin
4 of the ICS477-05 to the second power supply. Adjust
the voltage on pin 3 to 0V. Measure and record the
frequency of the 27 MHz output.
Quartz Crystal
2. Adjust the voltage on pin 4 to 3.3 V. Measure and
record the frequency of the same output.
The ICS477-05 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To
assure the best system performance (frequency pull
range) and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the
following section must be followed.
To calculate the centering error:
(f3.0V – ftarget) + (f0V – ftarget
)
Error = 106x
– errorxtal
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The ICS477-05 incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the ICS477-05 is designed to have zero frequency
error when the total of on-chip + stray capacitance is 14
pF.
------------------------------------------------------------------------------
ftarget
Where:
= nominal crystal frequency
f
target
error
=actual initial accuracy (in ppm) of the crystal
xtal
being measured
If the centering error is less than 25 ppm, no
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the ICS477-05. There should be no via’s
between the crystal pins and the X1 and X2 device
pins. There should be no signal traces underneath or
close to the crystal.
adjustment is needed. If the centering error is more
than 25 ppm negative, the PC board has excessive
stray capacitance and a new PCB layout should be
considered to reduce stray capacitance. (Alternately,
the crystal may be re-specified to a higher load
capacitance. Contact ICS for details.) If the centering
error is more than 25 ppm positive, add identical fixed
centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
See application note MAN05 for complete crystal
specifications.
MDS 477-05 H
3
Revision 062404
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS477-05
Quad PLL with VCXO for HDTV
External Capacitor =
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (typically less than 25 ppm).
2 x (centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied by
your crystal vendor. If you do not know the value,
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pins as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS477-05. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS477-05. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70°C
-40 to +85°C
-65 to +150°C
125°C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+85
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
-40
+3.15
+3.3
+3.45
V
MDS 477-05 H
4
Revision 062404
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS477-05
Quad PLL with VCXO for HDTV
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85°C
Parameter
Symbol
VDD
Conditions
Min.
Typ.
3.3
48
Max. Units
Operating Voltage
3.15
3.45
V
mA
mA
V
Supply Current
IDD
No load
Power Down Current
Input High Voltage
IDDPD No load
0.5
V
PDTS pin
PDTS pin
2
IH
Input Low Voltage
V
0.8
0.4
V
IL
Output High Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
Input Capacitance, inputs
Nominal Output Impedance
Internal Pull-up Resistor
Internal Pull-down Resistor
V
V
I
I
I
= -4 mA
= -12 mA
= 12 mA
VDD-0.4
2.4
V
OH
OH
OH
OH
OL
V
V
V
OL
OS
I
CLK output
80
5
mA
pF
Ω
C
IN
Z
20
OUT
R
PDTS pin
360
510
kΩ
kΩ
PUP
R
CLK outputs
PD
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Crystal input, Note 2
0V< VIN < 3.3 V
Min.
Typ. Max. Units
Input Frequency
f
27
MHz
ppm
ppm/V
ns
in
Crystal Pullability
VCXO Gain
F
100
P
K
VIN = VDD/2 + 1 V
20% to 80%, Note 1
80% to 20%, Note 1
150
1.2
1.0
0
Output Rise Time
Output Fall Time
t
OR
t
ns
OF
Clock Stabilization Time after
Power-up
10
ms
Cycle Jitter (short term jitter)
Long Term Jitter
t
200
1.0
ps
ns
ns
ps
µs
ja
54.054M, 54M clocks
74.175M clock
1.3
27M reference clock
300
250
Output Enable Time
Output Disable Time
PDTS high to output
locked to 1%
PDTS low to tri-state
20
ns
Note 1: Measured with a 15 pF load.
Note 2: With an ICS approved crystal.
MDS 477-05 H
5
Revision 062404
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS477-05
Quad PLL with VCXO for HDTV
Marking Diagram
Marking Diagram (Pb free)
28
28
15
15
ICS477R-05
ICS477R-05LF
######
YYWW
######
YYWW
14
15
14
1
1
Marking Diagram (industrial)
Marking Diagram (Pb free, industrial)
28
28
15
ICS477R-05I
ICS477R-05ILF
######
YYWW
######
YYWW
14
1
14
1
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week.
3. “LF” designates Pb (lead) free.
4. “I” designates industrial temperature grade.
MDS 477-05 H
6
Revision 062404
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS477-05
Quad PLL with VCXO for HDTV
Package Outline and Package Dimensions (28-pin SSOP, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
28
Millimeters
Inches
Min
Symbol
Min
Max
1.75
0.25
1.50
0.30
0.25
10.00
6.20
4.00
Max
.069
.010
.059
0.012
.010
.394
.244
.157
A
1.35
0.10
--
.053
.0040
--
0.008
.007
.386
.228
.150
E1
E
A1
A2
b
INDEX
AREA
0.20
0.18
9.80
5.80
3.80
C
D
E
1 2
E1
e
D
0.635 Basic
0.025 Basic
L
0.40
1.27
.016
.050
α
0°
8°
0°
8°
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
ICS477R-05 (top line)
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
ICS477R-05
ICS477R-05T
ICS477R-05I
ICS477R-05IT
ICS477R-05LF
ICS477R-05LFT
ICS477R-05ILF
ICS477R-05ILFT
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
YYWW (3rd line)
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
ICS477R-05I (top line)
YYWW (3rd line)
ICS477R-05LF (top line)
YYWW (3rd line)
ICS477R-05ILF (top line)
YYWW (3rd line)
“LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 477-05 H
7
Revision 062404
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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