ICS552ARI01 [ICSI]

Oscillator, Multiplier, and Buffer with 8 Outputs; 振荡器,乘法器和缓冲区有8个输出
ICS552ARI01
型号: ICS552ARI01
厂家: INTEGRATED CIRCUIT SOLUTION INC    INTEGRATED CIRCUIT SOLUTION INC
描述:

Oscillator, Multiplier, and Buffer with 8 Outputs
振荡器,乘法器和缓冲区有8个输出

振荡器
文件: 总10页 (文件大小:184K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ICS552A-01  
Oscillator, Multiplier, and Buffer with 8 Outputs  
ICS552A-01 (for B mode)  
Up to 200 MHz clock input/output at 3.3 V  
Description  
The ICS552A-01 produces 8 low-skew copies of the  
multiple input clock or fundamental, parallel-mode  
crystal. Unlike other clock drivers, these parts do not  
require a separate oscillator for the input. Using ICS’  
patented Phase-Locked Loop (PLL) to multiply the  
input frequency, it is ideal for generating and  
Low skew of 250 ps maximum for any bank of four  
Inputs can be connected together for a 1 to 8 buffer  
with 250 ps skew between any outputs  
Non-inverting buffer mode  
Ideal for clock networks  
distributing multiple high-frequency clocks. This is a  
single chip used for 3 different applications:  
Output Enable mode tri-states outputs  
Full CMOS output swing with 25 mA output drive  
1) ICS552A-01 (A mode) — an Oscillator mutiplier  
2) ICS552A-01 (B mode) — a Dual 1:4 buffer  
3) ICS552A-01 (C mode) — a 1:8 Oscillator buffer  
capability at TTL levels  
Advanced, low power, sub-micron CMOS process  
ICS552A-01 (for C mode)  
Use with 25 MHz crystal for networking  
Use with 27 MHz crystal for MPEG  
Features (all)  
Packaged as 20-pin SSOP (QSOP)  
Pb-free packaging available  
ICS552A-01 (for A and C modes)  
Input frequency of 10.0 to 27.0 MHz  
Provides 8 low-skew outputs (<250 ps)  
Output clock duty cycle of 40/60 at 3.3 V  
Operating voltages of 3.0 V to 5.5 V  
Industrial temperature available  
Features (specific)  
ICS552A-01 (for A mode)  
Contains on-chip multiplier with selections of x1,  
x1.33, x2, x2.66, x3, x3.33, x4, x4.66, x5, and x6  
Power-down and Tri-state modes  
Block Diagram (ICS552A-01—A mode)  
VDD  
4
CLK1  
CLK2  
CLK3  
S3:S0  
CLK4  
PLL  
Multiplier  
CLK5  
10.0 to 27.0 MHz  
CLK6  
CLK7  
CLK8  
crystal or clock input  
X1  
Crystal  
Buffer/  
Crystal  
Oscillator  
X2  
GND  
External capacitors are  
required with a crystal input.  
MDS 552A-01 B  
1
Revision 010906  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  
ICS552A-01  
Oscillator, Multiplier, and Buffer with 8 Outputs  
Multiplier Select Table  
Pin Assignment (ICS552A-01—A mode)  
S3  
0
S2  
0
S1  
0
S0  
0
Multiplier  
Power Down  
x1  
DC  
X2  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
S0  
DC  
0
0
0
1
X1/ICLK  
CLK8  
CLK7  
VDD  
0
0
1
0
x1.333  
x2  
VDD  
S2  
0
0
1
1
GND  
CLK1  
CLK2  
CLK3  
CLK4  
S3  
0
1
0
0
x2.666  
x3  
GND  
CLK6  
CLK5  
S1  
0
1
0
1
0
1
1
0
x3.333  
x4  
0
1
1
1
1
0
0
0
x5  
20-pin (150 mil) SSOP (QSOP)  
1
0
0
1
x4.66  
x6  
1
0
1
0
1
1
0
1
Tri-state all  
Pin Descriptions (ICS552A-01—A mode)  
Pin  
Number  
Pin  
Name  
Pin  
Type  
Pin Description  
1
2
DC  
X2  
Do not connect.  
XO  
Crystal connection. Connect to a 10 - 27 MHz fundamental mode crystal.  
Crystal connection. Connect to a 10 - 27 MHz fundamental mode crystal or  
clock.  
3
X1/ICLK  
XI  
4
VDD  
S2  
Power  
Input  
Connect to +3.3 V or 5 V. Decouple with pin 6. Must be same as other VDDs.  
Multiplier Select pin 2 per table above.  
5
6
GND  
CLK1  
CLK2  
CLK3  
CLK4  
S1  
Power  
Connect to ground.  
7
Output Output clock 1.  
Output Output clock 2.  
Output Output clock 3.  
Output Output clock 4.  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Input  
Multiplier Select pin 1 per table above  
CLK5  
CLK6  
GND  
S3  
Output Output clock 5.  
Output Output clock 6.  
Power  
Input  
Connect to ground.  
Multiplier Select pin 3 per table above  
Connect to +3.3 V or 5 V. Decouple with pin 14. Must be same as other VDDs.  
VDD  
CLK7  
CLK8  
DC  
Power  
Output Output clock 7.  
Output Output clock 8.  
Do not connect.  
S0  
Input  
Multiplier Select pin 0 per table above  
MDS 552A-01 B  
2
Revision 010906  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  
ICS552A-01  
Oscillator, Multiplier, and Buffer with 8 Outputs  
Block Diagram (ICS552A-01—B mode)  
INA  
S1  
QA1  
QA2  
QA3  
QA4  
QB1  
QB2  
QB3  
QB4  
Control  
Logic  
S0  
INB  
Pin Assignment (ICS552A-01—B mode)  
INA  
DC  
DC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
S0  
INB  
QB4  
QB3  
VDD  
VDD  
VDD  
GND  
QA1  
QA2  
QA3  
QA4  
VDD  
GND  
QB2  
QB1  
S1  
20-pin (150 mil) SSOP (QSOP)  
Clock Output Select Table (ICS552A-01—B mode)  
S1 S0  
Mode  
0
0
1
1
0
1
0
1
QA1:4 and QB1:4 running  
Test mode  
OE. All outputs in high impedance  
QA1:4 only. QB1:4 stopped low  
MDS 552A-01 B  
3
Revision 010906  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  
ICS552A-01  
Oscillator, Multiplier, and Buffer with 8 Outputs  
Pin Descriptions (ICS552A-01—B mode)  
Pin  
Pin  
Pin  
Type  
Pin Description  
Number Name  
1
2
INA  
DC  
CI  
Input to buffer A. Outputs QA1:4 will be the same frequency. Internal pull-up resistor.  
Do not connect.  
3
DC  
Do not connect.  
4
VDD  
VDD  
GND  
QA1  
QA2  
QA3  
QA4  
Power  
Power  
Power  
Connect to +3.3 V or 5.0 V. Must be same as other VDDs.  
Connect to +3.3 V or 5.0 V. Must be same as other VDDs.  
5
6
Connect to ground.  
7
Output Output 1 from buffer A.  
Output Output 2 from buffer A.  
Output Output 3 from buffer A.  
Output Output 4 from buffer A.  
8
9
10  
Mode Select pin 1. Selects mode for outputs. Must be at GND for all clocks on. Internal  
pull-up resistor.  
11  
S1  
I
12  
13  
14  
15  
16  
17  
18  
19  
QB1  
QB2  
GND  
VDD  
VDD  
QB3  
QB4  
INB  
Output Output 1 from buffer B.  
Output Output 2 from buffer B.  
Power  
Power  
Power  
Connect to ground.  
Connect to +3.3 V or 5.0 V. Must be same as other VDDs.  
Connect to +3.3 V or 5.0 V. Must be same as other VDDs.  
Output Output 3 from buffer B.  
Output Output 4 from buffer B.  
Input to buffer B. Outputs QA1:4 will be the same frequency. Internal pull-up resistor.  
CI  
Mode Select pin 0. Selects mode for outputs. Must be at GND for all clocks on. Internal  
pull-up resistor.  
20  
S0  
I
KEY: CI = clock input with pull-up resistor; I = input with internal pull-up resistor.  
MDS 552A-01 B  
4
Revision 010906  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  
ICS552A-01  
Oscillator, Multiplier, and Buffer with 8 Outputs  
Block Diagram (ICS552A-01—C mode)  
VDD  
5
CLK1  
CLK2  
CLK3  
CLK4  
CLK5  
CLK6  
CLK7  
CLK8  
10.0 to 27.0 MHz  
crystal input  
X1  
Crystal  
Oscillator  
X2  
3
External capacitors are  
required with a crystal input.  
GND  
Pin Assignment (ICS552A-01—C mode)  
DC  
X2  
X1  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VDD  
DC  
CLK8  
CLK7  
VDD  
VDD  
GND  
GND  
CLK1  
CLK2  
CLK3  
CLK4  
VDD  
GND  
CLK6  
CLK5  
VDD  
20-pin (150 mil) SSOP (QSOP)  
MDS 552A-01 B  
5
Revision 010906  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  
ICS552A-01  
Oscillator, Multiplier, and Buffer with 8 Outputs  
Pin Descriptions (ICS552A-01—C mode)  
Pin  
Number  
Pin  
Name  
Pin  
Type  
Pin Description  
1
2
DC  
X2  
Do not connect.  
XO  
Crystal connection. Connect to a 10 - 27 MHz fundamental mode crystal.  
Crystal connection. Connect to a 10 - 27 MHz fundamental mode crystal.  
Connect to +3.3 V or 5 V. Decouple with pin 6. Must be same as other VDDs.  
Connect to ground.  
3
X1  
XI  
4
VDD  
GND  
GND  
CLK1  
CLK2  
CLK3  
CLK4  
VDD  
CLK5  
CLK6  
GND  
VDD  
VDD  
CLK7  
CLK8  
DC  
Power  
Power  
Power  
5
6
Connect to ground.  
7
Output Output clock 1.  
Output Output clock 2.  
Output Output clock 3.  
Output Output clock 4.  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Power  
Connect to +3.3 V or 5 V. Must be same as other VDDs.  
Output Output clock 5.  
Output Output clock 6.  
Power  
Power  
Power  
Connect to ground.  
Connect to +3.3 V or 5 V. Must be same as other VDDs.  
Connect to +3.3 V or 5 V. Decouple with pin 14. Must be same as other VDDs.  
Output Output clock 7.  
Output Output clock 8.  
Do not connect.  
VDD  
Power  
Connect to +3.3 V or 5 V. Must be same as other VDDs.  
MDS 552A-01 B  
6
Revision 010906  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  
ICS552A-01  
Oscillator, Multiplier, and Buffer with 8 Outputs  
PCB Layout Recommendations  
External Components  
For optimum device performance and lowest output  
phase noise, the following guidelines should be  
observed.  
Series Termination Resistor  
Clock output traces over one inch should use series  
termination. To series terminate a 50trace (a  
commonly used trace impedance), place a 33resistor  
in series with the clock line, as close to the clock output  
pin as possible. The nominal impedance of the clock  
output is 20.  
1) Each 0.01µF decoupling capacitor should be  
mounted on the component side of the board as close  
to the VDD pin as possible. No vias should be used  
between decoupling capacitor and VDD pin. The PCB  
trace to VDD pin should be kept as short as possible,  
as should the PCB trace to the ground via.  
Decoupling Capacitors  
2) The external crystal should be mounted just next to  
the device with short traces. The X1 and X2 traces  
should not be routed next to each other with minimum  
spaces, instead they should be separated and away  
from other traces.  
As with any high-performance mixed-signal IC, the  
ICS552A-01 must be isolated from system power  
supply noise to perform optimally.  
Decoupling capacitors of 0.01µF must be connected  
between each VDD and GND on pins 4 and 6, and 16  
and 14. Other VDDs and GNDs can be connected to  
these pins or directly to their respective ground planes.  
3) To minimize EMI, the 33series termination resistor  
(if needed) should be placed close to the clock output.  
4) An optimum layout is one with all components on the  
same side of the board, minimizing vias through other  
signal layers.  
Crystal Load Capacitors  
The device crystal connections should include pads for  
small capacitors from X1 to ground and from X2 to  
ground. These capacitors are used to adjust the stray  
capacitance of the board to match the nominally  
required crystal load capacitance. Because load  
capacitance can only be increased in this trimming  
process, it is important to keep stray capacitance to a  
minimum by using very short PCB traces (and no vias)  
been the crystal and device. Crystal capacitors must be  
connected from each of the pins X1 and X2 to ground.  
The value (in pF) of these crystal caps should equal  
(C -12 pF)*2. In this equation, C = crystal load  
L
L
capacitance in pF. Example: For a crystal with a 18 pF  
load capacitance, two 12 pF capacitors should be  
used. For a clock input, connect it X1/ICLK and leave  
X2 unconnected (floating).  
MDS 552A-01 B  
7
Revision 010906  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  
ICS552A-01  
Oscillator, Multiplier, and Buffer with 8 Outputs  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the ICS552A-01. These ratings,  
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of  
the device at these or any other conditions above those indicated in the operational sections of the  
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can  
affect product reliability. Electrical parameters are guaranteed only over the recommended operating  
temperature range.  
Parameter  
Condition  
Min.  
Typ.  
Max.  
7
Units  
V
Supply Voltage, VDD  
Inputs  
Referenced to GND  
Referenced to GND  
Referenced to GND  
-0.5  
-0.5  
-65  
VDD+0.5  
VDD+0.5  
150  
V
Clock Outputs  
V
Storage Temperature  
Soldering Temperature  
Junction Temperature  
°C  
°C  
°C  
Max 10 seconds  
260  
125  
Recommended Operation Conditions  
Parameter  
Min.  
0
Typ.  
Max.  
+70  
Units  
°C  
Ambient Operating Temperature (commercial)  
Ambient Operating Temperature (industrial)  
-40  
+85  
°C  
DC Electrical Characteristics  
Unless stated otherwise, VDD = 3.3 V or 5 V, Ambient Temperature -40 to +85°C  
Parameter  
Operating Voltage  
Input High Voltage  
Input Low Voltage  
Input High Voltage  
Input Low Voltage  
Output High Voltage  
Symbol  
Conditions  
Min.  
Typ.  
Max. Units  
VDD  
3.0  
5.5  
V
V
V
V
V
V
V
ICLK  
ICLK  
VDD/2+1 VDD/2  
IH  
V
VDD/2 VDD/2-1  
0.8  
IL  
V
S3:S0  
2
IH  
V
S3:S0  
IL  
V
VDD = 3.3 V,  
2.4  
OH  
I
= -8 mA  
OH  
Output Low Voltage  
Output High Voltage  
Short Circuit Current  
V
VDD = 3.3 V,  
= 8 mA  
0.4  
V
V
OL  
OH  
OS  
I
OL  
V
VDD = 3.3 V or 5 V,  
= -8 mA  
VDD-0.4  
I
OH  
I
VDD = 3.3 V, each  
output  
50  
mA  
MDS 552A-01 B  
8
Revision 010906  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  
ICS552A-01  
Oscillator, Multiplier, and Buffer with 8 Outputs  
Parameter  
Symbol  
Conditions  
Min.  
Typ.  
Max. Units  
Operating Supply Current  
I
I
I
at 3.3 V, no load, 25  
MHz in, x4  
35  
mA  
DD  
DD  
DD  
Operating Supply Current  
at 5 V, no load, 25 MHz  
in, x4  
59  
55  
mA  
µA  
Power-down Supply  
Current  
S3:S0 = 0 (GND)  
AC Electrical Characteristics  
Unless stated otherwise, VDD = 3.3 V or 5 V, Ambient Temperature -40 to +85° C  
Parameter  
Symbol  
Conditions  
Fundamental crystal  
Input clock  
Min.  
10  
Typ.  
Max. Units  
Input Frequency  
F
27  
27  
MHz  
MHz  
ns  
IN  
10  
Output Rise Time  
Output Fall Time  
Duty Cycle  
t
0.8 to 2.0 V  
1.5  
1.5  
60  
OR  
t
2.0 to 0.8 V  
ns  
OF  
at VDD/2  
40  
50  
%
Output-to-Output Skew  
All modes, Rising  
edges at VDD/2  
250  
ps  
Absolute Jitter  
Mode A, Deviation from  
Mean  
75  
25  
ps  
ps  
One Sigma Clock Period Jitter  
Mode A  
Thermal Characteristics  
Parameter  
Symbol  
Conditions  
Min.  
Typ. Max. Units  
Thermal Resistance Junction to  
Ambient  
θ
θ
θ
Still air  
135  
93  
°C/W  
°C/W  
°C/W  
°C/W  
JA  
JA  
JA  
JC  
1 m/s air flow  
3 m/s air flow  
78  
Thermal Resistance Junction to Case  
θ
60  
MDS 552A-01 B  
9
Revision 010906  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  
ICS552A-01  
Oscillator, Multiplier, and Buffer with 8 Outputs  
Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Wide Body)  
Package dimensions are kept current with JEDEC Publication No. 95  
Millimeters  
Inches  
20  
Symbol  
Min  
Max  
1.75  
0.25  
1.50  
0.30  
0.25  
8.75  
6.20  
4.00  
Min  
Max  
A
A1  
A2  
b
1.35  
0.10  
--  
0.20  
0.18  
8.55  
5.80  
3.80  
0.053  
0.004  
--  
0.008  
0.007  
0.337  
0.228  
0.150  
0.069  
0.010  
0.059  
0.012  
0.010  
0.344  
0.244  
0.157  
E1  
E
INDEX  
AREA  
c
D
E
E1  
e
1
2
D
.635 Basic  
.025 Basic  
L
α
0.40  
0°  
1.27  
8°  
0.016  
0°  
0.050  
8°  
aaa  
--  
0.10  
--  
0.004  
A
A2  
A1  
c
- C -  
e
SEATING  
PLANE  
b
L
aaa C  
Ordering Information  
Part / Order Number  
Marking  
Shipping Packaging  
Tubes  
Package  
Temperature  
0 to +70°C  
ICS552AR-01  
ICS552AR-01T  
ICS552AR-01LF  
ICS552AR-01LFT  
ICS552ARI-01  
ICS552AR-01  
ICS552AR-01  
552AR-01LF  
552AR-01LF  
ICS552ARI01  
ICS552ARI01  
552ARI01LF  
552ARI01LF  
20-pin SSOP  
20-pin SSOP  
20-pin SSOP  
20-pin SSOP  
20-pin SSOP  
20-pin SSOP  
20-pin SSOP  
20-pin SSOP  
Tape and Reel  
Tubes  
0 to +70°C  
0 to +70°C  
Tape and Reel  
Tubes  
0 to +70°C  
-40 to +85°C  
-40 to +85°C  
-40 to +85°C  
-40 to +85°C  
ICS552ARI-01T  
ICS552ARI-01LF  
ICS552ARI-01LFT  
Tape and Reel  
Tubes  
Tape and Reel  
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)  
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would  
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial  
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary  
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any  
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or  
critical medical instruments.  
MDS 552A-01 B  
10  
Revision 010906  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  

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IDT

ICS552G-03LFT

Low Skew Clock Driver, 552 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.173 INCH, 0.65 MM PITCH, TSSOP-16
IDT