ICS552G-03IT [IDT]
Low Skew Clock Driver, 552 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.173 INCH, TSSOP-16;
| 型号： | ICS552G-03IT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 552 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.173 INCH, TSSOP-16 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：44K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS552-03
LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
Description
Features
The ICS552-03 is a low skew, single input to eight
output clock buffer. Four of the outputs are exact copies
of the input, while the other four are divide by 2 copies
of the input. It is part of ICS’ ClockBlocksTM family. See
the ICS553 for a 1 to 4 low skew buffer, or the
ICS552-02 for a 1 to 8 low skew buffer without divide by
2.
• Low skew outputs (50 ps maximum)
• Packaged in 16 pin TSSOP
• Low power CMOS technology
• Operating Voltages of 2.5 V to 5 V
• Output Enable pin tri-states outputs
• Low skew between 1X and 1/2X outputs (100 ps
maximum)
For more than 8 outputs see the MK74CBxxx BuffaloTM
series of clock drivers.
• One bank of 4 outputs at 1X
• One bank of 4 outputs at 1/2X
• 5V tolerant input clocks
• Input clock multiplexer
ICS makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact us for all of your clocking
needs.
• Industrial temperature
Block Diagram
Q0
Q1
Q2
Q3
P0
INA
INB
1
0
P1
Divide
by 2
P2
P3
SELA
OE
MDS 552-03 E
1
Revision 072202
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS552-03
LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
Pin Assignment
Input Source Select
SELA
Input
INB
OE
VDD
Q0
Q1
Q2
Q3
GND
INB
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SELA
VDD
P3
P2
P1
P0
GND
INA
0
1
INA
16 Pin 173 Mil (0.65mm) TSSOP
Pin Descriptions
Pin
Number
Pin
Name
OE
Pin
Type
Pin Description
1
Input
Output Enable. Tri-states outputs when low.Internal Pull-up resistor
2
VDD
Q0
Power Connect to +2.5 V, +3.3 V or +5.0 V. Must be the same as pin 15
Output Clock Output Q0
3
4
Q1
Output Clock Output Q1
5
Q2
Output Clock Output Q2
6
Q3
Output Clock Output Q3
7
GND
INB
INA
GND
P0
Power Ground
8
Input
Input
Clock Input B. 5 V tolerant input
Clock Input A. 5 V tolerant input
9
10
11
12
13
14
15
16
Power Ground
Output Clock Output P0
P1
Output Clock Output P1
P2
Output Clock Output P2
P3
Output Clock Output P3
VDD
SELA
Power Connect to +2.5 V, +3.3 V or +5.0 V. Must be the same as pin 2
Input
Selects either INA or INB. Internal pull-up resistor
External Components
A minimum number of external components are required for proper operation. Decoupling capacitors of
0.01 µF should be connected between VDD on pin 2 and GND on pin 7,and between VDD on pin 15 and
GND on pin 10, as close to the device as possible. A 33 Ω series terminating resistor should be used on
each clock output if the trace is longer than 1 inch.
To achieve the low output skews that the ICS552-03 is capable of, careful attention must be paid to board
layout. Essentially, all 8 outputs must have identical terminations, identical loads, and identical trace
geometries. If they do not, the output skew will be degraded. For example, using a 30Ω series termination
on one output (with 33Ω on the others) will cause at least 15 ps of skew.
MDS 552-03 E
2
Revision 072202
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS552-03
LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS552-03. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
SELA, OE, and all Outputs
INA and INB
7 V
-0.5 V to VDD+0.5 V
-0.5V to 5.5V
-40 to +85 °C
-65 to +150 °C
175 °C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260 °C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+85
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
-40
–
+2.375
+5.25
V
DC Electrical Characteristics
VDD=2.5V ±5%, Ambient temperature -40 to +85 °C, unless stated otherwise
Parameter
Operating Voltage
Symbol
VDD
VIH
Conditions
Min.
2.375
Typ.
Max.
Units
2.625
5.5
V
V
Input High Voltage, INA, INB
Input Low Voltage, INA, INB
Input High Voltage, OE, SELA
Input Low Voltage, OE, SELA
Output High Voltage
Note 1
VDD/2+0.5
VIL
Note 1
VDD/2-0.5
VDD
V
VIH
1.8
2.0
V
VIL
0.7
V
VOH
VOL
IDD
ZO
IOH = -16 mA
IOL = 16 mA
V
Output Low Voltage
0.4
V
Operating Supply Current
Nominal Output Impedance
Internal Pull-up Resistor
Input Capacitance
No load, 100 MHz
17
20
mA
Ω
RPU
CIN
TBD
5
kΩ
pF
pF
mA
OE pin
CIN
INA, INB
Each output
TBD
60
Short Circuit Current
IOS
MDS 552-03 E
3
Revision 072202
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS552-03
LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
DC Electrical Characteristics (continued)
VDD=3.3V ±5%, Ambient temperature -40 to +85 °C, unless stated otherwise
Parameter
Operating Voltage
Symbol
VDD
VIH
Conditions
Min.
3.135
Typ.
Max.
3.465
5.5
Units
V
Input High Voltage, INA, INB
Input Low Voltage, INA, INB
Input High Voltage, OE, SELA
Input Low Voltage, OE, SELA
Output High Voltage
Note 1
VDD/2+0.7
V
VIL
Note 1
VDD/2-0.7
VDD
V
VIH
2
V
VIL
0.8
V
VOH
VOL
IDD
ZO
IOH = -25 mA
2.4
V
Output Low Voltage
IOL = 25 mA
0.4
V
Operating Supply Current
Nominal Output Impedance
Internal Pull-up Resistor
Input Capacitance
No load, 100 MHz
22
20
mA
Ω
RPU
CIN
TBD
5
kΩ
pF
pF
mA
OE pin
CIN
INA, INB
Each output
TBD
80
Short Circuit Current
IOS
VDD=5V ±5%, Ambient temperature -40 to +85 °C, unless stated otherwise
Parameter
Operating Voltage
Symbol
VDD
VIH
Conditions
Min.
4.75
Typ.
Max.
5.25
Units
V
Input High Voltage, INA, INB
Input Low Voltage, INA, INB
Input High Voltage, OE, SELA
Input Low Voltage, OE, SELA
Output High Voltage
Note 1
VDD/2+1
5.5
V
VIL
Note 1
VDD/2-1
VDD
0.8
V
VIH
2
V
VIL
V
VOH
VOL
IDD
ZO
IOH = -35 mA
IOL = 35 mA
2.4
V
Output Low Voltage
0.4
V
Operating Supply Current
Nominal Output Impedance
Internal Pull-up Resistor
Input Capacitance
No load, 100 MHz
40
20
mA
Ω
RPU
CIN
TBD
5
kΩ
pF
pF
mA
OE pin
CIN
INA, INB
Each output
TBD
100
Short Circuit Current
IOS
Notes: 1. Nominal switching threshold is VDD/2
MDS 552-03 E
4
Revision 072202
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS552-03
LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
AC Electrical Characteristics
VDD = 2.5V ±5%, Ambient Temperature -40 to +85 °C, unless stated otherwise
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ. Max. Units
0
160
1.5
1.5
MHz
ns
Output Rise Time
Output Fall Time
Propagation Delay
tOR
tOF
0.8 to 2.0 V, CL=15 pF
2.0 to 0.8 V, CL=15 pF
1.0
1.0
6.5
0
ns
Note 1
Note 2
ns
Output to output skew. Between
any two Q outputs
Rising edges at VDD/2
Rising edges at VDD/2
Rising edges at VDD/2
50
50
ps
Output to output skew. Between
any two P outputs
Note 2
Note 2
Note 3
0
0
0
ps
ps
ps
Output to output skew. Between
any P to any Q output
100
50
Input A to Input B skew.
VDD = 3.3V ±5%, Ambient Temperature -40 to +85 °C, unless stated otherwise
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ. Max. Units
0
200
1.0
1.0
MHz
ns
Output Rise Time
Output Fall Time
Propagation Delay
tOR
tOF
0.8 to 2.0 V, CL=15 pF
2.0 to 0.8 V, CL=15 pF
0.6
0.6
5
ns
Note 1
Note 2
ns
Output to output skew. Between
any two Q outputs
Rising edges at VDD/2
Rising edges at VDD/2
Rising edges at VDD/2
0
50
50
ps
Output to output skew. Between
any two P outputs
Note 2
Note 2
Note 3
0
0
0
ps
ps
ps
Output to output skew. Between
any P to any Q output
100
50
Input A to Input B skew
MDS 552-03 E
5
Revision 072202
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS552-03
LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
AC Electrical Characteristics (continued)
VDD = 5.0V ±5%, Ambient Temperature -40 to +85 °C, unless stated otherwise
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ. Max. Units
0
160
0.7
0.7
MHz
ns
Output Rise Time
Output Fall Time
Propagation Delay
tOR
tOF
0.8 to 2.0 V, CL=15 pF
2.0 to 0.8 V, CL=15 pF
0.3
0.3
4
ns
Note 1
Note 2
ns
Output to output skew. Between
any two Q outputs
Rising edges at VDD/2
Rising edges at VDD/2
Rising edges at VDD/2
0
50
50
ps
Output to output skew. Between
any two P outputs
Note 2
Note 2
Note 3
0
0
0
ps
ps
ps
Output to output skew. Between
any P to any Q output
100
50
Input A to Input B skew
Notes: 1. With rail to rail input clock
2. Between any two outputs with equal loading
3. Propagation delay matching through the part
4. Duty cycle on outputs will match incoming clock duty cycle. Consult ICS for tight duty cycle clock
generators.
MDS 552-03 E
6
Revision 072202
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS552-03
LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
Package Outline and Package Dimensions (16 pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Millimeters
Min Max
Inches
Max
16
Symbol
Min
--
A
A1
A2
b
--
1.20
0.15
1.05
0.30
0.20
5.1
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E1
E
INDEX
AREA
C
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
D
E
6.40 BASIC
1
2
E1
e
4.30
4.50
0.65 Basic
D
L
0.45
0°
0.75
8°
0.018
0°
0.030
8°
α
aaa
--
0.10
--
0.004
A
2
A
A
1
c
- C -
e
SEATING
PLANE
α
b
L
aaa
C
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
Part / Order Number
Marking (both)
Shipping
packaging
Tubes
Package
Temperature
ICS552G-03I
ICS (top line)
16 pin TSSOP
16 pin TSSOP
-40 to +85 °C
-40 to +85 °C
ICS552G-03IT
552G-03I (2nd line)
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 552-03 E
7
Revision 072202
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
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