ICS554G-01T [ICSI]
LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT; 低偏移1至4时钟缓冲器PECL IN， OUT PECL
| 型号： | ICS554G-01T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT |
| 文件： | 总5页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P R E L I M I N A R Y I N F O R M A T I O N
ICS554-01
LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT
Description
Features
The ICS554-01 is a low skew clock buffer with a single
complimentary PECL input to four PECL outputs. Part
of ICS’ Clock BlocksTM family, this is our lowest skew
PECL clock buffer. For parts which do not require PECL
inputs or outputs, see the ICS553 for a 1 to 4 low skew
buffer, or the ICS552-02 for a 1 to 8 low skew buffer. For
more than 8 outputs see the MK74CBxxx BuffaloTM
series of clock drivers.
• Outputs are skew matched to within 50ps
• Packaged in 16 pin TSSOP
• One PECL input to 4 PECL output clock drivers
• Operating Voltages of 3.3V to 5V
ICS makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact us for all of your clocking
needs.
Block Diagram
VDD
62Ω
62Ω
IN
IN
Q0
Q0
270Ω 270Ω
VDD
62Ω
62Ω
Q1
Q1
270Ω 270Ω
VDD
62Ω
62Ω
Q2
Q2
270Ω 270Ω
VDD
62Ω
62Ω
Q3
Q3
270Ω 270Ω
VDD
1.1kΩ
RES
0.01mF
MDS 554-01 A
1
Revision 031901
Integrated Circuit Systems G 525 Race Street, San Jose, CA 95126 G tel (408) 295-9800 G www.icst.com
P R E L I M I N A R Y I N F O R M A T I O N
ICS554-01
LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT
Pin Assignment
N C
V D D
Q 0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R E S
V D D
Q 3
Q 3
Q 2
Q 2
G N D
IN
Q 0
Q 1
Q 1
G N D
IN
16 P in T S S O P
Pin Descriptions
Pin
Number
Pin
Name
NC
Pin
Type
Pin Description
1
-
No Connect.
2
VDD
Q0
Power Connect to +2.5 V, +3.3V or +5.0V. Must be the same as pin 15.
Output Clock Output Q0
3
4
Q0
Output Clock Output Q0
5
Q1
Output Clock Output Q1
6
Q1
Output Clock Output Q1
7
GND
IN
Power Ground
8
Input
Input
PECL Clock Input
9
IN
Complementary PECL Clock Input
10
11
12
13
14
15
16
GND
Q2
Power Ground
Output Clock Output Q2
Q2
Output Clock Output Q2
Q3
Output Clock Output Q3
Q3
Output Clock Output Q3
VDD
RES
Power Connect to +2.5V, +3.3V or +5.0V. Must be the same as pin 2
Input
Bias Resistor Input.
MDS 554-01 A
2
Revision 031901
Integrated Circuit Systems G 525 Race Street, San Jose, CA 95126 G tel (408) 295-9800 G www.icst.com
P R E L I M I N A R Y I N F O R M A T I O N
ICS554-01
LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT
External Components
The ICS554-01 requires a decoupling capacitor of 0.01µF to be connected between VDD on pin 2 and
GND on pin 7, as well as between VDD on pin 15 and GND on pin 10. These decoupling capacitors should
be placed as close to the device as possible. A 0.01µF capacitor must be placed between the RES (pin 16)
and Ground, also, a resistor must be connected between the RES (pin 16) and VDD. Another eight
resistors are needed for the PECL outputs as shown on the block diagram on page 1. Suggested values of
these resistors are shown in the Block Diagram, but they can be varied to change the differential pair
output swing, and the DC level. Refer to Application Note, MAN09.
To achieve the low output skews that the ICS554-01 is capable of, careful attention must be paid to board
layout. Essentially, all 8 outputs must have identical terminations, identical loads, and identical trace
geometries. If they do not, the output skew will be degraded. For example, using a 30Ω series termination
on one output (with 33Ω on the others) will cause at least 15ps of skew.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS554-01. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7V
-0.5V to VDD+0.5V
0 to +70°C
-65 to +150°C
175°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
–
+3.15
+5.25
V
MDS 554-01 A
3
Revision 031901
Integrated Circuit Systems G 525 Race Street, San Jose, CA 95126 G tel (408) 295-9800 G www.icst.com
P R E L I M I N A R Y I N F O R M A T I O N
ICS554-01
LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT
DC Electrical Characteristics
VDD=3.3V 5%, Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Operating Voltage
Symbol
VDD
IN
Conditions
Min.
3.15
Typ.
Max.
5.25
Units
V
Peak to Peak Input Voltage
Input Common Mode Range
Input Common Mode Range
Input High Voltage, OE
Input Low Voltage, OE
0.3
1.0
V
IN
VDD=3.3V
VDD-2.0
VDD-3.7
2
VDD-0.6
VDD-0.6
VDD
V
IN
VDD=5V
V
VIH
–
–
–
V
VIL
–
Note 1
–
0.4
V
Output High Voltage
VOH
VOL
IDD
IOS
VDD-1.2
–
V
Output Low Voltage
Note 1
–
VDD-2.0
V
Operating Supply Current
Short Circuit Current, 2.5V
Short Circuit Current, 3.3V
Short Circuit Current, 5V
No load, 135 MHz
67
40
50
60
mA
mA
mA
mA
IOS
IOS
Notes: 1. VOH and VOL can be set by the external resistor values on the PECL outputs.
2. IDD includes the current through the external resistors which can be modified.
AC Electrical Characteristics
VDD = 3.3V ±±%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ. Max. Units
0
200
MHz
ns
Propagation Delay (VDD=3.3V)
Propagation Delay (VDD=5V)
Output to output skew.
4
3
0
ns
Crossing point of pair
50
ps
MDS 554-01 A
4
Revision 031901
Integrated Circuit Systems G 525 Race Street, San Jose, CA 95126 G tel (408) 295-9800 G www.icst.com
P R E L I M I N A R Y I N F O R M A T I O N
ICS±±4-01
LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT
Package Outline and Package Dimensions (16 pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Min Max
Inches
Max
Symbol
Min
--
A
a
--
1.20
0.15
0.30
0.20
5.10
4.50
0.047
0.006
0.012
0.05
0.19
0.09
4.90
4.30
0.002
0.007
b
c
0.0035 0.008
D
E
e
0.193
0.169
0.201
0.177
E
H
0.65 Basic
6.40 Basic
0.45 0.75
0.0256 Basic
0.252 Basic
H
L
0.018
0.030
D
A
a
c
e
b
L
Ordering Information
Part / Order Number
Marking (both)
Shipping
packaging
Tubes
Package
Temperature
ICS554G-01
ICS554G-01T
ICS (top line)
16 pin TSSOP
16 pin TSSOP
0 to +70° C
0 to +70° C
554G-01 (2nd line)
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 554-01 A
5
Revision 031901
Integrated Circuit Systems G 525 Race Street, San Jose, CA 95126 G tel (408) 295-9800 G www.icst.com
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