ICS557-01 [ICSI]
PCI-EXPRESS CLOCK SOURCE; PCI - Express时钟源
| 型号： | ICS557-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | PCI-EXPRESS CLOCK SOURCE |
| 文件： | 总10页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS557-01
PCI-EXPRESS CLOCK SOURCE
Description
Features
TM
The ICS557-01 is a clock chip designed for use in
PCI-Express Cards as a clock source. It provides a pair
of differential outputs at 100 MHz in a small 8-pin SOIC
package.
• Supports PCI-Express HCSL Outputs
0.7 V current mode differential pair
• Supports LVDS Output Levels
• Packaged in 8-pin SOIC
Using ICS’ patented Phase-Locked Loop (PLL)
techniques, the device takes a 25 MHz crystal input
and produces HCSL (Host Clock Signal Level)
differential outputs at 100 MHz clock frequency. LVDS
signal levels can also be supported via an alternative
termination scheme.
• Available in Pb (lead) free package
• Operating voltage of 3.3 V
• Low power consumption
• Input frequency of 25 MHz
• Short term jitter 100 ps (peak-to-peak)
• Output Enable via pin selection
• Industrial temperature range available
Block Diagram
VDD
CLK
Phase Lock
Loop
CLK
X1
X2
Clock
Buffer/
Crystal
Oscillator
25 MHz
crystal /clock
Crystal Tuning Capacitors
RR(IREF)
GND
OE
MDS 557-01 F
1
Revision 011606
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-01
PCI-EXPRESS CLOCK SOURCE
Pin Assignment
1
8
7
6
5
VDD
CLK
CLK
IREF
OE
2
X1
3
4
X2
GND
8 Pi n (150 mi l ) SOIC
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
OE
Input Output Enable signal
(H = outputs are enabled, L = outputs are disabled/tristated).
Internal pull-up resistor.
2
3
X1
X2
Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
XO
Crystal Connection. Connect to a parallel mode crystal.
Leave floating if clock input.
4
5
GND
IREF
Power Connect to ground.
Output A 475Ω precision resistor connected between this pin and ground
establishes the external reference current.
6
7
8
CLK
CLK
VDD
Output HCSL differential complementary clock output.
Output HCSL differential clock output.
Power Connect to +3.3 V.
MDS 557-01 F
2
Revision 011606
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-01
PCI-EXPRESS CLOCK SOURCE
Applications Information
External Components
A minimum number of external components are
required for proper operation.
Output Structures
6*IREF
IREF
=2.3 mA
Decoupling Capacitors
Decoupling capacitors of 0.01 µF should be connected
between VDD and the ground plane (pin 4) as close to
the VDD pin as possible. Do not share ground vias
between components. Route power from power source
through the capacitor pad and then into ICS pin.
Crystal
See Output Termination
Sections - Pages 3 ~ 5
A 25 MHz fundamental mode parallel resonant crystal
Ω
RR 475
with C = 16 pF should be used. This crystal must have
L
less than 300 ppm of error across temperature in order
for the ICS557-01 to meet PCI Express specifications.
General PCB Layout Recommendations
Crystal Capacitors
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
Crystal capacitors are connected from pins X1 to
ground and X2 to ground to optimize the accuracy of
the output frequency.
1. Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible.
C = Crystal’s load capacitance in pF
L
Crystal Capacitors (pF) = (C - 8) * 2
L
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
2. No vias should be used between decoupling
capacitor and VDD pin.
Current Source (Iref) Reference Resistor - RR
3. The PCB trace to VDD pin should be kept as short
as possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from
the device is less critical.
If board target trace impedance (Z) is 50Ω, then R =
R
475Ω (1%), providing IREF of 2.32 mA. The output
current (I ) is equal to 6*IREF.
OH
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (any ferrite beads and bulk decoupling
capacitors can be mounted on the back). Other signal
traces should be routed away from the ICS557-01.This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-01 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown
in detail in the PCI-Express Layout Guidelines
section.
The ICS557-01can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section
MDS 557-01 F
3
Revision 011606
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-01
PCI-EXPRESS CLOCK SOURCE
PCI-Express Layout Guidelines
Recommendations for Differential Routing
as non-coupled 50 ohm trace.
as non-coupled 50 ohm trace.
Dimension
0.5
0.2
0.2
as non-coupled 50 ohm trace.
3
49
ferential Routing on a Single PCB
as coupled microstrip 100 ohm differential trace.
as coupled stripline 100 ohm differential trace.
Dimension
2 min to
1.8 min to
ial Routing to a PCI Express Connector
as coupled microstrip 100 ohm differential trace.
as coupled stripline 100 ohm differential trace.
Dimension
0.25 to
0.225 min t
Figure 1: PCI-Express Device Routing
L1
L2
L4
RS
RS
L4’
L1’
L2’
RT
RT
PCI-Express
Load or
Connector
ICS557-01
Output
L3’ L3
Clock
Typical PCI-Express (HCSL)
Waveform
700 mV
0
500 ps
500 ps
tOR
tOF
0.52 V
0.175 V
0.52 V
0.175 V
MDS 557-01 F
4
Revision 011606
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-01
PCI-EXPRESS CLOCK SOURCE
LVDS Compatible Layout Guidelines
LVDS Recommendations for Differential Routing
Dimension or Value Unit
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
RP
RQ
0.5 max
0.2 max
100
100
150
inch
inch
ohm
ohm
ohm
RT
L3 length, Route as coupled 50 ohm differential trace.
L3 length, Route as coupled 50 ohm differential trace.
Figure 3: LVDS Device Routing
L1
L3
RQ
RP
L3’
L1’
RT
RT
ICS557-01
Clock
LVDS
Device
Load
L2’ L2
Output
Typical LVDS Waveform
1325 mV
1000 mV
500 ps
500 ps
tOR
tOF
1250 mV
1150 mV
1250 mV
1150 mV
MDS 557-01 F
5
Revision 011606
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-01
PCI-EXPRESS CLOCK SOURCE
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-01. These ratings are
stress ratings only. Functional operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed
only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD, VDDA
5.5 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
0 to +70°C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
-40 to +85°C
-65 to +150°C
125°C
Junction Temperature
Soldering Temperature
260°C
ESD Protection (Input)
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85°C
Parameter
Supply Voltage
Input High Voltage
Symbol
Conditions
Min.
3.135
2.0
Typ.
Max.
Units
V
3.465
1
V
VDD +0.3
V
IH
1
Input Low Voltage
V
VSS-0.3
-5
0.8
5
V
IL
2
Input Leakage Current
I
0 < Vin < VDD
µA
mA
mA
pF
pF
nH
kΩ
kΩ
IL
Operating Supply Current
I
With 50Ω and 2 pF load
OE =Low
55
35
7
DD
I
DDOE
Input Capacitance
Output Capacitance
Pin Inductance
C
Input pin capacitance
Output pin capacitance
IN
C
6
OUT
L
5
PIN
Output Resistance
Pull-up Resistor
Rout
CLK outputs
OE
3.0
R
60
PUP
1 Single edge is monotonic when transitioning through region.
2 Inputs with pull-ups/-downs are not included.
MDS 557-01 F
6
Revision 011606
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-01
PCI-EXPRESS CLOCK SOURCE
AC Electrical Characteristics - CLK/CLK
Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature -40 to +85°C
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ.
25
Max.
Units
MHz
MHz
mV
Output Frequency
Output High Voltage
100
700
0
1,2
1,2
V
660
-150
250
850
OH
Output Low Voltage
Crossing Point
V
mV
OL
Absolute
350
550
140
mV
1,2
Voltage
Crossing Point
Variation over all edges
mV
1,2,4
Voltage
1,3
Jitter, Cycle-to-Cycle
100
332
344
ps
ps
ps
ps
1,2
Rise Time
t
from 0.175 V to 0.525 V
from 0.525 V to 0.175 V
175
175
700
700
125
OR
1,2
Fall Time
t
OF
Rise/Fall Time
1,2
Variation
1,3
Duty Cycle
45
55
%
µs
5
Output Enable Time
Output Disable Time
Stabilization Time
All outputs
30
30
5
All outputs
µs
t
From power-up VDD=3.3 V
Settling period after spread change
3.0
3.0
ms
ms
STABLE
Spread Change Time
t
SPREAD
1
Test setup is R =50 ohms with 2 pF, R = 475Ω (1%).
L
R
2
3
4
5
Measurement taken from a single-ended waveform.
Measurement taken from a differential waveform.
Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.
CLKOUT pins are tri-stated when OE is low asserted. CLKOUT is driven differential when OE is high.
Thermal Characteristics (8-pin SOIC)
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
150
140
120
40
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
MDS 557-01 F
7
Revision 011606
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-01
PCI-EXPRESS CLOCK SOURCE
Marking Diagram (ICS557M-01)
Marking Diagram (ICS557MI-01)
8
5
8
5
557MI01
######
YYWW
557M-01
######
YYWW
1
4
1
4
Marking Diagram (ICS557M-01LF)
Marking Diagram (ICS557MI-01LF)
8
5
8
5
557M-01L
######
YYWW
557MI01L
######
YYWW
1
4
1
4
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. “L” designates Pb (lead) free packaging.
4. Bottom marking: (orgin). Origin = country of origin if not USA.
MDS 557-01 F
8
Revision 011606
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-01
PCI-EXPRESS CLOCK SOURCE
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches*
Symbol
Min
Max
1.75
0.25
0.51
0.25
5.00
4.00
Min
Max
8
A
A1
B
C
D
E
e
1.35
0.10
0.33
0.19
4.80
3.80
.0532
.0040
.013
.0688
.0098
.020
.0075
.1890
.1497
.0098
.1968
.1574
E
H
INDEX
AREA
1.27 BASIC
0.050 BASIC
H
h
5.80
6.20
0.50
1.27
8°
.2284
.010
.016
0°
.2440
.020
.050
8°
1
2
0.25
0.40
0°
L
D
α
*For reference only. Controlling dimensions in mm.
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
MDS 557-01 F
9
Revision 011606
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-01
PCI-EXPRESS CLOCK SOURCE
Ordering Information
Part / Order Number
ICS557M-01
Marking
See Page 8
Shipping Packaging
Tubes
Package
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
Temperature
0 to +70° C
ICS557M-01T
Tape and Reel
Tubes
0 to +70° C
ICS557M-01LF
ICS557M-01LFT
ICS557MI-01
0 to +70° C
Tape and Reel
Tubes
0 to +70° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
ICS557MI-01T
ICS557MI-01LF
ICS557MI-01LFT
Tape and Reel
Tubes
Tape and Reel
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 557-01 F
10
Revision 011606
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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