ICS601-02 [ICSI]
Low Phase Noise Clock Multiplier; 低相位噪声时钟乘法器
| 型号： | ICS601-02 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Low Phase Noise Clock Multiplier |
| 文件： | 总5页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS601-02
Low Phase Noise Clock Multiplier
Description
Features
The ICS601-02 is a low cost, low phase noise, high
performance clock synthesizer for any application that
requires low phase noise and low jitter. The ICS601 is
ICS’ lowest phase noise multiplier. Using ICS’ patented
analog and digital Phase Locked Loop (PLL)
techniques, the chip accepts a 10-27 MHz crystal or
clock input, and produces output clocks up to 170
MHz at 3.3 V. A separate supply pin is provided so that
the output can be 2.5 V.
• Packaged in 16 pin SOIC (Pb free)
• Uses fundamental 10 - 27 MHz crystal, or clock
• Patented PLL with the lowest phase noise
• Output clocks up to 170 MHz at 3.3 V
• Low phase noise: -132 dBc/Hz at 10 kHz
• Output Enable function tri states outputs
• Low jitter - 18 ps one sigma
• Full swing CMOS outputs with 25 mA drive
capability at TTL levels
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
For applications which require defined input to output
timing, use the ICS670-01.
• Advanced, low power, sub-micron CMOS process
• Industrial temperature
• 3.3 V or 5 V core VDD. Output clock can operate
down to 2.5 V
Block Diagram
VDD
VDDP
Phase
Comparator
Charge
Pump
Loop
Filter
Output
Buffer
Reference
Divide
CLK
VCO
X1/ICLK
X2
VCO
Divide
Crystal
Oscillator
ROM Based
Multipliers
Optional crystal
capacitors
needed
GND
S3 S2 S1 S0
OE
for accurate
tuning
(not shown)
MDS 601-02 D
1
Revision 111204
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126 • (408) 295-9800tel • www.icst.com
ICS601-02
Low Phase Noise Clock Multiplier
Multiplier Select Table
Pin Assignment
S3 S2 S1 S0 CLK (see note 2 on following page)
CLK
VDDP
VDD
GND
GND
GND
1
16
15
14
13
12
11
10
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input x4/3
Input x4
2
3
4
5
6
7
Input x25/4
Input x3
VDD
GND
OE
S0
Input x7.5
Input x5
VDD
Input x6
X2
Input x8
S3
S1
Input x8/3
Input x8
S2
9
X1/ICLK
8
Input x12.5
Input x6
Input x15
Input x10
Input x12
Input x16
0=connect directly to ground
1=connect directly to VDD
Pin Descriptions
Number
Name
CLK
VDDP
VDD
VDD
VDD
X2
Type Description
1
2
O
P
P
P
P
XO
I
Clock output from VCO. Output frequency equals the input frequency times multiplier.
Supply pin for CLK output buffer. Sets output clock amplitude. Connect to 2.5V or 3.3V
Connect to +3.3V or +5V. Must match other VDDs.
3
4
Connect to +3.3V or +5V. Must match other VDDs.
5
Connect to +3.3V or +5V. Must match other VDDs.
6
Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal.
Multiplier select pin 1. Determines CLK output per table above. Internal pull-up.
Crystal connection. Connect to a 10-27 MHz fundamental parallel mode crystal, or clock.
Multiplier select pin 2. Determines CLK output per table above. Internal pull-up.
Multiplier select pin 3. Determines CLK output per table above. Internal pull-up.
Multiplier select pin 0. Determines CLK output per table above. Internal pull-up.
Output Enable. Tri-states the output clock when low. Internal pull-up.
Connect to ground.
7
S1
8
X1/ICLK
S2
XI
I
9
10
11
12
13
14
15
16
S3
I
S0
I
OE
I
GND
GND
GND
GND
P
P
P
P
Connect to ground.
Connect to ground.
Connect to ground.
Key: I = Input with internal pull-up resistor; O = output; P = power supply connection; XI, X2 = crystal connections.
MDS 601-02 D
2
Revision 111204
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126 • (408) 295-9800tel • www.icst.com
ICS601-02
Low Phase Noise Clock Multiplier
Achieving Low Phase Noise
Figure 1 shows a typical phase noise measurement in a 125 MHz system. There are a few simple steps that can be
taken to achieve these levels of phase noise from the ICS601-02. Variations in VDD will increase the phase noise, so
it is important to have a stable, low noise supply voltage at the device. Use decoupling capacitors of 0.1 µF in parallel
with 0.01 µF. It is important to have these capacitors as close as possible to the ICS601-02 supply pins.
Disabling the REFOUT clock is also important for achieving low phase noise; lab tests have shown that this can
reduce the phase noise by as much as 10 dBc/Hz.
0
-20
-40
-60
-80
-100
-120
-140
10.0E+0
100.0E+0
1.0E+3
10.0E+3
100.0E+3
1.0E+6
10.0E+6
Offset from Carrier (Hz)
Figure 1. Phase Noise of ICS601-02 at 125 MHz out, 25 MHz crystal input, VDD =
3.3 V.
External Components/Crystal Selection
The ICS601-02 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.01 µF and 0.1 µF should be connected between VDD and GND, as close to the part as possible. A series
termination resistor of 33 W may be used for the clock output. The crystal must be connected as close to the chip as
possible. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning
when using a crystal, capacitors should be connected from pins X1 to ground and X2 to ground. In general, the value
of these capacitors is given by the following equation, where C is the crystal load capacitance: Crystal caps (pF) =
L
(C -5) x 2. So for a crystal with 16 pF load capacitance, two 22 pF caps can be used. For any given board layout, ICS
L
can measure the board capacitance and recommend the exact capacitance value to use.
MDS 601-02 D
3
Revision 111204
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126 • (408) 295-9800tel • www.icst.com
ICS601-02
Low Phase Noise Clock Multiplier
Electrical Specifications
Parameter
Conditions
Referenced to GND
Minimum Typical Maximum Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
7
VDD+0.5
85
V
Inputs and Clock Outputs
Ambient Operating Temperature, I version
Soldering Temperature
Referenced to GND
Industrial temperature
Max of 10 seconds
-0.5
-40
V
°C
°C
°C
260
Storage temperature
-65
150
DC CHARACTERISTICS (VDD = VDDP = 3.3 V unless noted)
Operating Voltage, VDD
3.0
5.5
V
V
Output Buffer Voltage, VDDP
2.375
VDD
Input High Voltage, VIH, X1/ICLK pin only
Input Low Voltage, VIL, X1/ICLK pin only
Input High Voltage, VIH
Note 3
Note 3
(VDD/2)+1
V
(VDD/2)-1
0.8
V
2
V
Input Low Voltage, VIL
V
Output High Voltage, VOH, CMOS level
Output High Voltage, VOH
Output Low Voltage, VOL
IOH=-4mA
VDD-0.4
2.4
V
IOH=-12mA
V
IOL=12mA
0.4
20
V
Operating Supply Current, IDD
Short Circuit Current
No Load, 125 MHz
Each output
OE, select pins
9
±60
5
mA
mA
pF
±40
Input Capacitance
AC CHARACTERISTICS (VDD = VDDP = 3.3 V unless noted)
Input Frequency
10
45
27
170
1.5
1.5
55
MHz
MHz
ns
Output Frequency
at 3.3V or 5V
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
0.8 to 2.0V, no load
0.8 to 2.0V, no load
At VDD/2
ns
50
%
Maximum Absolute Jitter, short term, 125 MHz No load
Maximum Jitter, one sigma, 125 MHz (x5) No load
±50
18
±75
25
ps
ps
Phase Noise, relative to carrier, 125 MHz (x5) 100 Hz offset
Phase Noise, relative to carrier, 125 MHz (x5) 1 kHz offset
Phase Noise, relative to carrier, 125 MHz (x5) 10 kHz offset
Phase Noise, relative to carrier, 125 MHz (x5) 100 kHz offset
-108
-123
-132
-125
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the
device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may
affect device reliability.
2. The phase relationship between input and output can change at power up. For a fixed phase
relationship, see the ICS570 or ICS670.
3. Switching occurs nominally at VDD/2.
MDS 601-02 D
4
Revision 111204
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126 • (408) 295-9800tel • www.icst.com
ICS601-02
Low Phase Noise Clock Multiplier
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC no. 95.)
16 pin SOIC
Inches
Min Max
Millimeters
Min Max
Symbol
A
A1
B
C
D
E
e
0.0532 0.0688 1.35
0.0040 0.0098 0.10
0.0130 0.0200 0.33
0.0075 0.0098 0.19
1.75
0.24
0.51
0.24
E
H
INDEX
AREA
0.3859 0.3937 9.80 10.00
0.1497 0.1574 3.80
4.00
.050 BSC
1.27 BSC
H
h
0.2284 0.2440 5.80
0.0099 0.0195 0.25
0.0160 0.0500 0.41
6.20
0.50
1.27
h x 45°
L
D
A
A1
C
B
e
L
Ordering Information
Part/Order Number
ICS601M-02I
Marking
Shipping packaging
tubes
Package
Temperature
-40 to 85 °C
-40 to 85 °C
-40 to 85 °C
ICS601M-02I
ICS601M-02I
ICS601M-02IL
16 pin narrow SOIC
16 pin narrow SOIC
16 pin narrow SOIC
ICS601M-02IT
ICS601M-02ILF
tape and reel
tubes
ICS601M-02ILFT
ICS601M-02IL
tape and reel
16 pin narrow SOIC
-40 to 85 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems,
Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third
parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in
normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or
other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the
right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life
support devices or critical medical instruments.
MDS 601-02 D
5
Revision 111204
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126 • (408) 295-9800tel • www.icst.com
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