ICS650R-14I [ICSI]
Networking System Clock; 网络系统时钟型号: | ICS650R-14I |
厂家: | INTEGRATED CIRCUIT SOLUTION INC |
描述: | Networking System Clock |
文件: | 总4页 (文件大小:49K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY INFORMATION
ICS650-14B
Networking System Clock
Description
Features
• Packaged in 20 pin (150 mil) SSOP (QSOP)
• 25.00 MHz fundamental crystal or clock input
• One fixed output clock of one 25.0 MHz
• One bank of four frequency selectable
output clocks
The ICS650-14B is a low cost, low jitter, high
performance clock synthesizer customized for
networking systems applications. Using analog
Phase-Locked Loop (PLL) techniques, the device
accepts a 25.0 MHz clock or fundamental mode
crystal input to produce multiple output clocks of
one fixed 25.0 MHz, a four (plus one) frequency
selectable bank, and two frequency selectable
clocks. All output clocks are frequency locked
together. The ICS650R-14B outputs
• Three frequency selectable clock outputs
• Zero ppm synthesis error in all clocks
• Ideal for networking systems
all have 0 ppm synthesis error.
• Full CMOS output swing
• Advanced, low power, sub-micron CMOS process
• 3.0V to 5.5V operating voltage
Block Diagram
• Industrial temperature range available
VDD GND
2
2
2
2
4
Output
Buffer
SELA 0:1
CLKA 1:4
SELB 0:1
SELC
Output
Buffer
Clock Synthesis
and Control
Circuitry
CLKA5
CLKB
CLKC
Output
Buffer
Output
Buffer
25.00 MHz
crystal or clock
X1/ICLK
Clock
Buffer/
Output
Buffer
25.00 MHz
Crystal
Oscillator
X2
OE (All outputs)
Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).
MDS 650-14B A
1
Revision 082800
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel• www.icst.com
PRELIMINARY INFORMATION
ICS650-14B
Networking System Clock
Table 1
Pin Assignment
SELA1
SELA0
CLKA1:4
33.33
50
CLKA5
66.66
75
0
0
0
M
1
SELB0
X2
X1/ICLK
VDD
SELB1
GND
CLKB
CLKC
CLKA5
25M
1
2
3
4
5
6
7
8
9
10
20 SELC
19 SELA0
0
66.67
100
133.33
33.33
83.33
125
CLKA2
18
M
M
M
1
0
17 CLKA3
M
1
33.33
50
16
15
VDD
SELA1
0
33.33
25
100
14 GND
1
M
1
75
CLKA4
13
1
66.67
100
12 CLKA1
11
OE
Table 3
Table 2
SELC
CLKC
CLKB/4
62.5
SELB1
SELB0
CLKB
20 pin (150 mil) SSOP
0
M
1
0
0
0
1
1
1
0
M
1
30
27
125
48
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
0
83.33
19.44
80
M
1
Pin Descriptions
Number
Name
SELB0
X2
Type Description
1
T I
XO
XI
P
Select pin for CLKB. See Table 2.
2
Crystal connection. Connect to 25 MHz crystal or leave unconnected for a clock input.
Crystal connection. Connect to 25 MHz fundamental crystal or clock input.
Connect to +3.3 V or +5 V. Must be same as other VDDs.
3
X1/ICLK
VDD
4
5
SELB1
GND
I(Pu) Select pin for CLK B. See table 2.
6
P
O
O
O
O
Connect to ground.
7
CLKB
CLKC
CLKA5
25M
Selectable clock output. See Table 2.
Selectable clock output. See Table 3.
Selectable clock output. See Table 1.
25.0 MHz clock output.
8
9
10
11
12
13
14
15
16
17
18
19
20
OE
I(Pu) Output Enable. Tri-states all output clocks when low. Internal pull-up.
CLKA1
CLKA4
GND
O
O
Selectable clock output. See Table 1.
Selectable clock output. See Table 1.
P
Connect to ground.
SELA1
VDD
T I
P
Select pin for CLKA1:4 and CLKA5 outputs. See Table 1.
Connect to +3.3V or +5.0V. Must be same as other VDDs.
Selectable clock output. See Table 1.
CLKA3
CLKA2
SELA0
SELC
O
O
Selectable clock output. See Table 1.
T I
T I
Select pin for CLKA1:4 and CLKA5 outputs. See Table 1.
Select pin for CLKC output. See Table 3.
Key: XI, XO = crystal connections; I = Input; I(Pu) = Input with pull up O = Output; P = power supply connection; TI = tri level input
MDS 650-14B A
2
Revision 082800
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel• www.icst.com
PRELIMINARY INFORMATION
ICS650-14B
Networking System Clock
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
VDD+0.5
70
V
V
Inputs and Clock Outputs
Ambient Operating Temperature
Ambient Operating Temperature
Soldering Temperature
Referenced to GND
-0.5
0
°C
°C
°C
°C
Industrial "I" version
Max of 20 seconds
-40
85
260
Storage temperature
-65
150
DC CHARACTERISTICS (VDD = 3.3V unless noted)
Operating Voltage, VDD
3
5.5
VDD/2 - 1
0.5
V
V
Input High Voltage, VIH, X1 pin only
Input Low Voltage, VIL, X1 pin only
Input High Voltage, VIH, SEL pins only
Input Low Voltage, VIL, SEL pins only
Input High Voltage, VIH, OE pin only
Input Low Voltage, VIL, OE pin only
Output High Voltage, VOH
Clock Input
Clock Input
VDD/2 + 1
V
VDD - 0.5
2.0
V
V
V
0.8
V
IOH=-12mA
IOL=12mA
IOH=-8mA
No Load
2.4
V
Output Low Voltage, VOL
0.4
V
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD
Short Circuit Current
VDD-0.4
V
TBD
±50
mA
mA
Each output
AC CHARACTERISTICS (VDD = 3.3V unless noted)
Input Frequency
25.000
MH z
ns
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Frequency error
0.8 to 2.0V
1.5
1.5
55
0
2.0 to 0.8V
ns
At VDD/2
45
50
%
All clocks
ppm
ps
Absolute Jitter, short term
Variation from mean
TBD
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. CMOS level input, nominal trip point is VDD/2 for 3.3 V or 5 V operation.
External Components
The ICS650R-14B requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between each VDD and GND on Pins 4 and 6, and Pins 16 and
14, as close to the ICS650R-14B as possible. A series termination resistor of 33 Ω may be used for each
clock output. The 25.00 MHz crystal must be connected as close to the chip as possible. The crystal should
be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these
capacitors is given by the following equation, where C is the crystal load capacitance: Crystal caps (pF) =
L
(C -6) x 2. So for a crystal with 16 pF load capacitance, two 20 pF caps should be used.
L
MDS 650-14B A
3
Revision 082800
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel• www.icst.com
PRELIMINARY INFORMATION
ICS650-14B
Networking System Clock
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
20 pin SSOP
Inches
Symbol Min
Millimeters
Max
Min
1.35
0.10
0.20
0.18
8.55
Max
A
A1
b
0.053 0.069
0.004 0.010
0.008 0.012
0.007 0.010
0.337 0.344
.025 BSC
1.75
0.25
0.30
0.25
8.75
E1
E
c
D
e
INDEX
AREA
0.635 BSC
1
2
E
0.228 0.244
0.150 0.157
0.016 0.050
5.80
3.80
0.40
6.20
E1
L
4.00
1.27
D
A
A1
c
b
L
e
Ordering Information for ICS650-14B
Part/Order Number
ICS650R-14
Marking
Shipping packaging
tubes
Package
Temperature
0 to +70 °C
ICS650R-14
ICS650R-14
ICS650R-14I
ICS650R-14I
20 pin SSOP
20 pin SSOP
20 pin SSOP
20 pin SSOP
ICS650R-14T
ICS650R-14I
tape and reel
tubes
0 to +70 °C
-40 to +85 °C
-40 to +85 °C
ICS650R-14I
tape and reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc (ICS) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental
requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize
or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 650-14B A
4
Revision 082800
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel• www.icst.com
相关型号:
ICS650R-21ILF
Processor Specific Clock Generator, 100MHz, CMOS, PDSO20, 0.150 INCH, ROHS COMPLIANT, SSOP-20
IDT
ICS650R-21ILFT
Processor Specific Clock Generator, 100MHz, CMOS, PDSO20, 0.150 INCH, ROHS COMPLIANT, SSOP-20
IDT
ICS650R-21LF
Processor Specific Clock Generator, 100MHz, CMOS, PDSO20, 0.150 INCH, ROHS COMPLIANT, SSOP-20
IDT
©2020 ICPDF网 联系我们和版权申明