ICS83947AI147 [ICSI]
LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER; 低偏移， 1到9 LVCMOS / LVTTL扇出缓冲器
| 型号： | ICS83947AI147 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER |
| 文件： | 总10页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-9
LVCMOS/LVTTL FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83947I-147 is a low skew, 1-to-9
• 9 LVCMOS/LVTTL outputs
ICS
LVCMOS/LVTTL Fanout Buffer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50Ω
• Selectable CLK0 and CLK1 can accept the following
input levels:LVCMOS and LVTTL
HiPerClockS™
• Maximum output frequency: 250MHz
• Output skew: 115ps (maximum)
series or parallel terminated transmission lines. The effective
fanout can be increased from 9 to 18 by utilizing the ability of
the outputs to drive two series terminated lines.
• Part-to-part skew: 500ps (maximum)
• Additive phase jitter, RMS: 0.02ps (typical) @ 3.3V
• Full 3.3V or 2.5V operating supply
Guaranteed output and part-to-part skew characteristics make
the ICS83947I-147 ideal for high performance, 3.3V or 2.5V
single ended applications.
• -40°C to 85°C ambient operating temperature
• Pin compatible with the MPC947
BLOCK DIAGRAM
PIN ASSIGNMENT
D
CLK_EN
Q
LE
32 31 30 29 28 27 26 25
0
1
CLK0
CLK1
GND
Q3
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
CLK_SEL
CLK0
Q0
VDDO
Q4
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CLK1
CLK_SEL
ICS83947I-147
GND
Q5
CLK_EN
OE
VDDO
GND
VDD
GND
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
TopView
OE
83947AYI-147
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REV. A SEPTEMBER 24, 2004
1
ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-9
LVCMOS/LVTTL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Power
Input Pullup
Description
Power supply ground.
1, 8, 9, 12, 16, 17,
20, 24, 25, 29, 32
GND
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
2
CLK_SEL
3, 4
CLK0, CLK1
CLK_EN
OE
Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels.
Input Pullup Clock enable. LVCMOS / LVTTL interface levels.
Input Pullup Output enable. LVCMOS / LVTTL interface levels.
5
6
7
VDD
Power
Power
Core supply pin.
10, 14, 18, 22, 27, 31
VDDO
Output supply pins.
11, 13, 15, 19, 21,
23, 26, 28, 30
Q8, Q7, Q6, Q5,
Q4, Q3, Q2, Q1, Q0
Q0 thru Q8 clock outputs.
LVCMOS / LVTTL interface levels.
Output
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
12
pF
RPULLUP
ROUT
Input Pullup Resistor
Output Impedance
51
7
KΩ
Ω
TABLE 3. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE
Control Inputs
Output
Q0:Q8
OE
0
CLK_EN
X
0
1
Hi-Z
1
LOW
1
Follows CLK input
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REV. A SEPTEMBER 24, 2004
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ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-9
LVCMOS/LVTTL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.0
Typical
3.3
Maximum Units
3.6
2.625
3.6
V
V
VDD
Core Supply Voltage
2.375
3.0
2.5
3.3
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
50
V
IDD
Input Supply Current
Output Supply Current
mA
mA
IDDO
9
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
CLK0, CLK1, OE,
CLK_SEL, CLK_EN
2
3.6
0.8
V
V
IIN
Input Current
-100
2.5
µA
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
IOH = -20mA
IOL = 20mA
V
V
0.4
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section, 3.3V Output Load Test
Circuit Diagram.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
Input High Voltage
2
VDD + 0.3
1.3
V
V
V
CLK0, CLK1
-0.3
-0.3
VIL
Input Low Voltage
Input High Current
Input Low Current
CLK_SEL, CLK_EN, OE
0.8
CLK0, CLK1, OE,
CLK_SEL, CLK_EN
IIH
IIL
V
DD = VIN = 2.625V
5
µA
µA
V
DD = 32.625V,
VIN = 0V
CLK0, CLK1, OE,
CLK_SEL, CLK_EN
-150
1.8
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section, 2.5V Output Load Test
Circuit Diagram.
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REV. A SEPTEMBER 24, 2004
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ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT
BUFFER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum
250
Units
MHz
ns
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 5
f ≤ 250MHZ
Measured on
rising edge @VDDO/2
2
4.2
tsk(o)
115
500
ps
ps
Measured on
rising edge @VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
tjit(Ø)
(12KHz to 20MHz)
ps
0.2
tR / tF
tPW
odc
tEN
Output Rise/Fall Time
0.8V to 2.0V
f > 133MHz
f ≤ 133MHz
0.2
tPeriod/2 - 1
40
1
tPeriod/2 + 1
60
ns
ns
ꢀ
Output Pulse Width
Output Duty Cycle
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
Clock Enable Setup Time
Clock Enable Hold Time
10
ns
ns
ns
ns
tDIS
tS
10
0
1
tS
All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum
250
Units
MHz
ns
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 5
f ≤ 250MHZ
Measured on
rising edge @VDDO/2
2.4
4.5
tsk(o)
130
600
ps
ps
Measured on
rising edge @VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
tjit(Ø)
(12KHz to 20MHz)
20ꢀ - 80ꢀ
0.1
ps
tR / tF
tPW
tEN
tDIS
tS
Output Rise/Fall Time
300
800
tPeriod/2 + 1.2
10
ps
ns
ns
ns
ns
ns
Output Pulse Width
tPeriod/2 - 1.2
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
Clock Enable Setup Time
Clock Enable Hold Time
10
0
1
tS
All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A SEPTEMBER 24, 2004
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ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-9
LVCMOS/LVTTL FANOUT
BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
Additive Phase Jitter, RMS @
156.25MHz (12KHz to 20MHz)
= 0.02ps typical @ 3.3V
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
0
-10
-20
-30
-40
Additive Phase Jitter, RMS @
156.25MHz (12KHz to 20MHz)
= 0.01ps typical @ 2.5V
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
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REV. A SEPTEMBER 24, 2004
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ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-9
LVCMOS/LVTTL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 0.15V
1.25V 5ꢀ
SCOPE
SCOPE
VDD
,
VDD
,
VDDO
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 0.15V
-1.25V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
PART 1
VDDO
VDDO
Qx
2
Qx
2
PART 2
VDDO
VDDO
Qy
Qy
2
2
tsk(o)
tsk(pp)
PART-TO-PART SKEW
VDD
OUTPUT SKEW
VDDO
2
VDDO
2
VDDO
2
Q0:Q8
2
CLK0,CLK1
tPW
tPERIOD
VDDO
2
Q0:Q8
tPW
tPERIOD
t
odc =
PD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY
80ꢀ
80ꢀ
tR
2V
2V
20ꢀ
20ꢀ
0.8V
0.8V
Clock
Outputs
Clock
tF
tR
tF
Outputs
3.3V OUTPUT RISE/FALL TIME
2.5V OUTPUT RISE/FALL TIME
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REV. A SEPTEMBER 24, 2004
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ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-9
LVCMOS/LVTTL FANOUT
BUFFER
APPLICATION SCHEMATIC EXAMPLE
Figure 1 shows an example of ICS83947I-147 application sche- For the LVCMOS output drivers, only one termination example
matic. In this example, the device is operated at VCC=3.3V.The is shown in this schematic. Additional termination approaches
are shown in the LVCMOS Termination Application Note (refer
decoupling capacitors should be located as close as possible
to the power pin.The input is driven by a 3.3V LVCMOS driver. to ICS website).
VDDO
R1
43
Zo = 50
VCC
R3
43
Zo = 50 Ohm
U1
ICS83947I-147
LVCMOS
1
2
3
4
5
6
7
8
24
GND
GND
23
CLK_SEL
CLK0
CLK1
CLK_EN
OE
VDD
GND
Q3
22
VCC
VDDO
21
Q4
20
GND
19
Q5
18
R3
43
Zo = 50 Ohm
VDDO
17
GND
VDD
LVCMOS
C5
0.1u
VDD=3.3V
VDDO=3.3V
VDDO
(U1-10) (U1-14)
(U1-18)
(U1-22)
(U1-27)
(U1-31)
R2
43
Zo = 50
C1
0.1u
C2
0.1u
C3
0.1u
C4
0.1u
C2
0.1u
C3
0.1u
FIGURE 1. ICS83947I-147 SCHEMATIC LAYOUT
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REV. A SEPTEMBER 24, 2004
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ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-9
LVCMOS/LVTTL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83947I-147 is: 1040
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REV. A SEPTEMBER 24, 2004
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ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-9
LVCMOS/LVTTL FANOUT
BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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REV. A SEPTEMBER 24, 2004
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ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-9
LVCMOS/LVTTL FANOUT
BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS83947AYI-147
ICS83947AYI-147T
Marking
Package
32 Lead LQFP
Count
250 per tray -40°C to 85°C
1000 -40°C to 85°C
Temperature
ICS83947AI147
ICS83947AI147
32 Lead LQFP on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV. A SEPTEMBER 24, 2004
10
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