ICS83948AYILFT [ICSI]
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER; 低偏移， 1到12差分至LVCMOS扇出缓冲器
| 型号： | ICS83948AYILFT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER |
| 文件： | 总10页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS83948I is a low skew, 1-to-12 Differen-
• Twelve LVCMOS outputs
ICS
tial-to-LVCMOS Fanout Buffer and a member
of the HiPerClockS™ f a m ily of High Performance
Clock Solutions from ICS. The ICS83948I has
two selectable clock inputs. The CLK, nCLK
• Selectable LVCMOS clock or differential CLK, nCLK inputs
HiPerClockS™
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
pair can accept most standard differential input levels. The
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS outputs are designed to drive
50Ω series or parallel terminated transmission lines. The
effective fanout can be increased from 12 to 24 by utilizing
the ability of the outputs to drive two series terminated lines.
• LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 250MHz
• Output skew: 350ps (maximum)
• Part to part skew: 1.5ns (maximum)
• 3.3V core, 3.3V output
The ICS83948I is characterized at 3.3V core/3.3V output.
Guaranteed output and part-to-part skew characteristics
make the ICS83948I ideal for those clock distribution ap-
plications demanding well defined performance and re-
peatability.
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
D
CLK_EN
Q
LE
32 31 30 29 28 27 26 25
LVCMOS_CLK
1
0
GND
Q4
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CLK_SEL
LVCMOS_CLK
CLK
Q0
CLK
nCLK
VDDO
Q5
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
nCLK
CLK_SEL
ICS83948I
GND
Q6
CLK_EN
OE
VDDO
Q7
VDD
GND
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
TopView
OE
83948AYI
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REV.C DECEMBER 15, 2005
1
ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
Clock select input. Selects LVCMOS clock input
when HIGH. Selects CLK, nCLK inputs when LOW.
LVCMOS / LVTTL interface levels.
1
CLK_SEL
Input
Pullup
2
3
4
5
6
7
LVCMOS_CLK
CLK
Input
Input
Input
Input
Input
Power
Pullup
Pullup
Clock input. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
nCLK
Pulldown Inverting differential clock input.
CLK_EN
OE
Pullup
Pullup
Clock enable. LVCMOS / LVTTL interface levels.
Output enable. LVCMOS / LVTTL interface levels.
Positive supply pin.
VDD
8, 12, 16,
20, 24, 28, 32
GND
Power
Power supply ground.
9, 11, 13, 15,
17, 19, 21, 23
25, 27, 29, 31
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Output
Power
Clock outputs. LVCMOS / LVTTL interface levels.
Output supply pins.
10, 14, 18, 22, 26, 30
VDDO
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
25
pF
RPULLUP
Input Pullup Resistor
51
51
7
kΩ
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
CLK, nCLK
Selected
LVCMOS_CLK
De-selected
Selected
0
1
De-selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK_SEL LVCMOS_CLK
CLK
nCLK
Q0:Q12
LOW
0
0
0
0
0
0
1
1
—
—
—
—
—
—
0
0
1
Differential to Single Ended
Differential to Single Ended
Non Inverting
Non Inverting
1
0
HIGH
LOW
0
Biased; NOTE 1
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
Biased; NOTE 1
HIGH
HIGH
LOW
Biased; NOTE 1
0
1
Single Ended to Single Ended
Single Ended to Single Ended
Inverting
Inverting
Biased; NOTE 1
—
—
—
—
LOW
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
HIGH
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = -40° TO 85°
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Positive Supply Voltage
3.0
3.0
3.3
3.3
3.6
3.6
55
V
V
Output Supply Voltage
Power Supply Current
mA
TABLE 4B. DC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum
2
Typical Maximum Units
VIH
VIL
Input High Voltage
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
VPP
VCMR
IIN
Peak-to-Peak Input Voltage
Input Common Mode Voltage; NOTE 1, 2
Input Current
0.15
1.3
V
GND + 0.5
VDD - 0.85
100
V
µA
V
VOH
VOL
Output High Voltage
IOH = -20mA
IOL = 20mA
2.5
Output Low Voltage
0.4
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = -40° TO 85°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
CLK, nCLK;
NOTE 1A
LVCMOS_CLK;
NOTE 1B
f ≤ 150MHz
f ≤ 150MHz
2.25
2
3.75
4
ns
ns
tPD
Propagation Delay
Measured on
rising edge @VDDO/2
tsk(o)
Output Skew; NOTE 2, 6
350
ps
CLK, nCLK
LVCMOS_CLK
1.5
ns
ns
ns
ns
ps
ns
ns
Part-to-Part Skew;
NOTE 3, 6
Measured on
rising edge @VDDO/2
tsk(pp)
2
tR
Output Rise Time
Output Fall Time
Output Pulse Width
0.8V to 2V
0.8V to 2V
f < 150MHz
0.2
0.2
1.0
tF
1.0
tPW
tCycle/2 - 800
tCycle/2 + 800
tPZL, tPZH Output Disable Time; NOTE 4
11
11
t
PLZ, tPHZ Output Enable Time; NOTE 4
CLK_EN to
1
0
1
1
ns
ns
ns
ns
Clock Enable
Setup Time;
NOTE 5
CLK, nCLK
CLK_EN to
LVCMOS_CLK
CLK, nCLK to
CLK_EN
tS
Clock Enable
Hold Time;
NOTE 5
tH
LVCMOS_CLK
to CLK_EN
NOTE 1A: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 1B: Measured from the VDD/2 or crosspoint of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
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ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.65V 0.15V
VDD
SCOPE
VDD,
VDDO
nCLK
CLK
Qx
VPP
VCMR
Cross Points
LVCMOS
GND
GND = -1.65V 0.15V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
VDDO
2
PART 1
Qx
VDDO
Qx
2
PART 2
Qy
VDDO
VDDO
Qy
2
2
tsk(o)
tsk(pp)
PART-TO-PART SKEW
OUTPUT SKEW
2V
2V
VDDO
2
0.8V
0.8V
Clock
Outputs
LVCMOS_
tR
tF
CLK
nCLK
CLK
OUTPUT RISE/FALL TIME
VDDO
2
VDDO
2
VDDO
VDDO
Q0:Q11
2
2
Q0:Q11
tPW
➤
tPD
➤
tPERIOD
tPW
tPERIOD
odc =
PROPAGATION DELAY
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV.C DECEMBER 15, 2005
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ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CLK INPUT:
OUTPUTS:
LVCMOS OUTPUT:
For applications not requiring the use of a clock input, it can All unused LVCMOS output can be left floating. We
be left floating. Though not required, but for additional recommend that there is no trace attached.
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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REV.C DECEMBER 15, 2005
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ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOWTABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83948I is: 1040
Pin compatible with the MPC948/948L
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REV.C DECEMBER 15, 2005
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ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE -Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
REFERENCE DOCUMENT:JEDEC PUBLICATION 95, MS-026
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REV.C DECEMBER 15, 2005
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ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS83948AYI
ICS83948AYIT
ICS83948AYILF
ICS83948AYILFT
ICS83948AYI
ICS83948AYI
ICS83948AYIL
ICS83948AYIL
32 Lead LQFP
tray
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
32 Lead LQFP
1000 tape & reel
tray
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQFP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
83948AYI
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REV.C DECEMBER 15, 2005
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ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
T5
4
AC Characteristics table - tLZ, tHZ row changed symbol to read tPLZ, tPHZ and
changed Parameter to read Output Enable Time.
B
05/20/02
Added rows: tS "Clock Enable Setup Time" and tH "Clock Enable Hold Time".
T5
4
4
AC Characteristics table, tS and tH rows - replaced SYNC_OE with CLK_EN.
Added an extra note to Propagation Delay row.
B
6/26/02
B
B
T5
T5
AC Characteristics table, fMAX row corrected typo error of 150MHz to 250MHz.
8/8/02
4
1
2
6
AC Characteristics table - tPW row, added f< 150MHz for tPW Test Conditions.
Features Section - added Lead-Free bullet.
11/11/02
T2
T8
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
Added Recommendations for Unused Output Pins.
C
12/15/05
Ordering Information Table - added Lead-Free part number, marking and note.
9
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REV.C DECEMBER 15, 2005
10
相关型号：
ICS83948AYLF
Low Skew Clock Driver, 12 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
IDT
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