ICS83948AYLF [IDT]
Low Skew Clock Driver, 12 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32;
| 型号： | ICS83948AYLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 12 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总11页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS83948
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83948 is a low skew, 1-to-12 Differen-
• 12 LVCMOS outputs
tial-to-LVCMOS Fanout Buffer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS83948 has
two selectable clock inputs. The CLK, nCLK pair
• Selectable LVCMOS clock or differential CLK, nCLK inputs
HiPerClockS™
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
can accept most standard differential input levels. The
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS outputs are designed to drive
50Ω series or parallel terminated transmission lines. The
effective fanout can be increased from 12 to 24 by utilizing
the ability of the outputs to drive two series terminated lines.
• LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
• Maximum output frequency up to 250MHz
• Output skew: 350ps (maximum)
• Part to part skew: 1.5ns (maximum)
• 3.3V core, 3.3V output
The ICS83948 is characterized at 3.3V core/3.3V output.
Guaranteed output and part-to-part skew characteristics
make the ICS83948 ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Pin compatible with the MPC948/948L
BLOCK DIAGRAM
PIN ASSIGNMENT
D
CLK_EN
Q
LE
32 31 30 29 28 27 26 25
LVCMOS_CLK
1
0
GND
Q4
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
CLK_SEL
LVCMOS_CLK
CLK
Q0
CLK
nCLK
VDDO
Q5
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
nCLK
CLK_SEL
ICS83948
GND
Q6
CLK_EN
OE
VDDO
Q7
VDD
GND
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
OE
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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REV. A JANUARY 7, 2002
1
PRELIMINARY
ICS83948
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pullup
Pullup
Pullup
Description
Clock select input. Selects LVCMOS clock input when
HIGH. Selects CLK, nCLK inputs when LOW.
1
CLK_SEL
Input
2
3
4
5
6
7
LVCMOS_CLK
CLK
Input
Input
Clock input. LVCMOS interface levels.
Non-inverting differential clock input.
nCLK
Input Pulldown Inverting differential clock input.
CLK_EN
OE
Input
Input
Pullup
Pullup
Clock enable.
Output enable.
VDD
Power
Positive supply pins. Connect to 3.3V.
8, 12, 16,
20, 24, 28, 32
9, 11, 13, 15,
17, 19, 21, 23
25, 27, 29, 31
10, 14, 18,
GND
Power
Output
Power
Power supply ground. Connect to ground.
Clock outputs. LVCMOS interface levels.
Output supply pins. Connect to 3.3V.
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
VDDO
22, 26, 30
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
VDD, VDDO = 3.6V
pF
RPULLUP
Input Pullup Resistor
51
51
7
KΩ
KΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
CLK, nCLK
Selected
LVCMOS_CLK
De-selected
Selected
0
1
De-selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
Q0 thru
Q12
CLK-SEL LVCMOS_CLK
CLK
nCLK
0
0
0
0
0
0
1
1
—
—
—
—
—
—
0
0
1
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
Differential to Single Ended
Differential to Single Ended
Non Inverting
Non Inverting
1
0
0
Biased; NOTE 1
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
Biased; NOTE 1
Biased; NOTE 1
0
1
Single Ended to Single Ended
Single Ended to Single Ended
Inverting
Inverting
Biased; NOTE 1
—
—
—
—
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
NOTE 1: Please refer to the Application Information section on page 10, Figure 8, which discusses wiring the differential
input to accept single ended levels.
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REV. A JANUARY 7, 2002
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PRELIMINARY
ICS83948
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, Tstg -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
TABLE 4A. DC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
IDD
Input Supply Voltage
3.0
3.0
3.3
3.3
33
8
3.6
3.6
V
Output Supply Voltage
Input Supply Current
Output Supply Current
V
mA
mA
IDDO
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
LVCMOS_CLK
2
V
DD + 0.3
DD + 0.3
1.3
V
V
V
V
VIH
VIL
Input High Voltage
CLK_SEL, CLK_EN, OE
LVCMOS_CLK
2
V
-0.3
-0.3
Input Low Voltage
CLK_SEL, CLK_EN, OE
0.8
LVCMOS_CLK, OE,
CLK_SEL, CLK_EN
IIH
IIL
Input High Current
Input Low Current
VDD = VIN = 3.6V
5
µA
µA
LVCMOS_CLK, OE,
CLK_SEL, CLK_EN
V
DD = 3.6V, VIN = 0V
-150
2.5
VOH
VOL
Output High Voltage
Output Low Voltage
IOH = -20mA
IOL = 20mA
V
V
0.4
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PRELIMINARY
ICS83948
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = 0° TO 70°
Symbol Parameter
IIH Input High Current
Test Conditions
DD = VIN = 3.6V
Minimum Typical Maximum Units
nCLK
CLK
V
150
5
µA
µA
µA
µA
V
VDD = VIN = 3.6V
nCLK
CLK
V
DD = 3.6V, VIN = 0V
-5
IIL
Input Low Current
VDD = 3.6V, VIN = 0V
-150
0.15
VPP
Peak-to-Peak Input Voltage
1.3
Input Common Mode Voltage;
NOTE 1, 2
VCMR
GND + 0.5
VDD - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = 0° TO 70°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
CLK, nCLK;
NOTE 1
LVCMOS_CLK;
NOTE 2
f ≤ 250MHz
f ≤ 250MHz
2.6
2.6
ns
ns
Propagation Delay;
tpLH
Measured on
rising edge @VDDO/2
tsk(o)
Output Skew; NOTE 3, 6
350
1.5
ps
ns
Measured on
rising edge @VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 4, 6
tR
Output Rise Time
0.8V to 2V
0.8V to 2V
0.2
0.2
1.0
ps
ps
ps
ns
ns
ns
ns
tF
Output Fall Time
1.0
tPW
tEN
tDIS
tS
Output Pulse Width
tCycle/2 - 800
tCycle/2 + 800
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
Clock Enable Setup Time
Clock Enable Hold Time
11
11
TBD
TBD
tS
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A JANUARY 7, 2002
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PRELIMINARY
ICS83948
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 0.15V
SCOPE
VDD,
VDDO
Qx
LVCMOS
GND
-1.65V 0.15V
FIGURE 1 - 3.3V OUTPUT LOAD TEST CIRCUIT
VDD
nCLK
CLK
VPP
VCMR
Cross Points
GND
FIGURE 2 - DIFFERENTIAL INPUT LEVEL
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PRELIMINARY
ICS83948
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
VDDO
2
Qx
Qy
VDDO
2
tsk(o)
FIGURE 3 - OUTPUT SKEW
PART 1
Qx
VDDO
2
VDDO
PART 2
Qy
2
tsk(pp)
FIGURE 4 - PART-TO-PART SKEW
2.0V
2.0V
VSWING
0.8V
0.8V
Clock Inputs
and Outputs
tR
tF
FIGURE 5 - INPUT AND OUTPUT RISE AND FALL TIME
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REV. A JANUARY 7, 2002
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PRELIMINARY
ICS83948
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
VDD
2
CLK
nCLK
LVCMOS_CLK
VDDO
2
Q0 - Q11
➤
tPD
➤
FIGURE 6 - PROPAGATION DELAY
VDDO
2
VDDO
2
VDDO
2
Q0 - Q11
tPW
tPERIOD
tPW
odc =
tPERIOD
FIGURE 7 - tPW & tPERIOD
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REV. A JANUARY 7, 2002
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PRELIMINARY
ICS83948
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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PRELIMINARY
ICS83948
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83948 is: 1040
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PRELIMINARY
ICS83948
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-026
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REV. A JANUARY 7, 2002
PRELIMINARY
ICS83948
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS83948AY
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS83948AY
ICS83948AY
ICS83948AYT
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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11
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