ICS840021AGIT [ICSI]
FEMTOCLOCKS? CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER; FEMTOCLOCKS⑩ CRYSTAL -TO LVCMOS / LVTTL频率合成器
| 型号： | ICS840021AGIT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER |
| 文件： | 总11页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS840021I
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS840021I is a Gigabit Ethernet Clock • 1 LVCMOS/LVTTL output, 15Ω output impedence
ICS
Generator and a member of the HiPerClocksTM
• Crystal oscillator interface designed for 25MHz,
family of high performance devices from ICS.The
18pF parallel resonant crystal
HiPerClockS™
ICS840021I uses a 25MHz crystal to synthesize
125MHz. The ICS840021I has excellent phase
• Output frequency: 125MHz
jitter performance, over the 1.875MHz – 20MHz integration
range. The ICS840021I is packaged in a small 8-pin TSSOP,
making it ideal for use in systems with limited board space.
• VCO range: 560MHz to 680MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.48ps (typical) (3.3V)
Offset
Noise Power
100Hz ............... -97.8 dBc/Hz
1kHz ..............-124.6 dBc/Hz
10kHz ..............-132.5 dBc/Hz
100kHz ..............-131.1 dBc/Hz
• Voltage supply modes:
VDD/VDDA = 3.3V
VDD/VDDA = 2.5V
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
OE
VDDA
OE
VDD
Q0
1
2
3
4
8
7
6
5
25MHz
XTAL_IN
XTAL_OUT
XTAL_IN
GND
nc
Phase
Detector
Q0
÷5
OSC
VCO
XTAL_OUT
ICS840021I
÷25
(fixed)
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
TopView
840021AGI
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REV. A MAY 19, 2005
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ICS840021I
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VDDA
Power
Input
Analog supply pin.
Output enable pin. When HIGH, Q0 output is enabled.
When LOW, forces Q0 to HiZ state. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
2
OE
Pullup
XTAL_OUT,
XTAL_IN
3, 4
Input
5
6
nc
Unused
Power
No connect.
GND
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
15Ω output impedence.
Core supply pin.
7
8
Q0
Output
Power
VDD
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
CIN
Input Capacitance
4
7
pF
pF
pF
kΩ
Ω
VDD, VDDA = 3.465V
VDD, VDDA = 2.625V
CPD
Power Dissipation Capacitance
7
RPULLUP
ROUT
Input Pullup Resistor
Output Impedance
51
15
TABLE 3. CONTROL FUNCTION TABLE
Control Inputs
Output
Q0
OE
0
Hi-Z
1
Active
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ICS840021I
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
101.7°C/W (0 mps)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
3.465
3.465
65
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
V
mA
mA
IDDA
10
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
2.625
2.625
60
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
2.375
2.5
V
mA
mA
IDDA
10
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
DD = 3.3V
VDD = 2.5V
DD = 3.3V
V
2
VDD + 0.3
VDD + 0.3
0.8
V
V
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
V
V
Input Low Voltage
VDD = 2.5V
0.7
V
IIH
IIL
Input High Current OE
Input Low Current OE
VDD = VIN = 3.465V or 2.625V
VDD = 3.465V or 2.625V, VIN = 0V
5
µA
µA
V
-150
2.6
V
DD = 3.465V
VOH
Output High Voltage; NOTE 1
VDD = 2.625V
1.8
V
VOL
Output Low Voltage; NOTE 1
VDD = 3.465V or 2.625V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section,
"Output Load Test Circuit" diagrams.
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ICS840021I
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
25
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
125
MHz
RMS Phase Jitter
(Random); NOTE 1
tjit(Ø)
Integration Range: 1.875MHz to 20MHz
20ꢀ to 80ꢀ
0.48
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
48
500
52
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plot.
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
125
MHz
RMS Phase Jitter
(Random); NOTE 1
tjit(Ø)
Integration Range: 1.875MHz to 20MHz
20ꢀ to 80ꢀ
0.50
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
250
48
550
52
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plot.
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ICS840021I
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TYPICAL PHASE NOISE AT 125MHZ (3.3V OR 2.5V)
0
-10
-20
-30
-40
Gigabit Ethernet Filter
125MHz
RMS Phase Jitter (Random)
-50
-60
1.875MHz to 20MHz (3.3V) = 0.48ps (typical)
1.875MHz to 20MHz (2.5V) = 0.50ps (typical)
-70
-80
-90
-100
-110
-120
-130
-140
Raw Phase Noise Data
-150
-160
-170
-180
Phase Noise Result by adding
Gigabit Ethernet Filter to raw data
-190
100
1k
10k
100k
OFFSET FREQUENCY (HZ)
1M
10M
100M
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REV. A MAY 19, 2005
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ICS840021I
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.25V 5ꢀ
1.65V 5ꢀ
SCOPE
SCOPE
VDD,
VDDA
VDD,
VDDA
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-1.25V 5ꢀ
-1.65V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
80ꢀ
tF
80ꢀ
Phase Noise Mask
20ꢀ
20ꢀ
Clock
Outputs
tR
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
VDD
2
Q0
tPW
tPERIOD
tPW
x 100ꢀ
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
840021AGI
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REV. A MAY 19, 2005
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ICS840021I
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise.The ICS840021I provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL.VDD andVDDA should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required. Figure 1
illustrates how a 10Ω resistor along with a 10μF and a .01μF
bypass capacitor should be connected to each VDDA pin.
3.3V or 2.5V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840021I has been characterized with 18pF parallel resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
XTAL_OUT
XTAL_IN
C1
33p
X1
18pF Parallel Crystal
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
840021AGI
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ICS840021I
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
APPLICATION SCHEMATIC
Figure 3A shows a schematic example of the ICS840021I. An output frequency. The C1 = 22pF and C2 = 33pF are recom-
mended for frequency accuracy. For different board layout, the
C1 and C2 values may be slightly adjusted for optimizing fre-
quency accuracy.
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note.In this example, an 18pF
parallel resonant 25MHz crystal is used for generating 125MHz
VDD
VDDA
R2
10
C3
C4
10uF
0.1u
U1
R3
VDD
Q
1
8
7
6
5
33
Zo = 50 Ohm
VDDA
OE
XTAL_OUT
XTAL_IN
VDD
Q0
GND
NC
OE
2
3
4
C2
33pF
X1
C5
0.1u
LVCMOS
ICS840021i
C1
22pF
VDD=3.3V
FIGURE 3A. ICS840021I SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of ICS840021I P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age.The footprints of other components in this example are listed
in the Table 7.There should be at least one decoupling capacitor
per power pin.The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 7. FOOTPRINT TABLE
Reference
C1, C2
C3
Size
0402
0805
0603
0603
C4, C5
R2, R3
NOTE: Table 7, lists component
sizes shown in this layout example.
FIGURE 3B. ICS840021I PC BOARD LAYOUT EXAMPLE
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ICS840021I
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TRANSISTOR COUNT
The transistor count for ICS840021I is: 1961
840021AGI
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REV. A MAY 19, 2005
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ICS840021I
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
840021AGI
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REV. A MAY 19, 2005
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ICS840021I
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS840021AGI
Marking
021AI
021AI
TBD
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
8 lead TSSOP
ICS840021AGIT
ICS840021AGILF
ICS840021AGILFT
8 lead TSSOP
2500 tape & reel
tube
8 lead "Lead-Free" TSSOP
8 lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV. A MAY 19, 2005
11
相关型号：
ICS840024AGILFT
Clock Generator, 125MHz, PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20
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