ICS840021 [ICSI]
FEMTOCLOCKS? CRYSTAL-TO-LVCMOS/ LVTTL CLOCK GENERATOR; FEMTOCLOCKS ？ CRYSTAL - TO- LVCMOS / LVTTL时钟发生器
| 型号： | ICS840021 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO-LVCMOS/ LVTTL CLOCK GENERATOR |
| 文件： | 总11页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS840021
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS840021 is a Gigabit Ethernet Clock • 1 LVCMOS/LVTTL output, 7Ω output impedence
ICS
Generator and a member of the HiPerClocksTM
• Crystal oscillator interface designed for 25MHz,
family of high performance devices from ICS.The
18pF parallel resonant crystal
HiPerClockS™
ICS840021 uses a 25MHz crystal to synthesize
125MHz.The ICS840021 has excellent phase jitter
• Output frequency: 125MHz
performance, over the 1.875MHz – 20MHz integration range.
The ICS840021 is packaged in a small 8-pin TSSOP, making it
ideal for use in systems with limited board space.
• VCO range: 560MHz to 680MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.34ps (typical)
• RMS phase noise at 125MHz (typical)
Phase noise:
Offset
Noise Power
100Hz ............... -96.9 dBc/Hz
1KHz ..............-122.2 dBc/Hz
10KHz ..............-131.1 dBc/Hz
100KHz ..............-129.5 dBc/Hz
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
OE
VDDA
OE
VDD
Q0
1
2
3
4
8
7
6
5
25MHz
XTAL_IN
XTAL_OUT
XTAL_IN
GND
nc
Phase
Detector
Q0
÷5
OSC
VCO
XTAL_OUT
ICS840021
÷25
(fixed)
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
TopView
840021AG
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REV. A NOVEMBER 30, 2004
1
ICS840021
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VDDA
Power
Input
Analog supply pin.
Output enable pin. When HIGH, Q0 output is enabled.
2
OE
Pullup
When LOW, forces Q0 to HiZ state. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
XTAL_OUT,
XTAL_IN
3, 4
Input
5
6
nc
Unused
Power
No connect.
GND
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
7Ω output impedence.
Core supply pin.
7
8
Q0
Output
Power
VDD
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
CIN
Input Capacitance
4
24
51
7
pF
pF
KΩ
Ω
CPD
Power Dissipation Capacitance
Input Pullup Resistor
VDD, VDDA = 3.465V
RPULLUP
ROUT
Output Impedance
5
12
TABLE 3. CONTROL FUNCTION TABLE
Control Inputs
Output
Q0
OE
0
Hi-Z
1
Active
840021AG
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REV. A NOVEMBER 30, 2004
2
ICS840021
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
101.7°C/W (0 mps)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
3.465
3.465
75
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
V
mA
mA
IDDA
15
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VDD + 0.3
V
V
Input Low Voltage
-0.3
0.8
5
Input High Current OE
Input Low Current OE
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDD = VIN = 3.465V
µA
µA
V
IIL
VDD = 3.465V, VIN = 0V
-150
2.6
VOH
VOL
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
25
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
125
MHz
RMS Phase Jitter
(Random); NOTE 1
tjit(Ø)
Intergration Range: 1.875MHz to 20MHz
20ꢀ to 80ꢀ
0.34
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
250
48
550
52
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plot.
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840021AG
REV. A NOVEMBER 30, 2004
3
ICS840021
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
TYPICAL PHASE NOISE AT 125MHZ
0
-10
-20
-30
-40
10 Gb Ethernet Filter
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.34ps (typical)
-50
-60
-70
-80
-90
-100
-110
Raw Phase Noise Data
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
a 10 Gb Ethernet Filter to raw data
100k
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
840021AG
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REV. A NOVEMBER 30, 2004
4
ICS840021
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
Phase Noise Plot
SCOPE
VDD
Qx
Phase Noise Mask
LVCMOS
GND
Offset Frequency
f1
f2
-1.65V 5ꢀ
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
VDD
80ꢀ
tF
80ꢀ
tR
2
Q0
Pulse Width
tPERIOD
20ꢀ
20ꢀ
Clock
Outputs
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
840021AG
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REV. A NOVEMBER 30, 2004
5
ICS840021
Integrated
Circuit
Systems, Inc.
F
EMTO
CLOCKS™ CRYSTAL- -
TO
LVCMOS/LVTTL CLOCK
GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise.The ICS840021 provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL.VDD andVDDA should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required. Figure 1
illustrates how a 10Ω resistor along with a 10µF and a .01µF
bypass capacitor should be connected to each VDDA pin.
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840021 has been characterized with 18pF parallel resonant crystal and were chosen to minimize the ppm error.
resonant crystals. The capacitor values, C1 and C2, shown in The optimum C1 and C2 values can be slightly adjusted for
Figure 2 below were determined using a 25MHz, 18pF parallel different board layouts.
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
Figure 2. CRYSTAL INPUt INTERFACE
840021AG
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REV. A NOVEMBER 30, 2004
6
ICS840021
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
APPLICATION SCHEMATIC
Figure 3A shows a schematic example of the ICS840021. An output frequency. The C1 = 27pF and C2 = 33pF are recom-
example of LVCMOS termination is shown in this schematic. mended for frequency accuracy. For different board layout, the
C1 and C2 values may be slightly adjusted for optimizing fre-
Additional LVCMOS termination approaches are shown in the
LVCMOSTermination Application Note.In this example, an 18pF quency accuracy.
parallel resonant 25MHz crystal is used for generating 125MHz
VDD
VDDA
R2
10
C3
C4
10uF
0.1u
U1
R3
43
VDD
Q
1
8
7
6
5
Zo = 50 Ohm
VDDA
OE
XTAL_OUT
XTAL_I N
VDD
Q0
GND
NC
OE
2
3
4
C2
33pF
X1
C5
0.1u
LVCMOS
ICS840021
C1
27pF
VDD=3.3V
FIGURE 3A. ICS840021 SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of ICS840021 P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age.The footprints of other components in this example are listed
in the Table 7. There should be at least one decoupling capacitor
per power pin.The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 7. FOOTPRINT TABLE
Reference
C1, C2
C3
Size
0402
0805
0603
0603
C4, C5
R2, R3
NOTE: Table 6, lists component
sizes shown in this layout example.
FIGURE 3B. ICS840021 PC BOARD LAYOUT EXAMPLE
840021AG
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REV. A NOVEMBER 30, 2004
7
ICS840021
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TRANSISTOR COUNT
The transistor count for ICS840021 is: 1961
840021AG
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REV. A NOVEMBER 30, 2004
8
ICS840021
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
840021AG
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REV. A NOVEMBER 30, 2004
9
ICS840021
Integrated
Circuit
Systems, Inc.
F
EMTO
CLOCKS™ CRYSTAL- -
TO
LVCMOS/LVTTL CLOCK
GENERATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS840021AG
Marking
Package
Count
Temperature
0°C to 70°C
0°C to 70°C
021AG
021AG
8 lead TSSOP
100 per tube
2500
ICS840021AGT
8 lead TSSOP on Tape and Reel
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
840021AG
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REV. A NOVEMBER 30, 2004
10
ICS840021
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
REVISION HISTORY SHEET
Description of Change
Ordering Information Table - correct count from 154 to 100.
Rev
Table
Page
Date
A
T10
10
10/14/04
3
8
Absolute Maximum Ratings - corrected Package Thermal Impedance air flow.
Corrected air flow in table.
A
11/30/04
T8
840021AG
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REV. A NOVEMBER 30, 2004
11
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