ICS8430-111 [ICSI]
700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER; 700MHZ ，低抖动差分至3.3V的LVPECL频率合成器
| 型号： | ICS8430-111 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总16页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8430-111
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8430-111 is a general purpose, dual out- • Dual differential 3.3V LVPECL output
ICS
put high frequency synthesizer and a member of
• Selectable 14MHz to 27MHz differential CLK, nCLK
orTEST_CLK input
HiPerClockS™
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The CLK, nCLK pair
can accept most standard differential input lev-
• CLK, nCLK accepts any differential input signal:
LVPECL, LVHSTL, LVDS, SSTL, HCSL
els. The single ended TEST_CLK input accepts LVCMOS or
LVTTL input levels and translates them to 3.3V LVPECL levels.
TheVCO operates at a frequency range of 200MHz to 700MHz.
With the output configured to divide the VCO frequency by 2,
output frequency steps as small as 2MHz can be achieved
using a 16MHz differential or single ended reference clock. Out-
put frequencies up to 700MHz can be programmed using the
serial or parallel interfaces to the configuration logic. The low
jitter and frequency range of the ICS8430-111 makes it an ideal
clock generator for most clock tree applications.
• TEST_CLK accepts the following input types:
LVCMOS, LVTTL
• Output frequency range up to 700MHz
• VCO range: 200MHz to 700MHz
• Parallel or serial interface for programming counter
and output dividers
• Cycle-to-cycle jitter: 25ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial termperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
CLK_SEL
TEST_CLK
0
32 31 30 29 28 27 26 25
CLK
1
M5
M6
M7
M8
N0
N1
N2
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CLK
nCLK
TEST_CLK
CLK_SEL
VCCA
÷ 16
ICS8430-111
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
MR
VEE
0
VCO
FOUT0
nFOUT0
FOUT1
nFOUT1
÷ N
9
10 11 12 13 14 15 16
÷ M
1
÷ 2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
M0:M8
N0:N2
Y Package
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
1
PRELIMINARY
ICS8430-111
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
the parallel input mode.The relationship between theVCO fre-
quency, the input frequency and the M divider is defined as
The ICS8430-111 features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A differential clock input is used as the input to the
on-chip oscillator.The output of the oscillator is divided by 16
prior to the phase detector. A16MHz clock input provides a
1MHz reference frequency.TheVCO of the PLL operates over
a range of 200 to 700MHz.The output of the M divider is also
applied to the phase detector.
follows:
fVCO = fIN x M
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table.Valid M values for which the PLL will achieve lock for a
16MHz reference are defined as 100 ≤ M ≤ 350.The frequency
out is defined as follows:
fOUT = fVCO = fIN x M
N
N
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjust-
ing the VCO control voltage. Note that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
each of the LVPECL output buffers. The divider provides a
50% output duty cycle.
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output divider
when S_LOAD transitions from LOW-to-HIGH. The M divide
and N output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the
S_DATA input is passed directly to the M divider and N output
divider on each rising edge of S_CLOCK.The serial mode can
be used to program the M and N bits and test bits T1 and T0.
The internal registers T0 and T1 determine the state of the
The programmable features of the ICS8430-111 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial. Fig-
ure 1 shows the timing diagram for each mode. In
parallel mode the nP_LOAD input is initially LOW.The data on
inputs M0 through M8 and N0 through N2 is passed directly
to the M divider and N output divider. On the LOW-to-HIGH
transition of the nP_LOAD input, the data is latched and the M
divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M
and N bits can be hardwired to set the M divider and N output
divider to a specific default state that will automatically occur
during power-up.The TEST output is LOW when operating in
T1 T0
TEST Output
LOW
0
0
1
1
0
1
0
1
S_Data, Shift Register Input
Output of M divider
CMOS Fout
SERIAL
L
OADING
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
t
t
H
S
t
S
PARALLEL LOADING
M, N
M0:M8, N0:N1
nP_LOAD
t
t
H
S
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
8430DY-111
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REV. F JUNE 1, 2005
2
PRELIMINARY
ICS8430-111
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 3,
28, 29, 30
31, 32
M5, M6, M7,
M0, M1, M2,
M3, M4
Input
Pulldown
M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS/LVTTL interface levels.
4
M8
Input
Input
Pullup
Pulldown
Pullup
5, 6
N0, N1
Determines output divider value as defined in Table 3C
Function Table. LVCMOS/LVTTL interface levels.
7
N2
Input
8, 16
VEE
Power
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core supply pin.
9
TEST
VCC
FOUT1,
nFOUT1
VCCO
FOUT0,
nFOUT0
Output
Power
Output
Power
Output
10
11, 12
13
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Output supply pin.
14, 15
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inverted
17
MR
Input
Pulldown outputs nFOUTx to go high. When logic LOW, the internal dividers
and the outputs are enabled. Assertion of MR does not affect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS/LVTTL interface levels.
18
19
S_CLOCK
S_DATA
Input
Input
Pulldown
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
Analog supply pin.
20
21
S_LOAD
VCCA
Input
Pulldown
Power
Selects between differential clock or test inputs as the PLL reference
22
Input
Pullup
source. Selects CLK, nCLK inputs when HIGH. Selects TEST_CLK
when LOW. LVCMOS/LVTTL interface levels.
CLK_SEL
23
24
25
TEST_CLK
CLK
Input
Input
Input
Pulldown Test clock input. LVCMOS/LVTTL interface levels.
Pulldown Non-inverting differential clock input.
nCLK
Pullup
Inverting differential clock input.
Parallel load input. Determines when data present at M8:M0 is
26
nP_LOAD
Input
Pulldown loaded into the M divider, and when data present at N2:N0 sets
the N output divider value. LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
27
VCO_SEL
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
kΩ
kΩ
RPULLUP
RPULLDOWN
51
51
8430DY-111
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REV. F JUNE 1, 2005
3
PRELIMINARY
ICS8430-111
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
L
Data Data
Data Data
X
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
L
L
L
↑
L
L
↑
X
↑
L
X
H
H
X
X
X
X
Data
Data
L
L
L
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
256
M8
0
128
M7
0
64
M6
1
32
M5
1
16
M4
0
8
M3
0
4
M2
1
2
M1
0
1
M0
0
VCO Frequency
(MHz)
M Divide
200
202
204
206
•
100
101
102
103
•
0
0
1
1
0
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
696
698
700
348
349
350
1
0
1
0
1
1
1
0
0
1
0
1
0
1
1
1
0
1
1
0
1
0
1
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to an input frequency of 16MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Input
N1
0
Output Frequency (MHz)
N Divider Value
N2
0
N0
0
Minimum
100
50
Maximum
2
4
350
175
0
0
1
0
1
0
8
25
87.5
43.75
700
0
1
1
16
1
12.5
200
100
50
1
0
0
1
0
1
2
350
1
1
0
4
175
1
1
1
8
25
87.5
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
4
PRELIMINARY
ICS8430-111
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
CC
Inputs, V
-0.5V to VCC + 0.5 V
-0.5V to VCCO + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol
VCC
Parameter
Core Supply
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
V
VCCA
VCCO
IEE
Analog Voltage
3.135
3.3
3.465
V
Ouput Voltage
3.135
3.3
3.465
V
Power Supply Current
Analog Supply Current
120
10
mA
mA
ICCA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol
VIH
Parameter
Test Conditions
Minimum Typical Maximum Units
Input High Voltage
Input Low Voltage
2
VCC + 0.3
0.8
V
V
VIL
-0.3
M0-M7, N0, N1, MR,
S_CLOCK, S_DATA, S_LOAD,
TEST_CLK, nP_LOAD
M8, N2, CLK_SEL, VCO_SEL
M0-M7, N0, N1, MR,
S_CLOCK, S_DATA, S_LOAD,
TEST_CLK, nP_LOAD
VCC = VIN = 3.465V
150
5
µA
µA
µA
Input
High Current
IIH
V
CC = VIN = 3.465V
CC = 3.465V,
IN = 0V
VCC = 3.465V,
V
-5
Input
Low Current
V
IIL
M8, N2, CLK_SEL, VCO_SEL
TEST; NOTE 1
-150
2.6
µA
V
VIN = 0V
Output
High Voltage
Output
Low Voltage
VOH
VOL
TEST; NOTE 1
0.5
V
NOTE 1: Outputs terminated with 50Ω to VCCO/2.
8430DY-111
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REV. F JUNE 1, 2005
5
PRELIMINARY
ICS8430-111
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VCC = 3.465V
VIN = VCC = 3.465V
IN = 0V, VCC = 3.465V
IN = 0V, VCC = 3.465V
Minimum Typical Maximum Units
nCLK
CLK
5
µA
µA
µA
µA
V
150
nCLK
CLK
V
V
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
VEE + 0.5
VCC - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCCO - 1.4
VCCO - 2.0
0.6
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. See 3.3V Output Load Test Circuit figure in the
Parameter Measurement Information section.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK; NOTE 1
14
14
27
27
50
MHz
MHz
MHz
fIN
Input Frequency CLK, nCLK; NOTE 1
S_CLOCK
NOTE1: For the differential input and reference frequency range, the M value must be set for the VCO to operate within
the 200MHz to 700MHz range. Using the minimum input frequency of 14MHz, valid values of M are 115 ≤ M ≤ 400.
Using the maximum frequency of 27MHz, valid values of M are 60 ≤ M ≤ 208.
8430DY-111
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REV. F JUNE 1, 2005
6
PRELIMINARY
ICS8430-111
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FMAX
Output Frequency
700
25
MHz
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
%
fOUT > 87.5MHz
fOUT < 87.5MHz
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
40
tjit(per)
tsk(o)
tR / tF
Period Jitter, RMS
9.5
15
Output Skew; NOTE 1, 2
Output Rise/Fall Time
20% to 80%
200
5
700
M, N to nP_LOAD
tS
Setup Time
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
5
5
tH
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
N ≠ 1
48
45
52
55
1
odc
Output Duty Cycle
PLL Lock Time
N = 1
%
tLOCK
ms
See Parameter Measurement Information section.
NOTE 1:This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
8430DY-111
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REV. F JUNE 1, 2005
7
PRELIMINARY
ICS8430-111
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA, VCCO = 2V
VCC
SCOPE
Qx
nCLK
VPP
VCMR
Cross Points
LVPECL
CLK
VEE
nQx
VEE = -1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nFOUTx
FOUTx
80%
tF
80%
VSWING
Clock
20%
20%
nFOUTy
Outputs
tR
FOUTy
tsk(o)
OUTPUT RISE/FALL TIME
OUTPUT SKEW
VOH
nFOUTx
FOUTx
VREF
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
➤
➤
tcycle n
tcycle n+1
➤
➤
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
PERIOD JITTER
CYCLE-TO-CYCLE JITTER
nFOUTx
FOUTx
tPW
tPERIOD
tPW
odc =
x 100%
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
8430DY-111
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REV. F JUNE 1, 2005
8
PRELIMINARY
ICS8430-111
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8430-111 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10 μF
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.There are a few simple termination schemes.
Figures 3A and 3B show two different layouts which are recom-
mended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
V
- 2V
VCCCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
8430DY-111
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REV. F JUNE 1, 2005
9
PRELIMINARY
ICS8430-111
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position theV_REF in
Figure 4 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 4. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
8430DY-111
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PRELIMINARY
ICS8430-111
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700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 5A to 5E show inter- For example in Figure 5A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 5A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 5B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiver
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 5C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 5E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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PRELIMINARY
ICS8430-111
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700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8430-111.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8430-111 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA = 415.8mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 415.8mW + 60mW = 475.8mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W perTable 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.476W * 42.1°C/W = 90°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω) * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS8430-111
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700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8430-111 is: 3960
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700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
D
9.00 BASIC
7.00 BASIC
5.60
D1
D2
E
9.00 BASIC
7.00 BASIC
5.60
E1
E2
e
0.80 BASIC
0.60
L
0.45
0°
0.75
7°
q
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
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700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS8430DY-111
ICS8430DY-111T
ICS8430DY-111
ICS8430DY-111
32 Lead LQFP
32 Lead LQFP
tray
0°C to 70°C
0°C to 70°C
1000 tape & reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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相关型号：
ICS8430-71B
700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICSI
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