ICS8520DYT_技术文档

PRELIMINARY

ICS8520

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER

GENERAL DESCRIPTION

FEATURES

The ICS8520 is a low skew, high performance • 16 differential 3.3V LVHSTL outputs each with the ability to

1-to-16 Differential-to-3.3V LVHSTLFanout Buffer

and a member of the HiPerClockS™ family of

High Performance Clock Solutions from ICS. The

ICS8520 has 1 clock input pair. The CLK, nCLK

drive 50Ω to ground

HiPerClockS™

• 1 differential CLK, nCLK input pair

• CLK, nCLK pair can accept the following differential input

levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

pair can accept most standard differential input levels.

Guaranteed output skew, part-to-part skew and crossover

voltage characteristics make the ICS8520 ideal for interfac-

ing to today’s most advanced microprocessor and static

RAMs.

• Maximum output frequency up to 500MHz

• Translates single ended input levels to LVHSTL levels with

resistor bias nCLK input

• Output skew: 50ps (maximum)

• Part-to-part skew: 250ps (maximum)

• Propagation delay: 1.6ns (maximum)

• VOH: 1.2V (maximum)

• 40% of VOH ≤ Vcrossover ≤ 60% of VOH

• 3.3V core, 1.8V output operating supply voltages

• 0°C to 70°C ambient operating temperature

BLOCK DIAGRAM

PIN ASSIGNMENT

CLK

nCLK

48 47 46 45 44 43 42 41 40 39 38 37

Q0

Q15

1

CLK

VCCO

nQ0

Q0

VCCO

Q11

36

35

34

33

32

31

30

29

28

27

26

25

nQ0

nQ15

2

Q1

nQ1

Q14

nQ14

nQ11

Q10

3

4

nQ1

Q1

nQ10

GND

Q9

5

Q2

nQ2

Q13

nQ13

6

ICS8520

7

GND

nQ2

Q2

Q12

nQ12

Q3

nQ3

nQ9

8

Q8

9

Q11

nQ11

Q4

nQ4

10

11

12

nQ3

Q3

nQ8

VCCO

VCC

VCCO

Q10

nQ10

Q5

nQ5

13 14 15 16 17 18 19 20 21 22 23 24

Q9

nQ9

Q6

nQ6

Q8

nQ8

Q7

nQ7

48-Lead LQFP

7mm x 7mm x 1.4mm body package

Y Package

Top View

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

ICS8520DY

www.icst.com/products/hiperclocks.html

REV. B JULY 5, 2001

1

PRELIMINARY

ICS8520

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

1, 11,

14, 24,

25, 35,

38, 48

VCCO

Power

Output supply pins. Connect to 1.8V.

2, 3

4, 5

Q11, nQ11

Q10, nQ10

Output

Differential output pair. LVHSTL interface levels.

6, 19,

30, 43

VEE

Power

Negative supply pins. Connect to ground.

7, 8

Q9, nQ9

Q8, nQ8

VCC

Output

Power

Output

Input

Differential output pair. LVHSTL interface levels.

Positive supply pins. Connect to 3.3V.

9, 10

12, 13

15, 16

17, 18

20, 21

22, 23

26, 27

28, 29

36

Q7, nQ7

Q6, nQ6

Q5, nQ5

Q4, nQ4

Q3, nQ3

Q2, nQ2

CLK

Differential output pair. LVHSTL interface levels.

Pulldown Non inverting differential clock input.

37

nCLK

Input

Pullup

Inverting differential clock input.

39, 40

41, 42

44, 45

46, 47

Q15, nQ15

Q14, nQ14

Q13, nQ13

Q12, nQ12

Output

Differential output pair. LVHSTL interface levels.

NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

ICS8520DY

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REV. B JULY 5, 2001

2

PRELIMINARY

ICS8520

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER

TABLE 2. PIN CHARACTERISTICS

Symbol

CIN

Parameter

Test Conditions

Minimum Typical Maximum Units

Input Capacitance

Input Pullup Resistor

CLK, nCLK

4

pF

KΩ

RPULLUP

51

RPULLDOWN Input Pulldown Resistor

TABLE 3. FUNCTION TABLE

Inputs

Outputs

Input to Output Mode

Polarity

CLK

nCLK

Q0 thru Q15

LOW

nQ0 thru nQ15

HIGH

0

1

Differential to Differential

Single Ended to Differential

Non Inverting

Inverting

1

0

HIGH

LOW

0

Biased; NOTE 1

LOW

HIGH

1

Biased; NOTE 1

HIGH

LOW

Biased; NOTE 1

0

1

HIGH

LOW

HIGH

Inverting

NOTE 1: Single ended use requires that one of the differential inputs be biased. The voltage at the biased input sets the

switch point for the single ended input. For LVCMOS and LVTTL levels the recommended input bias network is a resistor

to VCC, a resistor of equal value to ground and a 0.1µF capacitor from the input to ground. The resulting switch point is

approximately VCC/2 ± 300mV.

ICS8520DY

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REV. B JULY 5, 2001

3

PRELIMINARY

ICS8520

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, VCCx

Inputs, V^I

4.6V

-0.5V to VCC+0.5 V

-0.5V to VCC+0.5V

Outputs, V^O

Package Thermal Impedance, θ^JA46°C/W (no air flow)

Storage Temperature, T^STG-65°C to 150°C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are

stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC

Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may

affect product reliability.

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 1.8V±0.2V, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

3.135

Typical

3.3

Maximum Units

VCC

VCCO

IEE

Positive Supply Voltage

3.465

2.0

V

Output Supply Voltage

Power Supply Current

1.6

1.8

120

mA

TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 1.8V±0.2V, TA = 0°C TO 70°C

Symbol

Parameter

Test Conditions

VIN = VCC = 3.465V

VIN = 0V, VCC = 3.465V

Minimum

Typical

Maximum Units

IIH

Input High Current

CLK

150

1

µA

V

nCLK

CLK

IIL

Input Low Current

-1

nCLK

-150

0.15

VPP

Peak-to-Peak Input Voltage

1.3

Common Mode Voltage Range;

NOTE 1, 2

VCMR

VEE + 0.5

VCC - 0.85

V

NOTE 1: Common mode voltage is defined as VIH.

NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.

TABLE 4C. LVHSTL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 1.8V±0.2V, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Output

VOH

High Voltage;

NOTE 1

1.0

1.2

V

Output

VOL

VOX

Low Voltage;

NOTE 1

Output

0

0.4

V

40% x (VOH - VOL) + VOL

60% x (VOH - VOL) + VOL

Crossover Voltage

NOTE 1:Outputs terminated with 50Ω to ground.

ICS8520DY

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REV. B JULY 5, 2001

4

PRELIMINARY

ICS8520

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER

TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 1.8V±0.2V, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical

Maximum

500

Units

MHz

ns

fMAX

tPD

Maximum Input Frequency

Propagation Delay, Low-to-High; NOTE 1

Output Skew; NOTE 2, 4

Part-to-Part Skew; NOTE 3, 4

Output Rise Time

0 < f ≤ 250MHz

1

1.6

tsk(o)

tsk(pp)

tR

50

ps

250

ps

20% to 80% @ 50MHz

300

47

700

ps

tF

Output Fall Time

700

ps

odc

Output Duty Cycle

53

%

All parameters measured at 250MHz unless noted otherwise

NOTE 1: Measured from the differential input crossing point to the differential ouput crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential

cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

ICS8520DY

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REV. B JULY 5, 2001

5

PRELIMINARY

ICS8520

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER

FIGURE 1A, 1B, 1C - INPUT CLOCK WAVEFORMS

VCC

CLK

CROSS POINTS

VPP

VCMR

nCLK

GND

FIGURE 1A - LVDS, HSTL, SSTL DIFFERENTIAL INPUT LEVELS

VCC

CLK

VCMR

CROSS POINTS

VPP

nCLK

GND

FIGURE 1B - LVPECL DIFFERENTIAL INPUT LEVEL

VCC

GND

CLK

or

nCLK

FIGURE 1C- LVCMOS AND LVTTL SINGLE ENDED INPUT LEVEL

ICS8520DY

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REV. B JULY 5, 2001

6

PRELIMINARY

ICS8520

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER

PACKAGE OUTLINE - Y SUFFIX

TABLE 6. PACKAGE DIMENSIONS

JEDEC VARIATION

ALL DIMENSIONS IN MILLIMETERS

BBC

SYMBOL

MINIMUM

NOMINAL

MAXIMUM

N

A

48

--

1.60

0.15

1.45

0.27

0.20

A1

A2

b

0.05

1.35

0.17

0.09

1.40

0.22

c

--

D

9.00 BASIC

7.00 BASIC

5.50 Ref.

9.00 BASIC

7.00 BASIC

5.50 Ref.

0.50 BASIC

0.60

D1

D2

E

E1

E2

e

L

0.45

0.75

q

--

0°

7°

ccc

--

0.08

Reference Document: JEDEC Publication 95, MS-026

ICS8520DY

www.icst.com/products/hiperclocks.html

REV. B JULY 5, 2001

7

PRELIMINARY

ICS8520

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER

ORDERING INFORMATION

Part/Order Number

ICS8520DY

Marking

ICS8520DY

Package

48 Lead LQFP

Count

250 per tray

1000

Temperature

0°C to 70°C

ICS8520DYT

48 Lead LQFP on Tape and Reel

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are

not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS

product for use in life support devices or critical medical instruments.

ICS8520DY

www.icst.com/products/hiperclocks.html

REV. B JULY 5, 2001

8


型号：	ICS8520DYT
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER 低偏移， 1至16差分至3.3V LVHSTL扇出缓冲器
文件：	总8页 (文件大小：103K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS8520DYT [ICSI]

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