ICS853017AMT [ICSI]
QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER; QUAD ， 1对1的差分至2.5V / 3.3V / 5V LVPECL / ECL接收器
| 型号： | ICS853017AMT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER |
| 文件： | 总12页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS853017
Integrated
Circuit
Systems, Inc.
Q
UAD, 1-TO-1
D
IFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
GENERAL DESCRIPTION
FEATURES
The ICS853017 is a quad 1-to-1, 2.5V/3.3V/5V dif- • 4 differential LVPECL / ECL 1:1 receivers
ICS
ferential LVPECL/ECL receiver and a member of
• 4 differential LVPECL clock input pairs
the HiperclocksTM family of High Performance Clock
HiPerClockS™
Solutions from ICS.The ICS853017 operates with
a positive or negative power supply at 2.5V, 3.3V or
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
5V, and can accept both single-ended and differential inputs.For
single-ended operation, an internally generated voltage, which is
available on output pinVBB, can be used as a switching bias volt-
age on the unused input of the differential pair.VBB can also be
used to rebias AC coupled inputs.
• Output frequency: >2GHz (typical)
• Translates any single ended input signal to
LVPECL levels with resistor bias on nPCLKx input
• Output skew: TBD
• Part-to-part skew: TBD
• Propagation delay: 320ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 5.25V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -5.25V to -2.375V
• -40°C to 85°C ambient operating temperature
• Pin compatible with MC100LVEL17
BLOCK DIAGRAM
PIN ASSIGNMENT
VCC
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
VCC
D0
nD0
D1
nD1
D2
nD2
D3
D0
Q0
nQ0
nD0
D1
Q1
nQ1
nD1
nQ3
VEE
9
10
nD3
VBB
D2
Q2
nQ2
nD2
ICS853017
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
D3
Q3
nQ3
nD3
Top View
VBB
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853017AM
www.icst.com/products/hiperclocks.html
REV. A APRIL 21, 2004
1
PRELIMINARY
ICS853017
Integrated
Circuit
Systems, Inc.
Q
UAD, 1-TO-1
D
IFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
TABLE 1. PIN DESCRIPTIONS
Number
1, 20
2
Name
VCC
Type
Description
Power
Input
Core supply pins.
D0
Pulldown Non-inverting differential clock input.
Pullup/
3
4
5
6
7
8
9
nD0
D1
Input
Input
Input
Input
Input
Input
Input
Inverting differential clock input. VCC/2 default when left floating.
Pulldown
Pulldown Non-inverting differential clock input.
Pullup/
nD1
D2
Inverting differential clock input. VCC/2 default when left floating.
Pulldown
Pulldown Non-inverting differential clock input.
Pullup/
nD2
D3
Inverting differential clock input. VCC/2 default when left floating.
Pulldown
Pulldown Non-inverting differential clock input.
Pullup/
nD3
Inverting differential clock input. VCC/2 default when left floating.
Pulldown
10
VBB
Power
Power
Output
Output
Output
Output
Bias Voltage.
11
VEE
Negative supply pin.
12, 13
14, 15
17, 18
19, 20
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
RPULLDOWN Input Pulldown Resistor
RVCC/2 Pullup/Pulldown Resistors
Parameter
Test Conditions
Minimum
Typical
75
Maximum
Units
KΩ
50
KΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
D0:D3
nD0:nD3
Q0:Q3
nQ0:nQ3,
HIGH
LOW
0
1
LOW
HIGH
LOW
HIGH
HIGH
LOW
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
853017AM
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REV. A APRIL 21, 2004
2
PRELIMINARY
ICS853017
Integrated
Circuit
Systems, Inc.
Q
UAD, 1-TO-1
D
IFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
5.5V (LVPECL mode, VEE = 0)
-5.5V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5V
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
VBB Sing/Source, IBB
0.5mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature,TSTG -65°C to 150°C
PackageThermal Impedance, θJA 46.2°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 5.25V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
3.3
Maximum Units
VCC
IEE
Core Supply Voltage
Power Supply Current
2.375
5.25
V
46
mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
-40°C
25°C
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
Min
Typ
2.295
1.52
Max
Min
Max
2.275
1.545
2.33
V
V
VOH
VOL
VIH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
1.535
2.075
1.43
1.86
2.075
1.43
1.86
2.075
1.43
1.86
V
V
VIL
V
VBB
VPP
800
800
800
mV
Input High Voltage
Common Mode Range; NOTE 3, 4
1.2
3.3
1.2
3.3
1.2
3.3
V
VCMR
IIH
Input
D0, D1, D2, D3
150
150
150
µA
High Current nD0, nD1,n D2, nD3
-10
-10
-10
µA
µA
D0, D1, D2, D3
Input
Low Current
IIL
-150
-150
-150
nD0, nD1,n D2, nD3
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
853017AM
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REV. A APRIL 21, 2004
3
PRELIMINARY
ICS853017
Integrated
Circuit
Systems, Inc.
Q
UAD, 1-TO-1
D
IFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
-40°C
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
Min
Max
Min
Max
1.475
0.745
1.495
0.72
1.53
V
V
V
V
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Peak-to-Peak Input Voltage
0.735
1.275
0.63
1.275
0.63
1.275
0.63
800
800
800
VPP
mV
Input High Voltage
Common Mode Range; NOTE 2, 3
1.2
2.5
1.2
2.5
1.2
2.5
V
VCMR
IIH
Input
D0, D1, D2, D3
150
150
150
µA
High Current nD0, nD1,n D2, nD3
-10
-10
-10
µA
µA
D0, D1, D2, D3
Input
Low Current
IIL
-150
-150
-150
nD0, nD1,n D2, nD3
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 5V; VEE = 0V
-40°C
Typ
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Max
Min
Max
Min
Max
3.975
3.245
3.995
3.22
4.03
V
V
V
V
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
3.235
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Peak-to-Peak Input Voltage
3.775
3.13
3.775
3.13
3.775
3.13
800
800
800
VPP
mV
Input High Voltage
Common Mode Range; NOTE 2, 3
1.2
5
1.2
5
1.2
5
V
VCMR
IIH
Input
D0, D1, D2, D3
150
150
150
µA
High Current nD0, nD1,n D2, nD3
-10
-10
-10
µA
µA
D0, D1, D2, D3
Input
Low Current
IIL
-150
-150
-150
nD0, nD1,n D2, nD3
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
853017AM
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REV. A APRIL 21, 2004
4
PRELIMINARY
ICS853017
Integrated
Circuit
Systems, Inc.
Q
UAD, 1-TO-1
D
IFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
TABLE 4C. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
-40°C
25°C
Typ Max
85°C
Typ Max
Symbol Parameter
Units
Min
Typ Max
-1.025
Min
Min
-1.005
-1.78
-0.97
V
V
VOH
VOL
VIH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
-1.755
-1.765
-1.225
-1.87
-1.44
-1.225
-1.87
-1.44
-1.225
-1.87
-1.44
V
V
VIL
V
VBB
VPP
800
800
800
mV
Input High Voltage
Common Mode Range; NOTE 3, 4
VEE+1.2V
0
VEE+1.2V
0
VEE+1.2V
0
V
VCMR
IIH
Input
D0, D1, D2, D3
150
150
150
µA
High Current nD0, nD1,n D2, nD3
-10
-10
-10
µA
µA
D0, D1, D2, D3
Input
Low Current
IIL
-150
-150
-150
nD0, nD1,n D2, nD3
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V OR VCC = 2.375V TO 5.25V; VEE = 0V
-40°C
Min Typ
25°C
85°C
Symbol Parameter
Units
Max Min Typ
Max Min Typ Max
fMAX
Output Frequency
>2
>2
>2
GHz
ps
tPLH
Propagation Delay, Low-to-High; NOTE 1
Propagation Delay, High-to-Low; NOTE 1
Output Skew; NOTE 2, 4
320
320
TBD
TBD
175
320
320
TBD
TBD
175
320
320
TBD
TBD
175
tPHL
ps
tsk(o)
tsk(pp)
tR/tF
ps
Part-to-Part Skew; NOTE 3, 4
ps
Output Rise/Fall Time
20% to 80%
ps
All parameters tested ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853017AM
www.icst.com/products/hiperclocks.html
REV. A APRIL 21, 2004
5
PRELIMINARY
ICS853017
Integrated
Circuit
Systems, Inc.
Q
UAD, 1-TO-1
D
IFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nD0:nD3
VPP
LVPECL
VCMR
Cross Points
D0:D3
nQx
VEE
VEE
-0.375V to -3.25V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nD0:nD3
nD0:D3
80%
tF
80%
VSWING
20%
Clock
20%
nQ0:nQ3
Outputs
tR
Q0:Q3
tpLH
tpHL
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
853017AM
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REV. A APRIL 21, 2004
6
PRELIMINARY
ICS853017
Integrated
Circuit
Systems, Inc.
Q
UAD, 1-TO-1
D
IFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF ~ VCC/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
PCLK
V_REF
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
853017AM
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REV. A APRIL 21, 2004
7
PRELIMINARY
ICS853017
Integrated
Circuit
Systems, Inc.
Q
UAD, 1-TO-1
D
IFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V ground level. The R3 in Figure 3B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 3C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
853017AM
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REV. A APRIL 21, 2004
8
PRELIMINARY
ICS853017
Integrated
Circuit
Systems, Inc.
Q
UAD, 1-TO-1
D
IFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
LVPECL CLOCK INPUT INTERFACE
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other suggested here are examples only. If the driver is from an-
differential signals. Both VSWING and VOH must meet the VPP other vendor, use their termination recommendation. Please
and VCMR input requirements. Figures 4A to 4E show inter- consult with the vendor of the driver component to confirm
face examples for the HiPerClockS PCLKx/nPCLKx input the driver termination requirements.
driven by the most common driver types.The input interfaces
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
nPCLK
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
Zo = 50 Ohm
R3
1K
R4
1K
Zo = 50 Ohm
Zo = 50 Ohm
C1
C2
LVDS
PCLK
PCLK
R5
100
nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
853017AM
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REV. A APRIL 21, 2004
9
PRELIMINARY
ICS853017
Integrated
Circuit
Systems, Inc.
Q
UAD, 1-TO-1
D
IFFERENTIAL
-
TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD SOIC
θ byVelocity (Linear Feet per Minute)
JA
0
200
65.7°C/W
39.7°C/W
500
57.5°C/W
36.8°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
46.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853017 is: 187
853017AM
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REV. A APRIL 21, 2004
10
PRELIMINARY
ICS853017
Integrated
Circuit
Systems, Inc.
Q
UAD, 1-TO-1
D
IFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
PACKAGE OUTLINE - Y SUFFIX FOR 20 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
20
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
12.60
7.40
2.55
0.51
0.32
13.00
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119
853017AM
www.icst.com/products/hiperclocks.html
REV. A APRIL 21, 2004
11
PRELIMINARY
ICS853017
Integrated
Circuit
Systems, Inc.
Q
UAD, 1-TO-1
D
IFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS853017AM
Marking
Package
Count
38 per tube
1000
Temperature
-40°C to 85°C
-40°C to 85°C
ICS853017AM
ICS853017AM
20 Lead SOIC
ICS853017AMT
20 Lead SOIC on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853017AM
www.icst.com/products/hiperclocks.html
REV. A APRIL 21, 2004
12
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