ICS85310I-11 [ICSI]
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER; 低偏移， 1到10差分至2.5V / 3.3V ECL / LVPECL扇出缓冲器
| 型号： | ICS85310I-11 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER |
| 文件： | 总16页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85310I-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS85310I-11 is a low skew, high perfor- • 10 differential 2.5V/3.3V LVPECL / ECL outputs
ICS
mance 1-to-10 Differential-to-2.5V/3.3V ECL/
• 2 selectable differential input pairs
HiPerClockS™
LVPECL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance
Clock Solutions from ICS. The CLKx, nCLKx
• CLKx, nCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
pairs can accept most standard differential input levels. The
ICS85310I-11 is characterized to operate from either a
2.5V or a 3.3V power supply. Guaranteed output and part-
to-part skew characteristics make the ICS85310I-11 ideal
for those clock distribution applications demanding well de-
fined performance and repeatability.
• Maximum output frequency: 700MHz
• Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
• Output skew: 30ps (typical)
• Part-to-part skew: 140ps (typical)
• Propagation delay: 2ns (typical)
• Additive phase jitter, RMS: <0.13ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.8V
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS complaint
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
CLK0
nCLK0
0
1
CLK1
nCLK1
Q1
nQ1
32 31 30 29 28 27 26 25
Q2
nQ2
VCC
CLK_SEL
CLK0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q3
nQ3
Q4
CLK_SEL
CLK_EN
Q3
nQ3
nCLK0
nQ4
Q5
ICS85310I-11
D
Q4
nQ4
CLK_EN
CLK1
Q
nQ5
Q6
LE
nCLK1
Q5
nQ5
nQ6
VEE
Q6
nQ6
9
10 11 12 13 14 15 16
Q7
nQ7
32-Lead LQFP
Q8
nQ8
7mm x 7mm x 1.4mm package body
Y Package
TopView
Q9
nQ9
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ICS85310I-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VCC
Power
Core supply pin.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.
2
CLK_SEL
Input Pulldown
3
4
CLK0
Input Pulldown Non-inverting differential clock input.
nCLK0
Input
Pullup
Inverting differential clock input.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
5
CLK_EN
Input
Pullup
6
7
CLK1
nCLK1
VEE
Input Pulldown Non-inverting differential clock input.
Input
Power
Power
Pullup
Inverting differential clock input.
8
Negative supply pin.
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
VCCO
Output supply pins.
nQ9, Q9 Output
nQ8, Q8 Output
nQ7, Q7 Output
nQ6, Q6 Output
nQ5, Q5 Output
nQ4, Q4 Output
nQ3, Q3 Output
nQ2, Q2 Output
nQ1, Q1 Output
nQ0, Q0 Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
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ICS85310I-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_EN
Selected Source
Q0:Q9
Disabled; LOW
Enabled
Q0:Q9
Disabled; HIGH
Enabled
0
1
CLK0, nCLK0
CLK1, nCLK1
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1, nCLK1 inputs as described
in Table 3B.
Enabled
Disabled
CLK0, nCLK0
CLK1, CLK1
CLK_EN
nQ0:nQ9
Q0:Q9
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK0 or CLK1
nCLK0 or nCLK1
Q0:Q9
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQ0:Q9
HIGH
LOW
0
1
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
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ICS85310I-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
Inputs, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
-0.5V toVCC + 0.5 V
-0.5V to VCCO + 0.5V
Outputs,VCCO
PackageThermal Impedance, θJA 47.9°C/W (0 lfpm)
StorageTemperature, TSTG -65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
3.3
Maximum Units
VCC
VCCO
IEE
Core Supply Voltage
3.8
3.8
120
V
V
Output Supply Voltage
Power Supply Current
2.375
3.3
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 2.375V TO 3.8V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK_SEL,
CLK_EN
CLK_SEL,
CLK_EN
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
Input High Current
-0.3
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
CC = VIN = 3.8V
CC = VIN = 3.8V
5
µA
µA
µA
µA
IIH
V
150
V
CC = 3.8V, VIN = 0V
-150
-5
IIL
Input Low Current
VCC = 3.8V, VIN = 0V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum
Typical
Maximum Units
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
V
CC = VIN = 3.8V
CC = VIN = 3.8V
150
5
µA
µA
µA
µA
V
V
V
CC = 3.8V, VIN = 0V
CC = 3.8V, VIN = 0V
-5
-150
IIL
Input Low Current
nCLK0, nCLK1
V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VCC + 0.3V.
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ICS85310I-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VCC - 1.4
Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 1.0
VCC - 1.7
0.85
V
V
V
VOL
Output Low Voltage; NOTE 1
VCC - 2.0
VSWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
700
2.5
55
MHz
ns
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
IJ 500MHz
2
tsk(o)
tsk(pp)
30
ps
Part-to-Part Skew; NOTE 3, 4
140
340
ps
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
tjit
<0.13
ps
tR
Output Rise Time
Output Fall Time
Output Duty Cycle
20% to 80%
20% to 80%
200
200
47
700
700
53
ps
ps
%
tF
odc
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS85310I-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
Additive Phase Jitter, RMS
@ 155.52MHz = <0.13ps typical
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
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ICS85310I-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
VCC,VCCO= 2V
VCC
SCOPE
Qx
nCLK0, nCLK1
VPP
LVPECL
VCMR
Cross Points
CLK0, CLK1
nQx
VEE
VEE = -0.375V to -1.8V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK0,
nCLK1
80%
tF
80%
CLK0,
CLK1
VSWING
20%
nQ0:nQ9
Clock
20%
Outputs
tR
Q0:Q9
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0:nQ9
Q0:Q9
tPW
tPERIOD
tPW
odc =
x 100%
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS85310I-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF ~ VCC/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 4A and Figure 4B show examples of termination for 2.5V ground level. The R3 in Figure 4B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 4C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
R3
250
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
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LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
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DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 5A to 5E show inter- For example in Figure 5A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 5A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 5B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiver
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 5C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 5E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85310I-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85310I-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 120mA = 456mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30.2mW = 302mW
Total Power_MAX (3.8V, with all outputs switching) = 456mW + 302mW = 758mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.758W * 42.1°C/W = 117°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θ byVelocity (Linear Feet per Minute)
JA
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 1.0V
OH_MAX
CCO_MAX
)
= 1.0V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
OH_MAX
CCO _MAX
OH_MAX
L
CCO
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
CCO
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
85310AYI-11
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REV. E JULY 7, 2005
12
ICS85310I-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θ byVelocity (Linear Feet per Minute)
JA
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85310I-11 is: 1034
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REV. E JULY 7, 2005
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ICS85310I-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
85310AYI-11
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REV. E JULY 7, 2005
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ICS85310I-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS85310AYI-11
Marking
Package
Shipping Packaging Temperature
ICS85310AYI11
ICS85310AYI11
ICS85310AI11L
ICS85310AI11L
32 lead LQFP
tray
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS85310AYI-11T
ICS85310AYI-11LF
ICS85310AYI-11LFT
32 lead LQFP
1000 tape & reel
tray
32 lead LQFP, "Lead-Free"
32 lead LQFP, "Lead-Free"
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
85310AYI-11
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REV. E JULY 7, 2005
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ICS85310I-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
AC Characterisitics table - tPD row, revised value from 2.25ns Max. to
2.5ns Max.
B
T5
5
4/29/02
5/29/02
9
5
Added Termination for LVPECL Outputs section.
4D
Added LVPECL DC Characterisitics table.
C
D
Changed part number from ICS85310-11 to ICS85310I-11 in title and all
subsequent areas throughout the datasheet.
Power Supply table - increased max. value for IEE to 120mA from 30mA max.
7/25/02
T4A
4
10/23/02
10
1
2
5
6
Power Considerations have re-adjusted to the increased IEE value.
Features Section - added Additive Phase Jitter bullet and Lead Free bullet.
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical
AC Characteristics Table - added Additive Phase Jitter row.
Added Additive Phase Jitter Section.
T2
T5
E
7/7/05
9
Added Termination for 2.5V LVPECL Outputs.
10
15
Added Differential Clock Input Interface.
Ordering Information Table - added Lead-Free Part Number and Note.
T9
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REV. E JULY 7, 2005
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