ICS85322AMIT [ICSI]
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR; 双LVCMOS / LVTTL到差分2.5V / 3.3V LVPECL译者
| 型号： | ICS85322AMIT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR |
| 文件： | 总13页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS85322I is a Dual LVCMOS / LVTTL-to- • 2 differential 2.5V/3.3V LVPECL outputs
ICS
Differential 2.5V / 3.3V LVPECL translator and a
member of the HiPerClocks™family of High Per-
formance Clocks Solutions from ICS. The
ICS85322I has selectable single ended clock in-
• Selectable CLK0, CLK1 LVCMOS/LVTTL clock inputs
HiPerClockS™
• CLK0 and CLK1 can accepts the following input levels:
LVCMOS or LVTTL
puts.The single ended clock input accepts LVCMOS or LVTTL
input levels and translate them to 2.5V / 3.3V LVPECL levels.
The small outline 8-pin SOIC package makes this device ideal
for applications where space, high performance and low power
are important.
• Maximum output frequency: 267MHz
• Part-to-part skew: 250ps (maximum)
• 3.3V operating supply voltage
(operating range 3.135V to 3.465V)
• 2.5V operating supply voltage
(operating range 2.375V to 2.625V)
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
CLK0
Q0
nQ0
Q1
VCC
1
2
3
4
8
7
6
5
CLK0
CLK1
VEE
Q1
nQ1
CLK1
nQ1
ICS85322I
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
TopView
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REV. B OCTOBER 7, 2003
1
ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Q0, nQ0
Q1, nQ1
VEE
Type
Description
1, 2
3, 4
5
Output
Output
Power
Input
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
6
CLK1
CLK0
VCC
Pullup
Pullup
LVCMOS / LVTTL clock input.
LVCMOS / LVTTL clock input.
Positive supply pin.
7
Input
8
Power
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
51
51
KΩ
KΩ
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ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5 V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
112.7°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
3.135
3.3
3.465
25
V
mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
Input Low Voltage
CLK0, CLK1
CLK0, CLK1
2
VCC + 0.3
V
V
-0.3
1.3
5
Input High Current CLK0, CLK1
Input Low Current CLK0, CLK1
VCC = VIN = 3.465V
VCC = VIN = 3.465V
µA
µA
IIL
-150
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol
VOH
Parameter
Test Conditions
VCC = VIN = 3.465V
VCC = VIN = 3.465V
Minimum
VCC - 1.4
VCC - 2.0
0.65
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCC - 1.0
VCC - 1.7
0.9
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4A. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
267
1.9
250
700
60
MHz
ns
tPD
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time
ƒ ≤ 267MHz
0.5
tsk(pp)
tR / tF
odc
ps
20ꢀ to 80ꢀ @ 50MHz
300
40
ps
Output Duty Cycle
ꢀ
All parameters measured at 133MHz unless noted otherwise.
NOTE 1: Measured from VCC/2 point of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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REV. B OCTOBER 7, 2003
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ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
TABLE 3D. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
2.5
2.625
25
V
mA
TABLE 3E. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
1.6
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
Input Low Voltage
CLK0, CLK1
CLK0, CLK1
VCC + 0.3
V
V
-0.3
0.9
5
Input High Current CLK0, CLK1
Input Low Current CLK0, CLK1
VCC = VIN = 2.625
VCC = VIN = 2.625
µA
µA
IIL
-150
TABLE 3F. LVPECL DC CHARACTERISTICS, VCC = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.65
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCC - 1.0
VCC - 1.7
0.9
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4B. AC CHARACTERISTICS, VCC = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
215
2.1
250
700
60
MHz
ns
tPD
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time
ƒ ≤ 215MHz
0.7
tsk(pp)
tR / tF
odc
ps
20ꢀ to 80ꢀ @ 50MHz
300
40
ps
Output Duty Cycle
ꢀ
All parameters measured at 133MHz unless noted otherwise.
NOTE 1: Measured from VCC/2 point of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65..
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ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
2V
SCOPE
SCOPE
VCC
VCC
Qx
Qx
LVPECL
LVPECL
nQx
nQx
VEE
VEE
-0.5V 0.125V
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx
PART 1
Qx
CLK0,
CLK1
nQ0, nQ1
nQy
PART 2
Q0, Q1
Qy
tPD
tsk(o)
PART-TO-PART SKEW
PROPAGATION DELAY
nQ0, nQ1
80ꢀ
tF
80ꢀ
Q0, Q1
VSWING
20ꢀ
Pulse Width
tPERIOD
Clock
20ꢀ
Outputs
tR
tPW
odc =
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 1A and 1B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
(VOH + VOL / VCC – 2) – 2
84Ω
84Ω
FIGURE 1A. LVPECL OUTPUT TERMINATION
FIGURE 1B. LVPECL OUTPUT TERMINATION
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ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 2A and Figure 2B show examples of termination for 2.5V ground level. The R3 in Figure 2B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 2C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
R3
250
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 2A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 2B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 2C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. B OCTOBER 7, 2003
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ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85322I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85322I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 25mA = 86.6mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.465V, with all outputs switching) = 86.6mW + 60.4mW = 147mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W perTable 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.147W * 103.3°C/W = 100.2°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 3.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 3. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 1.0V
OH_MAX
CC_MAX
)
= 1.0V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85322I is: 269
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ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
Millimeters
MINIMUN MAXIMUM
SYMBOL
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
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REV. B OCTOBER 7, 2003
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ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS85322AMI
Marking
5322AMI
5322AMI
Package
8 lead SOIC
Count
96 per tube -40°C to 85°C
2500 -40°C to 85°C
Temperature
ICS85322AMIT
8 lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV. B OCTOBER 7, 2003
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ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
A
8
6
Added Termination for LVPECL Outputs section.
5/30/02
3.3V Output Load Test Circuit Diagram, corrected VEE = -1.3V 0.135V
to read VEE = -1.3V 0.165V.
A
B
8/23/02
10/7/03
7
2
3
6
7
Updated Output Rise/Fall Time Diagram.
T2
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
Absolute Maximum Ratings, updated Inputs ratings.
Updated 3.3V LVPECL Output Termination Diagrams.
Added Termination for 2.5V LVPECL Outputs.
Updated format throughout data sheet.
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REV. B OCTOBER 7, 2003
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