ICS8533-11 [ICSI]
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER; 低偏移， 1到4 ，晶体振荡器/差分至3.3V的LVPECL扇出缓冲器
| 型号： | ICS8533-11 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER |
| 文件： | 总15页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8533-11 is a low skew, high performance
• 4 differential 3.3V LVPECL outputs
1-to-4 Crystal Oscillator/Differential-to-3.3V
• Selectable CLK, nCLK or crystal inputs
HiPerClockS™
LVPECL fanout buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8533-11 has select-
• CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
able differential clock or crystal inputs. The CLK, nCLK pair
can accept most standard differential input levels. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin.
• Maximum output frequency up to 650MHz
• Translates any single-ended input signal to 3.3V
LVPECLlevels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
Guaranteed output and part-to-part skew characteristics
make the ICS8533-11 ideal for those applications demand-
ing well defined performance and repeatability.
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 2ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
VEE
CLK_EN
CLK_SEL
CLK
Q0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
D
CLK_EN
nQ0
VCC
Q1
nQ1
Q2
nQ2
VCC
Q3
Q
LE
CLK
nCLK
XTAL1
XTAL2
0
1
nCLK
XTAL1
XTAL2
nc
nc
VCC
Q0
nQ0
Q1
nQ1
CLK_SEL
nQ3
Q2
nQ2
ICS8533-11
20-Lead TSSOP
6.5mm x 4.4mm x 0.92 Package Body
Q3
nQ3
G Package
Top View
8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
1
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VEE
Power
Input
Negative supply pin. Connect to ground.
Synchroning clock enable. When HIGH, clock outputs follows clock
input. When LOW, Q outputs are forced low, nQ outputs are forced
high. LVCMOS / LVTTL interface levels.
Clock select input. When LOW, selects CLK, nCLK input.
When HIGH, selects XTAL input. LVCMOS / LVTTL interface levels.
2
CLK_EN
Pullup
Pulldown
3
CLK_SEL
Input
4
5
CLK
nCLK
Input
Input
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Pulldown Crystal oscillator input.
6
XTAL1
XTAL2
nc
Input
7
Input
Pullup
Crystal oscillator input.
8, 9
Unused
Power
Output
Output
Output
Output
No connect.
10, 13, 18
11, 12
14, 15
16, 17
19, 20
VCC
Positive supply pins. Connect to 3.3V.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CLK, nCLK
4
4
pF
pF
CIN
Input Capacitance
Input Pullup Resistor
CLK_EN, CLK_SEL
RPULLUP
51
51
KΩ
KΩ
RPULLDOWN
Input Pulldown Resistor
REV. D JULY 16, 2001
2
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
CLK, nCLK
Q0 thru Q3
Disabled; LOW
Disabled; LOW
Enabled
nQ0 thru nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
0
0
1
1
0
1
0
1
XTAL1, XTAL2
CLK, nCLK
XTAL1, XTAL2
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled folowing a rising and falling input clock or
crystal oscillator edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK, nCLK and XTAL1, XTAL2 inputs as described
in Table 3B.
Enabled
Disabled
nCLK
CLK
CLK_EN
nQ0 - nQ3
Q0 - Q3
FIGURE 1 - CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK
nCLK
Q0 thru Q3
LOW
nQ0 thru nQ3
HIGH
0
1
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
HIGH
LOW
0
Biased; NOTE 1
LOW
HIGH
1
Biased; NOTE 1
HIGH
LOW
Biased; NOTE 1
Biased; NOTE 1
0
1
HIGH
LOW
LOW
HIGH
Inverting
NOTE 1:Please refer to the Application Information section on page 10, Figure 12, which discusses wiring the differential
input to accept single ended levels.
8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
3
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCx
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
73.2°C/W (0lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those
listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Power Supply Voltage
Power Supply Current
3.135
3.3
3.465
50
V
IEE
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK_EN,
CLK_SEL
CLK_EN,
CLK_SEL
VIH
Input High Voltage
2
3.765
0.8
V
V
VIL
IIH
Input Low Voltage
Input High Current
-0.3
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
IN = VCC = 3.465V
5
µA
µA
µA
µA
VIN = VCC = 3.465V
150
VIN = 0V, VCC = 3.465V
-150
-5
IIL
Input Low Current
V
IN = 0V, VCC = 3.465V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
Minimum Typical Maximum Units
nCLK
CLK
5
µA
µA
µA
µA
V
IIH
Input High Current
150
nCLK
CLK
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
VEE + 0.5
VCC - 0.85
V
NOTE1: For single ended applications the maximum input voltage for CLK and nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
REV. D JULY 16, 2001
4
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.6
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCC - 1.0
VCC - 1.7
0.85
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Frequency Tolerance
Frequency Stability
Drive Level
Fundamental
-50
50
ppm
ppm
mW
Ω
-100
100
0.1
Equivalent Series Resistance (ESR)
Shunt Capacitance
Series Pin Inductance
Operating Temperature Range
Aging
50
80
7
pF
3
0
7
nH
70
5
°C
Per year @ 25°C
-5
14
ppm
MHz
Frequency Range
25
TABLE 6. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol
fMAX
Parameter
Test Conditions
Minimum
Typical
Maximum
650
Units
MHz
ns
Maximum Input Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
Part-to-Part Skew; NOTE 3, 5
Output Rise Time
tPD
IJ 650MHz
1.0
2.0
tsk(o)
tsk(pp)
tR
30
ps
150
ps
20% to 80% @ 50MHz
20% to 80% @ 50MHzz
300
300
47
700
ps
tF
Output Fall Time
700
ps
odc
Output Duty Cycle; NOTE 4
Crystal Oscillator Tollerance
50
53
%
oscTOL
TBD
ppm
All parameters measured at 500MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: Measured using CLK. For XTAL input, refer to Application Note.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
5
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
VCC
SCOPE
Qx
LVPECL
VCC = 2V
nQx
VEE =-1.3V ± 0.135V
FIGURE 2 - OUTPUT LOAD TEST CIRCUIT
VCC
CLK
VPP
VCMR
Cross Points
nCLK
VEE
FIGURE 3 - DIFFERENTIAL INPUT LEVEL
REV. D JULY 16, 2001
6
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
Qx
nQx
Qy
nQy
tsk(o)
FIGURE 4 - OUTPUT SKEW
80%
80%
VSWING
20%
20%
Clock Inputs
and Outputs
tR
tF
FIGURE 5 - INPUT AND OUTPUT RISING/FALL TIME
CLK
nCLK
Q0 - Q3
nQ0 - nQ3
tPD
FIGURE 6 - PROPAGATION DELAY
CLK, Q0 - Q3
nCLK, nQ0 - nQ3
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
FIGURE 7 - odc & tPERIOD
8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
7
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
APPLICATION IINFORMATION
CRYSTAL OSCILLATOR CIRCUIT FREQUENCY FINE TUNING
A crystal can be characterized for either series or parallel mode operation. The ICS8533-11 and ICS8535-11 fanout buffers have
built-in crystal oscillator circuits that can accept either a series or parallel crystal without additional components. The frequency
accuracy provided by this configuration is sufficient for most computer applications.
For applications requiring highly accurate clock frequencies, the output frequency can be fine tuned by inserting a small series
capacitor C1 at the XTAL1 input (Pin 6 for ICS8533-11) as shown in Figure 8. This fine tuning approach can be applied in either
parallel or series crystal. The C1 value depends on the crystal type, frequency and the board layout. The parallel crystal fine
tuning results in smaller ppm and better performance. It is difficult to provide the precise value of C1. This section provides
recommended series capacitor C1 values to start with. This example uses 18pF parallel crystals.
Figure 9shows the suggested series capacitor value for a parallel crystal. For a 16.666 MHz crystal, the recommended C1 value is
about 33pF.
Figure 10 shows frequency accuracy versus series capacitance for 19.44MHz, 16.666MHz and 15MHz crystals. As seen from this
figure, a 24pF, 33pF and 43pF series capacitor is used to achieve the lowest ppm error for 19.44MHz, 16.666MHz and 15MHz
respectively.
Figure 11 shows the experiment results of crystal oscillator frequency drift due to temperature variation.
U1
XTAL2
X1
C1
XTAL1
FIGURE 8 - CRYSTAL INTERFACE WITH SERIES CAPACITOR C1.
REV. D JULY 16, 2001
8
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
60
14.318
50
40
30
20
10
0
15.000
16.666
19.440
20.000
24.000
14
15
16
17
18
19
20
21
22
23
24
25
Crystal Frequency (MHz)
FIGURE 9 - SUGGESTED SERIES CAPACITOR C1 FOR PARALLEL CRYSTAL
100
80
60
40
20
19.44MHz
16.666MHz
15.00MHz
0
0
10
20
30
40
50
60
-20
-40
-60
-80
-100
Series Capacitor, C1 (pF)
FIGURE 10 - FREQUENCY ACCURACY FOR PARALLEL CRYSTAL USING SERIES CAPACITOR C1
8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
9
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
60
40
20
0
19.44MHz
16.666MHz
0
10
20
30
40
50
60
70
80
-20
-40
-60
Temperature (deg. C)
FIGURE 11 - CRYSTAL OSCILLATOR CRCUIT FREQUENCY DRIFTED DUE TO TEMPERATURE VARIATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 12 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 12: SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
REV. D JULY 16, 2001
10
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8533-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8533-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 50mA = 173.3mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW
Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 120.8mW = 294.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.294W * 66.6°C/W = 89.58°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 7. Thermal Resistance qJA for 20-pin TSSOP, Forced Convection
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
11
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 13 - LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
)
OH_MAX
CC_MAX
CC_MAX
OH_MAX
L
– (V
- 2V))/R ] * (V
- V
)
OL_MAX
CC_MAX
CC_MAX
OL_MAX
L
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CC_MAX
Using V
= 3.465, this results in V
= 2.465V
= 1.765V
CC_MAX
OH_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CC_MAX
Using V
= 3.465, this results in V
OL_MAX
CC_MAX
Pd_H = [(2.465V - (3.465V - 2V))/50Ω] * (3.465V - 2.465V) = 20mW
Pd_L = [(1.765V - (3.465V - 2V))/50Ω] * (3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
REV. D JULY 16, 2001
12
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
200
0
500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8533-11 is: 428
8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
13
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - G SUFFIX
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MS-153
REV. D JULY 16, 2001
14
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
72 per tube
2500
Temperature
0°C to 70°C
0°C to 70°C
ICS8533AG-11
ICS8533AG-11T
ICS8533AG-11
ICS8533AG-11
20 lead TSSOP
20 lead TSSOP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
15
相关型号：
ICS8533AG-01LF
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, LEAD FREE, MS-153, TSSOP-20
IDT
ICS8533AG-01LFT
Low Skew Clock Driver, 8533 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MS-153, TSSOP-20
IDT
ICS8533AG-01LNT
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, LEAD FREE/ANNEALED, MS-153, TSSOP-20
IDT
ICS8533AG-11LF
Low Skew Clock Driver, 8533 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, LEAD FREE, MS-153, TSSOP-20
IDT
ICS8533AG-11LFT
Low Skew Clock Driver, 8533 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MS-153, TSSOP-20
IDT
©2020 ICPDF网 联系我们和版权申明