ICS8532AY-01 [ICSI]
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER; 低偏移， 1到17差分至3.3V的LVPECL扇出缓冲器
| 型号： | ICS8532AY-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER |
| 文件： | 总13页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8532-01 is a low skew, 1-to-17, Differ- • 17 differential 3.3V LVPECLoutputs
ential-to-3.3V LVPECL Fanout Buffer and a
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8532-01 has two selectable clock inputs.
• Selectable CLK, nCLK or LVPECL clock inputs
HiPerClockS™
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
The CLK, nCLK pair can accept most standard differential
input levels. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels. The clock enable is
internally synchronized to eliminate runt pulses on the out-
puts during asynchronous assertion/deassertion of the clock
enable pin.
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency up to 500MHz
• Translates any single-ended input signal (LVCMOS, LVTTL,
GTL) to 3.3V LVPECL levels with resistor bias on nCLK input
Guaranteed output and part-to-part skew characteristics
make the ICS8532-01 ideal for those clock distribution
applications demanding well defined performance and
repeatability.
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 2.5ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
D
CLK_EN
Q
LE
52 51 50 49 48 47 46 45 44 43 42 41 40
CLK
nCLK
VCCO
nc
1
VCCO
Q6
39
38
37
36
35
34
33
32
31
30
29
28
27
0
1
Q0 - Q16
nQ0 - nQ16
2
PCLK
nPCLK
nc
3
nQ6
Q7
VCC
4
CLK
5
nQ7
Q8
CLK_SEL
nCLK
CLK_SEL
PCLK
nPCLK
VEE
6
7
nQ8
Q9
ICS8532-01
8
9
nQ9
Q10
nQ10
nc
10
11
12
13
CLK_EN
nc
VCCO
Vcco
14 15 16 17 18 19 20 21 22 23 24 25 26
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
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ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 13, 26,
27, 39, 40
VCCO
Power
Power
Output supply pins. Connect to 3.3V.
4
VCC
nc
Positive supply pin. Connect to 3.3V.
No connect.
2, 3, 12, 28
Unused
Input
5
6
CLK
nCLK
Pulldown Non-inverting differential clock input.
Input
Pullup
Inverting differential clock input.
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
7
CLK_SEL
Input
Pulldown When LOW, selects CLK, nCLK inputs.
LVCMOS / LVTTL interface levels.
8
9
PCLK
nPCLK
VEE
Input
Input
Pulldown Non-inverting differential LVPECL clock input.
Pullup
Inverting differential LVPECL clock input.
Negative supply pin. Connect to ground.
10
Power
Synchronizing clock enable. When HIGH, clock outputs follow clock
input. When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
11
CLK_EN
Input
Pullup
14, 15
16, 17
18, 19
20, 21
22, 23
24, 25
29, 30
31, 32
33, 34
35, 36
37, 38
41, 42
43, 44
45, 46
47, 48
49, 50
51, 52
nQ16, Q16 Output
nQ15, Q15 Output
nQ14, Q14 Output
nQ13, Q13 Output
nQ12, Q12 Output
nQ11, Q11 Output
nQ10, Q10 Output
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
nQ9, Q9
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3 Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CLK,
nCLK
PCLK,
nPCLK
CLK_EN,
CLK_SEL
4
4
4
pF
pF
pF
CIN
Input Capacitance
RPULLUP
Input Pullup Resistor
51
51
KΩ
KΩ
RPULLDOWN Input Pulldown Resistor
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ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
CLK, nCLK
Q0 thru Q16
Disabled; LOW
Disabled; LOW
Enabled
nQ0 thru nQ16
Disabled; HIGH
Disabled; HIGH
Enabled
0
0
1
1
0
1
0
1
PCLK, nPCLK
CLK, nCLK
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1
In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described
.
in Table 3B
.
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0 - nQ16
Q0 - Q16
FIGURE 1: CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK or PCLK
nCLK or nPCLK
Q0 thru Q16
nQ0 thru nQ16
0
1
1
0
LOW
HIGH
LOW
Differential to Differential
Differential to Differential
Non Inverting
Non Inverting
HIGH
Single Ended to
Differential
Single Ended to
Differential
Single Ended to
Differential
Single Ended to
Differential
0
Biased; NOTE 1
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
Non Inverting
Non Inverting
Inverting
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Please refer to the Application Information section on page 8, Figure 9, which discusses wiring the differential
input to accept single ended levels.
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ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCx
Inputs, VI
4ꢀ6V
-0ꢀ5V to VCC + 0ꢀ5V
-0ꢀ5V to VCCO + 0ꢀ5V
Outputs, VO
Package Thermal Impedance, θJA
40°C/W
Storage Temperature, TSTG
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the deviceꢀ These ratings
are stress specifications onlyꢀ Functional operation of product at these conditions or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not impliedꢀ Exposure to absolute maximum rating conditions for extended
periods may affect product reliabilityꢀ
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
3.465
3.465
150
V
V
VCCO
IEE
3.135
3.3
122
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK_EN,
CLK_SEL
CLK_EN,
CLK_SEL
VIH
Input High Current
2
3.765
0.8
V
V
VIL
IIH
Input Low Current
Input High Current
-0.3
CLK_SEL
CLK_EN
CLK_SEL
CLK_EN
VIN = VCC = 3.465V
VIN = VCC = 3.465V
150
5
µA
µA
µA
µA
VIN = 0V, VCC = 3.465V
VIN = 0V, VCC = 3.465V
-5
IIL
Input Low Current
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum
Typical
Maximum Units
CLK
V
IN = VCC = 3.465V
150
5
µA
µA
µA
µA
V
nCLK
CLK
VIN = VCC = 3.465V
V
IN = 0V, VCC = 3.465V
-5
IIL
Input Low Current
nCLK
VIN = 0V, VCC = 3.465V
-150
0.15
VPP
Peak-to-Peak Input Voltage
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
VEE + 0.5
VCC - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK and nCLK is VCC + 0.3V.
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ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
PCLK
V
CC = VIN = 3.465V
150
5
µA
µA
µA
µA
V
IIH
Input High Current
nPCLK
PCLK
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
-5
-150
IIL
Input Low Current
nPCLK
VPP
Peak-to-Peak Input Voltage
0.3
1
VCMR
VOH
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Peak-to-Peak Voltage Swing
VEE + 1.5
VCCO - 1.4
VCCO - 2.0
0.6
VCC
V
VCCO - 1.0
VCCO - 1.7
0.85
V
VOL
V
VSWING
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
fMAX Maximum Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum Units
500
2.5
50
MHz
ns
ps
ps
ps
ps
%
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
IJ 500MHz
1.3
tsk(o)
tsk(pp)
tR
250
700
700
52
20% to 80% @ 50MHz
20% to 80% @ 50MHz
0 ≤ ƒ≤ 266MHz
300
300
48
tF
Output Fall Time
50
50
odc
Output Duty Cycle
266 ≤ ƒ≤ 500MHz
47
53
%
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
VCCO
VCC
SCOPE
Qx
LVPECL
VCC = 2.0V
VCCO = 2.0V
nQx
VEE = -1.3V ± 0.135V
FIGURE 2 - OUTPUT LOAD TEST CIRCUIT
VCC
CLK, PCLK
VPP
VCMR
Cross Points
nCLK, nPCLK
VEE
FIGURE 3 - DIFFERENTIAL INPUT LEVEL
Qx
nQx
Qy
nQy
tsk(o)
FIGURE 4 - OUTPUT SKEW
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ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
Qx
PART1
nQx
Qy
PART2
nQy
tsk(pp)
FIGURE 5 - PART-TO-PART SKEW
80%
80%
VSWING
20%
20%
Clock Inputs
and Outputs
tR
tF
FIGURE 6 - INPUT AND OUTPUT RISE AND FALL TIME
CLK, PCLK
nCLK, nPCLK
Q0 - Q16
nQ0 - nQ16
tPD
FIGURE 7 - PROPAGATION DELAY
CLK, PCLK, Qx
nCLK, nPCLK, nQx
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
FIGURE 8 - odc & tPERIOD
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ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 9 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 9: SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8531-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8531-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.8mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 17 * 30.2mW = 513.4mW
Total Power_MAX (3.465V, with all outputs switching) = 519.8mW + 513.4mW = 1033.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 0°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.1033W * 0°C/W = 0°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance qJA for 52-pin LQFP Forced Convection
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0°C/W
0°C/W
0°C/W
0°C/W
0°C/W
0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 10.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
Figure 10 - LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
)
OH_MAX
CC_MAX
CC_MAX
OH_MAX
L
– (V
- 2V))/R ] * (V
- V
)
OL_MAX
CC_MAX
CC_MAX
OL_MAX
L
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CC_MAX
Using V
= 3.465, this results in V
= 2.465V
= 1.765V
CC_MAX
OH_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CC_MAX
Using V
= 3.465, this results in V
OL_MAX
CC_MAX
Pd_H = [(2.465V - (3.465V - 2V))/50Ω] * (3.465V - 2.465V) = 20mW
Pd_L = [(1.765V - (3.465V - 2V))/50Ω] * (3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
q by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0°C/W
0°C/W
0°C/W
0°C/W
0°C/W
0°C/W
NOTE: Most all modern PCB designs use multi-layered boards, so the data in the second row will pertain to most designsꢀ
TRANSISTOR COUNT
The transistor count for ICS8532-01 is: 1398
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LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BCC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
52
--
--
1.60
0.15
1.45
0.38
0.20
A1
A2
b
0.05
1.35
0.22
0.09
--
1.40
0.32
c
--
D
12.00 BASIC
10.00 BASIC
7.80 Ref.
12.00 BASIC
10.00 BASIC
7.80 Ref.
0.65 BASIC
--
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS8532AY-01
Marking
Package
52 Lead LQFP
Count
160 per tray
500
Temperature
0°C to 70°C
0°C to 70°C
ICS8532AY-01
ICS8532AY-01
ICS8532AY-01T
52 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, LEAD FREE/ANNEALED, MS-153, TSSOP-20
IDT
ICS8533AG-11LF
Low Skew Clock Driver, 8533 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, LEAD FREE, MS-153, TSSOP-20
IDT
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