ICS8533AG-01LFT [IDT]
Low Skew Clock Driver, 8533 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MS-153, TSSOP-20;
| 型号： | ICS8533AG-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 8533 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MS-153, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总17页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8533-01 is a low skew, high performance 1-to-4 • Four differential 3.3V LVPECL outputs
Differential-to-3.3V LVPECL Fanout Buffer. The ICS8533-
• Selectable differential CLK, nCLK or LVPECL clock inputs
01 has two selectable clock inputs. The CLK, nCLK pair
can accept most standard differential input levels. The
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL
input levels. The clock enable is internally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin. Guaranteed
output and part-to-part skew characteristics make the
ICS8533-01 ideal for those applications demanding well
defined performance and repeatability.
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 1.4ns (maximum)
• Additive phase jitter, RMS: 0.06ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free packages available
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
Q0
VEE
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
D
CLK_EN
nQ0
VCC
Q1
nQ1
Q2
nQ2
VCC
Q3
Q
LE
CLK
nCLK
PCLK
0
1
Q0
nQ0
nPCLK
Q1
nQ1
9
10
nc
VCC
CLK_SEL
nQ3
Q2
nQ2
ICS8533-01
20-Lead TSSOP
Q3
nQ3
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
1
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VEE
Power
Input
Negative supply pin.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects differential PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
2
CLK_EN
Pullup
Pulldown
3
CLK_SEL
Input
4
5
CLK
nCLK
Input
Input
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Pulldown Non-inverting differential LVPECL clock input.
6
PCLK
Input
7
nPCLK
nc
Input
Pullup
Inverting differential LVPECL clock input.
No connect.
8, 9
Unused
Power
Output
Output
Output
Output
10, 13, 18
11, 12
14, 15
16, 17
19, 20
VCC
Positive supply pins.
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
2
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
CLK, nCLK
Q0:Q3
Disabled; LOW
Disabled; LOW
Enabled
nQ0:nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
0
0
1
1
0
1
0
1
PCLK, nPCLK
CLK, nCLK
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described
in Table 3B.
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0:nQ3
Q0:Q3
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK or PCLK
nCLK or nPCLK
Q0:Q3
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQ0:nQ3
HIGH
LOW
0
1
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
3
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
73.2°C/W (0 lfpm)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
3.135
3.3
3.465
50
V
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
Input High Voltage
2
VEE + 0.3
V
Input Low Voltage
-0.3
0.8
5
V
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
IN = VCC = 3.465V
µA
µA
µA
µA
IIH
Input High Current
VIN = VCC = 3.465V
150
VIN = 0V, VCC = 3.465V
-150
-5
IIL
Input Low Current
V
IN = 0V, VCC = 3.465V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
nCLK
CLK
V
CC = VIN = 3.465V
5
µA
µA
µA
µA
V
IIH
Input High Current
VCC = VIN = 3.465V
150
nCLK
CLK
V
V
CC = 3.465V, VIN = 0V
CC = 3.465V, VIN = 0V
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
VEE + 0.5
VCC - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
4
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VCC = VIN = 3.465V
VCC = VIN = 3.465V
CC = 3.465V, VIN = 0V
Minimum
Typical
Maximum Units
PCLK
150
5
µA
µA
µA
µA
V
IIH Input High Current
nPCLK
PCLK
V
-5
-150
IIL
Input Low Current
nPCLK
VCC = 3.465V, VIN = 0V
VPP
Peak-to-Peak Input Voltage
0.3
1
VCMR
VOH
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
VEE + 1.5
VCC - 1.4
VCC - 2.0
0.6
VCC
V
VCC - 0.9
VCC - 1.7
1.0
V
VOL
Output Low Voltage; NOTE 3
V
VSWING
Peak-to-Peak Output Voltage Swing
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
650
1.4
30
MHz
ns
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
IJ 650MHz
1.0
tsk(o)
tsk(pp)
ps
Part-to-Part Skew; NOTE 3, 4
150
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
tjit
0.06
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ @ 50MHz
300
47
700
53
ps
ꢀ
All parameters measured at 500MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Driving only one input clock.
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
5
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
Input/Output Additive Phase Jitter
at 156.25MHz = 0.06ps (typical)
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
160
-
-170
-180
-
190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues. The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
6
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nPCLK, nCLK
PCLK, CLK
VEE
LVPECL
VEE
VPP
VCMR
Cross Points
nQx
-1.3V 0.165
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nPCLK,
nCLK
nQx
Qx
PCLK,
CLK
nQ0:nQ3
nQy
Q0:Q3
Qy
tPD
tsk(o)
OUTPUT SKEW
PROPAGATION DELAY
nQ0:nQ3
Q0:Q3
80ꢀ
tF
80ꢀ
VSWING
20ꢀ
Pulse Width
Clock
20ꢀ
tPERIOD
Outputs
tR
tPW
odc =
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
www.idt.com
8533AG-01
REV. F AUGUST 4, 2010
7
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF in
single ended levels. The reference voltage V_REF = VCC/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1. This bias circuit clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin. The ratio and R2/R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
Z
o = 50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
8
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL examples only. Please consult with the vendor of the driver
and other differential signals. Both VSWING and VOH must meet component to confirm the driver termination requirements. For
the VPP and VCMR input requirements. Figures 4A to 4E show example in Figure 4A, the input termination applies for LVHSTL
interface examples for the CLK/nCLK input driven by the most drivers. If you are using an LVHSTL driver from another
common driver types. The input interfaces suggested here are vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 4A. CLK/NCLK INPUT DRIVEN BY
LVHSTL DRIVER
FIGURE 4B. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 4C. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
C2
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 4E. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
9
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other are examples only. If the driver is from another vendor, use
differential signals. Both VSWING and VOH must meet the VPP their termination recommendation. Please consult with the
and VCMR input requirements. Figures 5A to 5F show interface vendor of the driver component to confirm the driver
examples for the PCLK/nPCLK input driven by the most termination requirements.
common driver types. The input interfaces suggested here
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
R2
50
Zo = 50 Ohm
Zo = 50 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
R1
100
nPCLK
HiPerClockS
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
CML Built-In Pullup
FIGURE 5A. PCLK/nPCLK INPUT DRIVEN
FIGURE 5B. PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
R3
84
R4
84
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84
R2
84
FIGURE 5C. PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 5D. PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
2.5V
3.3V
3.3V
3.3V
2.5V
Zo = 50 Ohm
R3
1K
R4
1K
R3
120
R4
120
C1
C2
LVDS
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
PCLK
PCLK
R5
100
nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
1K
R2
1K
R1
120
R2
120
FIGURE 5E. PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 5F. PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
10
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8533-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8533-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 50mA = 173.3mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 120mW = 293.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.293W * 66.6°C/W = 89.5°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
11
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
12
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8533-01 is: 404
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
13
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MS-153
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
14
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
8533AG-01
Marking
Package
Shipping Packaging Temperature
ICS8533AG-01
ICS8533AG-01
ICS8533A01LN
ICS8533A01LN
ICS8533A01LF
ICS8533A01LF
20 lead TSSOP
tube
0°C to 70°C
0°C to70°C
0°C to 70°C
0°C to70°C
0°C to 70°C
0°C to70°C
8533AG-01T
20 lead TSSOP
2500 tape & reel
tube
8533AG-01LN
8533AG-01LNT
8533AG-01LF
8533AG-01LFT
20 lead "Lead Free/Annealed" TSSOP
20 lead "Lead Free/Annealed" TSSOP
20 lead "Lead Free" TSSOP
20 lead "Lead Free" TSSOP
2500 tape & reel
tube
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
15
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
REVISION HISTORY SHEET
Description of Change
VPP values changed from 0.1 Min. to 0.15 Min.
Rev
Table
4C
Page
4
Date
VCMR values changed from 0.13 Min., 1.3 Max. to 1.5 Min, VCC Max.
4D
5
5
5
Deleted VIH and VIL rows.
B
5/22/01
tR values changed from 100 Min. to 300 Min, and added 700 Max.
tF values changed from 100 Min., 600 Max. to 300 Min. to 700 Max.
For tR and tF rows changed test conditions from 30ꢀ to 70ꢀ to 20ꢀ to 80ꢀ.
tjit(cc) values changed 150 Max. to 0 Max.
B
B
5
5
5
Deleted tS and tH rows.
6/4/01
V
PP values changed from 0.15 Min., 1.3 Max. to 0.3 Min., 1 Max.
VCMR values changed from 1.5 Min., to VEE + 1.5 Min.
VIH values changed from 3.765 Max. to VCC + 0.3 Max.
4D
6/28/01
4B
5
4
5
C
10/15/01
Deleted tjit(cc) row.
C
C
C
6, 7
3
Revised Parameter Measurement diagrams.
Updated Figure 1, CLK_EN Timing Diagram.
Added Termination for LVPECL Outputs section.
Output Load Test Circuit diagram - corrected VEE equation to read,
10/18/01
11/1/01
5/28/02
8
C
D
6
10/03/02
10/12/03
VEE = -1.3V 0.165V from VEE = -1.3V 0.135V.
1
2
Added RMS Jitter to Features section.
T2
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
Changed Outputs Absolute Maximum Rating.
LVPECL Table - changed VSWING 0.85V max. to 1.0V max.
AC Characteristics Table - added RMS jitter.
Added Additive Phase Jitter Section.
4
T4D
T5
5
5
6
8
Updated LVPECL Output Termination diagrams.
Added Differential Clock Input Interface.
9
10
Added LVPECL Clock Input Interface.
Updated format throughout data sheet.
D
D
T9
15
Added Lead Free Annealed part number to Ordering Information table.
2/9/04
10
15
5
Updated LVPECL Clock Input Interface section.
6/17/04
T9
T4D
Ordering Information Table - added Lead Free part number.
LVPECL DC Characteristics Table -corrected VOH max. from VCC - 1.0V to
VCC- 0.9V.
E
F
11 - 12 Power Considerations - corrected power dissipation to reflect VOH max in
Table 4D.
4/12/07
8/4/10
T9
T9
15
Ordering Information Table - added lead-free note.
Updated datasheet's header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
15
17
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
16
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
netcom@idt.com
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
their respective owners.
Printed in USA
8533AG-01
www.idt.com
REV. F AUGUST 4, 2010
17
相关型号：
ICS8533AG-01LNT
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, LEAD FREE/ANNEALED, MS-153, TSSOP-20
IDT
ICS8533AG-11LF
Low Skew Clock Driver, 8533 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, LEAD FREE, MS-153, TSSOP-20
IDT
ICS8533AG-11LFT
Low Skew Clock Driver, 8533 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MS-153, TSSOP-20
IDT
ICS8533AGI-31LF
Clock Generator, 650MHz, PDSO20, 6.50 X 4.40 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20
IDT
ICS8533AGI-31T
Clock Generator, 650MHz, PDSO20, 6.50 X 4.40 MM, 0.925 MM HEIGHT, MO-153, TSSOP-20
IDT
©2020 ICPDF网 联系我们和版权申明