ICS8533AG-11LF [IDT]
Low Skew Clock Driver, 8533 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, LEAD FREE, MS-153, TSSOP-20;
| 型号： | ICS8533AG-11LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 8533 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, LEAD FREE, MS-153, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总16页 (文件大小：429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
ICS8533-11
LOW SKEW, 1-TO-4 CRYSTAL
OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT
GENERAL DESCRIPTION
ICS
FEATURES
The ICS8533-11 is a low skew, high performance
1-to-4 Crystal Oscillator/Differential-to-3.3V
LVPECL fanout buffer and a member of the
HiPerClockS™family of High Performance Clock
Solutions from ICS.The ICS8533-11 has select-
• 4 differential 3.3V LVPECL outputs
• Selectable differential CLK, nCLK or crystal inputs
HiPerClockS™
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
able differential clock or crystal inputs. The CLK, nCLK pair
can accept most standard differential input levels. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin.
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 2ns (maximum)
• 3.3V operating supply
Guaranteed output and part-to-part skew characteristics
make the ICS8533-11 ideal for those applications demand-
ing well defined performance and repeatability.
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
D
CLK_EN
VEE
CLK_EN
CLK_SEL
CLK
nCLK
XTAL1
XTAL2
nc
Q0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q
nQ0
VCC
Q1
nQ1
Q2
nQ2
VCC
Q3
LE
CLK
nCLK
XTAL1
0
1
Q0
nQ0
XTAL2
Q1
nQ1
CLK_SEL
nc
VCC
Q2
nQ2
nQ3
ICS8533-11
20-Lead TSSOP
Q3
nQ3
6.5mm x 4.4mm x 0.92 package body
G Package
TopView
IDT™ / ICS™ LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
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TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VEE
Power
Input
Negative supply pin.
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When LOW, selects CLK, nCLK input.
When HIGH, selects XTAL input. LVCMOS / LVTTL interface levels.
2
CLK_EN
Pullup
Pulldown
3
CLK_SEL
Input
4
5
CLK
nCLK
Input
Input
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Pulldown Crystal oscillator input.
6
XTAL1
XTAL2
nc
Input
7
Input
Pullup
Crystal oscillator input.
8, 9
Unused
Power
Output
Output
Output
Output
No connect.
10, 13, 18
11, 12
14, 15
16, 17
19, 20
VCC
Positive supply pins.
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
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TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
CLK, nCLK
Q0:Q3
Disabled; LOW
Disabled; LOW
Enabled
nQ0:nQ3
0
0
1
1
0
1
0
1
Disabled; HIGH
Disabled; HIGH
Enabled
XTAL1, XTAL2
CLK, nCLK
XTAL1, XTAL2
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled folowing a rising and falling input clock or
crystal oscillator edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK, nCLK and XTAL1, XTAL2 inputs as described
in Table 3B.
Enabled
Disabled
nCLK
CLK
CLK_EN
nQ0:nQ3
Q0:Q3
FIGURE 1. CLK_EN TIMING
DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK
nCLK
Q0:Q3
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQ0:nQ3
HIGH
LOW
0
1
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
73.2°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Power Supply Voltage
Power Supply Current
3.135
3.3
3.465
50
V
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK_EN,
CLK_SEL
CLK_EN,
CLK_SEL
VIH
Input High Voltage
2
V
CC + 0.3
V
V
VIL
IIH
Input Low Voltage
Input High Current
-0.3
0.8
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
IN = VCC = 3.465V
5
µA
µA
µA
µA
VIN = VCC = 3.465V
150
VIN = 0V, VCC = 3.465V
-150
-5
IIL
Input Low Current
V
IN = 0V, VCC = 3.465V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
Minimum Typical Maximum Units
nCLK
CLK
5
µA
µA
µA
µA
V
IIH
Input High Current
150
nCLK
CLK
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
V
EE + 0.5
VCC - 0.85
V
NOTE1: For single ended applications the maximum input voltage for CLK and nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.6
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 1.0
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
14
25
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
TABLE 6. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
650
Units
MHz
ns
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
Part-to-Part Skew; NOTE 3, 5
Output Rise/Fall Time
IJ 650MHz
1.0
2.0
tsk(o)
tsk(pp)
tR / tF
odc
30
ps
150
ps
20ꢀ to 80ꢀ @ 50MHz
300
47
700
ps
Output Duty Cycle; NOTE 4
50
53
ꢀ
All parameters measured at 500MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: Measured using CLK. For XTAL input, refer to Application Note.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
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PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nCLK
LVPECL
VEE
VPP
VCMR
Cross Points
nQx
CLK
VEE
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
nCLK
CLK
nQ0:nQ3
nQy
Q0:Q3
Qy
tPD
tsk(o)
OUTPUT SKEW
PROPAGATION DELAY
nQ0:nQ3
80ꢀ
tF
80ꢀ
Q0:Q3
VSWING
20ꢀ
Pulse Width
tPERIOD
Clock
20ꢀ
Outputs
tR
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
IDT™ / ICS™ LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
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APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
VCC
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- 50Ω transmission lines. Matched impedance techniques should
tion for LVPECL outputs.The two different layouts mentioned be used to maximize operating frequency and minimize signal
are recommended only as guidelines.
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
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DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 4A to 4E show inter- For example in Figure 4A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers.If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
IDT™ / ICS™ LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
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LOW SKEW, 1-TO-4CRYSTALOSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
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CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel
mode operation.The ICS8533-11 fanout buffer has a built-in
crystal oscillator circuit. This interface can accept either a
series or parallel crystal without additional components as
shown in Figure 5. The physical location of the crystal should
be located as close as possible to the XTAL1 and XTAL2 pins.
The experiments show that using a 19.44MHz crystal results
in an output frequency of 19.4404746MHz and approximately
44ꢀ of duty cycle.
XTAL2
XTAL1
C2
SPARE
X1
Cry stal
C1
40p
FIGURE 5. CRYSTAL INPUT INTERFACE
SCHEMATIC EXAMPLE
Figure 6 shows a schematic example of the ICS8533-11. In this should be physically located near the power pin. For ICS8533-11,
example, the XTAL input is selected. The decoupling capacitors the unused clock outputs can be left floating.
Zo = 50
+
3.3V
Zo = 50
-
R2
50
R1
50
R11
1K
R12
1K
U1
R3
50
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
VEE
Q0
nQ0
VCC
Q1
nQ1
Q2
nQ2
VCC
Q3
CLK_EN
CLK_SEL
CLK
nCLK
XTAL1
XTAL2
NC
3.3V
3.3V
40p - 60pF
C4
X1
NC
VCC
3.3V
C1
10
nQ3
C5
SPARE
ICS8533-11
0.1u
Zo = 50
Zo = 50
+
-
3.3V
C2
0.1u
C3
0.1u
R8
50
R7
50
R9
50
FIGURE 6. ICS8533-11 LVPECL BUFFER SCHEMATIC EXAMPLE
IDT™ / ICS™ LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8533-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8533-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 50mA = 173.3mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW
Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 120.8mW = 294.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W perTable 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.294W * 66.6°C/W = 89.58°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
IDT™ / ICS™ LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 1.0V
OH_MAX
CC_MAX
)
= 1.0V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
L
CC
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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11
ICS8533-11
LOW SKEW, 1-TO-4CRYSTALOSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TSD
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8533-11 is: 428
IDT™ / ICS™ LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ICS8533-11
12
ICS8533-11
LOW SKEW, 1-TO-4CRYSTALOSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TSD
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MS-153
IDT™ / ICS™ LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ICS8533-11
13
ICS8533-11
LOW SKEW, 1-TO-4CRYSTALOSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TSD
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
72 per tube
2500
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS8533AG-11
ICS8533AG-11T
ICS8533AG-11LF
ICS8533AG-11
ICS8533AG-11
ICS8533AG11L
20 Lead TSSOP
20 Lead TSSOP on Tape and Reel
20 Lead "Lead-Free" TSSOP
72 per tube
20 Lead "Lead-Free" TSSOP on
Tape and Reel
ICS8533AG-11LFT
ICS8533AG11L
2500
0°C to 70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
IDT™ / ICS™ LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ICS8533-11
14
ICS8533-11
LOW SKEW, 1-TO-4CRYSTALOSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TSD
REVISION HISTORY SHEET
Description of Change
Rev
D
Table
Page
Date
3
3
Revised Figure 1, CLK_EN Timing Diagram.
Revised Figure 1, CLK_EN Timing Diagram.
10/18/01
11/2/01
D
Deleted Crystal Oscillator Circuit Frequency Fine Tuning section from
datasheet.
Shortened Crystal Characteristics table.
ESR row, values have changed from 50Ω Min, 80Ω Max. to 70Ω Max.
Added Termination for LVPECL Outputs section.
D
D
8-10
5
12/11/01
T5
1/11/02
5/28/02
10/3/02
D
D
8
6
Output Load Test Circuit diagram - corrected VEE equation to read,
VEE = -1.3V 0.165V from VEE = -1.3V 0.135V.
T2
2
4
4
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
Absolute Maximum Ratings - revised Output rating.
T4B
LVCMOS DC Characteristics Table - changed VIH max. from 3.765V to
VCC + 0.3V.
5
5
5
7
7
8
9
LVPECL DC CHaracteristics Table - changed VSWING max. from 0.85V to 1.0V.
Crystal Characteristics Table - changed ESR from 70Ω max. to 50Ω max.
AC Characteristics Table - deleted oscTOL row from table.
Updated Single Ended Signal Driving Differential Input Diagram.
Updated LVPECL Output Termination Diagrams.
T4D
T5
E
E
10/30/03
12/14/04
Added Differential Clock Input Interface section.
Added Crystal section.
9
1
14
Added Schematic Example.
Features Section - added Lead-Free bullet.
Ordering Information Table - added "Lead-Free" part number.
T10
IDT™ / ICS™ LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ICS8533-11
15
31
CRYSTALOSCILLATOR/DIFFERENTIAL-TO-3.3VLVPECL FANOUT BUFFER
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